Queue Management Method and Device

Abstract

This application relates to the field of network communication technology and discloses a queue management method and apparatus. The queue management apparatus includes: a globally shared sub-queue resource pool containing multiple sub-queues; a queue configuration module for dynamically allocating several sub-queues from the sub-queue resource pool to a logical queue. The allocated sub-queues and the logical queue do not have a fixed binding relationship, and the number of allocated sub-queues ensures that the polling interval is not less than the hardware read latency. The logical queue is a queue corresponding to a set of ordered data, and the several sub-queues allocated to the logical queue collaboratively manage the access to the ordered data in the logical queue in a polling manner. By globally sharing and dynamically allocating sub-queue resources, the low hardware resource utilization problem in traditional fixed allocation schemes is solved, and by constraining the polling interval to be no less than the hardware read latency, continuous and conflict-free dequeue scheduling is achieved.

Description

Technical Field

[0001] This application relates to the field of network communication technology, and in particular to a queue management method and apparatus. Background Technology

[0002] In high-speed network communication and data processing systems, a large number of queues need to be maintained to queue and schedule different service flows in order to achieve sequential data access and service quality assurance.

[0003] As system scale increases, the number of logical queues that need to be supported also increases. In existing technologies, a common queue management scheme is to allocate a fixed set of sub-queue resources to each logical queue for independently maintaining the queue's data storage and sequence management. While this fixed allocation method is simple to implement, when the number of logical queues in the system is large, a large number of sub-queues need to be allocated. For example, in a multi-port, multi-channel time-division multiplexing (TDM) scheduling system, sufficient sub-queues need to be reserved for each logical queue to meet worst-case performance requirements. However, in most real-world scenarios, many logical queues are not simultaneously at full load, resulting in the sub-queues allocated to these logical queues remaining idle for extended periods, leading to a significant waste of hardware resources. Summary of the Invention

[0004] This application provides a queue management method and apparatus. By globally sharing and dynamically allocating sub-queue resources, it solves the problem of low hardware resource utilization in traditional fixed allocation schemes. Furthermore, by constraining the polling time interval to be no less than the hardware read latency, it achieves continuous and conflict-free dequeue scheduling.

[0005] In a first aspect, one embodiment of this application provides a queue management device, including: A globally shared sub-queue resource pool, wherein the sub-queue resource pool contains multiple sub-queues; The queue configuration module is used to dynamically allocate several sub-queues to the logical queue from the sub-queue resource pool. The allocated sub-queues do not form a fixed binding relationship with the logical queue, and the number of allocated sub-queues ensures that the polling time interval is not less than the hardware read latency. The polling time interval is the time interval between two consecutive accesses to the same sub-queue, and the hardware read latency is the delay required for the sub-queue to go from the current data being retrieved to the next data being ready. The logical queue is a queue corresponding to a set of ordered data. Several sub-queues allocated to the logical queue coordinate the storage and retrieval of ordered data in the logical queue in a round-robin manner.

[0006] Optionally, the queue configuration module is specifically used for: The number of sub-queues allocated to the logical queue is determined based on the link width mode currently used by the port where the logical queue is located.

[0007] Optionally, each link width mode corresponds to a pre-configured fixed number of sub-queues. The number of fixed sub-queues is determined according to the transmission characteristics of the corresponding link width mode, and the polling time interval in the link width mode is not less than the hardware read latency.

[0008] Optionally, the total number of sub-queues in the sub-queue resource pool is determined based on the maximum number of concurrent logical queues in the system and the number of sub-queues required for a single logical queue.

[0009] Optionally, the step of collaboratively managing the access to ordered data in the logical queue using a polling method specifically includes: When enqueuing, each piece of data in the ordered data is alternately distributed to the several sub-queues for storage; When dequeuing, data is retrieved from the aforementioned sub-queues in a round-robin fashion.

[0010] Optionally, each sub-queue has an independent head pointer and a tail pointer, wherein the head pointer is used to indicate the cache address of the data to be retrieved in the sub-queue, and the tail pointer is used to indicate the cache address of the last stored data in the sub-queue; The device also includes a globally shared linked list memory for storing the link relationships between data in each sub-queue. The linked list memory is accessed using the cache address pointed to by the head pointer as an index to read the cache address corresponding to the next data to be retrieved in the corresponding sub-queue.

[0011] Secondly, one embodiment of this application provides a queue management method, applied to any of the queue management devices in the first aspect, the method comprising: Several sub-queues are dynamically allocated to the logical queue from a globally shared sub-queue resource pool. The allocated sub-queues do not form a fixed binding relationship with the logical queue, and the number of allocated sub-queues ensures that the polling time interval is not less than the hardware read latency. The polling time interval is the time interval between two consecutive accesses to the same sub-queue, and the hardware read latency is the delay required for the sub-queue to go from the current data being retrieved to the next data being ready. The system controls several sub-queues allocated to the logical queue to collaboratively manage the access to ordered data in the logical queue in a round-robin manner.

[0012] Optionally, the method further includes: The number of sub-queues allocated to the logical queue is determined based on the link width mode currently used by the port where the logical queue is located.

[0013] Optionally, the total number of sub-queues in the sub-queue resource pool is determined based on the maximum number of concurrent logical queues in the system and the number of sub-queues required for a single logical queue.

[0014] Optionally, the step of collaboratively managing the access to ordered data in the logical queue using a polling method specifically includes: When enqueuing, the data in the ordered data are alternately distributed to the several sub-queues for storage; When dequeuing, data is retrieved from the aforementioned sub-queues in a round-robin fashion.

[0015] The queue management method and apparatus provided in this application avoid the resource waste caused by reserving a fixed number of sub-queues for each logical queue in traditional fixed allocation schemes by setting up a globally shared sub-queue resource pool and dynamically allocating sub-queues according to the actual needs of the logical queues. Furthermore, by constraining the number of allocated sub-queues to ensure that the polling time interval is not less than the hardware read latency, it guarantees that the next data in the current sub-queue is ready for each dequeue operation, thereby avoiding data read errors and dequeue idle periods caused by hardware read latency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram illustrating an application scenario of the queue management device provided in this application embodiment. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, a detailed description is provided below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of this application provide method operation steps as shown in the following embodiments or drawings, the method may include more or fewer operation steps based on conventional or non-inventive effort. For steps that do not logically have a necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0019] For ease of understanding, the terms used in the embodiments of this application are explained below: Logical queue: A queue corresponding to a set of ordered data. The scheduling object presented to the outside world is uniquely identified by the scheduler through a logical queue identifier (Qnumber), corresponding to a set of ordered data that needs to be processed sequentially.

[0020] Subqueues: The basic scheduling unit maintained by internal hardware. Each subqueue is an independent hardware unit used to access ordered data in its respective logical queue and maintain the order relationship between data. Multiple subqueues can be dynamically allocated to the same logical queue, together forming the complete storage and scheduling capabilities of that logical queue.

[0021] Sub-queue resource pool: A hardware resource pool consisting of all sub-queues. There is no fixed binding relationship between sub-queues and logical queues; sub-queues can be dynamically allocated and reclaimed according to scheduling needs.

[0022] Polling interval: The time interval between two consecutive accesses of the same subqueue.

[0023] Hardware read latency: The delay required from the time the current data is retrieved from the sub-queue until the next data is ready. Hardware read latency is a fixed latency inherent to the system hardware and does not change with port operating mode, number of logical queues, or traffic volume. This hardware read latency includes, but is not limited to: the latency of reading the successor pointer from the linked list memory, the latency of transmitting the successor pointer, and the latency of updating the head pointer.

[0024] Link width mode: The number of channels occupied by a port at the physical layer, used to represent the port's transmission bandwidth capacity. Common link width modes include x4 (occupying 4 channels), x8 (occupying 8 channels), x16 (occupying 16 channels), etc.

[0025] Scheduling time slot interval: refers to the time interval between two consecutive scheduling of the same logical queue in time-division multiplexing scheduling, which is determined by the total number of physical channels in the system and the port link width mode.

[0026] This application's solution can be applied to high-speed data communication systems such as Ethernet switching chips, network processors, PCIe bus controllers, multi-queue network interface cards, and on-chip network routers. These systems require independent data queue management for a large number of concurrent service flows in a multi-port, multi-channel time-division multiplexing scheduling environment to ensure sequential data transmission and quality of service. For example, in multi-port switching chips, independent queues need to be set up for the mapping relationship between each group of source ports and destination ports to avoid head-of-queue congestion; in PCIe bus systems, different scheduling time slot intervals and resource requirements need to be adapted according to different link width modes such as x4 / x8 / x16. This invention, through a globally shared sub-queue resource pool and dynamic allocation mechanism, can effectively improve hardware resource utilization in the above scenarios and support concurrent scheduling of more logical queues.

[0027] refer to Figure 1 This application scenario illustrates one application of the queue management device provided in this application. The system in this scenario includes multiple source ports (Source Port 0-3), multiple destination ports (Destination Port 0-3), physical transmission channels, and a queue management module. The source ports are used to send data, and the destination ports are used to receive data. Each source port can communicate with multiple destination ports, and each destination port can also receive data from multiple source ports, forming a fully cross-connected architecture between the source and destination ports.

[0028] Each source port uses a corresponding number of physical transmission channels for data transmission based on the currently selected link width mode. x4 mode uses 4 physical channels, x8 mode uses 8 physical channels, and x16 mode uses all 16 physical channels. Different source ports share all physical transmission channels through time-division multiplexing. The scheduler allocates corresponding transmission time slots according to the operating mode of each source port, ensuring that data from each source port is transmitted alternately on the physical channels without conflict.

[0029] The queue management module is located on the destination port side, and all destination ports share the same queue management module. To avoid head-of-queue blocking between service flows from different source ports, and to ensure that each flow control and sorting mechanism is independent and effective, the queue management module needs to set up an independent logical queue for each pair of source and destination port mappings. For example, Figure 1 In a fully cross-connected architecture, there can be a total of 16 logical queues: source port 0 and destination port 0 correspond to logical queue S0D0, source port 0 and destination port 1 correspond to logical queue S0D1, and source port 3 and destination port 3 correspond to logical queue S3D3.

[0030] Since a logical queue corresponds to a set of source port to destination port mappings, the data in this logical queue can only be transmitted in the time slots allocated to the corresponding source and destination ports. Therefore, the time interval between two adjacent scheduling operations is fixed, determined by the total number of physical channels in the system and the link width mode selected by the port. Let the total number of physical channels in the system be N, the port link width be n (e.g., 4, 8, 16), and the duration of each time slot be Δt, then the scheduling time slot interval Td = (N / n) × Δt.

[0031] Each logical queue appears externally as an independent scheduling queue, but internally it is divided into multiple parallel sub-queues. Data in each logical queue needs to be processed in a first-in, first-out (FIFO) order. When data is enqueued, it is stored in different sub-queues in turn; when data is dequeued, it is retrieved from different sub-queues in turn. By setting up multiple parallel sub-queues and using a round-robin scheduling method, the read latency in hardware linked list access can be masked, ensuring continuous dequeueing without interruption, thereby improving scheduling throughput.

[0032] In a current queue management scheme, the system configures the same number of sub-queues for each logical queue. For example, with a total of 16 physical channels in a fully cross-connected architecture, a maximum of 16 logical queues can operate concurrently in x4 mode. To meet the timing requirements of the most demanding operating mode (such as x16 mode), each logical queue needs to be configured with 6 or more sub-queues. Therefore, with the fixed configuration, the system needs to pre-allocate a total of 16 × 6 = 96 sub-queues.

[0033] However, in real-world scenarios, not all logical queues operate simultaneously in x16 mode. In most cases, the system operates in x4 or x8 mode, which requires fewer sub-queues. With a fixed configuration, regardless of the actual operating mode of the port, each logical queue occupies 6 sub-queue resources, resulting in a large number of sub-queue resources remaining idle for extended periods, causing a significant waste of hardware resources.

[0034] Therefore, this embodiment provides a queue management device, including a globally shared sub-queue resource pool and a queue configuration module.

[0035] The subqueue resource pool contains multiple subqueues. The total number of subqueues in the subqueue resource pool is predetermined, for example, based on the maximum number of concurrent logical queues in the system and the number of subqueues required for a single logical queue.

[0036] For example, the system has a total of 16 physical channels, supporting x4, x8, and x16 modes. In x4 mode, the maximum number of concurrent logical queues is 16, with each logical queue requiring 2 sub-queues, for a total of 32 sub-queues. In x8 mode, the maximum number of concurrent logical queues is 4, with each logical queue requiring 4 sub-queues, for a total of 16 sub-queues. In x16 mode, the maximum number of concurrent logical queues is 1, with each logical queue requiring 8 sub-queues, for a total of 8 sub-queues. Taking the maximum value of the requirements for each mode, the total number of sub-queues in the sub-queue resource pool can be configured to 32. The purpose of this configuration is that the sub-queue resource pool can meet the demand in any working mode, and in non-worst-case scenarios, idle sub-queues can be reclaimed and allocated to other logical queues, achieving dynamic resource reuse. Compared to the traditional fixed configuration scheme that requires 96 sub-queues, this embodiment can save 64 sub-queue resources, significantly improving hardware resource utilization. When the total number of physical channels in the system is greater, the resource saving effect of this embodiment is even more significant.

[0037] The queue configuration module is responsible for dynamically allocating subqueues from the subqueue resource pool for each logical queue. It should be noted that there is no fixed binding relationship between the allocated subqueues and the logical queues; that is, the same subqueue can be allocated to different logical queues at different times.

[0038] For example, when the system needs to create a new logical queue, the queue configuration module selects several sub-queues from the sub-queue resource pool and allocates them to the logical queue; when the logical queue is no longer in use, the queue configuration module reclaims the allocated sub-queues back to the sub-queue resource pool for use by other logical queues.

[0039] Each logical queue corresponds to a set of ordered data. For example, in a multi-port switching chip, a logical queue can correspond to a set of service flows from the source port to the destination port, and the data in this service flow needs to be processed in a first-in, first-out (FIFO) order.

[0040] For any given logical queue, several sub-queues allocated to that logical queue coordinate to manage the access to ordered data in that logical queue in a round-robin manner.

[0041] Specifically, when data needs to be enqueued, it is distributed to various sub-queues sequentially according to the polling order, and each sub-queue stores the corresponding data. For example, if the logical queue has two sub-queues, A and B, the first data is stored in sub-queue A, the second in sub-queue B, the third in sub-queue A, the fourth in sub-queue B, and so on. When data needs to be dequeued, it is retrieved from each sub-queue sequentially according to the same polling order. For example, the first data is retrieved from sub-queue A, the second from sub-queue B, the third from sub-queue A, the fourth from sub-queue B, and so on. In this way, although the data is distributed and stored in different sub-queues, the overall order of the data is ensured to be consistent with the enqueue order through polling for enqueueing and dequeueing.

[0042] Based on this, the number of sub-queues allocated to the logical queue by the queue configuration module needs to meet a constraint: the polling time interval is not less than the hardware read latency.

[0043] The polling interval refers to the time interval between two consecutive accesses of the same sub-queue. Taking a logical queue with two sub-queues (sub-queue A and sub-queue B) as an example, the scheduler allocates transmission time slots to each port using time-division multiplexing. The logical queue is scheduled once every scheduling time slot interval, accessing one sub-queue each time. After sub-queue A is accessed at a certain time, it will be accessed again after polling sub-queue B. Therefore, the polling interval Tp is equal to the scheduling time slot interval Td multiplied by the number of sub-queues m.

[0044] Hardware read latency refers to the delay required from the time the current data is retrieved from a subqueue until the next data is ready. For example, in a hardware linked list implementation, hardware read latency includes the delay of reading the successor pointer from the linked list memory and the delay of updating the head pointer. If the polling interval is less than the hardware read latency, when a subqueue is accessed by a dequeue operation, and then accessed again before the head pointer has been updated, incorrect data will be read. By configuring a sufficient number of subqueues so that the polling interval is not less than the hardware read latency, it can be guaranteed that the head pointer of the subqueue has been updated (i.e., the next data is ready) each time data is dequeued, thus achieving continuous and conflict-free dequeue scheduling.

[0045] Based on the above constraints and relevant system parameters, the number of sub-queues to be allocated to the logical queue can be determined: m ≥ delay / Td; m is the number of sub-queues to be allocated, m is a positive integer, delay is the hardware read delay, and Td is the scheduling time slot interval.

[0046] For example, assuming the hardware read latency is 6 clock cycles and the scheduling time slot interval is 4 clock cycles, m ≥ 6 / 4 = 1.5, and m rounded up to 2, therefore at least 2 sub-queues need to be configured. With 2 sub-queues, the polling time interval is 4 × 2 = 8 clock cycles, which is greater than the hardware read latency of 6 clock cycles, satisfying the constraint condition.

[0047] The queue management device provided in this embodiment avoids the resource waste problem caused by reserving a fixed number of sub-queues for each logical queue in the traditional fixed allocation scheme by setting up a globally shared sub-queue resource pool and dynamically allocating sub-queues according to the actual needs of logical queues. When a logical queue is no longer needed, the sub-queue resources it occupies can be reclaimed and reallocated to other logical queues, thereby supporting more concurrent logical queues with the same total amount of hardware resources.

[0048] In this embodiment, the queue management device dynamically allocates sub-queues by constraining the number of allocated sub-queues to ensure that the polling time interval is not less than the hardware read latency. This guarantees that the next data in the current sub-queue is ready for each dequeue operation, thereby avoiding data read errors and dequeue idle periods caused by hardware read latency. Furthermore, even with a fixed hardware read latency, the system can achieve continuous, conflict-free dequeue scheduling, improving scheduling throughput.

[0049] This embodiment achieves the above effects through a sub-queue resource pool and a round-robin scheduling mechanism. It does not require complex resource management algorithms or additional hardware support, making it simple to implement, with low hardware overhead, and easy to integrate into existing switching chips, network processors, and other systems.

[0050] Based on the above embodiments, this paper further explains how to determine the number of sub-queues according to different link width modes.

[0051] Different link width modes have different scheduling time slot intervals. Therefore, it is necessary to configure a corresponding number of sub-queues for the logical queue according to the link width mode currently used by the port where the logical queue is located, so as to ensure that the polling time interval under different link width modes meets the constraint that it is not less than the hardware read latency.

[0052] According to the definition in the glossary, the scheduling time slot interval Td = (N / n) × Δt, where N is the total number of physical channels in the system, n is the link width (4, 8, or 16), and Δt is the duration of each time slot. Combining the constraints in the aforementioned embodiments, the polling time interval Tp = Td × m must satisfy Tp ≥ delay, i.e., m ≥ delay / Td, where m is the number of sub-queues allocated to the logical queue, and delay is the hardware read latency.

[0053] Therefore, the number of sub-queues *m* allocated to the logical queue is directly proportional to the hardware read latency *delay* and inversely proportional to the scheduling time slot interval *Td*. When the hardware read latency is fixed, the smaller the scheduling time slot interval (i.e., the larger the port link width), the more sub-queues need to be allocated; conversely, the larger the scheduling time slot interval (i.e., the smaller the port link width), the fewer sub-queues need to be allocated.

[0054] This embodiment uses a system with a total number of physical channels N=16, a time slot duration Δt=1 clock cycle, and a hardware read latency delay=6 clock cycles as an example. It should be noted that these values ​​are merely examples, and those skilled in the art can adjust them according to actual system parameters; they do not constitute a limitation on the scope of protection of this application.

[0055] Based on the above parameters, the scheduling slot interval and the theoretical minimum number of sub-queues are calculated as follows for each link width mode: x4 mode: Td = (16 / 4) × 1 = 4 clock cycles, m ≥ 6 / 4 = 1.5, m is rounded up to 2; x8 mode: Td=(16 / 8)×1=2 clock cycles, m≥6 / 2=3, m is rounded up to 3; x16 mode: Td=(16 / 16)×1=1 clock cycle, m≥6 / 1=6, m is rounded up to 6.

[0056] In actual hardware implementations, the number of sub-queues is typically configured as a power of 2 (e.g., 2, 4, 8) to facilitate hardware addressing and scheduling. Therefore, the fixed number of sub-queues pre-configured for each link width mode in this embodiment is as follows: x4 mode: Configure 2 sub-queues (to meet the theoretical minimum value); x8 mode: Configure 4 sub-queues (theoretically minimum value is 3, upward alignment is the nearest power of 2, 4); x16 mode: Configure 8 sub-queues (theoretical minimum is 6, and the upward alignment is the nearest power of 2, 8).

[0057] Under the above configuration, the polling time interval for each mode is calculated as follows: x4 mode: Tp = 4 × 2 = 8 clock cycles, which is greater than the hardware read latency of 6 clock cycles; x8 mode: Tp = 2 × 4 = 8 clock cycles, which is greater than the hardware read latency of 6 clock cycles; x16 mode: Tp = 1 × 8 = 8 clock cycles, which is greater than the hardware read latency of 6 clock cycles.

[0058] The polling time interval in each mode reaches 8 clock cycles, which satisfies the constraint that it is not less than the hardware read latency.

[0059] In practice, the number of sub-queues can be determined in the following two ways: (1) Real-time calculation method When the port link width mode changes, the queue configuration module calculates the minimum number of sub-queues required in real time based on the current scheduling time slot interval and hardware read latency, and then allocates the corresponding number of sub-queues to the logical queue from the sub-queue resource pool. This approach is highly flexible and can adapt to dynamically changing system parameters.

[0060] (2) Pre-configuration method Since the total number of physical channels, hardware read latency, and scheduling time slot intervals corresponding to each link width mode are usually determined during system design, the number of sub-queues for each link width mode can be pre-configured at system startup. When the port operating mode switches, the queue configuration module directly allocates sub-queues to the logical queues according to the pre-configured fixed values. For example: x4 mode: configure 2 sub-queues; x8 mode: configure 4 sub-queues; x16 mode: configure 8 sub-queues.

[0061] Pre-configuration is simple to implement, requires no real-time calculation, and its behavior is predictable.

[0062] Regardless of whether real-time computing or pre-configuration is used, the final number of sub-queues must satisfy the constraint that m ≥ delay / Td to ensure that the polling time interval is not less than the hardware read latency.

[0063] In some optional embodiments, the destination end is configured with a globally shared data cache for storing data from each logical queue. This data cache is independent of the queue management module. Each piece of data is assigned a unique cache address when it is stored in the data cache. This cache address serves as the identifier of the data's storage location within the data cache.

[0064] Each subqueue uses a linked list structure to maintain the order of its internal data. Each subqueue has independent head and tail pointers. The head pointer indicates the cache address of the data currently to be retrieved in the subqueue. The tail pointer indicates the cache address of the last stored data in the subqueue.

[0065] This embodiment also includes a globally shared linked list memory. This linked list memory stores the link relationships between data in each sub-queue. The access address of the linked list memory corresponds one-to-one with the cache address of the data cache. The cache address of the message in the data cache is used as the access address of the linked list memory, which stores the next pointer of the corresponding data, thus achieving a precise match between the linked list structure and the data storage location. The queue management module accesses the linked list memory using the cache address pointed to by the head pointer as an index to read the cache address corresponding to the next piece of data to be retrieved in the corresponding sub-queue. No additional address calculation or mapping logic is required, resulting in fast access speed and simple hardware implementation.

[0066] For example, by polling through a subqueue, the cache addresses of the three pieces of data entering the subqueue are 0x1000, 0x2000, and 0x3000, respectively, in the order 0x1000→0x2000→0x3000. In the linked list memory, the memory cell at access address 0x1000 stores 0x2000, the memory cell at access address 0x2000 stores 0x3000, and the memory cell at access address 0x3000 can store an end flag (indicating the tail of the queue).

[0067] The linked list memory is globally shared, with all sub-queues sharing the same memory block. Data in different sub-queues is distinguished by its cache address as an index, and the linked lists of each sub-queue are naturally isolated in the linked list memory through address space, preventing conflicts between them. This design inherently supports the round-robin scheduling mechanism of this application: the head pointer of each sub-queue is updated independently without interference; the linked lists of each sub-queue are naturally isolated in address space, and access does not conflict with each other.

[0068] All sub-queues share the same linked list memory and the same data cache, eliminating the need for separate memory configuration for each sub-queue. Compared to the approach of configuring memory independently for each sub-queue, this embodiment significantly reduces storage resource overhead, chip area, and cost.

[0069] The following example illustrates the enqueue and dequeue process. Assume the system has a total of 16 physical channels, a scheduling time slot interval of 4 clock cycles in x4 mode, and a hardware read latency of 6 clock cycles. Assume a logical queue is configured with 2 sub-queues (sub-queue A and sub-queue B). The polling interval = scheduling time slot interval × number of sub-queues = 4 × 2 = 8 clock cycles, which is greater than the hardware read latency of 6 clock cycles, thus satisfying the constraint.

[0070] The data to be enqueued are data1, data2, data3, data4, data5, and data6 in sequence, and their cache addresses in the data cache are addr1, addr2, addr3, addr4, addr5, and addr6 in sequence.

[0071] The queue management module uses a polling method to alternately allocate the cache addresses of each data item in the logical queue to sub-queue A and sub-queue B: Data 1 (addr1) is assigned to sub-queue A. Data 2 (addr2) is assigned to sub-queue B. Data 3 (addr3) is assigned to sub-queue A. Data 4 (addr4) is assigned to sub-queue B. Data 5 (addr5) is assigned to sub-queue A. Data 6 (addr6) is assigned to sub-queue B. The enqueue process for subqueue A: When the first allocated data addr1 is received, subqueue A is empty. Addr1 is stored in the head pointer and tail pointer of subqueue A (both pointing to addr1). When the second allocated data addr3 is received, subqueue A is not empty. Addr3 is stored in the tail pointer of subqueue A (the tail pointer is updated to addr3). At the same time, addr3 is written into the memory unit with addr1 as the access address in the linked list memory. When the third allocated data, addr5, is received, addr5 is stored in the tail pointer of sub-queue A (the tail pointer is updated to addr5). At the same time, addr5 is written into the memory cell with addr3 as the access address in the linked list memory.

[0072] At this point, the cache addresses stored in sub-queue A are in the order addr1→addr3→addr5, with the head pointer pointing to addr1 and the tail pointer pointing to addr5.

[0073] The enqueueing process for subqueue B is similar. The final cache address order stored in subqueue B is addr2→addr4→addr6, with the head pointer pointing to addr2 and the tail pointer pointing to addr6.

[0074] When data needs to be dequeued, the queue management module retrieves data from sub-queue A and sub-queue B in a round-robin order: First dequeue: Retrieve data from subqueue A. Read the head pointer of subqueue A, obtain addr1, read data 1 from the data buffer and output it. At the same time, read the linked list memory using addr1 as the access address, obtain addr3, and update the head pointer of subqueue A with addr3.

[0075] Second dequeue: Retrieve data from subqueue B. Read the head pointer of subqueue B, obtain addr2, read data 2 from the data buffer and output it. At the same time, read the linked list memory using addr2 as the access address, obtain addr4, and update the head pointer of subqueue B with addr4.

[0076] Third dequeue: Data is retrieved from subqueue A. At this point, the head pointer of subqueue A has been updated to addr3. Data 3 is read and output. Simultaneously, the linked list memory is read using addr3 as the access address to obtain addr5, and the head pointer of subqueue A is updated using addr5.

[0077] Fourth dequeue: Data is retrieved from subqueue B. At this point, the head pointer of subqueue B has been updated to addr4. Data 4 is read and output. Simultaneously, the linked list memory is read using addr4 as the access address to obtain addr6, and the head pointer of subqueue B is updated using addr6.

[0078] Fifth dequeue: Take data from subqueue A. At this point, the head pointer of subqueue A has been updated to addr5. Read data 5 and output it. Now, the head pointer (addr5) of subqueue A equals the tail pointer (addr5), indicating that subqueue A is empty.

[0079] Sixth dequeue: Take data from subqueue B. At this point, the head pointer of subqueue B has been updated to addr6, read data 6 and output it. Now the head pointer (addr6) of subqueue B equals the tail pointer (addr6), indicating that subqueue B is empty.

[0080] In the example above, two sub-chains are formed by polling and enqueuing (sub-queue A stores odd-numbered data, and sub-queue B stores even-numbered data). Data is retrieved alternately from the two sub-chains during dequeueing. After the first dequeue, sub-queue A begins reading address addr3. After a hardware read delay of 6 clock cycles, addr3 is ready. Sub-queue A will not be accessed again until 8 clock cycles later, by which time the head pointer has been updated, thus preventing read errors or data conflicts. The data output order is 1, 2, 3, 4, 5, 6, consistent with the enqueue order, ensuring order preservation.

[0081] In one optional implementation, each sub-queue also maintains a depth counter to record the number of data items currently stored in the sub-queue. During an enqueue operation, the depth counter increments by 1; during a dequeue operation, the depth counter decrements by 1. A depth counter of 0 indicates that the sub-queue is empty, and a depth counter of 1 indicates that the sub-queue contains only one data item (in which case the head pointer equals the tail pointer).

[0082] When the depth counter is 1, after the dequeue operation reads the unique data, it directly clears the head and tail pointers (or sets them to invalid values), without needing to access the linked list memory to read the successor address (i.e., the cache address of the next data to be retrieved), because this data has no successor. When the depth counter is greater than 1, the dequeue operation needs to read the linked list memory to obtain the successor address and update the head pointer.

[0083] This embodiment provides a queue management method, applicable to the queue management device of any of the foregoing embodiments. It should be noted that the terminology definitions in this embodiment are consistent with those in the foregoing device embodiments, and will not be repeated here.

[0084] The queue management method in this embodiment includes the following steps S1 and S2: S1: Dynamically allocate sub-queues for the logical queue.

[0085] Several subqueues are dynamically allocated to the logical queue from a globally shared subqueue resource pool. There is no fixed binding relationship between the allocated subqueues and the logical queue. When a logical queue is no longer needed, the allocated subqueues are returned to the subqueue resource pool for use by other logical queues.

[0086] The number of sub-queues allocated to the logical queue must meet the constraint that the polling time interval is not less than the hardware read latency.

[0087] In one alternative implementation, the number of sub-queues allocated to the logical queue can be determined based on the link width mode currently used by the port where the logical queue is located. Different link width modes have different scheduling time slot intervals, thus requiring the configuration of different numbers of sub-queues.

[0088] For example, suppose the total number of physical channels in the system is N=16, the duration of each timeslot is Δt=1 clock cycle, and the hardware read latency is delay=6 clock cycles. Then: In x4 mode, the scheduling time slot interval Td = 4 clock cycles, and at least 2 sub-queues need to be configured; In x8 mode, the scheduling time slot interval Td = 2 clock cycles, and at least 3 sub-queues need to be configured; In x16 mode, the scheduling time slot interval Td = 1 clock cycle, and at least 6 sub-queues need to be configured.

[0089] In practice, the number of sub-queues can be calculated in real time (based on the current scheduling time slot interval and hardware read latency) or pre-configured (a fixed value is pre-configured for each link width mode, such as x4 with 2, x8 with 4, and x16 with 8).

[0090] In one alternative implementation, the total number of subqueues in the subqueue resource pool is determined based on the system's maximum concurrent logical queue count and the number of subqueues required for a single logical queue. For example, the maximum value of (number of concurrent queues × number of subqueues per queue) for each working mode is used for configuration.

[0091] Step S2: Collaboratively manage data access using a polling method.

[0092] The system controls several sub-queues allocated to the logical queue to collaboratively manage the access to ordered data within the logical queue using a round-robin approach. Specifically, during enqueueing, data from the ordered sequence is alternately distributed to different sub-queues for storage; during dequeueing, data is retrieved from each sub-queue in a round-robin fashion. By using round-robin enqueueing and dequeueing, the overall order of the data is ensured to match the enqueueing order.

[0093] In one alternative implementation, each sub-queue uses a linked list structure to maintain the order of its internal data. Each sub-queue has independent head and tail pointers. The head pointer indicates the cache address of the data currently to be retrieved in the sub-queue, and the tail pointer indicates the cache address of the last stored data in the sub-queue.

[0094] This embodiment also includes a globally shared linked list memory. This linked list memory stores the links between data in each sub-queue. The access address of the linked list memory corresponds one-to-one with the cache address of the data cache. The cache address of the data in the data cache is used as the access address of the linked list memory to store the successor pointer of the corresponding data, thereby achieving a precise match between the linked list structure and the data storage location. The queue management module accesses the linked list memory using the cache address pointed to by the head pointer as an index to read the cache address corresponding to the next piece of data to be retrieved in the corresponding sub-queue.

[0095] When an enqueue request is received, the enqueue request contains the logical queue identifier corresponding to the data to be enqueued and the cache address of the data. The enqueue processing flow is as follows: Based on the logical queue identifier, determine several sub-queues to be allocated to the logical queue, and select one sub-queue in a round-robin order; If the subqueue is empty, store the cache address into the head and tail pointers of the subqueue; If the subqueue is not empty, store the cache address into the tail pointer of the subqueue (update the tail pointer to the new address), and at the same time, write the cache address of the newly enqueued data into the storage unit in the linked list memory that uses the cache address of the current tail data as the access address.

[0096] When a dequeue request is received, the dequeue request contains the logical queue identifier corresponding to the data to be dequeued. The dequeue processing flow is as follows: Based on the logical queue identifier, determine several sub-queues to be allocated to the logical queue, and select one sub-queue in a round-robin order; Read the head pointer of the sub-queue to obtain the cache address of the data to be retrieved; Read data from the data cache based on the cache address and output it; Use the cache address as the access address to read the linked list memory and obtain the cache address of the next piece of data to be retrieved. After the hardware read delay, the head pointer of the sub-queue is updated with the cache address of the next data to be retrieved; If the updated head pointer equals the tail pointer, then the subqueue becomes empty.

[0097] The queue management device provided in this application embodiment adopts the same inventive concept as the above-described queue management method and can achieve the same beneficial effects, which will not be repeated here.

[0098] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the description of the above embodiments is only for the purpose of helping to understand the methods of the embodiments of this application and should not be construed as a limitation on the embodiments of this application. Any changes or substitutions that can be easily conceived by those skilled in the art should be covered within the protection scope of the embodiments of this application.

Claims

1. A queue management device, characterized in that, include: A globally shared sub-queue resource pool, wherein the sub-queue resource pool contains multiple sub-queues; The queue configuration module is used to dynamically allocate several sub-queues to the logical queue from the sub-queue resource pool. The allocated sub-queues do not form a fixed binding relationship with the logical queue, and the number of allocated sub-queues ensures that the polling time interval is not less than the hardware read latency. The polling time interval is the time interval between two consecutive accesses to the same sub-queue, and the hardware read latency is the delay required for the sub-queue to go from the current data being retrieved to the next data being ready. The logical queue is a queue corresponding to a set of ordered data. Several sub-queues allocated to the logical queue coordinate the storage and retrieval of ordered data in the logical queue in a round-robin manner.

2. The apparatus according to claim 1, characterized in that, The queue configuration module is specifically used for: The number of sub-queues allocated to the logical queue is determined based on the link width mode currently used by the port where the logical queue is located.

3. The apparatus according to claim 2, characterized in that, Each link width mode corresponds to a pre-configured fixed number of sub-queues. The number of fixed sub-queues is determined according to the transmission characteristics of the corresponding link width mode, and ensures that the polling time interval in the link width mode is not less than the hardware read latency.

4. The apparatus according to any one of claims 1 to 3, characterized in that, The total number of subqueues in the subqueue resource pool is determined based on the maximum number of concurrent logical queues in the system and the number of subqueues required for a single logical queue.

5. The apparatus according to any one of claims 1 to 3, characterized in that, The method of collaboratively managing the access to ordered data in the logical queue using a polling approach specifically includes: When enqueuing, each piece of data in the ordered data is alternately distributed to the several sub-queues for storage; When dequeuing, data is retrieved from the aforementioned sub-queues in a round-robin fashion.

6. The apparatus according to claim 5, characterized in that, Each subqueue has an independent head pointer and a tail pointer. The head pointer is used to indicate the cache address of the data to be retrieved in the subqueue, and the tail pointer is used to indicate the cache address of the last stored data in the subqueue. The device also includes a globally shared linked list memory for storing the link relationships between data in each sub-queue. The linked list memory is accessed using the cache address pointed to by the head pointer as an index to read the cache address corresponding to the next data to be retrieved in the corresponding sub-queue.

7. A queue management method, applied to the queue management device according to any one of claims 1 to 6, characterized in that, The method includes: Several sub-queues are dynamically allocated to the logical queue from a globally shared sub-queue resource pool. The allocated sub-queues do not form a fixed binding relationship with the logical queue, and the number of allocated sub-queues ensures that the polling time interval is not less than the hardware read latency. The polling time interval is the time interval between two consecutive accesses to the same sub-queue, and the hardware read latency is the delay required for the sub-queue to go from the current data being retrieved to the next data being ready. The system controls several sub-queues allocated to the logical queue to collaboratively manage the access to ordered data in the logical queue in a round-robin manner.

8. The method according to claim 7, characterized in that, The method further includes: The number of sub-queues allocated to the logical queue is determined based on the link width mode currently used by the port where the logical queue is located.

9. The method according to claim 7 or 8, characterized in that, The total number of subqueues in the subqueue resource pool is determined based on the maximum number of concurrent logical queues in the system and the number of subqueues required for a single logical queue.

10. The method according to claim 7 or 8, characterized in that, The method of collaboratively managing the access to ordered data in the logical queue using a polling approach specifically includes: When enqueuing, the data in the ordered data are alternately distributed to the several sub-queues for storage; When dequeuing, data is retrieved from the aforementioned sub-queues in a round-robin fashion.

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