Encoder and associated encoding method
By employing multi-core circuitry in the encoder to process superblocks in parallel and update the CDF table, the problem of bit rate control in low-latency applications of the encoder is solved, achieving efficient encoding process and bit rate control, and improving the overall performance of the encoder.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2025-03-13
- Publication Date
- 2026-07-17
AI Technical Summary
In existing technologies, encoders struggle to effectively control fixed or variable bit rates in low-latency applications. In particular, the use and updating of the CDF table presents problems in multi-core parallel processing, and the latency between the quantization parameter determination module and the CABAC encoding module leads to low encoding efficiency.
Multiple core circuits are used to process multiple superblocks in parallel. By updating the CDF table during the encoding process of each superblock and using the encoding result of the previous superblock as a reference, the update delay problem of the CDF table is solved. At the same time, preset information is used as a temporary reference for quantization parameters to ensure the smooth progress of the encoding process.
It enables effective bitrate control in low-latency applications, improves encoding efficiency and accelerates the process, reduces the impact of bitrate control, and enhances the overall performance of the encoder.
Smart Images
Figure CN122420531A_ABST