A high-frequency embedded component (HDI) circuit board manufacturing method and system

Abstract

The embodiment of the present application provides a kind of high-frequency embedded component HDI circuit board manufacturing method and system, belong to circuit board manufacturing technical field.The method comprises: after forming microcircuit in line etching, the measured parameter after etching of buried resistance setting area and buried capacity setting area is obtained, and the high-frequency drift prediction value of embedded area is determined;Embedded pre-compensation parameters of buried resistance component and buried capacity component are generated, and buried resistance component and buried capacity component are embedded into corresponding board layer according to embedded pre-compensation parameters, to form embedded passive component layer;Laminating linkage control is carried out to embedded passive component layer, to obtain laminated high-frequency interconnection board body;Adjust impedance compensation parameters and resistance soldering boundary parameters, and complete resistance soldering based on adjusted impedance compensation parameters and resistance soldering boundary parameters, to obtain high-frequency embedded component HDI circuit board.The present application scheme realizes impedance stability and low-loss control in the manufacturing process of high-frequency embedded component HDI circuit board.

Description

Technical Field

[0001] This invention relates to the field of circuit board manufacturing technology, and specifically to a method and system for manufacturing a high-frequency embedded component HDI circuit board. Background Technology

[0002] As 5G / 6G communication terminals evolve towards millimeter-wave bands, high integration, and miniaturization, RF front-end modules place higher demands on the line accuracy, dielectric loss, and impedance continuity of HDI (High Density Interconnect) circuit boards. Traditional HDI circuit boards typically mount passive components such as resistors and capacitors on the board surface. Component pads, vias, and surface interconnects introduce additional parasitic inductance and capacitance. In low-frequency applications, these effects can be absorbed by conventional wiring margins, but in high-frequency transmission scenarios, even short interconnect abrupt changes can lead to increased insertion loss, deteriorated return loss, and local impedance discontinuities.

[0003] To reduce the parasitic effects of surface-mount passive components, the industry has gradually adopted embedded passive component processes such as embedded resistors and capacitors, integrating some passive components within the PCB (Printed Circuit Board) to shorten signal paths and free up surface wiring space. However, in actual manufacturing, embedded passive components do not simply require simple embedding to achieve stable operation. After etching, fine lines exhibit deviations in line width, line spacing, residual copper thickness, and termination copper width. After embedding, embedded resistors and capacitors undergo processes such as lamination, drilling, electroplating, solder mask coating, and curing. Resin flow, dielectric thickness variations, and localized stress concentrations during lamination, as well as changes in the dielectric environment after solder mask curing, all contribute to continued high-frequency impedance drift in the embedded area.

[0004] Current processes focus more on controlling individual performance indicators, such as etching accuracy, lamination thickness, or finished product impedance testing. While this approach is sufficient for general high-density interconnect printed circuit boards, it is prone to issues with 5G / 6G high-frequency HDI boards. These issues often result in acceptable etching and embedding phases, but the final high-frequency performance deviates from design values. Particularly near the buried resistor termination area and buried capacitor electrode edges, local parasitic parameters, solder mask boundaries, and lamination dielectric variations overlap, often revealing problems only during final product testing. This leads to significant rework difficulties and poor batch stability. Therefore, there is an urgent need for a high-frequency embedded component HDI board manufacturing method that can identify high-frequency drift trends in the embedded area immediately after etching and integrate embedded compensation, lamination control, and solder mask compensation. Summary of the Invention

[0005] The purpose of this invention is to provide a method and system for manufacturing high-frequency embedded component HDI circuit boards, so as to at least solve the problem that impedance drift after embedded components are embedded in high-frequency HDI circuit boards is difficult to compensate in conjunction with the manufacturing process.

[0006] To achieve the above objectives, the first aspect of the present invention provides a method for manufacturing a high-frequency embedded component HDI circuit board. The method includes: after etching to form micro-circuits, obtaining post-etching measured parameters of the embedded resistor setting area and the embedded capacitor setting area, and determining the high-frequency drift prediction value of the embedded area based on the post-etching measured parameters; generating embedding pre-compensation parameters for the embedded resistor and embedded capacitor based on the high-frequency drift prediction value of the embedded area, and embedding the embedded resistor and embedded capacitor into the corresponding board layer according to the embedding pre-compensation parameters to form an embedded passive component layer; performing lamination linkage control on the embedded passive component layer based on the high-frequency drift prediction value of the embedded area to obtain a laminated high-frequency interconnect board; adjusting the solder mask boundary parameters and impedance compensation parameters based on the impedance retest results of the high-frequency interconnect board, and completing the solder mask treatment based on the adjusted solder mask boundary parameters and impedance compensation parameters to obtain a high-frequency embedded component HDI circuit board.

[0007] Optionally, the measured parameters of the buried resistor setting area and the buried capacitor setting area after etching are obtained, including: after the line is etched to form a fine line, the buried resistor setting area and the buried capacitor setting area are determined based on the designed embedding position of the buried resistor element and the buried capacitor element; the measured line width, measured line spacing, residual copper thickness, line edge roughness and termination residual copper width are collected in the buried resistor setting area and the buried capacitor setting area respectively; the measured line width, the measured line spacing, the residual copper thickness, the line edge roughness and the termination residual copper width are used as the measured parameters after etching.

[0008] Optionally, determining the predicted high-frequency drift value of the embedded area based on the measured parameters after etching includes: comparing the measured parameters after etching with the corresponding design parameters to obtain the line etching deviation and the termination etching deviation; determining the micro-line impedance offset based on the line etching deviation, and determining the termination parasitic offset of the embedded resistor and embedded capacitor based on the termination etching deviation; determining the predicted high-frequency drift value of the embedded area corresponding to the embedded resistor setting area and the embedded capacitor setting area based on the micro-line impedance offset and the termination parasitic offset; wherein, the predicted high-frequency drift value of the embedded area is used to characterize the predicted influence of the embedded resistor and embedded capacitor on the high-frequency transmission impedance after being embedded in the corresponding board layer.

[0009] Optionally, based on the predicted high-frequency drift value of the embedded area, embedding pre-compensation parameters for the embedded resistor and embedded capacitor are generated, including: comparing the predicted high-frequency drift value of the embedded area with a preset high-frequency drift allowable value to determine the compensation direction for the corresponding embedded resistor setting area and embedded capacitor setting area; adjusting the termination overlap length of the embedded resistor and the electrode edge clearance distance of the embedded capacitor based on the compensation direction to obtain the component termination compensation parameters; adjusting the embedding offset of the embedded resistor and embedded capacitor relative to the micro-circuit based on the compensation direction to obtain the component position compensation parameters; and using the component termination compensation parameters and the component position compensation parameters as embedding pre-compensation parameters.

[0010] Optionally, embedding the buried resistor and buried capacitor elements into the corresponding plate layer according to the embedded pre-compensation parameters to form an embedded passive component layer includes: determining the termination overlap position of the buried resistor element in the buried resistor setting area and the electrode edge position of the buried capacitor element in the buried capacitor setting area based on the embedded pre-compensation parameters; forming the buried resistor element in the corresponding plate layer according to the termination overlap position and connecting the buried resistor element to the micro-circuit; forming the buried capacitor element in the corresponding plate layer according to the electrode edge position and connecting the buried capacitor element to the micro-circuit; and performing a curing process on the corresponding plate layer in which the buried resistor element and the buried capacitor element are formed to obtain the embedded passive component layer.

[0011] Optionally, based on the predicted high-frequency drift value of the embedded area, lamination linkage control is performed on the embedded passive component layer to obtain a laminated high-frequency interconnect board. This includes: comparing the predicted high-frequency drift value of the embedded area with a preset lamination grading threshold to determine the lamination control level of the embedded passive component layer; calling the lamination process parameters corresponding to the lamination control level from a preset lamination parameter mapping table, wherein the lamination process parameters include heating rate, pre-pressure, main pressure, and holding time; laminating the embedded passive component layer with adjacent board layers according to the lamination process parameters; and performing alignment and thickness detection on the laminated board after lamination to obtain the laminated high-frequency interconnect board.

[0012] Optionally, based on the impedance retest results of the high-frequency interconnect board, the solder mask boundary parameters and impedance compensation parameters are adjusted, including: performing impedance retests on the RF traces in the corresponding buried resistor and buried capacitor areas of the high-frequency interconnect board to obtain impedance retest values; determining the solder mask compensation direction based on the deviation between the impedance retest values ​​and the target impedance values; adjusting the spacing between the RF traces and the solder mask coverage boundary based on the solder mask compensation direction to obtain solder mask boundary parameters; and adjusting the local compensation linewidth of the RF traces based on the solder mask compensation direction to obtain impedance compensation parameters.

[0013] Optionally, adjusting the spacing between the RF trace and the solder mask coverage boundary based on the solder mask compensation direction to obtain solder mask boundary parameters includes: determining an edge coupling segment in the RF trace adjacent to the termination area of ​​the buried resistor element and the electrode edge of the buried capacitor element based on the solder mask compensation direction; obtaining the solder mask curing shrinkage amount corresponding to the edge coupling segment, and determining the solder mask boundary retraction amount based on the solder mask curing shrinkage amount; when the solder mask compensation direction indicates that the solder mask medium needs to be away from the RF trace, moving the solder mask coverage boundary away from the edge coupling segment by the solder mask boundary retraction amount; when the solder mask compensation direction indicates that the solder mask medium needs to be close to the RF trace, moving the solder mask coverage boundary away from the edge coupling segment by the solder mask boundary retraction amount; and using the spacing between the moved solder mask coverage boundary and the edge coupling segment as the solder mask boundary parameter.

[0014] Optionally, the solder mask process is completed based on the adjusted solder mask boundary parameters and impedance compensation parameters to obtain a high-frequency embedded component HDI circuit board, including: forming a local compensation circuit pattern at the corresponding position of the RF trace to be solder masked on the surface layer of the high-frequency interconnect board according to the impedance compensation parameters; forming a solder mask window pattern on the high-frequency interconnect board to avoid the local compensation circuit pattern according to the solder mask boundary parameters; applying solder mask coating and curing to the high-frequency interconnect board based on the solder mask window pattern to form a solder mask layer; and performing high-frequency performance testing on the high-frequency interconnect board with the solder mask layer formed, and obtaining the high-frequency embedded component HDI circuit board after passing the test.

[0015] A second aspect of the present invention provides a high-frequency embedded component HDI circuit board manufacturing system, the system comprising: an acquisition unit, configured to acquire post-etching measured parameters of the embedded resistor setting area and the embedded capacitor setting area after the line etching forms micro-line, and determine the high-frequency drift prediction value of the embedded area based on the post-etching measured parameters; a compensation unit, configured to generate embedding pre-compensation parameters for the embedded resistor and embedded capacitor based on the high-frequency drift prediction value of the embedded area, and embed the embedded resistor and embedded capacitor into the corresponding board layer according to the embedding pre-compensation parameters to form an embedded passive component layer; a lamination unit, configured to perform lamination linkage control on the embedded passive component layer based on the high-frequency drift prediction value of the embedded area to obtain a laminated high-frequency interconnect board; and a solder mask unit, configured to adjust the solder mask boundary parameters and impedance compensation parameters based on the impedance retest results of the high-frequency interconnect board, and complete the solder mask processing based on the adjusted solder mask boundary parameters and impedance compensation parameters to obtain a high-frequency embedded component HDI circuit board.

[0016] Through the above technical solution, this invention obtains the measured deviation of the buried resistor and buried capacitor areas immediately after circuit etching, and predicts the high-frequency impedance drift that may occur after the embedded components are installed, thus advancing the compensation action before component embedding and lamination. The embedding state of the buried resistor and buried capacitor components is corrected by embedding pre-compensation parameters, and the lamination process is then controlled in conjunction with the high-frequency drift prediction value of the same embedded area, reducing secondary impedance shifts caused by lamination. After lamination, the solder mask boundary parameters and impedance compensation parameters are further adjusted based on impedance retest results, incorporating solder mask processing into the high-frequency performance compensation chain, thereby reducing impedance mismatch and transmission loss fluctuations in the finished product stage and improving the manufacturing consistency of high-frequency embedded component HDI circuit boards.

[0017] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the steps of a high-frequency embedded component HDI circuit board manufacturing method provided by one embodiment of the present invention; Figure 2 This is a logic block diagram of the manufacturing process of a high-frequency embedded component HDI circuit board provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of key workstations in the manufacturing process of a high-frequency embedded component HDI circuit board according to one embodiment of the present invention. Figure 4 This is a system structure diagram of a high-frequency embedded component HDI circuit board manufacturing system provided in one embodiment of the present invention. Detailed Implementation

[0019] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0020] like Figure 1 As shown, this invention provides a method for manufacturing a high-frequency embedded component HDI circuit board, the method comprising: Step S1: After the line is etched to form a fine line, the measured parameters of the buried resistor setting area and the buried capacitor setting area after etching are obtained, and the high frequency drift prediction value of the buried area is determined based on the measured parameters after etching.

[0021] Specifically, the measured parameters of the buried resistor setting area and the buried capacitor setting area after etching are obtained, including: after the line etching forms a fine line, the buried resistor setting area and the buried capacitor setting area are determined based on the designed embedding position of the buried resistor element and the buried capacitor element; the measured line width, measured line spacing, residual copper thickness, line edge roughness and termination residual copper width are collected in the buried resistor setting area and the buried capacitor setting area respectively; the measured line width, measured line spacing, residual copper thickness, line edge roughness and termination residual copper width are used as the measured parameters after etching.

[0022] Furthermore, determining the predicted high-frequency drift value of the embedded area based on the measured parameters after etching includes: comparing the measured parameters after etching with the corresponding design parameters to obtain the line etching deviation and the termination etching deviation; determining the micro-line impedance offset based on the line etching deviation, and determining the termination parasitic offset of the embedded resistor and embedded capacitor based on the termination etching deviation; determining the predicted high-frequency drift value of the embedded area corresponding to the embedded resistor setting area and the embedded capacitor setting area based on the micro-line impedance offset and the termination parasitic offset; wherein, the predicted high-frequency drift value of the embedded area is used to characterize the predicted influence of the embedded resistor and embedded capacitor on the high-frequency transmission impedance after being embedded in the corresponding board layer.

[0023] In this embodiment of the invention, after the line etching is completed, the fine lines have been formed. However, the line dimensions at this stage are usually affected by the etching factor, copper foil thickness, local pattern density, and development uniformity. The actual line width and termination copper width often differ from the design values. For ordinary low-frequency circuit boards, such differences can be screened through subsequent finished product inspection. However, in high-frequency embedded component HDI circuit boards, embedded resistors and capacitors will be embedded inside the board layers. Once lamination is completed, the rework space in the relevant areas is small. Therefore, in this embodiment, after the line etching forms the fine lines, the embedded resistor and capacitor areas are measured to identify local manufacturing deviations before component embedding.

[0024] In practical implementation, the corresponding embedded resistor and capacitor installation areas are determined based on their designed embedding positions in the design documents. The embedded resistor installation area may include the predetermined area of ​​the embedded resistor body and its termination area connecting to the micro-circuit; the embedded capacitor installation area may include the predetermined area of ​​the embedded capacitor electrode and the adjacent micro-circuit area. The detection object is not limited to the component body area itself, but should also cover the adjacent area where the component is electrically connected or coupled to the high-frequency transmission line.

[0025] Actual testing can be performed using image measurement, automated optical inspection, linewidth measurement equipment, copper thickness measurement equipment, or white light interferometry. The collected data includes measured linewidth, measured line spacing, residual copper thickness, line edge roughness, and residual copper width at termination. The residual copper width at termination reflects the connectable margin in the termination area of ​​buried resistors or the electrode edge of buried capacitors after etching; its variation directly affects the subsequent termination overlap length and local parasitic parameters.

[0026] As one embodiment, the measured parameters after etching can also be obtained using an industrial camera in conjunction with an image measurement program. The industrial camera is installed at the online inspection station after circuit etching. Before capturing images, a calibration board is used to determine the conversion relationship between pixel size and actual size; for example, the actual length corresponding to each pixel is calibrated to 0.5 μm. During acquisition, based on the coordinates of the buried resistor and buried capacitor components in the design file, local images of the buried resistor and buried capacitor setting areas are cropped from the image. Brightness equalization and edge enhancement processing are then applied to these local images to create a stable grayscale difference between the copper foil area and the substrate area.

[0027] The image measurement program extracts the copper boundary position along a preset measurement line, calculates the distance between the copper boundaries on opposite sides, and obtains the measured linewidth. It also calculates the interval distance along the relative boundaries of two adjacent micro-lines to obtain the measured line spacing. At the buried resistor termination area or the edge of the buried capacitor electrode, the residual copper width at the termination is calculated based on the overlap between the termination copper area contour and the designed termination boundary. For line edge roughness, multiple boundary sampling points can be continuously extracted along the RF trace length direction, and the average or maximum offset of the boundary sampling points relative to the fitted center line is calculated. The above image measurement results, together with the copper thickness detection results, constitute the post-etching measured parameters, which are then input into the subsequent calculation process of the high-frequency drift prediction value of the buried area.

[0028] After obtaining the measured parameters after etching, these parameters are compared with the corresponding design parameters. For example, the measured linewidth is compared with the target linewidth to obtain the linewidth deviation; the measured line spacing is compared with the target line spacing to obtain the line spacing deviation; and the residual copper width at the termination is compared with the designed copper width at the termination to obtain the termination etching deviation. The line etching deviation is used to calculate the impedance offset of fine lines, and the termination etching deviation is used to calculate the parasitic offset at the termination of buried resistors and capacitors after embedding.

[0029] The above calculations can be performed using a pre-calibrated impedance sensitivity table or a process experience model. The predicted high-frequency drift value of the embedded area, obtained by combining the impedance offset of the micro-line and the parasitic offset of the termination, serves as the basis for subsequent embedding pre-compensation, lamination linkage control, and solder resist compensation, enabling subsequent processes to adjust around the same local high-frequency deviation source.

[0030] In another implementation, after the trace etching forms a fine line, the industrial camera, in addition to acquiring the measured line width, measured line spacing, and residual copper width at the termination, also performs local magnified acquisition of the copper boundaries on both sides of the residual copper width at the termination within the buried resistor setting area, and extracts the undulating contour of the copper boundaries along the length of the RF trace. If the boundary undulations between adjacent sampling points are mainly distributed continuously along the RF current transmission direction, they are marked as forward roughness. If the boundary undulations are mainly distributed abruptly along the direction perpendicular to the RF current transmission direction, they are marked as transverse roughness. Transverse roughness is more likely to cause local current congestion during high-frequency transmission. Therefore, when calculating the termination etching deviation, the residual copper width at the termination corresponding to the transverse roughness is reduced by a preset correction amount before being included in the calculation of the parasitic offset at the termination. This allows the adequacy of the termination copper width to be further refined to whether the termination copper boundary is suitable for high-frequency current passage, avoiding the judgment of the termination status based solely on the average copper width.

[0031] Step S2: Based on the high-frequency drift prediction value of the embedded area, generate the embedding pre-compensation parameters for the embedded resistor and embedded capacitor, and embed the embedded resistor and embedded capacitor into the corresponding plate layer according to the embedding pre-compensation parameters to form an embedded passive component layer.

[0032] Specifically, based on the predicted high-frequency drift value of the embedded area, embedding pre-compensation parameters for the embedded resistor and embedded capacitor are generated, including: comparing the predicted high-frequency drift value of the embedded area with a preset high-frequency drift allowable value to determine the compensation direction for the corresponding embedded resistor setting area and embedded capacitor setting area; adjusting the termination overlap length of the embedded resistor and the electrode edge clearance distance of the embedded capacitor based on the compensation direction to obtain the component termination compensation parameters; adjusting the embedding offset of the embedded resistor and embedded capacitor relative to the micro-circuit based on the compensation direction to obtain the component position compensation parameters; and using the component termination compensation parameters and the component position compensation parameters as embedding pre-compensation parameters.

[0033] Furthermore, embedding the buried resistor and buried capacitor elements into the corresponding plate layers according to the embedded pre-compensation parameters to form an embedded passive component layer includes: determining the termination overlap position of the buried resistor element in the buried resistor setting area and the electrode edge position of the buried capacitor element in the buried capacitor setting area based on the embedded pre-compensation parameters; forming the buried resistor element in the corresponding plate layer according to the termination overlap position and connecting the buried resistor element to the micro-circuit; forming the buried capacitor element in the corresponding plate layer according to the electrode edge position and connecting the buried capacitor element to the micro-circuit; and performing a curing process on the corresponding plate layer in which the buried resistor element and the buried capacitor element are formed to obtain the embedded passive component layer.

[0034] In this embodiment, the predicted high-frequency drift value of the embedded region is used to determine the correction method for the embedded resistor and capacitor components before embedding. Since step S1 has already obtained the actual deviation of the embedded resistor and capacitor setting areas after etching, this step compares the predicted high-frequency drift value of the embedded region with a preset high-frequency drift allowable value. The preset high-frequency drift allowable value can be preset based on the target impedance control range, high-frequency transmission loss index, and product grade. For example, for a 50Ω RF trace, the allowable drift range can be set within the impedance deviation range specified in the process document. The comparison result is used to determine the compensation direction of the corresponding area. The compensation direction includes at least three cases: reducing the influence of local equivalent impedance, increasing the influence of local equivalent impedance, and maintaining the original embedding parameters.

[0035] After determining the compensation direction, the system or process control program corrects the termination-related dimensions of buried resistors and buried capacitors. For buried resistors, the termination overlap length affects the contact stability and termination parasitic parameters between the buried resistor and the micro-line. If the predicted high-frequency drift value of the buried area indicates that the termination area may cause excessive parasitic effects, the termination overlap length can be shortened while meeting the conductivity reliability requirements, or the termination overlap position can be adjusted to reduce the abrupt change in the termination copper area. If the prediction result indicates insufficient connection margin, the termination overlap length can be appropriately increased to avoid insufficient contact after subsequent lamination and curing. For buried capacitors, the electrode edge clearance distance is used to define the relative position between the edge of the buried capacitor electrode and the adjacent micro-line and termination copper area. If the electrode edge clearance distance is too small, it is easy to increase edge coupling; if the clearance distance is too large, it may affect the target capacitance value or occupy too much wiring space. Therefore, in this embodiment, the electrode edge clearance distance of the buried capacitor is adjusted according to the compensation direction to obtain the component termination compensation parameters.

[0036] In addition to termination dimensions, the embedding offset of buried resistors and capacitors relative to the micro-line can be adjusted based on the same compensation direction. The embedding offset describes the correction distance of the buried resistor or capacitor relative to its designed embedding position within the corresponding board plane; it can be set along the line length direction, the line width direction, or a combination of both. In actual production, the offset should not deviate from process alignment capabilities and safety clearance requirements, and can be limited by alignment tolerances, minimum line spacing, component edge spacing, and interlayer registration capabilities. The embedding pre-compensation parameter, composed of termination overlap length, electrode edge clearance distance, and embedding offset, is used to apply the high-frequency drift prediction results obtained in step S1 to the component formation position and termination geometry.

[0037] When forming the embedded passive component layer, the termination overlap position of the embedded resistor element within the embedded resistor setting area and the electrode edge position of the embedded capacitor element within the embedded capacitor setting area are first determined according to the embedded pre-compensation parameters. The embedded resistor element can be formed by printing, electroplating, sputtering, thin film deposition, or other patterning processes suitable for embedded resistor materials. Both ends of the embedded resistor material are connected to the reserved micro-line termination portions. During the formation process, the termination overlap position should be consistent with the aforementioned component termination compensation parameters, so that the effective resistance length of the embedded resistor element and the termination connection area simultaneously meet the resistance value requirements and high-frequency connection requirements.

[0038] Embedded capacitors can be disposed in corresponding layers by forming a lower electrode, a dielectric layer, and an upper electrode, or they can be formed by combining a pre-fabricated embedded capacitor material layer with a patterned electrode. The electrode edge position of the embedded capacitor is determined by the electrode edge setback distance, so that the embedded capacitor can obtain the target capacitance value while maintaining a compensated edge distance with adjacent micro-circuits.

[0039] After the embedded resistor and capacitor elements are formed, the corresponding layers are cured. The curing process may include baking, pre-curing before hot pressing, photocuring, or a combination of curing steps suitable for the selected material system. The purpose of this curing process is to stabilize the position and material state of the embedded resistor material, capacitor dielectric layer, and related termination structures, providing a relatively stable embedded passive component layer for subsequent lamination and linkage control. For different material systems, the curing temperature, curing time, and heating method can be determined according to material supplier parameters or process verification results; this embodiment is not limited to a specific curing curve. After curing, the corresponding layers containing the embedded resistor and capacitor elements serve as the embedded passive component layer and continue into subsequent lamination processes.

[0040] In another implementation, after generating embedded pre-compensation parameters based on the high-frequency drift prediction value of the embedded area, if it is determined that the width difference between the residual copper width of the termination area of ​​the embedded resistor element and the measured line width of the adjacent micro-line exceeds the preset abrupt change allowable value, the embedded resistor element is not directly connected according to the rectangular termination copper area, but a gradually shrinking transition copper area is formed between the termination area of ​​the embedded resistor element and the micro-line.

[0041] One end of the tapered transition copper region is connected to the termination area of ​​the buried resistor element, and the other end is connected to the micro-line. The copper width gradually transitions from the residual termination copper width to the measured linewidth of the micro-line along the RF current transmission direction. In actual fabrication, the copper foil profile of this region can be simultaneously corrected in the embedded pre-compensation pattern to prevent abrupt geometric narrowing between the termination copper region and the micro-line. For a 28GHz RF branch, for example, with a residual termination copper width of 59μm and a measured micro-line linewidth of 47.2μm, the length of the tapered transition copper region can be set to 30μm to 50μm. This process allows for a smoother change in the local conductor width of the termination region, reducing high-frequency current concentration at the subsequent termination position of the buried resistor element.

[0042] Step S3: Based on the predicted high-frequency drift value of the embedded area, perform lamination linkage control on the embedded passive component layer to obtain the laminated high-frequency interconnect board.

[0043] Specifically, the predicted high-frequency drift value of the embedded area is compared with a preset lamination grading threshold to determine the lamination control level of the embedded passive component layer; the lamination process parameters corresponding to the lamination control level are retrieved from a preset lamination parameter mapping table, including heating rate, pre-compression pressure, main pressure, and holding time; the embedded passive component layer and adjacent board layers are laminated according to the lamination process parameters; after lamination, the laminated board is aligned and its thickness is measured to obtain the laminated high-frequency interconnect board.

[0044] In this embodiment of the invention, before the embedded passive component layer enters the lamination process, the high-frequency drift prediction value of the embedded area has been obtained according to step S1, and the embedding pre-compensation of the embedded resistor and capacitor elements is completed in step S2. The lamination process will further change the dielectric thickness, resin filling state, and interlayer alignment state around the embedded area. Therefore, this embodiment continues to use the high-frequency drift prediction value of the embedded area as the basis for selecting lamination process parameters, so that the lamination stage and the previous embedding compensation maintain the same control source.

[0045] In practice, a lamination grading threshold is preset, and the predicted high-frequency drift value of the embedded area is compared with the preset lamination grading threshold to determine the lamination control level of the embedded passive component layer. The lamination control levels can be divided according to drift risk from low to high, without limiting the specific number of levels. Each lamination control level corresponds to a set of lamination process parameters in a preset lamination parameter mapping table. These lamination process parameters include heating rate, pre-compression pressure, main pressure, and holding time. This preset lamination parameter mapping table can be jointly determined by trial production data, material supplier-recommended pressing curves, and the company's internal process window, and stored in the lamination equipment control program or manufacturing execution system. Table 1 provides an example of a preset lamination parameter mapping table.

[0046] Table 1 Preset Lamination Parameter Mapping Table

[0047] When the predicted high-frequency drift value of the embedded area is at a low level, lamination process parameters close to those of a conventional lamination curve can be used. When the predicted high-frequency drift value of the embedded area indicates a significant risk of dielectric thickness drift or parasitic displacement at the termination in the embedded region, a gentler heating rate, a longer pre-compression stage, or a modified holding time can be used to ensure more thorough filling of the resin in the termination area of ​​the embedded resistor element and around the electrode edge of the embedded capacitor element. The main pressure setting should simultaneously meet the requirements of interlayer bonding and embedded element stability, avoiding insufficient interlayer lamination simply due to reduced local stress.

[0048] According to the lamination process parameters obtained from the call, the embedded passive component layer is stacked with the adjacent board layer and lamination is performed. After lamination, the laminated board is subjected to alignment and thickness checks. Alignment checks are used to confirm the registration status between the embedded components, micro-circuit lines, and adjacent board layers; thickness checks are used to confirm whether the dielectric thickness and board thickness after lamination fall within the allowable process range. The laminated board that passes the checks is used as a high-frequency interconnect board and proceeds to subsequent impedance retesting and solder mask compensation processing.

[0049] Step S4: Based on the impedance retest results of the high-frequency interconnect board, adjust the solder mask boundary parameters and impedance compensation parameters, and complete the solder mask processing based on the adjusted solder mask boundary parameters and impedance compensation parameters to obtain the high-frequency embedded component HDI circuit board.

[0050] Specifically, based on the impedance retest results of the high-frequency interconnect board, the solder mask boundary parameters and impedance compensation parameters are adjusted, including: performing impedance retests on the RF traces in the corresponding buried resistor and buried capacitor areas of the high-frequency interconnect board to obtain impedance retest values; determining the solder mask compensation direction based on the deviation between the impedance retest values ​​and the target impedance values; adjusting the spacing between the RF traces and the solder mask coverage boundary based on the solder mask compensation direction to obtain solder mask boundary parameters; and adjusting the local compensation linewidth of the RF traces based on the solder mask compensation direction to obtain impedance compensation parameters.

[0051] Furthermore, adjusting the spacing between the RF trace and the solder mask coverage boundary based on the solder mask compensation direction to obtain solder mask boundary parameters includes: determining an edge coupling segment in the RF trace adjacent to the termination area of ​​the buried resistor element and the electrode edge of the buried capacitor element based on the solder mask compensation direction; obtaining the solder mask curing shrinkage amount corresponding to the edge coupling segment, and determining the solder mask boundary retraction amount based on the solder mask curing shrinkage amount; when the solder mask compensation direction indicates that the solder mask medium needs to be away from the RF trace, moving the solder mask coverage boundary away from the edge coupling segment by the solder mask boundary retraction amount; when the solder mask compensation direction indicates that the solder mask medium needs to be close to the RF trace, moving the solder mask coverage boundary away from the edge coupling segment by the solder mask boundary retraction amount; and using the spacing between the moved solder mask coverage boundary and the edge coupling segment as the solder mask boundary parameter.

[0052] Furthermore, based on the adjusted solder mask boundary parameters and impedance compensation parameters, solder mask processing is completed to obtain a high-frequency embedded component HDI circuit board, including: forming a local compensation circuit pattern at the corresponding position of the RF trace to be solder masked on the surface layer of the high-frequency interconnect board according to the impedance compensation parameters; forming a solder mask window pattern on the high-frequency interconnect board to avoid the local compensation circuit pattern according to the solder mask boundary parameters; applying solder mask coating and curing to the high-frequency interconnect board based on the solder mask window pattern to form a solder mask layer; and performing high-frequency performance testing on the high-frequency interconnect board with the solder mask layer formed, and obtaining the high-frequency embedded component HDI circuit board after passing the test.

[0053] In this embodiment of the invention, in step S4, before the high-frequency interconnect board after lamination enters the solder mask treatment, the impedance of the RF traces related to the buried resistor and buried capacitor areas is retested. After lamination, the local dielectric thickness, resin filling state, and interlayer registration state may all change, especially near the termination area of ​​the buried resistor element and the electrode edge of the buried capacitor element, where the local high-frequency transmission environment is different from that in the etching and component embedding stages. Therefore, this embodiment retests the impedance before solder mask treatment to determine the high-frequency impedance state of the board after lamination, and the retest results are used for solder mask compensation.

[0054] In practice, time-domain reflectometry, high-frequency network analysis, or impedance testing equipment can be used to inspect the RF traces in the corresponding buried resistor and buried capacitor areas of the high-frequency interconnect board to obtain impedance remeasurement values. The deviation between the impedance remeasurement value and the target impedance value is used to determine the solder mask compensation direction. The solder mask compensation direction can include reducing the coverage effect of the solder mask on the RF traces, increasing the dielectric constraint of the solder mask on local areas, or maintaining the current solder mask boundary state. Since the solder mask layer itself is part of the dielectric layer, its coverage boundary, thickness, and opening position will change the local dielectric environment near the RF traces. Therefore, the solder mask stage is not just a cosmetic protection process, but continues to participate in high-frequency impedance control.

[0055] After determining the solder mask compensation direction, the spacing between the RF trace and the solder mask coverage boundary is adjusted. This spacing is used to limit the proximity between the solder mask and the RF trace. For RF traces near the termination area of ​​buried resistors and the electrode edge of buried capacitors, this embodiment further introduces an edge coupling segment as the object of solder mask boundary correction. The edge coupling segment refers to a local line segment in the RF trace that is adjacent to the termination area of ​​buried resistors and the electrode edge of buried capacitors and is easily affected by edge electric field coupling. The range of the edge coupling segment can be determined based on the termination size of the buried resistor, the electrode edge size of the buried capacitor, and the RF trace spacing, and is not limited to a fixed length.

[0056] During the solder resist curing process, the solder resist material shrinks, and the local shrinkage can cause a shift in the original solder resist boundary position. For high-frequency HDI circuit boards, this shift has limited impact in ordinary digital circuits, but near the edge coupling section, it can further alter the local dielectric environment. Therefore, this embodiment obtains the solder resist curing shrinkage corresponding to the edge coupling section and determines the solder resist boundary retraction amount based on the solder resist curing shrinkage amount. The solder resist curing shrinkage amount can be determined based on the characteristics of the solder resist material, curing temperature, curing time, and existing process calibration results. If the solder resist compensation direction indicates that the solder resist medium needs to be away from the RF trace, the solder resist coverage boundary is moved away from the edge coupling section by the corresponding solder resist boundary retraction amount; if the solder resist compensation direction indicates that the solder resist medium needs to be close to the RF trace, the solder resist coverage boundary is moved closer to the edge coupling section by the corresponding solder resist boundary retraction amount. The distance between the moved solder resist coverage boundary and the edge coupling section is used as the solder resist boundary parameter for subsequent solder resist window pattern generation.

[0057] In addition to the solder mask boundary, this embodiment also performs local conductor compensation on the RF traces based on the same solder mask compensation direction. Since the local line width, edge roughness, and solder mask dielectric environment have changed after lamination, impedance offsets may still exist in some areas. In this case, the local compensation linewidth of the RF trace to be soldered can be adjusted based on the solder mask compensation direction. The local compensation linewidth is used to correct the equivalent impedance of the local line, and its adjustment range should meet the requirements of minimum line width, minimum line spacing, and subsequent solder mask windowing capability. The resulting local compensation line pattern and solder mask windowing pattern jointly participate in subsequent solder mask processing.

[0058] In the specific solder mask process, according to the impedance compensation parameters, a local compensation circuit pattern is formed at the corresponding position of the surface layer RF trace to be soldered on the high-frequency interconnect board. This local compensation circuit pattern can be formed through pattern trimming, compensation etching, or other methods suitable for surface layer circuit correction, with the aim of making the local circuit state near the edge coupling section closer to the target impedance after solder masking. Subsequently, according to the solder mask boundary parameters, a solder mask window pattern is formed on the high-frequency interconnect board to avoid the local compensation circuit pattern. A predetermined interval is maintained between the solder mask window pattern and the local compensation circuit pattern to prevent the solder mask medium from forming additional dielectric disturbances near the local compensation circuit.

[0059] After the pattern is generated, the high-frequency interconnect board is coated with solder resist and cured to form a solder resist layer. The solder resist material can be photosensitive solder resist ink, spray-on solder resist material, or low-dielectric resistance solder material suitable for high-frequency HDI boards. The temperature profile, exposure conditions, and curing time during the solder resist curing process can be determined according to the material system and board structure; this embodiment is not limited to a specific curing method. After the solder resist layer is formed, the high-frequency interconnect board is subjected to high-frequency performance testing again. The testing content may include impedance testing, insertion loss testing, return loss testing, or other high-frequency test items suitable for millimeter-wave band HDI circuit boards. After passing the test, a high-frequency embedded component HDI circuit board is obtained. In the entire step S4, the solder resist boundary parameters and impedance compensation parameters jointly participate in the local high-frequency compensation of the solder resist stage, so that the solder resist treatment and the aforementioned etching compensation, embedding compensation, and lamination linkage control form a continuous process chain.

[0060] In another implementation, if impedance retesting results indicate a high impedance in the edge coupling section before solder masking, and one side of this edge coupling section is adjacent to the edge of a buried capacitor electrode, while the other side is adjacent to a regular micro-line, then the solder mask boundary clearance amount is determined based on the strength of dielectric coupling on both sides. For the side adjacent to the edge of the buried capacitor electrode, the spacing between the solder mask coverage boundary and the RF trace is increased; for the side adjacent to the regular micro-line, the original solder mask coverage boundary is maintained or a smaller clearance amount is used.

[0061] During implementation, an image of the coupling section before solder mask is acquired using an industrial camera. The relative positions between the RF trace, the edge of the embedded capacitor electrode, and the original solder mask coverage boundary are identified, and then an asymmetric solder mask window pattern is generated. For example, the solder mask coverage boundary on the side closest to the embedded capacitor electrode edge is moved outward by 18μm, and the other side is moved outward by 6μm. This method can allow for solder mask dielectric retreat on the side with concentrated local electric field, avoiding excessive expansion of the entire solder mask window.

[0062] Example: like Figure 2 This paper describes a high-frequency embedded component HDI circuit board used in a 28GHz RF front-end module. The circuit board adopts a six-layer structure with a finished board thickness of 0.85mm. The target impedance of the RF traces is 50Ω, and the minimum trace width / spacing is 50 / 50μm. Embedded resistors are placed on the L2 layer, and embedded capacitors are placed on the L3-L4 layers. The loss factor Df of the high-frequency substrate used is 0.002@10GHz.

[0063] After the circuit etching is completed, local images of the buried resistor and buried capacitor areas are acquired using an industrial camera, and the measured line width, measured line spacing, and residual copper width at the termination are extracted by the image measurement program. Taking the buried resistor area as an example, the designed line width is 50μm, and the measured line width is 47.2μm; the designed line spacing is 50μm, and the measured line spacing is 53.1μm; the designed termination copper width is 65μm, and the measured residual copper width at the termination is 59μm. Based on the deviation between the measured parameters after etching and the corresponding design parameters, the predicted high-frequency drift value of the buried area in this region is calculated to be +3.2Ω, indicating that after the buried components are formed and lamination is completed in this region, there is a tendency for the impedance to be relatively high.

[0064] Embedding pre-compensation parameters are generated based on the predicted high-frequency drift value of the embedded area. The overlap length of the embedded resistor element termination is adjusted from 60μm to 54μm, and the embedding offset of the embedded resistor element relative to the micro-circuit is set to +4μm; the electrode edge clearance distance of the embedded capacitor element is adjusted from 20μm to 28μm. After the embedded resistor element and embedded capacitor element are formed, the corresponding plate layer is pre-cured to obtain the embedded passive component layer.

[0065] During lamination, +3.2Ω was assigned to Level III lamination control, and the following lamination process parameters were used: heating rate 1.5℃ / min, pre-pressure 1.0MPa, main pressure 2.8MPa, and holding time 90min. After lamination, the measured board thickness was 0.86mm, with a alignment deviation of less than 15μm. Before solder mask treatment, the impedance of the corresponding RF traces was retested, and the measured impedance was 52.1Ω. Based on the high impedance, the solder mask coverage boundary corresponding to the edge coupling section was moved 18μm away from the RF trace, and the local compensation linewidth of the RF traces to be solder masked was increased by 2μm.

[0066] After the solder resist coating and curing are completed, the finished product is subjected to high-frequency performance testing. The test results show that the impedance of the buried resistor branch is controlled between 49.6Ω and 50.8Ω, the impedance of the buried capacitor branch is controlled between 49.5Ω and 50.7Ω, the insertion loss at 28GHz is 0.76dB / inch, and the buried resistor value deviation is ±7.5%. Figure 3 (a) shows an industrial camera image of the area after etching and buried resist setup. Figure 3 Image (b) shows a local image after the pre-compensation process has been performed. Figure 3 Image (c) shows the solder mask boundary adjustment image after lamination. Figure 3 Image (d) shows a partial image of the finished product after solder resist treatment.

[0067] like Figure 4 As shown, this invention provides a high-frequency embedded component HDI circuit board manufacturing system. The system includes: a data acquisition unit, used to acquire post-etching measured parameters of the embedded resistor setting area and the embedded capacitor setting area after etching to form micro-circuits, and to determine the high-frequency drift prediction value of the embedded area based on the post-etching measured parameters; a compensation unit, used to generate embedding pre-compensation parameters for the embedded resistor and embedded capacitor components based on the high-frequency drift prediction value of the embedded area, and to embed the embedded resistor and embedded capacitor components into the corresponding board layers according to the embedding pre-compensation parameters to form an embedded passive component layer; a lamination unit, used to perform lamination linkage control on the embedded passive component layer based on the high-frequency drift prediction value of the embedded area to obtain a laminated high-frequency interconnect board; and a solder mask unit, used to adjust the solder mask boundary parameters and impedance compensation parameters based on the impedance retest results of the high-frequency interconnect board, and to complete the solder mask processing based on the adjusted solder mask boundary parameters and impedance compensation parameters to obtain a high-frequency embedded component HDI circuit board.

[0068] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a microcontroller, chip, or processor to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0069] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details described above. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not further describe the various possible combinations.

[0070] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the embodiments of the present invention, they should also be regarded as the content disclosed by the embodiments of the present invention.

Claims

1. A method for manufacturing a high-frequency embedded component HDI circuit board, characterized in that, The method includes: After etching to form micro-circuits, measured parameters of the buried resistor and buried capacitor regions are obtained, and the predicted high-frequency drift value of the buried region is determined based on these measured parameters; wherein, Determining the predicted high-frequency drift value of the embedded area based on the measured parameters after etching includes: comparing the measured parameters after etching with the corresponding design parameters to obtain the line etching deviation and the termination etching deviation; determining the micro-line impedance offset based on the line etching deviation; determining the termination parasitic offset of the embedded resistor and embedded capacitor based on the termination etching deviation; and determining the predicted high-frequency drift value of the embedded area corresponding to the embedded resistor setting area and the embedded capacitor setting area based on the micro-line impedance offset and the termination parasitic offset. The predicted high-frequency drift value of the embedded area is used to characterize the predicted influence of the embedded resistor and embedded capacitor on the high-frequency transmission impedance after embedding them in the corresponding board layer. Based on the high-frequency drift prediction value of the embedded area, embedding pre-compensation parameters for embedded resistors and embedded capacitors are generated, and the embedded resistors and embedded capacitors are embedded into the corresponding plate layers according to the embedding pre-compensation parameters to form an embedded passive component layer. Based on the predicted high-frequency drift value of the embedded area, lamination linkage control is performed on the embedded passive component layer to obtain the laminated high-frequency interconnect board. Based on the impedance retest results of the high-frequency interconnect board, the solder mask boundary parameters and impedance compensation parameters are adjusted, and the solder mask processing is completed based on the adjusted solder mask boundary parameters and impedance compensation parameters to obtain a high-frequency embedded component HDI circuit board; wherein... Based on the impedance retest results of the high-frequency interconnect board, the solder mask boundary parameters and impedance compensation parameters are adjusted, including: performing impedance retests on the RF traces in the corresponding buried resistor and buried capacitor areas of the high-frequency interconnect board to obtain the impedance retest values; determining the solder mask compensation direction based on the deviation between the impedance retest values ​​and the target impedance values; adjusting the spacing between the RF traces and the solder mask coverage boundary based on the solder mask compensation direction to obtain the solder mask boundary parameters; and adjusting the local compensation linewidth of the RF traces based on the solder mask compensation direction to obtain the impedance compensation parameters.

2. The method for manufacturing a high-frequency embedded component HDI circuit board according to claim 1, characterized in that, Obtain the measured parameters after etching of the buried resistor setting area and the buried capacitor setting area, including: After the micro-line is etched, the embedded positions of the embedded resistor and embedded capacitor are determined based on the design embedding positions of the embedded resistor and embedded capacitor. The measured line width, measured line spacing, residual copper thickness, line edge roughness, and termination residual copper width are collected in the buried resistor setting area and the buried capacitor setting area, respectively. The measured line width, the measured line spacing, the residual copper thickness, the line edge roughness, and the residual copper width at the termination are used as the measured parameters after etching.

3. The method for manufacturing a high-frequency embedded component HDI circuit board according to claim 1, characterized in that, Based on the predicted high-frequency drift value of the embedded region, embedding pre-compensation parameters for the embedded resistor and capacitor are generated, including: The predicted high-frequency drift value of the buried area is compared with the preset high-frequency drift allowable value to determine the compensation direction of the corresponding buried resistance setting area and buried capacity setting area. Based on the compensation direction, the terminal overlap length of the buried resistor element and the electrode edge clearance distance of the buried capacitor element are adjusted to obtain the element terminal compensation parameters. Based on the compensation direction, the embedding offset of the embedded resistor and embedded capacitor relative to the micro-circuit is adjusted to obtain the component position compensation parameters. The component termination compensation parameter and the component position compensation parameter are used as embedded pre-compensation parameters.

4. The method for manufacturing a high-frequency embedded component HDI circuit board according to claim 3, characterized in that, Embedded resistors and capacitors are embedded into corresponding plate layers according to the embedded pre-compensation parameters to form an embedded passive component layer, including: Based on the embedded pre-compensation parameters, the termination overlap position of the buried resistor element in the buried resistor setting area and the electrode edge position of the buried capacitor element in the buried capacitor setting area are determined. An embedded resistor element is formed on the corresponding board layer according to the termination overlap position, and the embedded resistor element is connected to the micro-line. Embedded capacitors are formed on the corresponding plate layer according to the electrode edge position, and the embedded capacitors are connected to the micro-circuit. The corresponding plate layer on which the embedded resistor and the embedded capacitor are formed is cured to obtain the embedded passive component layer.

5. The method for manufacturing a high-frequency embedded component HDI circuit board according to claim 1, characterized in that, Based on the predicted high-frequency drift value of the embedded area, lamination linkage control is performed on the embedded passive component layer to obtain a laminated high-frequency interconnect board, including: The high-frequency drift prediction value of the embedded area is compared with the preset lamination grading threshold to determine the lamination control level of the embedded passive component layer. The lamination process parameters corresponding to the lamination control level are retrieved from the preset lamination parameter mapping table. The lamination process parameters include heating rate, pre-compression pressure, main pressure, and holding time. According to the lamination process parameters, the embedded passive component layer and the adjacent plate layer are laminated. After lamination, the laminated board is subjected to alignment and thickness detection to obtain the laminated high-frequency interconnect board.

6. The method for manufacturing a high-frequency embedded component HDI circuit board according to claim 5, characterized in that, Based on the solder mask compensation direction, the spacing between the RF trace and the solder mask coverage boundary is adjusted to obtain the solder mask boundary parameters, including: Based on the solder resist compensation direction, the edge coupling segment in the RF trace that is adjacent to the termination area of ​​the buried resistor element and the electrode edge of the buried capacitor element is determined. Obtain the solder resist curing shrinkage amount corresponding to the edge coupling segment, and determine the solder resist boundary retraction amount based on the solder resist curing shrinkage amount; When the solder mask compensation direction indicates that the solder mask medium needs to be away from the RF trace, the solder mask coverage boundary is moved away from the edge coupling segment by the amount of solder mask boundary retraction. When the solder mask compensation direction indicates that the solder mask medium needs to be close to the RF trace, the solder mask coverage boundary is moved along the direction close to the edge coupling segment by the amount of solder mask boundary retraction. The distance between the moved solder resist coverage boundary and the edge coupling segment is used as the solder resist boundary parameter.

7. The method for manufacturing a high-frequency embedded component HDI circuit board according to claim 5, characterized in that, Solder masking is completed based on the adjusted solder mask boundary parameters and impedance compensation parameters, resulting in a high-frequency embedded component HDI circuit board, including: According to the impedance compensation parameters, a local compensation circuit pattern is formed at the corresponding position of the RF trace on the surface layer of the high-frequency interconnect board to be soldered. According to the solder mask boundary parameters, a solder mask window pattern that avoids the local compensation circuit pattern is formed on the high-frequency interconnect board. Based on the solder resist window pattern, the high-frequency interconnect board is coated with solder resist and cured to form a solder resist layer. The high-frequency interconnect board with the solder resist layer is subjected to high-frequency performance testing. After passing the test, a high-frequency embedded component HDI circuit board is obtained.

8. A high-frequency embedded component HDI circuit board manufacturing system, characterized in that, The system is used to perform the high-frequency embedded component HDI circuit board manufacturing method according to any one of claims 1-7, the system comprising: The acquisition unit is used to acquire the measured parameters of the buried resistor setting area and the buried capacitor setting area after the line is etched to form a micro line, and to determine the high frequency drift prediction value of the buried area based on the measured parameters after etching. The compensation unit is used to generate embedded pre-compensation parameters for the embedded resistor and embedded capacitor based on the high-frequency drift prediction value of the embedded area, and to embed the embedded resistor and embedded capacitor into the corresponding plate layer according to the embedded pre-compensation parameters to form an embedded passive component layer. A lamination unit is used to perform lamination linkage control on the embedded passive component layer based on the high-frequency drift prediction value of the embedded area to obtain a laminated high-frequency interconnect board. The solder mask unit is used to adjust the solder mask boundary parameters and impedance compensation parameters based on the impedance retest results of the high-frequency interconnect board, and to complete the solder mask process based on the adjusted solder mask boundary parameters and impedance compensation parameters to obtain a high-frequency embedded component HDI circuit board.

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