半导体结构、半导体存储器及其制作方法

By widening the gate structure and setting a cavity structure, the problem of electrical performance degradation caused by the diffusion of active metal atoms in SRAM devices is solved, thereby improving the reliability and electrical performance of the devices.

CN122421333APending Publication Date: 2026-07-17NEXCHIP SEMICON CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-17
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In existing SRAM devices, the diffusion of active metal atoms such as aluminum atoms leads to a decline in electrical performance and reliability issues, especially the severe threshold voltage mismatch at the junction of pull-up and pull-down transistors.

Method used

By widening the gate structure in the second transistor region and setting a cavity structure at the junction, a closed cavity is formed using the first barrier layer and the second work function layer, blocking the diffusion path of active metal atoms and optimizing the interface stability of the gate structure.

Benefits of technology

It effectively prevents the diffusion of active metal atoms from the pull-up transistor to the pull-down transistor, improving the electrical performance and reliability of SRAM devices and ensuring the performance and reliability of the pull-up transistor.

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Abstract

本申请公开了一种半导体结构、半导体存储器及其制作方法,应用在半导体技术领域。其中,栅极结构包括栅介质层、第一功函数层、第一阻挡层、第二功函数层和导电层;所述第一阻挡层位于第一功函数层上,且第一阻挡层的边缘在沿靠近第一晶体管区的方向水平延伸超出第一功函数层的边缘;所述第二功函数层位于所述第一阻挡层上,且延伸覆盖在第一晶体管区中的栅介质层上,并与第一阻挡层以及第一功函数层共同界定出一空腔;由于在第一功函数层和第二功函数层之间增设了第一阻挡层和空腔,从而阻挡了活跃金属原子从第二功函数层扩散到第一功函数层或其他膜层中的扩散路径,保证了SRAM器件中第二晶体管区中的上拉晶体管的性能和可靠性。
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