Display device

Abstract

This disclosure relates to a display device, which may include: a substrate, pixels, a first common voltage line, an external common voltage trunk line, a first external common voltage line, and a second external common voltage line. The substrate may include a display area and a non-display area. The pixels may be disposed on the display area. The first common voltage line may be at least partially disposed on the display area. The external common voltage trunk line may be disposed on the non-display area, electrically connected to the pixels via the first common voltage line, and may include a recess. The first external common voltage line may protrude from the external common voltage trunk line. The second external common voltage line may protrude from the external common voltage trunk line. The recess may be disposed between the second external common voltage line and the first common voltage line.

Description

[0001] This application is a divisional application, the parent application being the invention patent application filed on September 18, 2020, with application number 202010987405.4 and title "Display Device". Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0114735, filed on September 18, 2019, with the Korean Intellectual Property Office; all contents of that Korean Patent Application are incorporated herein by reference. Technical Field

[0003] The technical field relates to display devices. Background Technology

[0004] Display devices can display images. Modern display devices may include light-emitting diode (LED) display devices.

[0005] LED display devices do not require a separate light source, and therefore can have minimized thickness and weight. Other advantages of LED display devices include low power consumption, high brightness, and / or high response speed.

[0006] Generally, a light-emitting diode (LED) display device includes: a substrate; a thin-film transistor disposed on the substrate; an insulating layer disposed between wirings connected to the thin-film transistor; and light-emitting elements, each connected to the thin-film transistor. For example, the light-emitting element may be an organic light-emitting element.

[0007] Display devices may include display areas and non-display areas. By minimizing the non-display areas, the density of current flowing in these areas can be significantly higher. Therefore, a considerable amount of heat may be generated in the non-display areas.

[0008] This background section is used to understand the context of the embodiments. This background section may include information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0009] The embodiments may relate to a display device in which unwanted heat generation from wiring in non-display areas is prevented or mitigated.

[0010] The display device according to an embodiment includes the following elements: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a first common voltage line connected to a plurality of pixels disposed in the display area and one end of the external common voltage line, wherein the other end of the external common voltage line is branched into a first external common voltage line and a second external common voltage line, and includes a groove disposed between the second external common voltage line and the first common voltage line.

[0011] The first external common voltage line, the second external common voltage line, and the first common voltage line can be configured to be parallel to the second direction, and the groove can be configured to be parallel to the first direction perpendicular to the second direction.

[0012] In the first common voltage line, the number of first common voltage lines connected to the first external common voltage line can be greater than the number of first common voltage lines connected to the second external common voltage line.

[0013] The display device may also include an external initialization voltage line disposed between the external common voltage line and the display area and configured to be parallel to the second direction.

[0014] The external common voltage line may include a first end and a second end facing each other, the first end and the second end may be located on the same side of the display area, the display device may also include an external driving voltage line located between the first end and the second end, and the external driving voltage line and each pixel located in the display area may be connected by the driving voltage line.

[0015] External common voltage lines can be configured to surround the four sides of the display area.

[0016] A subset of pixels may overlap with the first common voltage line, and a subset of pixels connected to the first common voltage line may not overlap with the driving voltage line.

[0017] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0018] The first common voltage line can be set between multiple pixels and can be set to be parallel to the driving voltage line connected to each of the multiple pixels.

[0019] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0020] At least one of the external common voltage lines can be configured to be parallel to one side of the display area, and another external common voltage line can be configured to be parallel to the other side facing the display area.

[0021] A portion of the pixels may overlap with the first common voltage line, and the portion of pixels that overlaps with the first common voltage line may not overlap with the driving voltage line.

[0022] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0023] The first common voltage line can be set between multiple pixels and can be set to be parallel to the driving voltage line connected to each of the multiple pixels.

[0024] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0025] A display device according to another embodiment includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; and a first common voltage line connected to a plurality of pixels disposed in the display area and one end of the external common voltage line, wherein the external common voltage line includes a first external common voltage line and a second external common voltage line separated by an opening therebetween.

[0026] The first external common voltage line, the second external common voltage line, and the first common voltage line can be configured to be parallel to the second direction, and the opening can be configured to be parallel to the second direction.

[0027] The opening may also include a region parallel to the first direction perpendicular to the second direction.

[0028] In the first common voltage line, the number of first common voltage lines connected to the first external common voltage line can be greater than the number of first common voltage lines connected to the second external common voltage line.

[0029] The display device may also include an external initialization voltage line disposed between the external common voltage line and the display area and parallel to the second direction.

[0030] An external common voltage line may include a first end and a second end facing each other. The first end and the second end may be located on the same side of the display area. An external driving voltage line may be located between the first end and the second end. The external driving voltage line and each pixel located in the display area may be connected through the driving voltage line.

[0031] External common voltage lines can be configured to surround the four sides of the display area.

[0032] A portion of the pixels may overlap with the first common voltage line, and the portion of pixels that overlaps with the first common voltage line may not overlap with the driving voltage line.

[0033] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0034] The first common voltage line can be positioned between multiple pixels and parallel to the driving voltage line connected to each of the multiple pixels.

[0035] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0036] At least one external common sub-voltage line of the external common voltage line can be configured to be parallel to one side of the display area, and another external common sub-voltage line of the external common voltage line can be configured to be parallel to the other side facing said side.

[0037] A portion of the pixels may overlap with the first common voltage line, and the portion of pixels that overlaps with the first common voltage line may not overlap with the driving voltage line.

[0038] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0039] The first common voltage line can be positioned between multiple pixels and parallel to the driving voltage line connected to each of the multiple pixels.

[0040] The display device may further include a second common voltage line that is connected to and intersects with the first common voltage line.

[0041] The embodiments may relate to a display device. The display device may include: a substrate, pixels, a first common voltage line, an external common voltage trunk line, a first external common voltage line, and a second external common voltage line. The substrate includes a display area and a non-display area. Pixels may be disposed on the display area. The first common voltage line may be at least partially disposed on the display area. The external common voltage trunk line may be disposed on the non-display area, electrically connected to the pixels via the first common voltage line, and may include a recess. The first external common voltage line may protrude from the external common voltage trunk line. The second external common voltage line may protrude from the external common voltage trunk line. The recess may be disposed between the second external common voltage line and the first common voltage line.

[0042] The longitudinal direction of the second external common voltage line can be perpendicular to the longitudinal direction of the groove.

[0043] The shortest electrical path between the first common voltage line and the first external common voltage line is shorter than the shortest electrical path between the first common voltage line and the second external common voltage line.

[0044] The display device may include: an external initialization voltage line disposed between an external common voltage trunk and the display area and electrically connected to at least some of the pixels.

[0045] The display device may include the following elements: a driving voltage line, at least partially disposed on the display area; and an external driving voltage trunk line, disposed on a non-display area, disposed between a first end and a second end of the external common voltage trunk line, electrically insulated from the external common voltage trunk line, and electrically connected to at least some pixels in the pixels via the driving voltage line.

[0046] The external common voltage trunk line may include a first section, a second section, a third section, a fourth section, and a fifth section. The first section may be opposite the second section in a first direction. The third section may be opposite each of the fourth and fifth sections in a second direction, different from the first direction. A display area may be positioned between the first and second sections in the first direction. A display area may be positioned between the third section and each of the fourth and fifth sections in the second direction.

[0047] Some pixels in the pixel array overlap with the first common voltage line, but do not overlap with the driving voltage line.

[0048] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0049] The first common voltage line can be positioned between a first subset of pixels and a second subset of pixels. The longitudinal direction of the first common voltage line can be parallel to the longitudinal direction of the driving voltage line.

[0050] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0051] The external common voltage trunk line may include a first part and a second part. The second part may be opposite to the first part. The two opposite sides of the display area may be located between the first part and the second part of the external common voltage trunk line.

[0052] Some pixels in the pixel array overlap with the first common voltage line, but do not overlap with the driving voltage line.

[0053] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0054] The first common voltage line can be positioned between a first subset of pixels and a second subset of pixels. The longitudinal direction of the first common voltage line can be parallel to the longitudinal direction of the driving voltage line.

[0055] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0056] The embodiments may relate to a display device. The display device may include the following elements: a substrate including a display area and a non-display area; pixels disposed on the display area; a first common voltage line, at least partially disposed on the display area; a first external common voltage trunk line configured to transmit a common voltage, disposed on the non-display area, and electrically connected to at least a first subset of the pixels via the first common voltage line; a second external common voltage trunk line spaced apart from the first external common voltage trunk line in at least a first direction, configured to transmit a common voltage, and disposed on the non-display area; a first external common voltage line protruding from the first external common voltage trunk line in a second direction and disposed on the non-display area, wherein the second direction may be different from the first direction; and a second external common voltage line protruding from the second external common voltage trunk line and disposed on the non-display area.

[0057] Each of the longitudinal directions of the first external common voltage line, the second external common voltage line, and the first common voltage line can be perpendicular to the first direction.

[0058] The first side of the first external common voltage trunk line may be opposite to the first side of the second external common voltage trunk line in a first direction. The second side of the first external common voltage trunk line may be opposite to the second side of the second external common voltage trunk line in a second direction.

[0059] The total number of common voltage lines directly connected to the first external common voltage trunk can be greater than the total number of common voltage lines directly connected to the second external common voltage trunk.

[0060] The display device may include: an external initialization voltage line disposed between a second external common voltage trunk and the display area and electrically connected to at least some of the pixels.

[0061] The display device may include the following components: a third external common voltage trunk line, spaced apart from a first external common voltage trunk line in a first direction, wherein the first external common voltage trunk line may be disposed between the second and third external common voltage trunk lines; a driving voltage line, at least partially disposed on the display area; and an external driving voltage trunk line, disposed on a non-display area, disposed between the first and third external common voltage trunk lines, electrically insulated from each of the first and third external common voltage trunk lines, and electrically connected to at least some of the pixels via the driving voltage line.

[0062] The display area can be set between the first part of the second external common voltage trunk and the second part of the second external common voltage trunk.

[0063] Some pixels in the pixel array overlap with the first common voltage line, but do not overlap with the driving voltage line.

[0064] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0065] The first common voltage line can be positioned between a first subset of pixels and a second subset of pixels. The longitudinal direction of the first common voltage line can be parallel to the longitudinal direction of the driving voltage line.

[0066] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0067] At least one edge of the first external common voltage line may be parallel to one side of the display area, and may be positioned in a second direction between the edge of the second external common voltage line and one side of the display area.

[0068] Some pixels in the pixel array overlap with the first common voltage line, but do not overlap with the driving voltage line.

[0069] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0070] The first common voltage line can be positioned between a first subset of pixels and a second subset of pixels. The longitudinal direction of the first common voltage line can be parallel to the longitudinal direction of the driving voltage line.

[0071] The display device may include a second common voltage line that is electrically connected to and intersects with the first common voltage line.

[0072] According to an embodiment, in a display device, the heat generated in the wiring disposed in the non-display area can be minimized and / or the heat generated in the wiring disposed in the non-display area can be effectively dissipated. Attached Figure Description

[0073] Figure 1 It is a view (e.g., a floor plan) showing a display device according to an embodiment.

[0074] Figure 2 This is a view showing the flow of current in a display device according to an embodiment.

[0075] Figure 3 This is a schematic view illustrating the flow of current in a display device according to an embodiment.

[0076] Figure 4 This illustrates the relationship between the display device and the embodiment of the present invention. Figure 1 The view of the same location as area A.

[0077] Figure 5 This illustrates the relationship between the display device and the embodiment of the present invention. Figure 1 The view of the same location as area A.

[0078] Figure 6 This is a view (e.g., a plan view) of a display device according to an embodiment, including an external common voltage line, an external drive voltage line, and an external initialization voltage line.

[0079] Figure 7 This is a view showing a display device according to an embodiment.

[0080] Figure 8 This is a view showing a display device according to an embodiment.

[0081] Figure 9 This is a view showing a display device according to an embodiment.

[0082] Figure 10 This is a view showing a display device according to an embodiment.

[0083] Figure 11 This is a view showing a display device according to an embodiment.

[0084] Figure 12 It is a view (e.g., a plan view) showing the display area in the display device according to an embodiment.

[0085] Figure 13 This is a view showing the display area in a display device according to an embodiment.

[0086] Figure 14 This is a view showing the display area in a display device according to an embodiment.

[0087] Figure 15 This is a view showing the display area in a display device according to an embodiment.

[0088] Figure 16 It is a schematic diagram (e.g., a plan view) showing the structure of the drive voltage connection lines, drive voltage lines and first common voltage lines in the display area.

[0089] Figure 17 This is a schematic view illustrating the structure of the drive voltage connection line, drive voltage line, first common voltage line and second common voltage line within the display area of ​​a display device according to an embodiment.

[0090] Figure 18 This is a view schematically illustrating the structure of the drive voltage connection line, drive voltage line, and first common voltage line within the display area of ​​a display device according to an embodiment.

[0091] Figure 19 This is a schematic view illustrating the structure of the drive voltage connection line, drive voltage line, first common voltage line and second common voltage line within the display area of ​​a display device according to an embodiment.

[0092] Figure 20 This is an equivalent circuit diagram of a pixel of the transmitting display device according to an embodiment.

[0093] Figure 21 This is a layout diagram of a pixel region of an organic light-emitting device according to an embodiment.

[0094] Figure 22 It is according to the embodiment along Figure 21 The cross-sectional view taken from line XXII-XXII' in the diagram.

[0095] Figure 23 This is a layout diagram of the pixel area of ​​a display device according to an embodiment. Detailed Implementation

[0096] The embodiments are described with reference to the accompanying drawings. The described embodiments can be modified in various ways.

[0097] The same or similar elements may be represented by the same reference numerals.

[0098] The dimensions may be exaggerated in the accompanying drawings for clarity.

[0099] Although the terms "first," "second," etc., may be used to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. A first element may be referred to as a second element without departing from the teachings of one or more embodiments. Describing an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first," "second," etc., may be used to distinguish different categories or groups of elements. For the sake of brevity, the terms "first," "second," etc., may respectively represent "first type (or first group)," "second type (or second group)," etc.

[0100] When the first element is referred to as being "on" the second element, the first element may be directly on the second element, or there may be one or more intermediate elements between the first element and the second element. When the first element is referred to as being "directly on" the second element, there are no intermediate elements between the first element and the second element (except for environmental elements such as air).

[0101] Unless explicitly stated otherwise, the words “including,” “contains,” “comprising,” or “has” may imply the inclusion of the stated element, but do not exclude any other element.

[0102] The term "external common voltage line" can mean "external common voltage trunk line". The term "connection" can mean "electrical connection". The term "insulation" can mean "electrical insulation" or "electrical isolation". The term "groove" can mean "opening" or "hole". The term "opening" can mean "gap". The term "same as" can mean "substantially the same as", "substantially identical to", or "similar to".

[0103] Figure 1 This is a view showing a display device 1000 according to an embodiment. (Refer to...) Figure 1 The display device 1000 includes a display area DA and a non-display area NDA. The substrate of the display device 1000 (e.g., Figure 22 The substrate 110 shown may include display areas and non-display areas corresponding to display area DA and non-display area NDA, respectively.

[0104] Reference Figure 1 An external common voltage line 7410 can substantially surround the display area DA. The external common voltage line 7410 is connected to a first common voltage line 741a and a second common voltage line 741b disposed in the display area DA. The external common voltage line 7410 applies a common voltage ELVSS (in...) in the display area DA. Figure 20 (as shown in the image).

[0105] exist Figure 1 For ease of description, only some first common voltage lines 741a and some second common voltage lines 741b are shown, but the first common voltage lines 741a and the second common voltage lines 741b can form a grid over the entire display area DA. In an embodiment, either the first common voltage line 741a or the second common voltage line 741b may be provided in the display area DA, but not both may be provided in the display area DA.

[0106] Each first common voltage line 741a may be longitudinal in the second direction DR2, and each second common voltage line 741b may be longitudinal in the first direction DR1. The third direction DR3 is perpendicular to the plane formed by the first direction DR1 and the second direction DR2.

[0107] exist Figure 1 For clarity, the portion marked with A is enlarged and shown separately. (See reference...) Figure 1 On one edge of the display device 1000, the external common voltage line 7410 is directly connected to the first external common voltage line 7410a and the second external common voltage line 7410b. For example... Figure 1As shown, on one edge of the pad portion connected to the display device 1000, the external common voltage line 7410 can be directly connected to the first external common voltage line 7410a and the second external common voltage line 7410b.

[0108] Reference Figure 1 Part B, the external common voltage line 7410 includes a recess 7410c. (See reference...) Figure 1 The groove 7410c can be longitudinal in the direction parallel to the second common voltage line 741b, that is, longitudinal in the first direction DR1.

[0109] The groove 7410c is disposed between a plurality of first common voltage lines 741a and a second external common voltage line 7410b, thereby extending the electrical path between the plurality of first common voltage lines 741a and the second external common voltage line 7410b.

[0110] Therefore, potential heat generation problems caused by excessive current flowing simultaneously to the second external common voltage line 7410b can be prevented or mitigated. Advantageously, satisfactory reliability and / or durability of the display device 1000 can be obtained.

[0111] Figure 2 This is a view illustrating the current flow in a display device 1000 according to an embodiment. In the display device 1000, the external common voltage line 7410 is not included. Figure 1 The groove shown is indicated by the arrow. Figure 2 The flow of current in the display device 1000 is shown. Figure 2 In the diagram, the thickness of the arrow indicates the amount of current, and the location where significant heat is generated is indicated by C.

[0112] Reference Figure 2 Near the second external common voltage line 7410b, current flowing from the external common voltage line 7410 (located in the non-display area NDA) and current flowing from the first common voltage line 741a (at least partially located in the display area DA) are collected. Regarding the first external common voltage line 7410a, since the current flowing from the external common voltage line 7410 flows out to the second external common voltage line 7410b, only the current flowing from the common voltage line 741a is collected.

[0113] Therefore, the current flowing toward the second external common voltage line 7410b is greater than the current flowing toward the first external common voltage line 7410a, and thus, the heat generation near the second external common voltage line 7410b is more significant.

[0114] Reference Figure 1 and Figure 3By providing a groove 7410c between the second external common voltage line 7410b and the multiple first common voltage lines 741a, the current in the first common voltage line 741a may not flow significantly to the second external common voltage line 7410b, but may instead flow to the first external common voltage line 7410a. Therefore, excessive heat generation can be prevented or mitigated.

[0115] Figure 3 This is a view illustrating the flow of current in a display device according to an embodiment. (Comparison) Figure 3 and Figure 2 ,exist Figure 3 In the embodiment, the current flowing to the second external common voltage line 7410b is significantly less than that in Figure 2 In the embodiment, the amount of current flowing to the second external common voltage line 7410b. Therefore, according to Figure 3 The embodiments can effectively prevent or reduce excessive heat generation on the external common voltage line 7410.

[0116] Figure 4 This illustrates the relationship between the display device and the embodiment of the present invention. Figure 1 A view of the same location as area A. (Refer to...) Figure 4 In the display device, the first external common voltage line 7410a and the second external common voltage line 7410b are separate and / or directly connected to separate trunk lines.

[0117] Reference Figure 4 The opening 7410d can separate the first external common voltage line 7410a from the second external common voltage line 7410b. The opening 7410d includes an edge parallel to the first direction DR1 and an edge parallel to the second direction DR2.

[0118] Reference Figure 4 The current in the first common voltage line 741a is transferred to the first external common voltage line 7410a and not to the second external common voltage line 7410b. Therefore, unwanted heat generation can be prevented or mitigated near the second external common voltage line 7410b.

[0119] Figure 5 This illustrates the relationship between the display device and the embodiment of the present invention. Figure 1 The view of the same location as area A.

[0120] Reference Figure 5The first external common voltage line 7410a and the second external common voltage line 7410b are completely separated from each other via an opening 7410d, which may have opposing edges parallel to the second direction DR2. Therefore, the amount of current flowing into the first external common voltage line 7410a and the amount of current flowing into the second external common voltage line 7410b can be appropriately controlled to prevent excessive heat generation. Even though the first external common voltage line 7410a and the second external common voltage line 7410b are separated from each other, as... Figure 1 As shown, the first external common voltage line 7410a and the second external common voltage line 7410b are still connected to each other in the display area DA via the second common voltage line 741b disposed in the display area DA. Therefore, the common voltage transmitted by the first external common voltage line 7410a is equal to the common voltage transmitted by the second external common voltage line 7410b.

[0121] Reference Figure 5 The total number of first common voltage lines 741a directly connected to the first external common voltage line 7410a may be equal to or not equal to the total number of first common voltage lines 741a directly connected to the second external common voltage line 7410b. The number of first common voltage lines 741a directly connected to the first external common voltage line 7410a may be significantly greater than the number of first common voltage lines 741a directly connected to the second external common voltage line 7410b. In embodiments, no first common voltage line 741a may be directly connected to the second external common voltage line 7410b, and some first common voltage lines 741a may be directly connected only to the first external common voltage line 7410a. The number of first common voltage lines 741a directly connected to the first external common voltage line 7410a and the number of first common voltage lines 741a directly connected to the second external common voltage line 7410b may be suitably selected to minimize heat at the second external common voltage line 7410b.

[0122] Figure 6 This is a view showing a display device 1000 according to an embodiment, including an external common voltage line 7410, an external drive voltage line 1720, and an external initialization voltage line 1270. Figure 6 For ease of illustration, only some wiring is shown in the diagram.

[0123] Reference Figure 6 In the non-display area NDA outside the display area DA, the external common voltage line 7410 can substantially surround the display area DA. The external drive voltage line 1720 can be disposed between opposite portions of the external common voltage line 7410.

[0124] The first external common voltage line 7410a and the second external common voltage line 7410b can protrude from the external common voltage line 7410, and a groove 7410c is provided between the first external common voltage line 7410a and the second external common voltage line 7410b. The external common voltage line 7410 can be connected to the first common voltage line 741a and the second common voltage line extending to the display area DA (similar to...). Figure 1 The second common voltage line 741b is shown in the figure. In the display area DA, the first common voltage line 741a can be longitudinal in the second direction DR2, and the second common voltage line can be longitudinal in the first direction DR1.

[0125] The external drive voltage line 1720 can be positioned between opposite ends of the external common voltage line 7410. The external drive voltage line 1720 can be positioned within the space between opposite portions of the external common voltage line 7410. The external drive voltage line 1720 transmits the drive voltage ELVDD to the display area DA.

[0126] External drive voltage line 1720 is directly connected to drive voltage line 172, which can be at least partially located in the display area DA. Drive voltage line 172 can be vertical in the second direction DR2. (Refer to...) Figure 6 and Figure 12 The driving voltage connection line 172c can be longitudinal in the first direction DR1 and can be at least partially disposed in the display area DA. The driving voltage connection line 172c can intersect with the driving voltage line 172 to uniformly transmit the driving voltage in the display area DA. The driving voltage line 172 and the driving voltage connection line 172c form a grid in the display area DA and are connected to each other, so that pixels not directly connected to the driving voltage line 172 can also receive the driving voltage ELVDD.

[0127] An external initialization voltage line 1270 is disposed between the external common voltage line 7410 and the display area DA. The external initialization voltage line 1270 is directly connected to the initialization voltage line 127, which may be at least partially disposed within the display area DA and may transmit the initialization voltage to the display area DA. The initialization voltage line 127 may be longitudinal in the first direction DR1.

[0128] Despite Figure 6 Not shown, but the second common voltage line running longitudinally along the first direction DR1 can be at least partially disposed in the display area DA. Configuration can be made according to embodiments. Figure 6 The number and location of the wiring / line shown.

[0129] Despite Figure 6Only portions of the first common voltage line 741a are shown, but the first common voltage line 741a can be connected to portions of the external common voltage line 7410 located on opposite sides of the display area DA. The drive voltage line 172 can also extend from one edge of the display area DA to the other edge of the display area DA in the second direction DR2. In an embodiment, the external initialization voltage line 1270 can be located on both sides or more sides of the display area DA. The initialization voltage line 127 can extend from one edge of the display area DA to the other edge of the display area DA in the first direction DR1.

[0130] Figure 7 This is a view illustrating a display device according to an embodiment. (Refer to...) Figure 7 The first external common voltage line 7410a and the second external common voltage line 7410b are separated by a gap / opening. The first common voltage line 741a can not be directly connected to the second external common voltage line 7410b.

[0131] The first external common voltage line 7410a and the second external common voltage line 7410b are separated by an opening 7410d, which may have opposite edges parallel to the first direction DR1 and opposite edges parallel to the second direction DR2. Current from the first common voltage line 741a is transmitted to the first external common voltage line 7410a. Therefore, current is not concentrated in the second external common voltage line 7410b, and excessive heat generation is prevented. The first external common voltage line 7410a and the second external common voltage line 7410b can be electrically connected to each other via the second common voltage line 741b disposed in the display area DA; therefore, the common voltage transmitted by the first external common voltage line 7410a is equal to the common voltage transmitted by the second external common voltage line 7410b.

[0132] Figure 8 This is a view illustrating a display device according to an embodiment. (Refer to...) Figure 8 The first external common voltage line 7410a and the second external common voltage line 7410b are separate. (Refer to...) Figure 8 The opening 7410d can have opposing edges longitudinally in the second direction DR2. The operation and effect are similar to... Figure 7 The operation and effects in the embodiments.

[0133] Figure 9 This is a view illustrating a display device according to an embodiment. (Refer to...) Figure 9 The external common voltage line 7410 is located on the opposite side of the display area DA.

[0134] The display area DA can be set between the external common voltage lines 7410, but not on the first direction DR1. (Refer to...) Figure 9 The external common voltage line 7410 may include a first external common sub-voltage line 7410_S1 and a second external common sub-voltage line 7410_S2.

[0135] The first external common sub-voltage line 7410_S1 and the second external common sub-voltage line 7410_S2 can be electrically connected through the first common voltage line 741a, which can be at least partially disposed in the display area DA. Therefore, the common voltage ELVSS can be provided substantially uniformly above the display area DA. Since no external common voltage lines are disposed on the left and right sides of the display area DA, the left and right non-display areas NDA can be minimized.

[0136] Figure 10 This is a view illustrating a display device according to an embodiment. (Refer to...) Figure 10 The first external common sub-voltage line 7410_S1 and the second external common sub-voltage line 7410_S2 are located on opposite sides of the display area DA. The second external common sub-voltage line 7410_S2 is spaced apart in the first direction DR1 and the second direction DR2. The effect of separating the external common voltage line 7410 is similar to that of the reference. Figure 9 The effects described are the same or similar.

[0137] Figure 11 This is a view illustrating a display device according to an embodiment. (Refer to...) Figure 11 The first external common sub-voltage line 7410_S1 and the second external common sub-voltage line 7410_S2 are located on opposite sides of the display area DA. The second external common sub-voltage line 7410_S2 is spaced apart in the first direction DR1. The separation effect of the external common voltage line 7410 is related to... Figure 9 The effects described herein are the same or similar.

[0138] Reference Figures 12 to 15 One or more structures of the display area DA described in one or more of the accompanying drawings can be applied to reference. Figures 6 to 11 The display area DA is described in one or more of the accompanying drawings.

[0139] Figure 12 This is a view showing the display area DA in a display device according to an embodiment. (Refer to...) Figure 12 One of the driving voltage lines 172 connected to the multiple pixels PX1, PX2, and PX3 is replaced with a first common voltage line 741a. Therefore, an external common voltage line 7410 set along the second direction DR2 via the display area DA can be connected. When the separate external common voltage line 7410 is set on opposite sides of the display area DA, as... Figures 9 to 11As shown, the first common voltage line 741a can be electrically connected to the isolated external common voltage line 7410. (Refer to...) Figures 6 to 8 Even if the external common voltage line 7410 is electrically connected in the non-display area NDA, the common voltage is still transmitted to the first common voltage line 741a inside the display area DA, so that the common voltage can be uniformly provided in the display area DA.

[0140] Reference Figure 12 The driving voltage connection line 172c can cross the driving voltage line 172. The driving voltage connection line 172c can be electrically connected to the driving voltage line 172 at the intersection point. Therefore, the driving voltage transmitted to the driving voltage line 172 can be transmitted to adjacent pixels. The driving voltage connection line 172c can be located on a different layer than the driving voltage line 172.

[0141] Figure 13 This is a view showing the display area DA in a display device according to an embodiment. In addition to further including a second common voltage line 741b, Figure 13 The display area DA according to the embodiment and Figure 12 The embodiments are the same. The first common voltage line 741a can be configured to be parallel to the second direction DR2, and the second common voltage line 741b can be configured to be parallel to the first direction DR1.

[0142] Figure 13 The display device according to an embodiment includes a grid structure where a first common voltage line 741a and a second common voltage line 741b intersect. In this case, a decrease in the common voltage ELVSS can be effectively prevented. The common voltage ELVSS is uniformly transmitted to the pixels in the display area DA along the common voltage lines 741a and 741b with the grid structure.

[0143] Figure 14 This is a view showing the display area DA in a display device according to an embodiment. (Refer to...) Figure 14 Display device and Figure 12 The difference in the display device is that the structure (and / or material) of the first common voltage line 741a can be substantially different from the structure (and / or material) of each of the driving voltage lines 172 connected to pixels PX1, PX2, and PX3. The first common voltage line 741a can be formed without removing any existing driving voltage lines 172.

[0144] Figure 15 This is a view showing the display area DA in a display device according to an embodiment. Except that a first common voltage line 741a is formed separately in the display area DA without removing the driving voltage line 172, Figure 15 and Figure 13The display device according to the embodiment is the same.

[0145] exist Figures 12 to 15 In this configuration, the driving voltage connection line 172c, the driving voltage line 172, and the first common voltage line 741a can be directly disposed on different material layers. Although the driving voltage connection line 172c and the driving voltage line 172 are disposed on different layers, they are connected to each other through contact holes, allowing for uniform transmission of the driving voltage.

[0146] Figure 16 This is a schematic view showing the structure of the drive voltage connection line 172c, drive voltage line 172, and first common voltage line 741a in the display area. Figure 16 In this process, pixels PX1, PX2, and PX3 are marked to distinguish the pixels to which the wiring is connected.

[0147] Reference Figure 16 The driving voltage connection line 172c, driving voltage line 172, and first common voltage line 741a are located on different layers. For example, driving voltage connection line 172c can be disposed between the substrate and driving voltage line 172; driving voltage connection line 172c and driving voltage line 172 can be disposed between the substrate and first common voltage line 741a. In an embodiment, driving voltage line 172 and first common voltage line 741a can be directly disposed on the same layer.

[0148] Reference Figure 16 The width of the drive voltage connection line 172c overlapping with the first common voltage line 741a can be narrower than the width of the drive voltage connection line 172c overlapping with the drive voltage line 172. Therefore, the risk of a short circuit between the first common voltage line 741a and the drive voltage connection line 172c can be reduced. The drive voltage connection line 172c and the drive voltage line 172 are connected to each other through the contact hole 28.

[0149] Figure 17 This is a schematic view illustrating the structure of the drive voltage connection line 172c, drive voltage line 172, first common voltage line 741a, and second common voltage line 741b within the display area of ​​a display device according to an embodiment. The first common voltage line 741a is connected to the second common voltage line 741b.

[0150] The first common voltage line 741a and the second common voltage line 741b can be disposed on the same layer and can be directly connected to each other. The common voltage lines 741a and 741b can form a grid. The common voltage lines 741a and 741b can be separated from and insulated from the driving voltage line 172 through an intermediate insulating layer. The driving voltage line 172 can be disposed closer to the substrate than the common voltage lines 741a and 741b.

[0151] Figure 18 This is a schematic view illustrating the structure of the driving voltage connection line 172c, driving voltage line 172, and first common voltage line 741a within the display area of ​​a display device according to an embodiment. (Refer to...) Figure 18 A first common voltage line 741a is disposed outside pixels PX1, PX2, and PX3. The first common voltage line 741a is disposed without removing the existing driving voltage lines 172. Each driving voltage line 172 is connected to either pixel PX1, PX2, or PX3, and the first common voltage line 741a is disposed between two pixel groups, each pixel group including pixels PX1, PX2, and PX3. The first common voltage line 741a can be directly disposed on the same layer as the driving voltage lines 172.

[0152] Figure 19 This is a schematic view illustrating the structure of the driving voltage connection line 172c, driving voltage line 172, and first common voltage line 741a within the display area of ​​a display device according to an embodiment. The common voltage line includes a first common voltage line 741a and a second common voltage line 741b.

[0153] The first common voltage line 741a and the second common voltage line 741b can be disposed on the same layer and can be directly connected to each other. The display device may include a grid structure in which the first common voltage line 741a intersects with the second common voltage line 741b. The common voltage lines 741a and 741b can be separated from and insulated from the driving voltage line 172 by an intermediate insulating layer. The driving voltage line 172 may be positioned closer to the substrate than the common voltage lines 741a and 741b.

[0154] Figure 20 This is an equivalent circuit diagram of a pixel of the transmitting display device according to an embodiment.

[0155] Reference Figure 20 The pixel PX of the emission display device includes multiple transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst and a light-emitting diode LED. The multiple transistors T1, T2, T3, T4, T5, T6 and T7, the storage capacitor Cst and the light-emitting diode LED are connected to several signal lines 127, 151, 152, 153, 158, 171, 172 and 741.

[0156] The transmitting display device includes a display area for displaying images, and these pixels PX are arranged in various forms in the display area.

[0157] The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, a switching transistor connected to scan line 151 (i.e., including the second transistor T2 and the third transistor T3), and the remaining transistors are transistors required to operate the light-emitting diode (LED) (hereinafter referred to as compensation transistors). The compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0158] Multiple signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include scan line 151, previous scan line 152, light emission control line 153, bypass control line 158, data line 171, drive voltage line 172, initialization voltage line 127, and common voltage line 741. The bypass control line 158 may be part of the previous scan line 152, or may be electrically connected to the previous scan line 152.

[0159] Scan line 151 is connected to the gate driver and transmits the scan signal Sn to the second transistor T2 and the third transistor T3. Previous scan line 152 is connected to the gate driver and transmits the previous scan signal Sn-1 applied to the pixel PX located at the previous stage to the fourth transistor T4. Light emission control line 153 is connected to the light emission controller and transmits the light emission control signal EM, which controls the timing of LED illumination, to the fifth transistor T5 and the sixth transistor T6. Bypass control line 158 transmits the bypass signal GB to the seventh transistor T7.

[0160] Data line 171 is used to transmit the data voltage Dm generated by the data driver, and the brightness of the light-emitting diode (LED) (also called a light-emitting element) varies according to the data voltage Dm. Drive voltage line 172 applies the drive voltage ELVDD. Initialization voltage line 127 transmits the initialization voltage Vint that initializes the drive transistor T1. Common voltage line 741 applies the common voltage ELVSS. The voltages applied to drive voltage line 172, initialization voltage line 127, and common voltage line 741 can each be applied at a constant voltage.

[0161] The driving transistor T1 is used to regulate the magnitude of the output current based on the applied data voltage Dm. The output driving current Id is applied to the light-emitting diode (LED) to adjust the brightness of the LED according to the data voltage Dm. For this purpose, the first electrode S1 of the driving transistor T1 allows the application of a driving voltage ELVDD. The first electrode S1 is connected to the driving voltage line 172 via the fifth transistor T5. Additionally, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2 to receive the data voltage Dm. The second electrode D1 (output electrode) of the driving transistor T1 can output current towards the LED. The second electrode D1 of the driving transistor T1 is connected to the anode of the LED via the sixth transistor T6. On the other hand, the gate electrode G1 is connected to one electrode (second storage electrode E2) of the storage capacitor Cst. The voltage of the gate electrode G1 changes according to the voltage stored in the storage capacitor Cst, and thus is changed by the driving current Id output by the driving transistor T1.

[0162] The second transistor T2 receives the data voltage Dm into pixel PX. Gate electrode G2 is connected to scan line 151, and first electrode S2 is connected to data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through scan line 151, it transmits the data voltage Dm transmitted through data line 171 to the first electrode S1 of the driving transistor T1.

[0163] The third transistor T3 transfers the compensation voltage (Dm+Vth) from the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst, where Vth is the threshold voltage of the driving transistor T1, which is not within the threshold voltage range of the driving transistor T1. Figure 20 As shown in the diagram, the gate electrode G3 is connected to the scan line 151, and the first electrode S3 is connected to the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is turned on according to the scan signal Sn received through the scan line 151 to connect the gate electrode G1 and the second electrode D1 of the driving transistor T1, and also to connect the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst.

[0164] A fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 is connected to the previous scan line 152, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the previous scan signal Sn-1 received via the previous scan line 152. Therefore, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint has a low voltage value, thus being the voltage that turns on the driving transistor T1.

[0165] The fifth transistor T5 is used to transmit the drive voltage ELVDD to the drive transistor T1. Its gate electrode G5 is connected to the light-emitting control line 153, and its first electrode S5 is connected to the drive voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the drive transistor T1.

[0166] The sixth transistor T6 is used to transfer the drive current Id output from the driving transistor T1 to the light-emitting diode (LED). The gate electrode G6 is connected to the light-emitting control line 153, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the LED.

[0167] If the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light-emitting control signal EM transmitted through the light-emitting control line 153, and the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, then the driving transistor T1 outputs a driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (i.e., the voltage of the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transmitted to the light-emitting diode LED through the sixth transistor T6. When the current Id flows through the light-emitting diode LED, the light-emitting diode LED emits light.

[0168] The seventh transistor T7 is used to initialize the anode of the light-emitting diode (LED). The gate electrode G7 is connected to the bypass control line 158, the first electrode S7 is connected to the anode of the LED, and the second electrode D7 is connected to the initialization voltage line 127. The bypass control line 158 can be connected to the previous scan line 152 and applies a bypass signal GB with the same timing as the previous scan signal Sn-1. The bypass control line 158 can transmit a signal separate from the previous scan signal Sn-1 without being connected to the previous scan line 152. When the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode of the LED and initialized.

[0169] The first storage electrode E1 of the storage capacitor Cst is connected to the drive voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the drive transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. Therefore, the second storage electrode E2 determines the voltage of the gate electrode G1 of the drive transistor T1, and receives the data voltage Dm through the second electrode D3 of the third transistor T3, or the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0170] On the other hand, the anode of the light-emitting diode (LED) is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7, and the cathode is connected to the common voltage line 741 that transmits the common voltage ELVSS.

[0171] exist Figure 20 In one embodiment, the pixel circuit includes seven transistors (T1 to T7) and one capacitor Cst. The number of transistors, the number of capacitors, and their connections can be configured according to the embodiment.

[0172] Figure 21 This is a layout diagram of a pixel region of an organic light-emitting device according to an embodiment, and Figure 22 It is according to the embodiment along Figure 21 The cross-sectional view taken from line XXII-XXII' in the diagram.

[0173] Reference Figure 21 The transmitting display device includes: a scan line 151 extending along a first direction D1 and transmitting a scan signal Sn; a previous scan line 152 transmitting a previous scan signal Sn-1; a light emission control line 153 transmitting a light emission control signal EM; and an initialization voltage line 127 transmitting an initialization voltage Vint. A bypass signal GB is transmitted through the previous scan line 152.

[0174] The transmitting display device includes: a data line 171 extending in a second direction DR2 intersecting the first direction DR1 and transmitting a data voltage Dm, and a first common voltage line 741a transmitting a common voltage ELVSS. Figure 21 and Figure 22 The first pixel PX1 described herein is the first pixel PX1 in which the driving voltage line 172 is replaced with the first common voltage line 741a. Figure 21 and Figure 22 The first pixel PX1 is an embodiment in which the driving voltage line 172 connected to that pixel is replaced with a first common voltage line 741a. Figure 21 In the second pixel PX2 shown, the driving voltage line 172 is not replaced with the first common voltage line 741a, and the existing driving voltage line 172 is used. The first pixel PX1 is described below in comparison to the second pixel PX2.

[0175] The transmitting display device includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light-emitting diode (LED).

[0176] Each channel of driving transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 is disposed within the elongated semiconductor layer 130. Furthermore, at least a portion of the first and second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 are disposed within the semiconductor layer 130. Semiconductor layer 130 ( Figure 21 The shaded portion (of which) can be formed into various shapes. Semiconductor layer 130 may include polycrystalline semiconductors such as polycrystalline silicon or oxide semiconductors.

[0177] Semiconductor layer 130 includes a channel doped with n-type or p-type impurities, and a first doped region and a second doped region with a doping concentration higher than that of the channel. The first doped region and the second doped region correspond to the first electrode and the second electrode of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, respectively. One of the first doped regions and the second doped region can be a source region, and the other doped region can be a drain region. Moreover, in semiconductor layer 130, the region between the first electrode and the second electrode of different transistors can be doped, so that the two transistors can be electrically connected to each other.

[0178] Each channel of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 overlaps with the gate electrode of each transistor T1, T2, T3, T4, T5, T6, and T7, and is disposed between the first and second electrodes of each transistor T1, T2, T3, T4, T5, T6, and T7. The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 may have substantially the same stacked structure. In the following description, the driving transistor T1 is described in detail, while the remaining transistors T2, T3, T4, T5, T6, and T7 are described briefly.

[0179] The driving transistor T1 includes a channel, a first gate electrode 155, a first electrode S1, and a second electrode D1. The channel of the driving transistor T1 lies between the first electrode S1 and the second electrode D1, and overlaps with the first gate electrode 155 in a planar view. The channel is bent to form a longer channel length in a confined area. As the channel length increases, the driving range of the gate voltage Vg applied to the first gate electrode 155 of the driving transistor T1 becomes wider, and the driving current Id increases constantly according to the gate voltage Vg. Therefore, the grayscale of the light emitted from the light-emitting diode (LED) can be controlled more precisely by changing the magnitude of the gate voltage Vg, and the display quality of the emission display device can be improved. In addition, since the channel extends in all directions instead of in one direction, there is an advantage in eliminating the directional effect in the manufacturing process, thereby reducing the effect of process dispersion. Therefore, it is possible to prevent image quality degradation such as non-uniformity defects (e.g., brightness differences depending on the pixel even when the same data voltage Dm is applied), which may be caused by characteristic differences in the driving transistors T1 depending on the region of the display device due to process dispersion. The shape of this channel can be varied and is not limited to the Ω type shown.

[0180] The first gate electrode 155 overlaps with the channel in a plane. The first electrode S1 and the second electrode D1 are located on their respective sides of the channel. An extension of the storage line 126 is insulated from the first gate electrode 155 and is disposed above the first gate electrode 155. The extension of the storage line 126 overlaps with the gate electrode 155 in a plane via a second gate insulating layer therebetween, thereby forming a storage capacitor Cst. The extension of the storage line 126 is the first storage electrode of the storage capacitor Cst. Figure 20 E1), and the first gate electrode 155 is the second storage electrode ( Figure 20(E2). An extension of the storage line 126 has an opening 56, such that the first gate electrode 155 is connected to the first data connection member 71. Within the opening 56, the upper surface of the first gate electrode 155 and the first data connection member 71 are electrically connected through a contact hole 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0181] The gate electrode of the second transistor T2 can be part of the scan line 151. The data line 171 contacts the first electrode S2 of the second transistor T2 through the contact hole 62. The first electrode S2 and the second electrode D2 can be disposed on the semiconductor layer 130.

[0182] The third transistor T3 can be composed of two adjacent transistors. Figure 21 Within pixel PX, the two portions of the third transistor T3, bent relative to semiconductor layer 130, are located on the left and bottom sides. These two portions respectively function as the third transistor T3, and have a structure in which the first electrode S3 of one portion of the third transistor T3 is connected to the second electrode D3 of the other portion of the third transistor T3. The gate electrodes of the two transistors T3 can be a portion of scan line 151 or a portion protruding upwards from scan line 151. This structure can be referred to as a dual-gate structure and can be used to block leakage current. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through contact hole 63.

[0183] The fourth transistor T4 consists of two fourth transistors T4, which are formed at the intersection of the previous scan line 152 and the semiconductor layer 130. The gate electrode of the fourth transistor T4 may be a portion of the previous scan line 152. A portion of the first electrode S4 of the fourth transistor T4 is connected to the second electrode D4 of the other portion of the fourth transistor T4. This structure can be referred to as a dual-gate structure and can be used to block leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through a contact hole 65, and the first data connection member 71 is connected to the second electrode D4 of the fourth transistor T4 through a contact hole 63.

[0184] In this way, by using a dual-gate structure as the third transistor T3 and the fourth transistor T4, leakage current can be effectively prevented by blocking the electron movement path of the channel in the off state.

[0185] The gate electrode of the fifth transistor T5 can be part of the light-emitting control line 153. The drive voltage connection line 172c is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 77, and the second electrode D5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0186] Since the driving voltage line 172 connected to the pixel is replaced with the first common voltage line 741a, the first pixel PX1 receives the driving voltage ELVDD from the adjacent pixel PX2 through the driving voltage connection line 172c connected to the driving voltage line 172 of the adjacent pixel PX2.

[0187] However, in the second pixel PX2, the driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 67, and the second electrode D5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0188] The gate electrode of the sixth transistor T6 may be part of the light-emitting control line 153. The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1 through the semiconductor layer 130.

[0189] The gate electrode of the seventh transistor T7 may be part of the previous scan line 152. The first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6, and the second electrode D7 is connected to the first electrode S4 of the fourth transistor T4.

[0190] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2, which overlap with a second gate insulating layer 142 interposed therebetween. The second storage electrode E2 may correspond to the gate electrode 155 of the driving transistor T1, and the first storage electrode E1 may be an extension of the storage line 126. The second gate insulating layer 142 serves as a dielectric material, and the capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the first gate electrode 155 as the second storage electrode E2, space for forming the storage capacitor Cst can be secured within the space narrowed by the channel of the driving transistor T1, which occupies a large area in the pixel.

[0191] The first storage electrode E1 of the storage capacitor Cst receives a driving voltage via the driving voltage connection line 172c. Therefore, the storage capacitor Cst stores a charge corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 via the driving voltage connection line 172c and the gate voltage Vg of the gate electrode 155.

[0192] However, the drive voltage line 172 is connected to the first storage electrode E1 of the storage capacitor Cst through the contact hole 68. Therefore, the storage capacitor Cst stores a charge corresponding to the difference between the drive voltage ELVDD transmitted to the first storage electrode E1 through the drive voltage line 172 and the gate voltage Vg of the gate electrode 155.

[0193] The second data connection member 72 is connected to the initialization voltage line 127 via contact hole 64. The first electrode is connected to the third data connection member 73 via contact hole 81. The first electrode may be a pixel electrode.

[0194] A parasitic capacitor control pattern 79 can be set between the dual gate electrodes of the third transistor T3. Parasitic capacitors exist within pixels. If the voltage applied to the parasitic capacitor changes, the image quality characteristics may change. Figure 21 In the first pixel PX1, a first common voltage line 741a is provided to replace the driving voltage line 172, such that the driving voltage line 172 and the parasitic capacitor control pattern 79 are not connected. However, in the second pixel PX2, the parasitic capacitor control pattern 79 is connected to the driving voltage line 172 through a contact hole 66. Therefore, by applying a driving voltage ELVDD with a constant DC voltage to the parasitic capacitor, changes in image quality characteristics can be prevented. The parasitic capacitor control pattern 79 can be set in a region different from the area shown, and a voltage other than the driving voltage ELVDD can be applied.

[0195] One end of the first data connection member 71 is connected to the gate electrode 155 through the contact hole 61, and the other end is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the contact hole 63.

[0196] One end of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the other end is connected to the initialization voltage line 127 through the contact hole 64.

[0197] The third data connection member 73 is connected to the second electrode of the sixth transistor T6 through the contact hole 69.

[0198] Reference Figure 22 as well as Figure 21 The cross-sectional structure of the transmitting display device according to an embodiment is described.

[0199] The transmission display device includes a first substrate 110.

[0200] The first substrate 110 may include a plastic layer and a barrier layer. The plastic layer and the barrier layer may be stacked alternately.

[0201] The plastic layer may include one selected from the group consisting of polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), poly(arylene ether sulfone), and combinations thereof.

[0202] The barrier layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide, and may include any inorganic material, but is not limited thereto.

[0203] A buffer layer 112 is disposed on the first substrate 110. The buffer layer 112 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide, or an organic insulating material such as polyimide acrylic resin.

[0204] A semiconductor layer 130, including channels of multiple transistors T1, T2, T3, T4, T5, T6 and T7, as well as a first electrode and a second electrode, is disposed on a buffer layer 112.

[0205] A first gate insulating layer 141 is provided on the semiconductor layer 130 to cover the semiconductor layer 130. A first gate conductor including a first gate electrode 155, a scan line 151, a previous scan line 152 and a light emission control line 153 is provided on the first gate insulating layer 141.

[0206] A second gate insulating layer 142 is disposed on the first gate conductor, covering the first gate conductor. The first gate insulating layer 141 and the second gate insulating layer 142 may comprise inorganic insulating materials or organic insulating materials such as silicon nitride, silicon oxide, and aluminum oxide.

[0207] A second gate conductor, including a storage line 126, an initialization voltage line 127, and a parasitic capacitor control pattern 79, is disposed on the second gate insulating layer 142.

[0208] An interlayer insulating layer 160 covering the second gate conductor is disposed on the second gate conductor. The interlayer insulating layer 160 may include inorganic insulating materials such as silicon nitride, silicon oxide, and aluminum oxide, or may include organic insulating materials.

[0209] A data conductor, including a data line 171, a drive voltage line 172, a drive voltage connection line 172c, a first data connection member 71, a second data connection member 72, and a third data connection member 73, is disposed on the interlayer insulating layer 160. The first data connection member 71 can be connected to the first gate electrode 155 through a contact hole 61.

[0210] A passivation layer 180 is provided on the data conductor to cover the data conductor. The passivation layer 180 may be a planarization layer and may include organic insulating material or inorganic insulating material.

[0211] A first electrode 191 is disposed on the passivation layer 180. The first electrode 191 is connected to the third data connection member 73 through a contact hole 81 formed in the passivation layer 180.

[0212] A separator 350 is formed on the passivation layer 180 and the first electrode 191. The separator 350 has an opening 351 that overlaps with the first electrode 191. An emission layer 370 is disposed on the opening 351. A second electrode 270 is disposed on the emission layer 370 and the separator 350. The first electrode 191, the emission layer 370, and the second electrode 270 form a light-emitting element (LED). The first electrode 191 may be a pixel electrode, and the second electrode 270 may be a common electrode.

[0213] According to an embodiment, the pixel electrode can be an anode serving as a hole injection electrode, and the common electrode can be a cathode serving as an electron injection electrode. Conversely, the pixel electrode can be a cathode and the common electrode can be an anode. When holes and electrons are injected into the emitter layer from the pixel electrode and the common electrode, respectively, the excitons formed by the injected holes and electrons emit light when they transition from the excited state to the ground state.

[0214] An encapsulation layer 400 protecting the light-emitting element LED is disposed on the second electrode 270. According to an embodiment, the encapsulation layer 400 can be as follows: Figure 22 The ground shown is in contact with the second electrode 270, or may be spaced apart from the second electrode 270.

[0215] The encapsulation layer 400 may be a thin-film encapsulation layer in which inorganic and organic films are stacked, and may include three layers consisting of an inorganic film, an organic film, and an inorganic film. According to an embodiment, a cover layer and a functional layer may be located between the second electrode 270 and the encapsulation layer 400.

[0216] Figure 23 This is a layout diagram of the pixel areas of a display device according to an embodiment. (Refer to...) Figure 23 The display device includes multiple signal lines 127, 151, 152, 153, 171, 172, and 741a. These signal lines 127, 151, 152, 153, 171, 172, and 741a may include a scan line 151, a previous scan line 152, and a light emission control line 153 disposed on a first direction DR1, and a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741a disposed on a second direction DR2.

[0217] The display device includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst.

[0218] Each channel of driving transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 extends and is disposed within semiconductor layer 130. At least a portion of the first and second electrodes of the plurality of transistors T1, T2, T3, T4, T5, and T6 are disposed in semiconductor layer 130.

[0219] The signal lines and semiconductor layers are connected through multiple contact holes 82, 83, 84, 85, 86, 87 and 88.

[0220] The structure of transistors and signal lines can be similar to Figure 21 The structure shown.

[0221] Reference Figure 23 The first common voltage line 741a is located outside the regions of pixels PX1, PX2, and PX3. That is, in Figure 21 In the display device of the embodiment, the driving voltage line 172 of some pixels PX1 is replaced with a first common voltage line 741a, and the pixel PX1 receives driving voltage from the neighboring pixel through the driving voltage connection line 172c.

[0222] The separate first common voltage line 741a is disposed outside the regions of pixels PX1, PX2, and PX3. Therefore, the first common voltage line 741a can be disposed without removing the existing driving voltage lines 172 of pixels PX1, PX2, and PX3.

[0223] Although exemplary embodiments have been described, practical embodiments are not limited to the disclosed embodiments. Practical embodiments cover various modifications and equivalent arrangements within the scope of this disclosure.

Claims

1. A display device, wherein, The display device includes: The substrate includes both the display area and the non-display area; Pixels are disposed on the display area; A first common voltage line is at least partially disposed on the display area; An external common voltage trunk line is disposed on the non-display area, electrically connected to the pixel via the first common voltage line, and includes a groove; A first external common voltage line protrudes from the external common voltage trunk line; and The second external common voltage line protrudes from the external common voltage trunk line. The groove is disposed between the second external common voltage line and the first common voltage line.

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