晶圆切割方法
By forming dicing grooves on the wafer and filling them with an etched protective layer, and then removing the packaging layer, a plasma cutting process is used to solve the problem of cutting narrow dicing channels, thus achieving low-cost cutting applicable to all types of 3D stacked packages.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SJ SEMICONDUCTOR (JIANGYIN) CORP
- Filing Date
- 2025-01-15
- Publication Date
- 2026-07-17
AI Technical Summary
With the advancement of semiconductor technology nodes, the width of the dicing channels on wafers is becoming increasingly narrow. General plasma cutting processes are insufficient to meet the wafer cutting requirements in 3D stacking packaging, especially when there is metal on the dicing channel, the dicing channel width is less than 5µm.
The process involves first cutting the wafer along the dicing track to form chip circuit units and dicing grooves, forming an etched protective layer, filling the encapsulation layer, removing the encapsulation layer on the dicing track, then using plasma cutting technology to cut the silicon substrate, and finally performing back-side thinning to separate the dicing track.
It is suitable for wafers with or without metal on the dicing track, meets the dicing requirements of all types of 3D stacked packaging, has a low cost, and solves the dicing problem of narrow dicing tracks.
Smart Images
Figure CN122421680A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a wafer dicing method. Background Technology
[0002] In hybrid bonding (HB) technology, wafer-to-wafer (W2W) bonding and chip-to-wafer (C2W) bonding are two main bonding methods. W2W bonding achieves electrical connection and physical stacking between wafers by directly bonding two wafers, making it particularly suitable for homogeneous or heterogeneous wafer stacking in mass production. C2W bonding, on the other hand, directly packages the chip onto the wafer, offering greater flexibility and adaptability to different types and sizes of chips, resulting in more diverse 3D stacking configurations.
[0003] Currently, in C2W bonding technology, the wafer needs to be diced into individual chips before hybrid bonding. 3D stacking packaging places very strict requirements on wafer dicing into individual chips, and currently only plasma dicing can meet the relevant defect control and uniformity requirements. Because plasma dicing cannot cut metal, it has strict requirements on the dicing channels of the incoming wafer, requiring a sufficiently wide, metal-free clearance area, generally greater than 40µm. However, with the continuous updates of semiconductor technology nodes, the width of the dicing channels on the wafer is becoming narrower. For example, for cost considerations, the electrical test metal required for WAT (Wafer Acceptance Test) needs to be placed on the dicing channel, resulting in a very narrow clearance area, generally less than 5µm. Using conventional plasma dicing processes is difficult to meet the wafer dicing requirements in 3D stacking packaging. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer dicing method to solve the problem that, with the continuous updating of semiconductor technology nodes, the width of the dicing channels on the wafer is getting narrower and narrower, and it is difficult to meet the wafer dicing requirements in the 3D stacking packaging process using general plasma dicing technology.
[0005] To achieve the above and other related objectives, the present invention provides a wafer dicing method, the wafer dicing method comprising:
[0006] S1, a wafer to be cut is provided with a plurality of dicing channels, the wafer to be cut including a silicon substrate and a redistribution layer in sequence along the thickness direction, the redistribution layer including a wiring dielectric layer and a wiring metal layer;
[0007] S2, cut the wafer to be cut from top to bottom along the cutting path until the silicon substrate is exposed, forming a chip circuit unit and a cutting groove between the chip circuit unit;
[0008] S3, an etching protective layer is formed on the sidewall of the cutting groove;
[0009] S4, forming a flat encapsulation layer that at least fills the cutting groove;
[0010] S5, forming a chip pad that is electrically connected to the redistribution layer above the chip circuit unit;
[0011] S6, Remove the encapsulation layer located on the cutting path;
[0012] S7. The silicon substrate is cut from top to bottom along the cutting path using a plasma cutting process until a preset depth is reached in the silicon substrate.
[0013] S8, the silicon substrate is thinned on the back side to at least completely separate all the dicing channels.
[0014] Optionally, at least one of the cutting paths has the wiring metal layer and an electrical test metal layer electrically connected thereto formed thereon.
[0015] Optionally, in step S2, the wafer to be cut is cut from top to bottom along the cutting path using a laser cutting process.
[0016] Optionally, in step S6, a wet etching process is used to remove the encapsulation layer located on the dicing channel.
[0017] Furthermore, the etching protective layer is a stacked structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide or a stacked structure of silicon oxide-silicon nitride-silicon oxide-silicon nitride; the wet etching solution used in the wet etching process in step S6 includes hydrofluoric acid.
[0018] Optionally, in step S3, the method for forming the etching protective layer includes:
[0019] S31, the etching protective layer is formed on the surface of the chip circuit unit and the surface of the dicing groove using CVD process;
[0020] S32, dry etching process is used to remove the etching protective layer from the bottom wall of the dicing groove and the surface of the chip circuit unit.
[0021] Optionally, in step S4, the method for forming the encapsulation layer includes:
[0022] S41, The encapsulation layer is formed using a CVD process to at least fill the cut groove;
[0023] S42, mechanically grind the upper surface of the encapsulation layer to reduce its thickness;
[0024] S43, The upper surface of the coarsely thinned encapsulation layer is planarized using CMP process.
[0025] Optionally, in step S5, the chip pads are formed using a damascus process.
[0026] Optionally, before step S6, a step of forming a pad protection layer on the chip pads is included; after step S7, a step of removing the pad protection layer is included.
[0027] Optionally, in step S7, the preset depth is 100μm to 200μm.
[0028] As described above, the wafer dicing method of the present invention has the following beneficial effects: First, the wafer to be diced is diced along the dicing track to form chip circuit units and dicing grooves between the chip circuit units. Then, an etch protective layer is formed on the sidewall of the dicing groove, followed by encapsulation layer filling. Next, the encapsulation layer located on the dicing track is removed. A plasma dicing process is then used to diced the silicon substrate along the dicing track. Finally, the back side of the silicon substrate is thinned to ensure that at least all dicing tracks are completely separated to form chip units. The wafer dicing method of the present invention is applicable to wafers with metal on the dicing track, and also to wafers without metal on the dicing track. That is, it meets the dicing requirements of wafers to be diced in all types of 3D stacked packaging, and has a lower cost. It solves the problem that with the continuous updating of semiconductor technology nodes, the width of the dicing track on the wafer to be diced is becoming increasingly narrow, making it difficult to meet the dicing requirements of wafers to be diced in 3D stacked packaging using general plasma dicing processes. Attached Figure Description
[0029] Figure 1 The diagram shown is a schematic flowchart of the wafer dicing method of the present invention.
[0030] Figures 2 to 13 The diagram shows the structural schematics of each step in the wafer dicing method of the present invention.
[0031] Component designation explanation
[0032] 1. Wafer to be cut
[0033] 10 Silicon substrate
[0034] 11 Rerouting layer
[0035] 111 Wiring Metal Layer
[0036] 112 Diffusion Barrier Layer
[0037] 113 Wiring Media Layer
[0038] 12 Electrically measured metals
[0039] 13 Cutting Track
[0040] 14 Chip Circuit Units
[0041] 15 Cutting grooves
[0042] 16 Etching Protective Layer
[0043] 17 Encapsulation layer
[0044] 18 Chip Pads
[0045] 19 Dielectric layers
[0046] 20 Pad Protective Layer
[0047] 21 chip units
[0048] Steps S1 to S8 Detailed Implementation
[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0050] Please see Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0051] This embodiment provides a wafer dicing method, such as... Figure 1 As shown, the wafer dicing method includes:
[0052] S1, a wafer to be cut is provided with a plurality of dicing channels, the wafer to be cut including a silicon substrate and a redistribution layer in sequence along the thickness direction, the redistribution layer including a wiring dielectric layer and a wiring metal layer;
[0053] S2, cut the wafer to be cut from top to bottom along the cutting path until the silicon substrate is exposed, forming a chip circuit unit and a cutting groove between the chip circuit unit;
[0054] S3, an etching protective layer is formed on the sidewall of the cutting groove;
[0055] S4, forming a flat encapsulation layer that at least fills the cutting groove;
[0056] S5, forming a chip pad that is electrically connected to the redistribution layer above the chip circuit unit;
[0057] S6, Remove the encapsulation layer located on the cutting path;
[0058] S7. The silicon substrate is cut from top to bottom along the cutting path using a plasma cutting process until a preset depth is reached in the silicon substrate.
[0059] S8, the silicon substrate is thinned on the back side to at least completely separate all the dicing channels.
[0060] The wafer dicing method of this embodiment first cuts the wafer to be diced along the dicing track to form chip circuit units and dicing grooves between the chip circuit units. Then, an etch protective layer is formed on the sidewall of the dicing groove, followed by the filling of the encapsulation layer. Next, the encapsulation layer located on the dicing track is removed, and a plasma dicing process is used to cut the silicon substrate along the dicing track. Finally, the back side of the silicon substrate is thinned to ensure that at least all dicing tracks are completely separated to form chip units. The wafer dicing method of this embodiment is applicable to wafers to be diced with metal on the dicing track, as well as wafers to be diced without metal on the dicing track. That is, it meets the dicing requirements of wafers to be diced in all types of 3D stacked packaging, and has a lower cost. It solves the problem that as semiconductor technology nodes continue to be updated, the width of the dicing track on the wafer to be diced becomes narrower and narrower, and the use of general plasma dicing processes is difficult to meet the dicing requirements of wafers to be diced in 3D stacked packaging.
[0061] The wafer dicing method of this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0062] like Figure 1 and Figure 2 As shown, step S1 is performed first, providing a wafer 1 to be cut with a plurality of dicing channels 13. The wafer 1 to be cut includes a silicon substrate 10 and a redistribution layer 11 in sequence along the thickness direction. The redistribution layer 11 includes a wiring dielectric layer 113 and a wiring metal layer 111.
[0063] After the chip fabrication process is completed, the wafer 1 to be cut is divided into individual chip units through dicing channel 13. For ease of understanding, as follows... Figure 2 As shown in the accompanying drawings of this embodiment, the example described is that the wafer 1 to be cut has three cutting channels 13. Those skilled in the art can easily understand the cutting method of this embodiment as an implementation process on the entire wafer 1 to be cut.
[0064] The size of the silicon substrate 10 is set as needed, such as common 6-inch, 8-inch, and 12-inch sizes; in addition, the thickness of the silicon substrate 10 is also set as needed. Device structures are formed in the silicon substrate 10. Since the focus of this embodiment is on the dicing process after wafer fabrication, the device structures formed in the silicon substrate 10 are not shown in the accompanying drawings.
[0065] As an example, such as Figure 2 As shown, the redistribution layer 11 includes a wiring metal layer 111, a diffusion barrier layer 112, and a wiring dielectric layer 113, wherein the wiring metal layer 111 is embedded in the wiring dielectric layer 113; the material of the wiring dielectric layer 113 includes one or more combinations of materials selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, silicon nitride, phosphosilicate glass, and fluorine-containing glass, or other low-k dielectric materials; and the redistribution layer 11 may include multiple layers of wiring metal layers 111, multiple layers of diffusion barrier layers 112, and multiple layers of wiring dielectric layers 113. Figure 2 The following description uses the redistribution layer 11 as an example, comprising two wiring metal layers 111, three diffusion barrier layers 112, and two wiring dielectric layers 113. In this embodiment, the material of the wiring dielectric layer 113 is silicon oxide, and the material of the diffusion barrier layer 112 is silicon nitride, to prevent electrical short circuits between different conductive layers caused by molecular diffusion of the wiring metal layer 111 material. The structure of the redistribution layer 11 can be designed according to the specific requirements of different device structures, and no excessive restrictions are imposed here, as long as the redistribution layer 11 can rearrange the circuitry of the device structure in the silicon substrate 10 according to a preset method.
[0066] As described in the background section, with the continuous updates of semiconductor technology nodes, the width of the dicing channels on wafers is becoming increasingly narrow. In this embodiment, after the wafer dicing method completes the dicing into chip units, a WAT test is required, and the electrical test metals needed for the test must be arranged on the dicing channel 13. Therefore, as... Figure 2 As shown, at least one of the cutting tracks 13 has a wiring metal layer 111 and an electrical test metal 12 electrically connected thereto formed thereon. This embodiment is described using the example that each of the cutting tracks 13 has the wiring metal layer 111 and the electrical test metal 12 electrically connected thereto formed thereon.
[0067] The electrical testing metal 12 is electrically connected to the wiring metal layer 111 to achieve electrical lead-out. As an example, the electrical testing metal 12 is embedded in the interlayer dielectric layer. The number of layers and the material of the interlayer dielectric layer can be selected as needed, and no excessive restrictions are imposed here.
[0068] The materials of the wiring metal layer 111 and the electrical testing metal 12 include one or more combinations of the group consisting of copper, aluminum, nickel, gold, silver and titanium. In this embodiment, the materials selected for the wiring metal layer 111 and the electrical testing metal 12 mainly include copper.
[0069] like Figure 1 and Figure 3 As shown, step S2 is then performed, cutting the wafer 1 to be cut from top to bottom along the cutting path 13 until the silicon substrate 10 is exposed, forming the chip circuit unit 14 and the cutting groove 15 between the chip circuit units.
[0070] As an example, the wafer 1 to be cut is cut from top to bottom along the cutting path 13 using a laser cutting process. The laser cutting process can cut structures with metal layers and can provide high precision and good surface quality.
[0071] like Figure 1 and Figure 5 As shown, step S3 is then performed to form an etching protective layer 16 on the sidewall of the cutting groove 15.
[0072] The etching protection layer 16 located on the sidewall of the dicing groove 15 can prevent over-etching when the encapsulation layer on the dicing groove 13 is subsequently etched, and protect the wiring metal layer 111, the diffusion barrier layer 112 and the wiring dielectric layer 113 on the sidewall of the dicing groove 15 from being damaged. Therefore, preferably, the material selection of the etching protection layer 16 has a high etching selectivity ratio with the material of the encapsulation layer subsequently formed.
[0073] As an example, a method for forming the etched protective layer 16 includes:
[0074] S31, such as Figure 4 As shown, the etching protection layer 16 is formed on the surface of the chip circuit unit 14 and the surface of the dicing groove 15 using a CVD process. The etching protection layer 16 can be, for example, a stacked structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide (i.e., NONO) or a stacked structure of silicon oxide-silicon nitride-silicon oxide-silicon nitride (i.e., ONON). Since silicon nitride and silicon oxide have a high wet etching selectivity, the etching protection layer 16 with the silicon nitride layer can serve as an etching stop layer during the subsequent removal of the silicon oxide packaging layer, protecting the wiring metal layer 111, the diffusion barrier layer 112, and the wiring dielectric layer 113 on the sidewall of the dicing groove 15 from being etched to the wiring metal layer.
[0075] S32, such as Figure 5 As shown, the etching protective layer 16 on the bottom wall of the cutting groove 15 and the surface of the chip circuit unit 14 is removed by a dry etching process.
[0076] As an example, a dry etching process can be used to remove the etch protection layer 16 from the bottom wall of the dicing groove 15 and the surface of the chip circuit unit 14. Dry etching, by selecting appropriate etching gases and process parameters, can achieve selective etching of specific materials, thereby precisely removing the etch protection layer 16. Furthermore, dry etching provides good anisotropy, allowing the removal of the etch protection layer 16 from the bottom wall of the dicing groove 15 and the surface of the chip circuit unit 14 without damaging the etch protection layer 16 on the sidewall of the dicing groove 15. The methods for forming the etch protection layer 16 and removing it from the bottom wall of the dicing groove 15 are not excessively limited here.
[0077] After removing the etched protective layer 16 from the bottom wall of the dicing groove 15 and the surface of the chip circuit unit 14, the process generally includes a wet cleaning step of the inside of the dicing groove 15 to remove impurities, residues, oxide layers or other contaminants from the dicing groove 15.
[0078] like Figure 1 and Figure 7 As shown, step S4 is then performed to form a flat encapsulation layer 17, which at least fills the cutting groove 15.
[0079] As a preferred example, the method of forming the encapsulation layer 17 includes:
[0080] S41, as Figure 6 As shown, the encapsulation layer 17 is formed using a CVD process to at least fill the dicing groove 15. As an example, the precursor materials used to form the encapsulation layer 17 include, but are not limited to, tetraethyl orthosilicate (TEOS) and silicon tetrahydrogenate (SiH4), ultimately forming the SiO2 material encapsulation layer 17. The use of TEOS can enhance the adhesion between the encapsulation layer 17 and the etch protection layer 16, thereby improving the bonding strength.
[0081] S42, the upper surface of the encapsulation layer 17 is mechanically ground to reduce its thickness, thereby improving the grinding efficiency;
[0082] S43, the upper surface of the coarsely thinned encapsulation layer 17 is planarized using CMP (Chemical Mechanical Polishing) process; the CMP process combines the effects of mechanical grinding and chemical etching to form a smooth and flat surface on the encapsulation layer 17, providing a good surface foundation for subsequent processes.
[0083] like Figure 1 and Figure 8As shown, step S5 is then performed, where a chip pad 18 electrically connected to the redistribution layer 11 is formed above the chip circuit unit 14 to facilitate the subsequent C2W bonding process or WAT testing.
[0084] For example, the chip pads 18 can be formed using a damascus process.
[0085] like Figure 1 and Figure 10 As shown, step S6 is then performed to remove the encapsulation layer 17 located on the cutting channel 13.
[0086] The encapsulation layer 17 is generally quite thick, typically greater than 10 μm. Dry etching is costly, so as a preferred example, the encapsulation layer 17 is made of an oxide material, such as silicon oxide. A wet etching process can be used to remove the encapsulation layer 17 located on the dicing channel 13 to expose the silicon substrate 10. The wet etching process improves etching efficiency while ensuring etching quality and is more suitable for mass production. When the etch protection layer 16 is a stacked structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide or silicon oxide-silicon nitride-silicon oxide-silicon nitride, the wet etching solution used in this wet etching process includes hydrofluoric acid. Hydrofluoric acid has a high selectivity for etching oxide materials and silicon materials, which can ensure that the etching depth stops at the upper surface of the silicon substrate 10.
[0087] like Figure 1 and Figure 11 As shown, step S7 is then performed, in which a plasma cutting process is used to cut the silicon substrate 10 from top to bottom along the cutting path 13 until a predetermined depth is reached within the silicon substrate 10.
[0088] As an example, such as Figure 9 As shown, before step S6 removes the packaging layer 17 located on the dicing channel 13, the method further includes forming a pad protection layer 20 on the chip pad 18; as Figure 12 As shown, after step S7, the step of removing the pad protective layer 20 is also included.
[0089] Furthermore, the pad protection layer 20 can be formed using processes such as photolithography. The planar dimensions of the pad protection layer 20 are not smaller than the planar dimensions of the chip pad 18, so as to protect the chip pad 18 from damage and prevent the introduction of defects when removing the packaging layer 17 and cutting the silicon substrate 10. In other embodiments, the pad protection layer 20 can also be removed after the subsequent step S8 to protect the chip pad 18 from damage when performing backside thinning on the silicon substrate 10.
[0090] In actual cutting process, if the silicon substrate 10 is completely cut or cut too deeply in step S9, it may cause the wafer 1 to be cut to break. Therefore, in this embodiment, the preset depth when cutting the silicon substrate 10 along the cutting path 13 is preferably 100μm to 200μm.
[0091] like Figure 13 As shown, step S8 is then performed to thin the back side of the silicon substrate 10 to completely separate at least all of the dicing channels 13. This forms the chip cell 21.
[0092] In summary, the wafer dicing method of the present invention involves first dicing the wafer to be diced along the dicing channels to form chip circuit units and dicing grooves between the chip circuit units. Next, an etched protective layer is formed on the sidewalls of the dicing grooves, followed by encapsulation layer filling. Then, the encapsulation layer located on the dicing channels is removed. A plasma dicing process is then used to dice the silicon substrate along the dicing channels. Finally, the back side of the silicon substrate is thinned to ensure that at least all dicing channels are completely separated to form chip units. The wafer dicing method of the present invention is applicable to wafers with metal on the dicing channels, as well as wafers without metal on the dicing channels. That is, it meets the dicing requirements of wafers in all types of 3D stacked packaging, and has a lower cost. It solves the problem that with the continuous updating of semiconductor technology nodes, the width of the dicing channels on the wafers to be diced is becoming increasingly narrow, making it difficult to meet the dicing requirements of conventional plasma dicing processes in 3D stacked packaging. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A wafer dicing method, characterized in that, The wafer dicing method includes: S1, a wafer to be cut is provided with a plurality of dicing channels, the wafer to be cut including a silicon substrate and a redistribution layer in sequence along the thickness direction, the redistribution layer including a wiring dielectric layer and a wiring metal layer; S2, cut the wafer to be cut from top to bottom along the cutting path until the silicon substrate is exposed, forming a chip circuit unit and a cutting groove between the chip circuit unit; S3, an etching protective layer is formed on the sidewall of the cutting groove; S4, forming a flat encapsulation layer that at least fills the cutting groove; S5, forming a chip pad that is electrically connected to the redistribution layer above the chip circuit unit; S6, Remove the encapsulation layer located on the cutting path; S7. The silicon substrate is cut from top to bottom along the cutting path using a plasma cutting process until a preset depth is reached in the silicon substrate. S8, the silicon substrate is thinned on the back side to at least completely separate all the dicing channels.
2. The wafer dicing method according to claim 1, characterized in that: At least one of the cutting channels has the wiring metal layer and the electrical test metal electrically connected thereto formed thereon.
3. The wafer dicing method according to claim 1, characterized in that: In step S2, the wafer to be cut is cut from top to bottom along the cutting path using a laser cutting process.
4. The wafer dicing method according to claim 1, characterized in that: In step S6, a wet etching process is used to remove the encapsulation layer located on the dicing channel.
5. The wafer dicing method according to claim 4, characterized in that: The etching protective layer is a stacked structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide or a stacked structure of silicon oxide-silicon nitride-silicon oxide-silicon nitride; the wet etching solution used in the wet etching process in step S6 includes hydrofluoric acid.
6. The wafer dicing method according to claim 1, characterized in that: In step S3, the method for forming the etching protective layer includes: S31, the etching protective layer is formed on the surface of the chip circuit unit and the surface of the dicing groove using CVD process; S32, dry etching process is used to remove the etching protective layer from the bottom wall of the dicing groove and the surface of the chip circuit unit.
7. The wafer dicing method according to claim 1, characterized in that: In step S4, the method for forming the encapsulation layer includes: S41, The encapsulation layer is formed using a CVD process to at least fill the cut groove; S42, mechanically grind the upper surface of the encapsulation layer to reduce its thickness; S43, The upper surface of the coarsely thinned encapsulation layer is planarized using CMP process.
8. The wafer dicing method according to claim 1, characterized in that: In step S5, the chip pads are formed using the damascus process.
9. The wafer dicing method according to claim 1, characterized in that: Before step S6, a step of forming a pad protection layer on the chip pads is included; after step S7, a step of removing the pad protection layer is included.
10. The wafer dicing method according to claim 1, characterized in that: In step S7, the preset depth is 100μm to 200μm.