Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the structure comprising: a substrate; a first dielectric layer on top of the substrate, the first dielectric layer exposing a top surface of the substrate in an electrode region; a resistive heating layer covering the first dielectric layer in a device region and covering the top surface of the substrate exposed by the first dielectric layer, the resistive heating layer exposing a top surface of the first dielectric layer in a partition region; a conductive layer on top of the resistive heating layer in the electrode region, the conductive layer exposing a top surface of the resistive heating layer in a heating region; and a second dielectric layer covering the conductive layer and covering the top surface of the resistive heating layer exposed by the conductive layer. By providing the second dielectric layer covering the conductive layer and the resistive heating layer in the device region, the probability of damage to the resistive heating layer is reduced, and the risk of polymer residue on the surface of the conductive layer and the resistive heating layer is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Thermal inkjet printhead chips typically include a resistive heating layer formed on a substrate and a conductive layer electrically connected to the resistive heating layer. Driven by a high-density current, the resistive heating layer generates Joule heat, causing the ink in contact to vaporize instantaneously, forming bubbles. The expansion of these bubbles propels ink droplets out of the nozzle. The patterning accuracy of the resistive heating layer and the conductive layer, as well as the reliability of their electrical contact, have a significant impact on the overall performance of the printhead.

[0003] In the manufacturing process of semiconductor structures, multiple photolithography and etching processes are typically required to form predetermined patterns of resistive heating layers and conductive layers in specific areas of the substrate. These processes involve steps such as coating, exposure, development, and subsequent mask removal of organic mask layers. The etching selectivity between different material layers, the removal of etching byproducts, and the integrity of each film surface during the process are key factors determining the uniformity and stability of the final device.

[0004] Currently, the electrical performance and product reliability of semiconductor structures still need to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance and product reliability of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a plurality of device regions and a partition region located between adjacent device regions, the device regions including an electrode region and a heating region located between adjacent electrode regions; a first dielectric layer located on top of the substrate, the first dielectric layer exposing a portion of the top surface of the substrate in the electrode regions; a resistive heating layer covering the first dielectric layer in the device regions and covering the top surface of the substrate exposed by the first dielectric layer, the resistive heating layer exposing the top surface of the first dielectric layer in the partition region; a conductive layer located on top of the resistive heating layer in the electrode regions, the conductive layer exposing the top surface of the resistive heating layer in the heating region, and the conductive layer and the resistive heating layer being in contact and electrically connected; and a second dielectric layer covering the top of the conductive layer and covering the top of the resistive heating layer exposed by the conductive layer.

[0007] Optionally, the material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0008] Optionally, the thickness of the second dielectric layer is between 50 nanometers and 300 nanometers in the normal direction of the substrate surface.

[0009] Optionally, the substrate includes: a substrate; a top metal line located in the substrate, with the top surface of the top metal line exposed on the substrate; a first dielectric layer exposed on the top surface of the top metal line; and a resistive heating layer covering the top surface and sidewalls of the first dielectric layer in the device region, as well as covering the top surface of the exposed top metal line of the first dielectric layer.

[0010] Optionally, the semiconductor structure further includes: an insulating layer covering the top of the first dielectric layer and the second dielectric layer, and sidewalls covering the second dielectric layer, the conductive layer and the resistance heating layer.

[0011] Optionally, the material of the resistance heating layer may include a conductive material with high resistivity.

[0012] Optionally, the material of the resistance heating layer includes one or more of TaN, AlTaN, TaAl, TaSiN, and NiCr.

[0013] Optionally, the material of the conductive layer may include a conductive material with low resistivity.

[0014] Optionally, the conductive layer may be made of one or more of aluminum, copper, nickel, and gold.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of device regions and a partition region located between adjacent device regions, the device regions including an electrode region and a heating region located between adjacent electrode regions, a first dielectric layer formed on the top of the substrate, the first dielectric layer exposing a portion of the top surface of the substrate of the electrode regions, a first dielectric layer covering the device regions and a resistive heating layer covering the exposed top surface of the substrate of the first dielectric layer formed on the top of the substrate, a conductive layer covering the resistive heating layer of the electrode regions formed on the top of the substrate, the conductive layer exposing the resistive heating layer of the heating regions, and the conductive layer and the resistive heating layer being in contact and electrically connected; forming a second dielectric layer covering the conductive layer and the resistive heating layer on the top of the substrate of the device regions, the second dielectric layer exposing the conductive layer of the partition region; and removing the conductive layer and the resistive heating layer of the partition region using the second dielectric layer as a hard mask.

[0016] Optionally, the step of forming the second dielectric layer includes: forming a second dielectric material layer covering a conductive layer and a resistance heating layer on top of a substrate; forming a first mask layer having a first mask opening on top of the second dielectric material layer, wherein the first mask opening exposes the top surface of the second dielectric material layer in the partition region; using the first mask layer as a mask, removing the second dielectric material layer exposed by the first mask layer along the first mask opening, and using the remaining second dielectric material layer as the second dielectric layer; and removing the first mask layer.

[0017] Optionally, the material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0018] Optionally, the thickness of the second dielectric layer is between 50 nanometers and 300 nanometers in the normal direction of the substrate surface.

[0019] Optionally, the process for removing the first mask layer includes a wet stripping process.

[0020] Optionally, the process of removing the conductive layer and the resistance heating layer in the isolation region using the second dielectric layer as a hard mask includes plasma dry etching.

[0021] Optionally, in the step of providing the substrate, the substrate includes a substrate and a top metal line located in the substrate, the substrate exposing the top surface of the top metal line, a first dielectric layer covering the substrate and having a via exposing the top surface of the top metal line in the first dielectric layer, a resistive heating layer covering the top surface of the first dielectric layer in the device region, as well as the bottom and sidewalls of the via, and the resistive heating layer being electrically connected to the top metal line.

[0022] Optionally, the step of forming the conductive layer includes: forming a conductive material layer covering the resistance heating layer on top of the substrate; forming a second mask layer having a second mask opening on top of the conductive material layer, wherein the second mask opening exposes the conductive material layer of the heating area; using the second mask layer as a mask, removing the conductive material layer of the heating area along the second mask opening, and using the remaining conductive material layer as the conductive layer; and removing the second mask layer.

[0023] Optionally, after removing the second mask layer, the method further includes forming an insulating layer on top of the substrate that covers the top of the first dielectric layer and the second dielectric layer, as well as the sidewalls of the second dielectric layer, the conductive layer, and the resistance heating layer.

[0024] Optionally, the process for removing the second mask layer includes a wet stripping process.

[0025] Optionally, after removing the second mask layer, the method further includes forming an insulating layer on top of the substrate that covers the top of the first dielectric layer and the second dielectric layer, as well as the sidewalls of the second dielectric layer, the conductive layer, and the resistance heating layer.

[0026] Optionally, in the step of removing the conductive layer and the resistance heating layer of the partition area, an opening is formed at the top of the first dielectric layer of the partition area, penetrating the second dielectric layer, the conductive layer and the resistance heating layer; after removing the conductive layer and the resistance heating layer of the partition area and before forming the insulating layer, the forming method further includes cleaning the sidewalls and bottom of the opening.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: The semiconductor structure formation method provided in this invention exposes the resistance heating layer in the heating region, and the second dielectric layer simultaneously covers both the conductive layer and the resistance heating layer in the device region, exposing only the conductive layer in the isolation region. Therefore, when the conductive layer and the resistance heating layer in the isolation region are removed using the second dielectric layer as a hard mask, the top of the resistance heating layer in the device region is always completely covered by the second dielectric layer, making it less likely to be exposed to the plasma environment used for etching the conductive layer and the resistance heating layer in the isolation region. This avoids the risk of the top surface of the resistance heating layer being bombarded by plasma, oxidized, and thinned, ensuring the stability and uniformity of the resistance value generated by the resistance heating layer when the semiconductor structure is working. At the same time, since the conductive layer and the resistance heating layer in the isolation region are removed by self-alignment using the second dielectric layer as an etching hard mask, there is no need to separately coat organic photoresist as an etching mask. Therefore, the subsequent ashing step for removing the organic photoresist is completely eliminated, avoiding the risk of the organic photoresist reacting chemically with the etching gas to generate polymers that are difficult to remove. In summary, by forming a second dielectric layer covering the conductive layer and the resistive heating layer in the device region, the probability of damage to the resistive heating layer is reduced, and the risk of polymer residues on the surfaces of the conductive layer and the resistive heating layer is avoided, thereby improving the electrical performance of the semiconductor structure and the reliability of the product.

[0028] The semiconductor structure provided in this invention features a second dielectric layer covering the top of the conductive layer and the exposed top of the resistance heating layer. This second dielectric layer protects the top of the resistance heating layer, preventing it from being subjected to plasma bombardment, oxidation, and thinning. This ensures the stability and uniformity of the resistance value generated by the resistance heating layer during semiconductor structure operation. Furthermore, in the semiconductor structure formation process, the conductive layer and resistance heating layer in the isolation region are self-aligned and removed using the second dielectric layer as an etching hard mask. This eliminates the need for additional organic photoresist coating as an etching mask, thus completely eliminating the subsequent ashing step for removing the organic photoresist and avoiding the risk of the organic photoresist reacting chemically with the etching gas to form difficult-to-remove polymers. In summary, by providing a second dielectric layer covering the conductive layer and resistance heating layer in the device region, the probability of damage to the resistance heating layer is reduced, and the risk of polymer residues on the surfaces of the conductive layer and resistance heating layer is avoided, thereby improving the electrical performance and product reliability of the semiconductor structure. Attached Figure Description

[0029] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure formation method. Figures 3 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0030] Currently, the electrical performance and product reliability of semiconductor structures still need improvement. This paper analyzes the reasons why the electrical performance and product reliability of a particular semiconductor structure still require further improvement.

[0031] in, Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure formation method.

[0032] refer to Figure 1 A substrate 13 is provided, which includes a plurality of device regions 10A and a partition region 10B located between adjacent device regions 10A. The device regions 10A include electrode regions 10a and heating regions 10b located between adjacent electrode regions 10a. A first dielectric layer 12 is formed on the top of the substrate 13, and the first dielectric layer 12 exposes a portion of the top surface of the substrate 13 above the electrode regions 10a. A resistance heating layer 28 is formed on the top of the substrate 13, covering the first dielectric layer 12 and the exposed top surface of the substrate 13. A conductive layer 23 is formed on the top of the substrate 13, covering the resistance heating layer 28. The conductive layer 23 exposes the resistance heating layer 28 in the heating region 10b, and the conductive layer 23 is in contact with the resistance heating layer 28.

[0033] refer to Figure 2 The conductive layer 23 and the resistance heating layer 28 of the isolation region 10B are removed by plasma dry etching process.

[0034] Research has revealed that when the conductive layer 23 and the resistance heating layer 28 of the isolation region 10B are directly removed using plasma dry etching, the resistance heating layer 28 of the heating region 10b is exposed, and no protective mask is placed above the conductive layer 23 except for the isolation region 10B. High-energy ions generated during plasma dry etching directly bombard the exposed top surface of the resistance heating layer 28 in the heating region 10b, causing physical damage, oxidation, and thinning of the resistance heating layer 28 surface. This results in an uncontrollable increase in the actual resistance value of the resistance heating layer 28 relative to the design value. Furthermore, when plasma dry etching contains materials of the resistance heating layer 28 (especially tantalum-containing materials), it generates polymer byproducts that are difficult to remove through conventional cleaning. These polymers remain on the sidewalls and bottom of the etching opening, affecting not only the adhesion and uniformity of the subsequent insulating layer but also potentially introducing leakage paths during device operation, thereby reducing the overall electrical performance of the semiconductor structure and product reliability.

[0035] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of device regions and a partition region located between adjacent device regions, each device region including an electrode region and a heating region located between adjacent electrode regions; forming a first dielectric layer on the top of the substrate, the first dielectric layer exposing the top surface of the substrate of the electrode regions; forming a first dielectric layer covering the device regions and a resistive heating layer covering the exposed top surface of the substrate of the first dielectric layer on the top of the substrate; forming a conductive layer on the top of the substrate covering the resistive heating layer of the electrode regions, the conductive layer exposing the resistive heating layer of the heating regions, and the conductive layer and the resistive heating layer being in contact and electrically connected; forming a second dielectric layer on the top of the substrate of the device regions covering the conductive layer and the resistive heating layer, the second dielectric layer exposing the conductive layer of the partition region; and removing the conductive layer and the resistive heating layer of the partition region using the second dielectric layer as a mask.

[0036] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] in, Figures 3 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0038] refer to Figures 3 to 8 A substrate 103 is provided, which includes a plurality of device regions 100A and a partition region 100B located between adjacent device regions 100A. The device regions 100A include electrode regions 100a and heating regions 100b located between adjacent electrode regions 100a. A first dielectric layer 102 is formed on the top of the substrate 103, and the first dielectric layer 102 exposes part of the top surface of the substrate 103 of the electrode regions 100a. A first dielectric layer 102 covering the device regions 100A and a resistance heating layer 108 covering the exposed top surface of the substrate 103 of the first dielectric layer 102 are formed on the top of the substrate 103. A conductive layer 113 covering the resistance heating layer 108 is formed on the top of the substrate 103, and the conductive layer 113 exposes the resistance heating layer 108 of the heating region 100b, and the conductive layer 113 is in contact with the resistance heating layer 108.

[0039] Substrate 103 provides a process platform for the subsequent formation of semiconductor structures.

[0040] Specifically, the substrate 103 integrates drive circuit elements (such as transistors).

[0041] In this embodiment, the semiconductor structure is the heating resistor unit and its driving interconnection structure in the thermal inkjet printhead chip, which is used to generate Joule heat in the resistor heating layer 108 under current excitation, thereby causing the ink to vaporize instantly to form bubbles to eject ink droplets.

[0042] It should be noted that device region 100A is the smallest unit in the semiconductor structure that implements the heating function. Each device region 100A corresponds to an independent resistance heating layer 108 and a conductive layer 113 electrically connected to it, which is used to generate heat when energized. Isolation region 100B is located between adjacent device regions 100A. It is used to achieve electrical isolation between different device regions 100A in subsequent processes by removing the conductive layer 113 and the resistance heating layer 108 of isolation region 100B, thereby preventing electrical crosstalk between adjacent device regions 100A. Inside the device region 100A, the electrode region 100a is used to introduce external driving current into the resistive heating layer 108. A conductive layer 113 covers the resistive heating layer 108 of the electrode region 100a to reduce the overall resistance of the electrode region 100a. The heating region 100b is located between two adjacent electrode regions 100a. The conductive layer 113 of the heating region 100b is removed, exposing the top surface of the resistive heating layer 108, so that the current is forced to pass through the resistive heating layer 108 of the heating region 100b, thereby generating Joule heat in the heating region 100b.

[0043] The first dielectric layer 102 is located on the top surface of the substrate 103 and is used to cover the non-electrically connected area of ​​the substrate 103 to prevent electrical contact between the resistance heating layer 108 in the non-electrically connected area and the substrate 103. At the same time, by exposing part of the top surface of the substrate 103 in the electrode region 100a, the first dielectric layer 102 allows the subsequently deposited resistance heating layer 108 to directly contact the top surface of the substrate 103, thereby establishing an electrical connection channel between the resistance heating layer 108 and the internal driving circuit of the substrate 103. This ensures that current can flow from the substrate 103 through the resistance heating layer 108 into the conductive layer 113 and finally through the heating region 100b, where Joule heating is generated.

[0044] When current passes through the resistive heating layer 108, the resistive heating layer 108 will generate Joule heat in the current path. The heat is transferred to the ink, causing it to vaporize and expand, thereby realizing the inkjet printing function.

[0045] In this embodiment, the material of the resistance heating layer 108 includes a conductive material with high resistivity.

[0046] Specifically, the material of the resistance heating layer 108 is a conductive material with high resistivity, which enables the resistance heating layer 108 to generate a higher resistance value, thereby obtaining a greater Joule heat power under the same current, thus ensuring that the heating zone 100b can generate enough heat to vaporize the ink in a very short time; at the same time, the conductive material with high resistivity allows the thickness and width of the resistance heating layer 108 itself to be adjusted within a large range without significantly reducing the heating efficiency.

[0047] In this embodiment, the material of the resistance heating layer 108 includes one or more of TaN, AlTaN, TaAl, TaSiN, and NiCr.

[0048] It should be noted that TaN, AlTaN, TaAl, TaSiN, and NiCr materials have good thermal stability and are not prone to diffusion or phase transition at high temperatures. They also exhibit good adhesion and chemical stability with the materials selected for the first dielectric layer 102 and the conductive layer 113. Furthermore, TaN, AlTaN, TaAl, TaSiN, and NiCr can be deposited using chemical vapor deposition and are compatible with subsequent wet stripping or dry etching processes. In addition, TaN, AlTaN, TaAl, TaSiN, and NiCr materials have high resistivity, which meets the resistivity requirements of the resistance heating layer 108.

[0049] The conductive layer 113 covers the top surface of the resistance heating layer 108 in the electrode region 100a of the device region 100A and is electrically connected to the resistance heating layer 108 to introduce driving current from the substrate 103 to the heating region 100b.

[0050] It should be noted that the conductive layer 113 is electrically connected to the resistance heating layer 108, which allows current to flow smoothly from the conductive layer 113 into the resistance heating layer 108 in the heating zone 100b. At the same time, since the conductive layer 113 covers the resistance heating layer 108, in subsequent processes, the conductive layer 113 can also serve as a physical protective layer for the resistance heating layer 108 in the electrode region 100a, preventing the resistance heating layer 108 from being damaged in the plasma environment.

[0051] refer to Figures 5 to 8 In this embodiment, the step of forming the conductive layer 113 includes: forming a conductive material layer 110 covering the resistive heating layer 108 on the top of the substrate 103; forming a second mask layer 111 having a second mask opening 112 on the top of the conductive material layer 110, wherein the second mask opening 112 exposes the conductive material layer 110 of the heating region 100b; using the second mask layer 111 as a mask, removing the conductive material layer 110 of the heating region 100b along the second mask opening 112, and using the remaining conductive material layer 110 as the conductive layer 113.

[0052] The second mask opening 112 exposes the conductive material layer 110 of the heating region 100b, so that only the conductive material layer 110 in the heating region 100b is selectively removed, while the conductive material layer 110 in the electrode region 100a is protected and retained by the second mask layer 111. This allows the heating region 100b (without conductive layer 113 coverage) and the electrode region 100a (with conductive layer 113 coverage) to be separated in the device region 100A. This creates a path for current to flow from the conductive layer 113 through the electrode region 100a into the resistance heating layer 108 of the heating region 100b, thus achieving the heating effect of the heating region 100b.

[0053] In this embodiment, the material of the second mask layer 111 includes organic materials.

[0054] Specifically, the second mask layer 111 is made of organic material (such as photoresist), which facilitates the high-precision formation of the second mask opening 112 through photolithography. Organic materials are also inexpensive and easy to coat and remove.

[0055] In this embodiment, the process of removing the conductive material layer 110 of the heating zone 100b includes a wet stripping process.

[0056] It should be noted that the wet stripping process has high selectivity for the materials used in the conductive material layer 110, and will not damage the underlying resistance heating layer 108. Furthermore, the wet stripping process does not generate plasma, thereby avoiding ion bombardment or oxidation of the resistance heating layer 108 when the top surface of the heating zone 100b is exposed.

[0057] In this embodiment, the conductive layer 113 is made of a conductive material with low resistivity.

[0058] Specifically, the conductive layer 113 is made of a low resistivity conductive material, which can significantly reduce the series resistance of the electrode region 100a and avoid unnecessary Joule heating in the electrode region 100a. This concentrates almost all of the Joule heat generated by the driving current on the resistance heating layer 108 of the heating region 100b, thus preventing the electrode region 100a from reducing energy efficiency or causing local overheating failure due to heat generation.

[0059] In this embodiment, the material of the conductive layer 113 includes one or more of aluminum, copper, nickel, and gold.

[0060] It should be noted that aluminum, copper, nickel, and gold are all low-resistivity metals, and these materials can form good ohmic contact with the resistance heating layer 108. It can be understood that the material of the resistance heating layer 108 is a high-resistivity conductive material, while the material of the conductive layer 113 includes low-resistivity conductive materials; here, high resistivity and low resistivity are relative terms.

[0061] refer to Figure 3 and Figure 4 In this embodiment, in the step of providing the substrate 103, the substrate 103 includes a substrate 100 and a top metal line 101 located in the substrate 100. The substrate 100 exposes the top surface of the top metal line 101. A first dielectric layer 102 covers the substrate 100 and has a through hole 104 that exposes the top surface of the top metal line 101. A resistance heating layer 108 covers the top surface of the first dielectric layer 102 of the device region 100A, as well as the bottom and sidewalls of the through hole 104. The resistance heating layer 108 is in contact with the top metal line 101.

[0062] The substrate 100 provides mechanical support for the semiconductor structure and integrates driving circuits (such as transistors) and metal interconnect layers connecting these driving circuits. The top metal line 101 is the uppermost metal wiring in the substrate 100 and is used to transmit driving current to the resistance heating layer 108.

[0063] The top metal line 101 serves as the output terminal of the internal driving circuit of the substrate 100. Its top surface is exposed and used to make contact with the resistance heating layer 108, thereby transferring the driving current from the inside of the substrate 100 to the resistance heating layer 108.

[0064] The substrate 100 exposes the top surface of the top metal line 101, allowing the subsequently formed resistance heating layer 108 to directly contact the top surface of the top metal line 101, thereby improving the current transmission efficiency and the response speed of the resistance heating layer 108 in heating up.

[0065] The through-hole 104 penetrates the first dielectric layer 102 and exposes the top surface of the top metal line 101, providing a vertical electrical connection channel between the resistance heating layer 108 and the top metal line 101. At the same time, the sidewall of the through-hole 104 increases the contact area between the resistance heating layer 108 and the first dielectric layer 102, which helps to improve the adhesion of the structure.

[0066] In this embodiment, the resistance heating layer 108 covers the top surface of the first dielectric layer 102, as well as the bottom and sidewalls of the through hole 104. This means that the resistance heating layer 108 conformally covers the top surface and sidewalls of the first dielectric layer 102 and the top surface of the top metal wire 101.

[0067] It should be noted that the conformal coverage of the resistance heating layer 108 on the top surface and sidewalls of the first dielectric layer 102 and the top surface of the top metal line 101 enables the resistance heating layer 108 to achieve stable large-area electrical contact with the top metal line 101 at the bottom of the through hole 104, reducing contact resistance. At the same time, the conformal coverage means that the resistance heating layer 108 only covers the sidewalls of the through hole 104 in the form of a thin film and does not fill the through hole 104. This can avoid stress generated inside the through hole 104 due to excessive thickness of the resistance heating layer 108. Furthermore, it can maintain the thickness of the resistance heating layer 108 at the through hole 104 consistent with the thickness of the resistance heating layer 108 on the top surface of the first dielectric layer 102, thereby ensuring the uniformity of the resistance value of the entire resistance heating layer 108.

[0068] Continue to refer to Figure 8 Remove the second mask layer 111.

[0069] After removing the second mask layer 111, the conductive material layer 110 of the heating region 100b is removed, exposing the resistance heating layer 108 of the heating region 100b, while the conductive material layer 110 of the electrode region 100a is retained. At the same time, removing the second mask layer 111 provides a clean deposition surface for the subsequent deposition of the second dielectric layer.

[0070] In this embodiment, the process for removing the second mask layer 111 includes a wet stripping process.

[0071] Specifically, when the wet stripping process removes the second mask layer 111, the stripping solution only reacts chemically with the second mask layer 111 and does not react chemically with the conductive layer 113 and the resistance heating layer 108. This completely avoids the risk of ion bombardment and oxidation damage that oxygen plasma ashing may cause to the exposed top surface of the resistance heating layer 108.

[0072] refer to Figures 9 to 11 A second dielectric layer 160 is formed on top of the substrate 103 in the device region 100A, covering the conductive layer 113 and the resistance heating layer 108, and the second dielectric layer 160 exposes the conductive layer 113 in the isolation region 100B.

[0073] It should be noted that the second dielectric layer 160 simultaneously covers the conductive layer 113 and the resistance heating layer 108 in the device region 100A, exposing only the conductive layer 113 in the isolation region 100B. Therefore, when the conductive layer 113 and the resistance heating layer 108 in the isolation region 100B are removed using the second dielectric layer 160 as a mask, the top of the resistance heating layer 108 in the device region 100A is always completely covered by the second dielectric layer 160, making it less likely to be exposed to the plasma environment used for etching the conductive layer 113 and the resistance heating layer 108 in the isolation region 100B. This avoids the risk of the top surface of the resistance heating layer 108 being bombarded by plasma, oxidized, and thinned, ensuring the stability and uniformity of the resistance value generated by the resistance heating layer 108 when the semiconductor structure is working, and improving the electrical performance of the semiconductor structure.

[0074] In this embodiment, the step of forming the second dielectric layer 160 includes: forming a second dielectric material layer 116 covering the conductive layer 113 and the resistance heating layer 108 on the top of the substrate 103; forming a first mask layer 130 with a first mask opening 131 on the top of the second dielectric material layer 116, wherein the first mask opening 131 exposes the top surface of the second dielectric material layer 116 of the partition region 100B; using the first mask layer 130 as a mask, removing the second dielectric material layer 116 exposed by the first mask layer 130 along the first mask opening 131, and using the remaining second dielectric material layer 116 as the second dielectric layer 160.

[0075] In this embodiment, the material of the second dielectric layer 160 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0076] Silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide are all common dielectric materials with good insulation properties and good adhesion and thermal matching with the subsequently deposited insulating layer. Furthermore, silicon nitride has high density and can effectively block moisture and ion intrusion. Silicon oxide has a mature process and controllable stress. All these materials are compatible with conductive layer 113 and resistance heating layer 108.

[0077] It should be noted that the thickness of the second dielectric layer 160 in the normal direction of the substrate 103 surface should not be too large or too small. If the thickness of the second dielectric layer 160 is too large, it will result in an excessively long deposition time, increasing process costs. Furthermore, during the subsequent etching of the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B using the second dielectric layer 160 as a mask, the excessive thickness of the second dielectric layer 160 will lead to an excessively large aspect ratio of the mask openings, affecting the transport of etching gas and resulting in uneven etching. If the thickness of the second dielectric layer 160 is too small, during the etching of the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B using the second dielectric layer 160 as a mask, the second dielectric layer 160 may be prematurely consumed or broken down, failing to effectively protect the resistance heating layer 108 within the device region 100A, causing the top surface of the resistance heating layer 108 to be exposed to the plasma environment. Therefore, in this embodiment, the thickness of the second dielectric layer 160 is between 50 nanometers and 300 nanometers in the normal direction of the surface of the substrate 103. For example, the thickness of the second dielectric layer 160 is 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers, or 300 nanometers.

[0078] Continue to refer to Figure 11 Remove the first mask layer 130.

[0079] After the first mask layer 130 is removed, the second dielectric material layer 116 above the device region 100A is completely retained. The second dielectric material layer 116 above the isolation region 100B is removed, exposing the conductive layer 113 of the isolation region 100B, so that the second dielectric layer 160 becomes the hard mask for subsequent etching to remove the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B.

[0080] In this embodiment, the process for removing the first mask layer 130 includes a wet stripping process.

[0081] When the wet stripping process removes the first mask layer 130, the stripping solution has high selectivity for the first mask layer 130 and will not damage the underlying second dielectric layer 160, conductive layer 113 or resistance heating layer 108; at the same time, the wet stripping process does not generate plasma, avoiding any potential risk of ion bombardment.

[0082] refer to Figure 12 Using the second dielectric layer 160 as a hard mask, the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B are removed.

[0083] Specifically, using the second dielectric layer 160 as a hard mask, the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B are removed. This means that the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B are removed by self-alignment using the second dielectric layer 160 as an etching hard mask, without the need to separately coat organic photoresist as an etching mask. Therefore, the subsequent ashing step for removing organic photoresist is completely eliminated, avoiding the risk of organic photoresist reacting chemically with etching gas to generate polymers that are difficult to remove, thereby improving the product reliability of the semiconductor structure.

[0084] In this embodiment, the process of removing the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B using the second dielectric layer 160 as a hard mask includes a plasma dry etching process.

[0085] The plasma dry etching process enables anisotropic etching, which removes the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B vertically downwards, while the conductive layer 113 and the resistance heating layer 108 in the device region 100A are protected by the second dielectric layer 160.

[0086] It should be noted that the plasma dry etching process will not damage the top surface of the resistive heating layer 108 in the device region 100A. This is because the top surface of the resistive heating layer 108 in the device region 100A is always completely covered by the second dielectric layer 160. Ions and free radicals in the plasma cannot penetrate the second dielectric layer 160 to contact the top surface of the resistive heating layer 108. Only the conductive layer 113 and the resistive heating layer 108 in the isolation region 100B are exposed to the plasma. The conductive layer 113 and the resistive heating layer 108 in the isolation region 100B will eventually be completely removed and will not participate in the operation of the semiconductor structure. Therefore, even if they are bombarded, it will not affect the device performance.

[0087] In this embodiment, after removing the conductive layer 113 and the resistance heating layer 108 of the partition region 100B, an opening 199 is formed on the top of the first dielectric layer 102 of the partition region 100B, which penetrates the second dielectric layer 160, the conductive layer 113 and the resistance heating layer 108.

[0088] Specifically, the opening 199 completely disconnects the conductive layer 113 and the resistance heating layer 108 between adjacent device regions 100A, so that there are no conductive paths between different device regions 100A, thereby achieving electrical isolation; at the same time, the bottom of the opening exposes the top surface of the first dielectric layer 102, providing space for the subsequent filling of the insulating layer.

[0089] Continue to refer to Figure 12 The side walls and bottom of opening 199 were cleaned.

[0090] It should be noted that cleaning the sidewalls and bottom of the opening 199 can remove polymer byproducts remaining on the sidewalls and bottom of the opening 199 during the dry etching process of the conductive layer 113 and the resistance heating layer 108 of the partition region 100B. This ensures clean contact between the subsequently formed insulating layer and the sidewalls and bottom of the opening 199, and improves the adhesion and insulation reliability of the insulating layer.

[0091] In this embodiment, the cleaning process can use organic solvents to remove polymer byproducts.

[0092] refer to Figure 13 In this embodiment, after removing the second mask layer 111 and cleaning the opening 199, an insulating layer 190 is formed on the top of the substrate 103, covering the top of the first dielectric layer 102 and the second dielectric layer 160, as well as covering the sidewalls of the second dielectric layer 160, the conductive layer 113 and the resistance heating layer 108.

[0093] The insulating layer 190 covers the top of the first dielectric layer 102 and the second dielectric layer 160, as well as the sidewalls of the second dielectric layer 160, the conductive layer 113, and the resistance heating layer 108, providing moisture-proof, oxidation-proof, and mechanical protection for the resistance heating layer 108 and the conductive layer 113.

[0094] In this embodiment, during the formation of the insulating layer 190, the insulating layer 190 covers the bottom and sidewalls of the opening 199.

[0095] The insulating layer 190 covers the bottom and sidewalls of the opening 199, ensuring electrical isolation between device areas 100A, while preventing the sidewalls of the conductive layer 113 or the resistance heating layer 108 from contacting the external environment, thus avoiding short circuits or corrosion.

[0096] In this embodiment, the material of the insulating layer 190 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. Optionally, the material of the insulating layer 190 is the same as the material of the first dielectric layer 102.

[0097] Accordingly, the present invention also provides a semiconductor structure. Wherein, Figure 13 This is a schematic diagram of a semiconductor structure according to one embodiment of the present invention.

[0098] The semiconductor structure includes: a substrate 103, which includes a plurality of device regions 100A and a partition region 100B located between adjacent device regions 100A; each device region 100A includes an electrode region 100a and a heating region 100b located between adjacent electrode regions 100a; a first dielectric layer 102 located on top of the substrate 103, and the first dielectric layer 102 exposes a portion of the top surface of the substrate 103 above the electrode regions 100a; and a resistance heating layer 108 covering the first dielectric layer 102 of the device regions 100A and covering the partition region 100B. The first dielectric layer 102 exposes the top surface of the substrate 103, and the resistance heating layer 108 exposes the top surface of the first dielectric layer 102 in the partition region 100B; the conductive layer 113 is located on top of the resistance heating layer 108 in the electrode region 100a, the conductive layer 113 exposes the top surface of the resistance heating layer 108 in the heating region 100b, and the conductive layer 113 is in contact with the resistance heating layer 108; the second dielectric layer 160 covers the top of the conductive layer 113 and the top of the resistance heating layer 108 exposed by the conductive layer 113.

[0099] It should be noted that by setting a second dielectric layer 160 covering the top of the conductive layer 113 and the top of the exposed resistance heating layer 108, the second dielectric layer 160 protects the top of the resistance heating layer 108, avoiding the risk of plasma bombardment, oxidation, and thinning of the top surface of the resistance heating layer 108, thus ensuring the stability and uniformity of the resistance value generated by the resistance heating layer 108 when the semiconductor structure is working. At the same time, in the semiconductor structure formation process, the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B are removed by self-alignment using the second dielectric layer 160 as an etching hard mask, without the need to separately coat organic photoresist as an etching mask. Therefore, the subsequent ashing step for removing organic photoresist is completely eliminated, avoiding the risk of organic photoresist reacting chemically with etching gas to generate polymers that are difficult to remove. In summary, by providing a second dielectric layer 160 covering the conductive layer 113 and the resistance heating layer 108 in the device region 100A, the probability of damage to the resistance heating layer 108 is reduced, and the risk of polymer residues on the surfaces of the conductive layer 113 and the resistance heating layer 108 is avoided, thereby improving the electrical performance of the semiconductor structure and the reliability of the product.

[0100] Substrate 103 provides a process platform for the subsequent formation of semiconductor structures.

[0101] Specifically, the substrate 103 integrates drive circuit elements (such as transistors).

[0102] In this embodiment, the semiconductor structure is the heating resistor unit and its driving interconnection structure in the thermal inkjet printhead chip, which is used to generate Joule heat in the resistor heating layer 108 under current excitation, thereby causing the ink to vaporize instantly to form bubbles to eject ink droplets.

[0103] It should be noted that device region 100A is the smallest unit in the semiconductor structure that implements the heating function. Each device region 100A corresponds to an independent resistance heating layer 108 and a conductive layer 113 electrically connected to it, used to generate heat when energized. Isolation region 100B is located between adjacent device regions 100A, used to achieve electrical isolation between different device regions 100A and prevent electrical crosstalk between adjacent device regions 100A. Inside device region 100A, electrode region 100a is used to introduce external driving current into resistance heating layer 108. The resistive heating layer 108 of electrode region 100a is covered with conductive layer 113 to reduce the overall resistance of electrode region 100a. Heating region 100b is located between two adjacent electrode regions 100a. The conductive layer 113 of heating region 100b is removed, exposing the top surface of resistance heating layer 108, so that current is forced to pass through resistance heating layer 108 of heating region 100b, thereby generating Joule heat in heating region 100b.

[0104] In this embodiment, the substrate 103 includes: a substrate 100; a top metal line 101 located in the substrate 100, with the top surface of the top metal line 101 exposed in the substrate 100.

[0105] The substrate 100 provides mechanical support for the semiconductor structure and integrates driving circuits (such as transistors) and metal interconnect layers connecting these driving circuits. The top metal line 101 is the uppermost metal wiring in the substrate 100 and is used to transmit driving current to the resistance heating layer 108.

[0106] The top metal line 101 serves as the output terminal of the internal driving circuit of the substrate 100. Its top surface is exposed and used to make contact with the resistance heating layer 108, thereby transferring the driving current from the inside of the substrate 100 to the resistance heating layer 108.

[0107] The substrate 100 exposes the top surface of the top metal line 101, allowing the resistance heating layer 108 to directly contact the top surface of the top metal line 101, thereby improving the current transmission efficiency and the response speed of the resistance heating layer 108 in heating up.

[0108] The first dielectric layer 102 is located on the top surface of the substrate 103 and is used to cover the non-electrically connected area of ​​the substrate 103 to prevent electrical contact between the resistance heating layer 108 in the non-electrically connected area and the substrate 103. At the same time, the first dielectric layer 102 provides a channel for electrical connection between the resistance heating layer 108 and the internal circuit of the substrate 103 by exposing the top surface of the electrode area 100a of the substrate 103.

[0109] In this embodiment, the first dielectric layer 102 exposes the top surface of the top metal line 101.

[0110] It should be noted that the first dielectric layer 102 exposes the top surface of the top metal line 101, allowing the resistance heating layer 108 to directly contact the top surface of the top metal line 101, thereby establishing an electrical connection channel between the resistance heating layer 108 and the internal driving circuit of the substrate 103. This ensures that current can flow from the substrate 103 through the resistance heating layer 108 into the conductive layer 113 and finally through the heating zone 100b, generating Joule heat in the heating zone 100b.

[0111] When current passes through the resistive heating layer 108, the resistive heating layer 108 will generate Joule heat in the current path. The heat is transferred to the ink, causing it to vaporize and expand, thereby realizing the inkjet printing function.

[0112] In this embodiment, the material of the resistance heating layer 108 includes a conductive material with high resistivity.

[0113] Specifically, the material of the resistance heating layer 108 is a conductive material with high resistivity, which enables the resistance heating layer 108 to generate a higher resistance value, thereby obtaining a greater Joule heat power under the same current, thus ensuring that the heating zone 100b can generate enough heat to vaporize the ink in a very short time; at the same time, the conductive material with high resistivity allows the thickness and width of the resistance heating layer 108 itself to be adjusted within a large range without significantly reducing the heating efficiency.

[0114] In this embodiment, the material of the resistance heating layer 108 includes one or more of TaN, AlTaN, TaAl, TaSiN, and NiCr.

[0115] It should be noted that TaN, AlTaN, TaAl, TaSiN, and NiCr materials have good thermal stability and are not prone to diffusion or phase transition at high temperatures. They also exhibit good adhesion and chemical stability with the materials selected for the first dielectric layer 102 and the conductive layer 113. Furthermore, TaN, AlTaN, TaAl, TaSiN, and NiCr can be deposited using chemical vapor deposition and are compatible with subsequent wet stripping or dry etching processes. In addition, TaN, AlTaN, TaAl, TaSiN, and NiCr materials have high resistivity, which meets the resistivity requirements of the resistance heating layer 108.

[0116] In this embodiment, the resistance heating layer 108 covers the top surface and sidewalls of the first dielectric layer 102 of the device region 100A, as well as the top surface of the exposed top metal line 101 of the first dielectric layer 102.

[0117] It should be noted that the conformal coverage of the resistance heating layer 108 on the top surface and sidewalls of the first dielectric layer 102 and the top surface of the top metal line 101 enables the resistance heating layer 108 to achieve stable large-area electrical contact with the top metal line 101 at the bottom of the via, reducing contact resistance. At the same time, the conformal coverage means that the resistance heating layer 108 only covers the sidewalls of the via in the form of a thin film and does not fill the via. This can avoid stress generated inside the via due to excessive thickness of the resistance heating layer 108. Furthermore, it can maintain the thickness of the resistance heating layer 108 at the via with the thickness of the resistance heating layer 108 on the top surface of the first dielectric layer 102, thereby ensuring the uniformity of the resistance value of the entire resistance heating layer 108.

[0118] The conductive layer 113 covers the top surface of the resistance heating layer 108 in the electrode region 100a of the device region 100A and is electrically connected to the resistance heating layer 108 to introduce driving current from the substrate 103 to the heating region 100b.

[0119] It should be noted that the conductive layer 113 is electrically connected to the resistance heating layer 108, which allows current to flow smoothly from the conductive layer 113 into the resistance heating layer 108. At the same time, since the conductive layer 113 covers the resistance heating layer 108, in subsequent processes, the conductive layer 113 can also serve as a physical protective layer for the resistance heating layer 108 in the electrode region 100a, preventing the resistance heating layer 108 from being damaged in the plasma environment.

[0120] In this embodiment, the conductive layer 113 is made of a conductive material layer with low resistivity.

[0121] Specifically, the conductive layer 113 is made of a low resistivity conductive material layer, which can significantly reduce the series resistance of the electrode region 100a and avoid unnecessary Joule heating in the electrode region 100a. This concentrates almost all of the Joule heat generated by the driving current on the resistance heating layer 108 of the heating region 100b, thus preventing the electrode region 100a from reducing energy efficiency or causing local overheating failure due to heat generation.

[0122] In this embodiment, the material of the conductive layer 113 includes one or more of aluminum, copper, nickel, and gold.

[0123] It should be noted that aluminum, copper, nickel and gold are all low resistivity metals, and these materials can form good ohmic contact with the resistance heating layer 108.

[0124] It should be noted that the second dielectric layer 160 simultaneously covers the conductive layer 113 and the resistance heating layer 108 in the device region 100A, exposing only the conductive layer 113 in the isolation region 100B. Therefore, when the conductive layer 113 and the resistance heating layer 108 in the isolation region 100B are removed using the second dielectric layer 160 as a mask, the top of the resistance heating layer 108 in the device region 100A is always completely covered by the second dielectric layer 160, making it less likely to be exposed to the plasma environment used for etching the conductive layer 113 and the resistance heating layer 108 in the isolation region 100B. This avoids the risk of the top surface of the resistance heating layer 108 being bombarded by plasma, oxidized, and thinned, ensuring the stability and uniformity of the resistance value generated by the resistance heating layer 108 when the semiconductor structure is working, and improving the electrical performance of the semiconductor structure.

[0125] In this embodiment, the material of the second dielectric layer 160 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0126] Silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide are all common dielectric materials with good insulation properties and good adhesion and thermal matching with the subsequently deposited insulating layer 190. Furthermore, silicon nitride has high density and can effectively block moisture and ion intrusion. Silicon oxide has a mature process and controllable stress. All these materials are compatible with the conductive layer 113 and the resistance heating layer 108.

[0127] It should be noted that the thickness of the second dielectric layer 160 in the normal direction of the substrate 103 surface should not be too large or too small. If the thickness of the second dielectric layer 160 is too large, the deposition time of the second dielectric layer 160 will be too long, increasing the process cost. At the same time, during the formation of the semiconductor structure, when etching the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B using the second dielectric layer 160 as a mask, the excessive thickness of the second dielectric layer 160 will result in an excessively large aspect ratio of the mask opening in the second dielectric layer 160, affecting the transport of etching gas and causing uneven etching. If the thickness of the second dielectric layer 160 is too small, during the etching of the conductive layer 113 and the resistance heating layer 108 of the isolation region 100B using the second dielectric layer 160 as a mask, the second dielectric layer 160 may be prematurely consumed or broken down, failing to effectively protect the resistance heating layer 108 in the device region 100A, causing the top surface of the resistance heating layer 108 to be exposed to the plasma environment. Therefore, in this embodiment, the thickness of the second dielectric layer 160 is between 50 nanometers and 300 nanometers in the normal direction of the surface of the substrate 103. For example, the thickness of the second dielectric layer 160 is 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers, or 300 nanometers.

[0128] In this embodiment, the semiconductor structure further includes an insulating layer 190, which covers the top of the first dielectric layer 102 and the second dielectric layer 160, and the sidewalls of the second dielectric layer 160, the conductive layer 113 and the resistance heating layer 108.

[0129] Specifically, the insulating layer 190 covers the top of the first dielectric layer 102 and the second dielectric layer 160, as well as the sidewalls of the second dielectric layer 160, the conductive layer 113, and the resistance heating layer 108, providing moisture-proof, oxidation-proof, and mechanical protection for the resistance heating layer 108 and the conductive layer 113.

[0130] In this embodiment, the material of the insulating layer 190 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0131] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a plurality of device regions and a partition region located between adjacent device regions, the device regions including an electrode region and a heating region located between adjacent electrode regions; A first dielectric layer is located on top of the substrate, and the first dielectric layer exposes a portion of the top surface of the substrate of the electrode region; A resistive heating layer covers the first dielectric layer of the device region and the top surface of the substrate exposed by the first dielectric layer, and the resistive heating layer exposes the top surface of the first dielectric layer of the partition region. A conductive layer is located on top of the resistance heating layer in the electrode region. The conductive layer is exposed above the top surface of the resistance heating layer in the heating region, and the conductive layer is in contact with and electrically connected to the resistance heating layer. A second dielectric layer covers the top of the conductive layer and the top of the resistance heating layer exposed by the conductive layer, and the second dielectric layer exposes the conductive layer of the isolation area. The partition region has an opening that penetrates the second dielectric layer, the conductive layer, and the resistance heating layer. The bottom of the opening exposes the top surface of the first dielectric layer, and the sidewalls of the second dielectric layer, the conductive layer, and the resistance heating layer located in the partition region are flush with each other.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

3. The semiconductor structure as described in claim 1, characterized in that, In the normal direction of the substrate surface, the thickness of the second dielectric layer is between 50 nanometers and 300 nanometers.

4. The semiconductor structure as described in claim 1, characterized in that, The substrate includes: a substrate; a top metal line located in the substrate, wherein the top surface of the top metal line is exposed on the substrate; The first dielectric layer exposes the top surface of the top metal wire; The resistive heating layer covers the top surface and sidewalls of the first dielectric layer in the device region, as well as the top surface of the exposed top metal wire of the first dielectric layer.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an insulating layer that covers the top of the first dielectric layer and the second dielectric layer, and the sidewalls that cover the second dielectric layer, the conductive layer, and the resistance heating layer.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the resistance heating layer includes a conductive material with high resistivity.

7. The semiconductor structure as described in claim 1 or 6, characterized in that, The material of the resistance heating layer includes one or more of TaN, AlTaN, TaAl, TaSiN, and NiCr.

8. The semiconductor structure as described in claim 1, characterized in that, The conductive layer is made of a conductive material with low resistivity.

9. The semiconductor structure as described in claim 1 or 8, characterized in that, The conductive layer is made of one or more of aluminum, copper, nickel, and gold.

10. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a plurality of device regions and a partition region located between adjacent device regions, the device regions including electrode regions and heating regions located between adjacent electrode regions, a first dielectric layer is formed on the top of the substrate, the first dielectric layer exposing a portion of the top surface of the substrate of the electrode regions, a resistive heating layer is formed on the top of the substrate covering the first dielectric layer of the device regions and covering the exposed top surface of the substrate of the first dielectric layer, a conductive layer is formed on the top of the substrate covering the resistive heating layer of the electrode regions, the conductive layer exposing the resistive heating layer of the heating regions, and the conductive layer is in contact with the resistive heating layer; A second dielectric layer is formed on top of the substrate in the device region, covering the conductive layer and the resistance heating layer, and the second dielectric layer exposes the conductive layer in the isolation region; Using the second dielectric layer as a hard mask, the conductive layer and the resistance heating layer of the isolation area are removed.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The steps for forming the second dielectric layer include: A second dielectric material layer is formed on top of the substrate, covering the conductive layer and the resistance heating layer; A first mask layer with a first mask opening is formed on top of the second dielectric material layer, and the first mask opening exposes the top surface of the second dielectric material layer in the partition region; Using the first mask layer as a mask, along the opening of the first mask, the second dielectric material layer exposed by the first mask layer is removed, and the remaining second dielectric material layer is used as the second dielectric layer. Remove the first mask layer.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the normal direction of the substrate surface, the thickness of the second dielectric layer is between 50 nanometers and 300 nanometers.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process of removing the conductive layer and the resistance heating layer of the isolation region using the second dielectric layer as a hard mask includes a plasma dry etching process.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing a substrate, the substrate includes a substrate and a top metal line located in the substrate, the substrate exposing the top surface of the top metal line, a first dielectric layer covering the substrate and having a via exposing the top surface of the top metal line, a resistive heating layer covering the top surface of the first dielectric layer of the device region, as well as the bottom and sidewalls of the via, and the resistive heating layer being electrically connected to the top metal line.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, The steps for forming the conductive layer include: A conductive material layer covering the resistance heating layer is formed on top of the substrate; A second mask layer with a second mask opening is formed on top of the conductive material layer, and the second mask opening exposes the conductive material layer of the heating zone; Using the second mask layer as a mask, the conductive material layer of the heating zone is removed along the opening of the second mask, and the remaining conductive material layer is used as the conductive layer. Remove the second mask layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, After removing the second mask layer, the process also includes: An insulating layer is formed on top of the substrate, covering the top of the first dielectric layer and the second dielectric layer, as well as the sidewalls of the second dielectric layer, the conductive layer, and the resistance heating layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, In the step of removing the conductive layer and the resistance heating layer of the partition region, an opening is formed at the top of the first dielectric layer of the partition region that penetrates the second dielectric layer, the conductive layer and the resistance heating layer. After removing the conductive layer and resistance heating layer of the partition area and before forming the insulating layer, the forming method further includes cleaning the sidewalls and bottom of the opening.

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