Wafer level IPD radio frequency module integration method and system based on self-coiled three-dimensional passive structure, system level radio frequency module and composite wafer

Abstract

The present application relates to the technical field of radio frequency front-end integrated package and integrated passive device, and discloses a wafer-level IPD radio frequency module integration method based on a self-coiled three-dimensional passive structure, a system-level radio frequency module and a composite wafer.The method forms a germanium sacrifice layer, a SiNx strain layer, a titanium layer, a copper layer and a gold layer on a substrate, forms a three-dimensional self-coiled inductance structure through patterning and xef2 dry etching release; in the uncut state of the IPD wafer, a radio frequency chip module layer with flip-chip interconnection bumps is flipped to the pad area; then, local laser modification is carried out along the preset cutting path which avoids the flip-chip interconnection area and the coiled suspended area, and the system-level radio frequency module is obtained through splitting separation.The scheme is conducive to shortening the interconnection path between the active chip and the three-dimensional passive inductance, reducing the dependence of discrete mounted inductance, and improving the consistency of wafer-level heterogeneous integration.

Description

Technical Field

[0001] This invention relates to the fields of radio frequency front-end integrated packaging, integrated passive devices, and wafer-level heterogeneous integration technology. Specifically, it relates to a wafer-level IPD radio frequency module integration method based on a self-curling three-dimensional passive structure, a system-level radio frequency module formed by the method, and a composite wafer for fabricating the system-level radio frequency module. Background Technology

[0002] As RF front-end modules evolve towards higher frequencies, smaller sizes, and higher integration, the impact of passive components in low-noise amplifiers, power amplifiers, filters, matching networks, and bias networks on the overall module size and RF performance is becoming increasingly significant. Existing RF front-end modules typically use printed circuit boards (PCBs) to house discrete inductors, capacitors, and other passive components, interconnecting them with active chips via pads, traces, vias, and packages. While this structure is technologically mature, in high-frequency applications, the connection paths between discrete passive components and active chips are relatively long. Traces and solder joints can easily introduce parasitic inductance, parasitic capacitance, and impedance discontinuities, thus affecting the stability of the matching network and RF transmission performance. Furthermore, discrete passive components require a large board area, hindering further miniaturization of the RF front-end module.

[0003] To reduce the dependence of discrete passive devices on PCB area and interconnect paths, integrated passive device (IPD) technology has been used in RF modules. IPD technology can form inductors, capacitors, resistors, and interconnect structures on substrates such as silicon, glass, and sapphire through thin-film processes, thereby integrating some passive networks onto independent substrates. For example, patent document CN104009014B discloses a wafer-level packaged three-dimensional stacked structure and fabrication method for integrated passive devices, which achieves short-distance interconnection between chips and passive devices through IPD chips and metal wiring. This type of technology can shorten signal connection paths to a certain extent, but its passive structure is usually still mainly a planar thin-film structure. Inductors and other devices are easily limited by planar layout area, substrate loss, and wiring parasitics, and there is still room for improvement in further increasing integration density and reducing module size.

[0004] Existing technologies also disclose methods for forming three-dimensional self-curling inductors using the internal stress difference of thin films. For example, patent document CN113488453B discloses a curled inductor for radio frequency integrated circuits, in which the inductor unit includes a strain layer and a conductive pattern, and the inductor unit is curled into a cylindrical structure by strain release. Patent document US9224532B2 also discloses a curled inductor structure suitable for RFICs, which forms a multi-turn curled inductor through sacrificial layer release and strain layer curling. The above technologies can reduce the planar area occupied by the inductor by utilizing the three-dimensional curled structure and provide a way to achieve the miniaturization of radio frequency passive devices.

[0005] However, in the actual manufacturing process of RF front-end modules, simply forming a three-dimensional self-curled inductor structure is not enough to directly complete system-level module integration. Self-curled inductors are typically released three-dimensional floating microstructures, which are highly sensitive to subsequent mounting, flip-chip interconnects, and dicing processes. If the IPD wafer is first diced into individual chips before being mounted, alignment errors and batch assembly variations are likely to increase. Conversely, if conventional dicing methods are used near the released three-dimensional floating structure, mechanical disturbances or contamination may occur to the curled structure and flip-chip solder joints. Therefore, how to reliably interconnect the released three-dimensional self-curled passive structure with the active RF chip while maintaining wafer-level processing consistency, and how to minimize the impact on the three-dimensional floating structure and flip-chip interconnect areas during subsequent separation processes, remain problems that need further resolution in RF front-end module integration. Summary of the Invention

[0006] The technical problem to be solved by this invention is: how to reliably integrate the released three-dimensional self-curling inductor structure with the active radio frequency chip at the wafer level, and reduce the impact on the flip-chip interconnect region and the curled floating region during the subsequent separation process.

[0007] To address the aforementioned technical problems, this invention provides a wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure, comprising the following steps: S1. An IPD wafer comprising a germanium sacrificial layer, a SiNx strain layer, a metal interconnect layer, and a pad layer is formed on a substrate, wherein the SiNx strain layer comprises a low-frequency plasma-deposited silicon nitride layer and a high-frequency plasma-deposited silicon nitride layer stacked along the thickness direction, the metal interconnect layer comprises a titanium layer and a copper layer, and the pad layer comprises a gold layer.

[0008] S2. The IPD wafer is patterned, wherein the IPD wafer includes multiple arrayed module units, each module unit is provided with the self-curling structure region and the pad region, and the preset dicing channel is reserved between adjacent module units.

[0009] S3. The germanium sacrificial layer is removed by dry etching with xenon difluoride, causing the low-frequency plasma-deposited silicon nitride layer and the high-frequency plasma-deposited silicon nitride layer to be released and curled up, forming a three-dimensional self-curled inductor structure in the self-curled structure region.

[0010] S4. While the IPD wafer remains uncut, a Die-to-Wafer flip-chip interconnect process is used to flip-chip the RF chip module layer with flip-chip interconnect bumps onto the pad area, and the flip-chip interconnect bumps are electrically connected to the gold layer to form a composite wafer.

[0011] S5. The composite wafer is attached to the UV film, and the composite wafer is laser-modified along the preset dicing path, so that the substrate forms a laser-modified area at a local position corresponding to the preset dicing path. The preset dicing path is located between adjacent module units and is spaced apart from the flip-chip interconnect area where the flip-chip interconnect bump is located and the curled suspended area where the three-dimensional self-curling inductor structure is located on the plane projection.

[0012] S6. Using the laser-modified region as the dicing guide position, the composite wafer is diced and separated, and the UV film is debonded to obtain an independent system-level radio frequency module.

[0013] Furthermore, the IPD wafer also includes a first aluminum oxide layer and a second aluminum oxide layer, wherein the first aluminum oxide layer is disposed between the germanium sacrificial layer and the low-frequency plasma-deposited silicon nitride layer, and the second aluminum oxide layer is disposed between the high-frequency plasma-deposited silicon nitride layer and the metal interconnect layer.

[0014] Furthermore, after forming the second alumina layer, the second alumina layer and the SiNx strain layer below it are first patterned to define the planar outline of the self-curling structure region, the strain layer pattern, the fixed anchoring region and the metal connection region. The titanium layer is formed in the metal connection area as an adhesion layer or transition connection layer, and the copper layer is formed on the titanium layer, together with the titanium layer, to form a metal interconnect structure connecting the three-dimensional self-curling inductor structure and the pad area. The gold layer is formed on the copper layer, and at least in the pad area, a pad surface layer is formed; After the metal interconnect layer and the pad layer are patterned, a release window communicating with the germanium sacrificial layer is formed in the self-curling structure region.

[0015] Furthermore, in S2, the SiNx strain layer, the metal interconnect layer, and the pad layer are patterned by photolithography and etching processes, so that the metal interconnect layer forms an inductively conductive pattern in the self-curling structure region, and the gold layer forms a pad surface layer in the pad region for connection with the flip-chip interconnect bump.

[0016] Further, in S3, the xenon difluoride dry etching enters from the release window of the self-curling structure region and removes the germanium sacrificial layer. The low-frequency plasma-deposited silicon nitride layer and the high-frequency plasma-deposited silicon nitride layer are released and curled after the germanium sacrificial layer is removed, so that the metal conductive pattern disposed in the self-curling structure region forms a spatial curled conductive path. The titanium layer is formed in the metal connection region and is electrically connected to the spatial curled conductive path.

[0017] Furthermore, in S4, the RF chip module layer is picked up and transferred to the pad area of ​​the IPD wafer by a flip-chip nozzle, and the flip-chip interconnect bump is located on the side of the RF chip module layer facing the IPD wafer and is aligned and connected with the gold layer.

[0018] Furthermore, the radio frequency chip module layer is a low-noise amplifier chip or a power amplifier chip; When the RF chip module layer is a low-noise amplifier chip, the three-dimensional self-curling inductor structure is electrically connected to the low-noise amplifier chip through the metal interconnect layer, and is connected to the corresponding port of the low-noise amplifier chip as at least one of drain choke inductor, input matching inductor, output matching inductor or bias isolation inductor. When the RF chip module layer is a power amplifier chip, the three-dimensional self-curling inductor structure is connected between the drain terminal and the power supply terminal, the input terminal, or the output terminal of the power amplifier chip through the metal interconnect layer.

[0019] Furthermore, in S5, the laser beam scans along the preset cutting path, causing the laser-modified region to extend along the preset cutting path; the laser-modified region, the flip-chip interconnection region, and the curled-up suspended region are spaced apart on the planar projection.

[0020] The present invention also provides a system-level radio frequency module, including an IPD substrate and a radio frequency chip module layer, wherein the IPD substrate includes a substrate and a three-dimensional self-curling inductor structure and a pad area disposed on one side of the substrate; The radio frequency chip module layer is disposed on the side of the IPD substrate having the pad area, and is electrically connected to the gold layer in the pad area through flip-chip interconnect bumps; The three-dimensional self-curling inductor structure includes a curled support structure formed by the release and curling of a low-frequency plasma-deposited silicon nitride layer and a high-frequency plasma-deposited silicon nitride layer, and a metal conductive pattern disposed on the curled support structure; a titanium layer is formed in the pad area or metal connection area and is electrically connected to the metal conductive pattern; the three-dimensional self-curling inductor structure is electrically connected to the RF chip module layer through the metal conductive pattern and the pad area.

[0021] The present invention also provides a composite wafer for fabricating system-level radio frequency modules, comprising an uncut IPD wafer, a three-dimensional self-curling inductor structure, and a radio frequency chip module layer. The IPD wafer includes multiple arrayed module units, with a pre-defined dicing line between adjacent module units. The three-dimensional self-curling inductor structure is disposed within each of the module units and is formed by curling a low-frequency plasma-deposited silicon nitride layer and a high-frequency plasma-deposited silicon nitride layer after the germanium sacrificial layer is removed. The radio frequency chip module layer is flip-chip connected to the pad area of ​​the corresponding module unit through flip-chip interconnect bumps; The pad area includes a titanium layer, a copper layer and a gold layer stacked sequentially, and the flip-chip interconnect bump is electrically connected to the gold layer; the preset dicing channel is located between adjacent RF chip module layers and is spaced apart from the flip-chip interconnect area where the flip-chip interconnect bump is located and the curled suspended area where the three-dimensional self-curling inductor structure is located.

[0022] This invention first releases and forms a three-dimensional self-curling inductor structure on the IPD wafer, then performs die-to-wafer flip-chip interconnection while the IPD wafer is still uncut, and finally performs local laser refining and dicing separation along a predetermined dicing path. This process sequence allows the formation of the three-dimensional self-curling inductor structure, the interconnection of active RF chips, and the separation of independent modules to be completed continuously at the wafer level, avoiding the inconsistencies in alignment references and process dispersion problems caused by dicing followed by chip-by-chip assembly.

[0023] Since the RF chip module layer is directly connected to the pad area of ​​the IPD wafer via flip-chip interconnect bumps, the three-dimensional self-curling inductor structure can form a shorter electrical connection path with the RF chip module layer through the metal interconnect layer. Compared with RF front-end structures that rely on PCB traces and discrete inductors, this solution helps reduce the use of external discrete passive components, reduces parasitic effects caused by interconnect paths, and improves the miniaturization and integration of the RF module.

[0024] After completing the flip-chip interconnect, this invention performs laser refining on the composite wafer along a predetermined dicing path, ensuring that the dicing path avoids the areas containing the flip-chip interconnect bumps and the three-dimensional self-curled inductor structure. This concentrates the action area during wafer separation between adjacent module units, reducing disturbance to the flip-chip solder joints and the curled suspended structure during the separation process. This allows the released three-dimensional self-curled inductor structure to maintain good structural integrity during subsequent module separation.

[0025] Meanwhile, this invention lays out the substrate, three-dimensional self-rolled inductor structure, pad area, RF chip module layer, and pre-defined dicing channels as a whole process object. This allows the IPD wafer to be used not only to form a three-dimensional passive structure, but also to support the flip-chip interconnects of active RF chips, and for subsequent module array separation. This solution can better adapt to the wafer-level packaging requirements of three-dimensional suspended self-rolled structures, providing a more complete manufacturing path for forming compact system-level RF modules. Attached Figure Description

[0026] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in this specification are briefly described below.

[0027] Figure 1 This is a schematic diagram of the front-end stacked structure and patterning process of IPD wafers. Figure 2 A schematic diagram of the formation process of the three-dimensional self-curling inductor structure after the removal of the germanium sacrificial layer; Figure 3 A schematic diagram illustrating the process of Die-to-Wafer flip-chip interconnection between the RF chip module layer and the IPD wafer; Figure 4 A top view of X-ray non-destructive testing after the RF chip module layer and IPD wafer have been flip-chip interconnected; Figure 5 A top view of X-ray non-destructive testing after flip-chip interconnection of another RF chip module layer with IPD wafer; Figure 6 This is a schematic diagram of the arrayed arrangement of heterogeneous integrated structures of power amplifier chips and low-noise amplifier chips in a composite wafer. In the figure: 1. Substrate; 2. Germanium sacrificial layer; 3. First aluminum oxide layer; 4. Low-frequency plasma-deposited silicon nitride layer; 5. High-frequency plasma-deposited silicon nitride layer; 6. Second aluminum oxide layer; 7. Titanium layer; 8. Copper layer; 9. Gold layer; 10. Flip-chip interconnect bump; 11. RF chip module layer; 12. Flip-chip nozzle; 13. RF probe pin pad; 14. DC probe pin pad; 15. Heterogeneous integration structure of power amplifier chip; 16. Heterogeneous integration structure of low-noise amplifier chip. Detailed Implementation

[0028] The following is combined Figures 1 to 6 The technical solution of the present invention will be described below. It should be noted that the following embodiments are used to explain the process sequence, structural relationships, and usage of the present invention, and are not intended to limit the scope of protection of the present invention. Unless otherwise explicitly stated, the following descriptions of orientation such as "upper," "lower," "one side," and "away from" are for ease of understanding based on the states shown in the accompanying drawings, and should not be construed as the sole limitation on the actual preparation direction or usage state.

[0029] Example 1 This embodiment provides a wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure. For example... Figure 1As shown, substrate 1 is provided first. Substrate 1 serves as the support base for the IPD wafer, supporting the subsequent fabrication of the sacrificial layer, strain layer, metal interconnect layer, and pad layer. Substrate 1 can be a glass substrate, quartz substrate, or other low-loss insulating substrate, preferably a glass substrate. In actual fabrication, substrate 1 can be first subjected to solvent cleaning, deionized water rinsing, plasma cleaning, and drying to reduce the impact of particles, organic residues, and moisture on thin film deposition.

[0030] Subsequently, a germanium sacrificial layer 2 is formed on one side of the substrate 1. The germanium sacrificial layer 2 can be formed by sputtering or evaporation and is selectively removed during subsequent xenon difluoride dry etching, thus providing space for the release and curling of the overlying thin film structure. For example, the thickness of the germanium sacrificial layer 2 can be 45 nm to 120 nm. In actual fabrication, the thickness of the germanium sacrificial layer 2 can be selected based on the pattern width of the self-curling structure region, the release window position, the xenon difluoride release rate, and the target curling diameter, so that the germanium sacrificial layer 2 can both support the preceding thin film fabrication and be effectively removed during the release step.

[0031] Furthermore, a first aluminum oxide layer 3 is formed on the side of the germanium sacrificial layer 2 facing away from the substrate 1, and a low-frequency plasma-deposited silicon nitride layer 4 is formed on the side of the first aluminum oxide layer 3 facing away from the germanium sacrificial layer 2. The first aluminum oxide layer 3 can be formed by atomic layer deposition, sputtering, or other thin film deposition methods, and serves to provide transition and isolation between the germanium sacrificial layer 2 and the low-frequency plasma-deposited silicon nitride layer 4. The low-frequency plasma-deposited silicon nitride layer 4 can be formed by low-frequency plasma-enhanced chemical vapor deposition, and serves to form a SiNx strain layer with stress difference together with the subsequent high-frequency plasma-deposited silicon nitride layer 5.

[0032] like Figure 1 As shown, a high-frequency plasma-deposited silicon nitride layer 5 is formed on one side of the low-frequency plasma-deposited silicon nitride layer 4. The high-frequency plasma-deposited silicon nitride layer 5 can be formed using high-frequency plasma-enhanced chemical vapor deposition. The low-frequency plasma-deposited silicon nitride layer 4 and the high-frequency plasma-deposited silicon nitride layer 5 are stacked along the thickness direction. Due to the different deposition conditions, their internal stress states differ, which can generate a curling driving force after the germanium sacrificial layer 2 is removed. In one specific embodiment, the thickness of the low-frequency plasma-deposited silicon nitride layer 4 is 20 nm, and the thickness of the high-frequency plasma-deposited silicon nitride layer 5 is 30 nm. In actual fabrication, the thickness of the low-frequency plasma-deposited silicon nitride layer 4 and the high-frequency plasma-deposited silicon nitride layer 5 can be adjusted by considering the material of the substrate 1, the release size of the germanium sacrificial layer 2, the thickness of the metal conductive pattern in the self-curling structure region, the pattern width of the self-curling structure region, and the required curling diameter, so that the released thin film structure can form a stable three-dimensional self-curling inductor structure.

[0033] Next, a second aluminum oxide layer 6 is formed on the side of the high-frequency plasma-deposited silicon nitride layer 5 that faces away from the low-frequency plasma-deposited silicon nitride layer 4. The second aluminum oxide layer 6 is located between the SiNx strained layer and the metal interconnect layer, and can be used to improve the interlayer bonding between the metal layer and the SiNx strained layer, and also serves as an isolation layer during subsequent etching and release processes. In one specific embodiment, the thickness of the first aluminum oxide layer 3 is 5 nm, and the thickness of the second aluminum oxide layer 6 is 20 nm. In actual fabrication, the thickness of the first aluminum oxide layer 3 and the second aluminum oxide layer 6 can be selected based on the material of the germanium sacrificial layer 2, the deposition process of the SiNx strained layer, the adhesion requirements of the metal interconnect layer, and the isolation requirements during the release etching process.

[0034] Combination Figure 1 After forming the second aluminum oxide layer 6, the second aluminum oxide layer 6 and the SiNx strain layer below it are first patterned to define the planar outline of the self-curling structure region, the strain layer pattern, the fixed anchoring region and the metal connection region. Then, a titanium layer 7 is formed in the metal connection area. The titanium layer 7 is set as an adhesion layer between the copper layer 8 and the underlying layer structure. Subsequently, a copper layer 8 is formed, which together with the titanium layer 7 constitutes a metal interconnect structure connecting the curled structure region and the pad region; then, a gold layer 9 is formed in the region where a pad surface or metal connection surface needs to be formed, and the gold layer 9 forms a pad surface layer for connection with the flip-chip interconnect bump 10 at least in the pad region. After completing the patterning of the metal interconnect layer and the pad layer, a release window connected to the germanium sacrificial layer 2 is formed in the self-curled structure region.

[0035] Through this step-by-step patterned structure, the titanium layer 7, copper layer 8, and gold layer 9 can jointly form the metal connection structure, metal conductive pattern, and pad surface between the subsequent three-dimensional self-curling inductor structure and the pad area.

[0036] The titanium layer 7 can be formed by sputtering or evaporation, and is mainly used for interlayer adhesion and transition connections in the metal connection area. The copper layer 8 can be formed by sputtering or evaporation, and is used to form a conductive metal pattern in the self-curled structure area and to form a metal interconnect path that connects to the pad area. That is to say, the titanium layer 7 is mainly used for adhesion and transition connections between the copper layer 8 and the underlying layer structure, and is not limited to a planar layer that covers the entire surface of the second aluminum oxide layer 6, nor is it limited to a rolled layer that is rolled up as a whole with the SiNx strained layer. The titanium layer 7 can be located in the pad area or the metal connection area, and cooperates with the copper layer 8 to form a metal interconnect path from the three-dimensional self-curled inductive structure to the pad area.

[0037] In one specific embodiment, the thickness of the titanium layer 7 is 10 nm, and the thickness of the copper layer 8 is 200 nm. In actual fabrication, the thicknesses of the titanium layer 7 and the copper layer 8 can be adjusted according to the linewidth of the inductive conductive pattern, the target resistance, the metal adhesion stability, and the mechanical load of the rolled-up metal conductive pattern.

[0038] Next, a gold layer 9 is formed in the area where the pad surface or metal connection surface needs to be formed. The gold layer 9 can be formed by sputtering, evaporation, electroplating, or electroless plating. The gold layer 9 serves as the connection surface for the flip-chip interconnect bumps 10 and reduces the impact of copper layer 8 surface oxidation on the solder connection. For example, the thickness of the gold layer 9 can be 20 nm to 200 nm. In actual fabrication, the thickness of the gold layer 9 can be selected based on the material of the flip-chip interconnect bumps 10, the pad area size, the soldering method, and the pad connection reliability requirements.

[0039] The above patterning process can be performed step-by-step as the stacked structure is formed, creating self-curling structure regions, pad regions, pre-defined dicing paths, and release windows on the IPD wafer. The patterning process may include steps such as photoresist coating, exposure, development, etching, photoresist stripping, and metal lift-off. Through this process, the copper layer 8 and its corresponding metal layer portions can form a conductive metal pattern within the self-curling structure region, and the gold layer 9 can form a pad surface layer within the pad region for connection with the flip-chip interconnect bumps 10. Pre-defined dicing paths are positioned between adjacent module units and spaced apart from the pad regions and the self-curling structure regions.

[0040] Then, as Figure 2 As shown, the germanium sacrificial layer 2 is removed by dry etching with xenon difluoride. Xenon difluoride can enter through the release window of the self-curling structure region to selectively etch the germanium sacrificial layer 2. Since dry etching with xenon difluoride does not require the participation of liquid etchant, it can reduce the adverse effects of liquid surface tension on the film release process, making it more suitable for forming a three-dimensional suspended curled structure. After the germanium sacrificial layer 2 is removed, the low-frequency plasma-deposited silicon nitride layer 4 and the high-frequency plasma-deposited silicon nitride layer 5 lose their local support and release and curl under the action of internal stress difference. The metal conductive pattern set in the self-curling structure region forms a spatial curled conductive path with the SiNx strain layer, thereby forming a three-dimensional self-curling inductor structure; the titanium layer 7 is located in the metal connection region and is electrically connected to the spatial curled conductive path to form a metal connection between the spatial curled conductive path and the pad region or fixed connection region.

[0041] In one specific structure, the curl diameter of the three-dimensional self-curling inductor structure can be 50μm to 90μm, and the curl length can be 3000μm to 4000μm. In actual design, the curl diameter and curl length can be selected according to the target inductance, quality factor, operating frequency band, chip port layout, metal interconnect layer thickness, and IPD wafer layout area.

[0042] exist Figure 2 During the release process shown, the germanium sacrificial layer 2 in the self-rolled structure region is removed, while the non-released region retains its corresponding support, creating a connection between the rolled structure and the fixed end. The conductive metal pattern within the self-rolled structure region forms a conductive path with a spatial winding shape after rolling, which can be used as an inductor structure. The gold layer 9 can have different functions in different regions: When the gold layer 9 is located in the pad area, it serves as the connection surface of the flip-chip interconnect bump 10; When the gold layer 9 is located on the surface of the metal conductive pattern, it can participate in the structural forming along with the corresponding metal conductive pattern.

[0043] The titanium layer 7 mainly serves as an adhesion and connection structure in the metal connection area, ensuring the electrical connection between the spatially curled conductive path and the pad area or fixed connection area.

[0044] Next, as Figure 3 As shown, after the three-dimensional self-curling inductor structure is formed, the IPD wafer is not sliced ​​first; instead, die-to-wafer flip interconnect is performed while the IPD wafer remains uncut. Specifically, flip interconnect bumps 10 are pre-formed on the side of the RF chip module layer 11 facing the IPD wafer. The flip interconnect bumps 10 can be gold balls, SnAgCu solder bumps, AuSn alloy bumps, or other bump structures suitable for flip interconnect. In one specific embodiment, the diameter of the flip interconnect bumps 10 is 75 μm. In actual fabrication, the diameter of the flip interconnect bumps 10 can be selected based on the pad area size, the port spacing of the RF chip module layer 11, the alignment capability of the flip interconnect device, and the soldering method.

[0045] The flip-chip nozzle 12 picks up the RF chip module layer 11 and transfers it over the pad area of ​​the IPD wafer. The flip-chip interconnect bumps 10 are aligned with the gold layer 9 in the pad area via optical alignment, marking alignment, or device visual alignment. In one specific embodiment, the alignment accuracy of the flip-chip interconnect is controlled within ±1 μm. In actual fabrication, the alignment accuracy requirement can be determined based on the diameter of the flip-chip interconnect bumps 10, the pad area size, the port spacing of the RF chip module layer 11, and the layout density of the module cells.

[0046] After alignment, the flip-chip interconnect bumps 10 and the gold layer 9 can be electrically connected by thermocompression bonding, thermocompression welding, reflow soldering, or ultrasonic-assisted bonding. Through this process, the RF chip module layer 11 can be interconnected with the corresponding module unit in the uncut state of the IPD wafer, forming a composite wafer.

[0047] During the aforementioned flip-chip interconnect process, the IPD wafer remains uncut, and multiple module units are still on the same wafer carrier reference. This allows for individual or array-based interconnection using wafer-level alignment equipment, reducing assembly reference differences caused by slicing followed by individual mounting. Since the RF chip module layer 11 is directly connected to the gold layer 9 in the pad area via the flip-chip interconnect bumps 10, the RF chip module layer 11 can access the three-dimensional self-curling inductor structure through the pad area and the metal interconnect layer. The connection path is relatively short, making it suitable for forming miniaturized RF front-end modules.

[0048] After forming the composite wafer, it is attached to a UV film. The UV film can adhere to the back of the composite wafer to temporarily fix it during subsequent laser refining, dicing, and handling. During film attachment, the module unit areas of the composite wafer remain flat and supported, preventing direct pressure on the areas containing the RF chip module layer 11 and the three-dimensional self-curling inductor structure. Subsequently, the composite wafer is laser-refined along a predetermined dicing path, forming a laser-refined region within the substrate 1 at a localized location corresponding to the predetermined dicing path.

[0049] Optionally, the laser modification process can employ a laser slicing method. In one specific embodiment, the laser wavelength is 980 nm, the laser power is 20 W, the laser step size is 0.5 μm, and the preset slicing width is 50 μm. During actual fabrication, the laser wavelength, laser power, scanning step size, and slicing width can be adjusted based on the substrate 1 material and thickness, module unit size, preset slicing width, the arrangement position of the RF chip module layer 11, and the distance between the three-dimensional self-curled inductor structure and the preset slicing width.

[0050] The laser beam scans along a preset cutting path to form a laser-modified region corresponding to the preset cutting path. Since the preset cutting path is located between adjacent module units and is spaced apart from the flip-chip interconnection region where the flip-chip interconnection bump 10 is located and the curled suspended region where the three-dimensional self-curling inductor structure is located on the plane projection, the stress concentration position during subsequent splitting is mainly located between adjacent module units, which can reduce the direct disturbance to the flip-chip interconnection bump 10 and the three-dimensional self-curling inductor structure.

[0051] After laser refining, the composite wafer is diced using the laser-refined area as a dicing guide. Dicing can be achieved through film expansion, mechanical dicing, or by applying controlled external force along the laser-refined area. After the composite wafer is separated into multiple independent modules along a preset dicing path, the UV film is debonded to obtain independent system-level RF modules. UV film debonding can be achieved by reducing adhesion through UV irradiation, allowing the separated modules to be removed from the UV film. This step preserves the three-dimensional self-curling inductor structure, RF chip module layer 11, and pad interconnects after module separation.

[0052] The process sequence in this embodiment is as follows: first, a three-dimensional self-curling inductor structure is formed and released on the IPD wafer; then, die-to-wafer flip-chip interconnection is performed on the uncut IPD wafer; finally, independent modules are obtained by local laser modification and dicing along a preset dicing path. This sequence allows the substrate 1 to serve as the basis for the formation of the thin film stack structure, the flip-chip interconnection reference for the RF chip module layer 11, and the separation support basis for the composite wafer at different stages, which is beneficial for balancing the formation of the three-dimensional self-curling inductor structure, the integration of the RF chip module layer 11, and the reliability of subsequent module separation.

[0053] Example 2 This embodiment, based on Embodiment 1, describes the application of a low-noise amplifier chip in the RF chip module layer 11. After being picked up by the flip-chip nozzle 12, the RF chip module layer 11 is placed above the pad area with the flip-chip interconnect bumps 10 facing the IPD wafer, and the flip-chip interconnect bumps 10 are aligned and connected to the gold layer 9. After connection, the low-noise amplifier chip forms an electrical connection with the three-dimensional self-curling inductor structure on the IPD wafer.

[0054] In this embodiment, the three-dimensional self-rolling inductor structure is electrically connected to the corresponding port of the low-noise amplifier chip via a metal interconnect layer, and can be used as at least one of drain choke inductor, input matching inductor, output matching inductor, or bias isolation inductor, depending on the port function. For example, the three-dimensional self-rolling inductor structure can be connected by forming a connection line from the pad area to the three-dimensional self-rolling inductor structure through copper layer 8, and a pad surface that contacts the flip-chip interconnect bump 10 through gold layer 9, so that the corresponding port of the low-noise amplifier chip is connected to the corresponding matching network, bias network, or choke inductor connection path through flip-chip interconnect bump 10, gold layer 9, copper layer 8, and three-dimensional self-rolling inductor structure.

[0055] Optionally, in low-noise amplifier chip applications, the three-dimensional self-rolled inductor structure may include one or more self-rolled inductors connected to the circuit, each inductor performing drain choke, input matching, output matching, or bias isolation functions according to the port function of the low-noise amplifier chip. In one specific embodiment, when two self-rolled inductors are used as drain choke inductors, the inductances of the two self-rolled inductors are 6.6nH and 9.0nH, respectively, corresponding to quality factors Q of 10.4 and 7.1. In actual design, the inductance and quality factor of the self-rolled inductors can be designed according to the operating frequency band of the low-noise amplifier chip, the drain bias network, the input matching network, the output matching network, and the bias isolation requirements, by adjusting the roll diameter, roll length, metal interconnect layer width, and inductor connection method.

[0056] like Figure 4As shown, the RF chip module layer 11 is located in the corresponding area of ​​the IPD wafer, with surrounding structures related to flip-chip interconnects and passive networks visible. This figure illustrates that active chips and IPD passive structures can form an integrated module at the wafer level. With this structure, the three-dimensional self-curling inductor structure no longer participates in assembly as a separate discrete device, but rather serves as an integrated passive network on the IPD wafer connected to the low-noise amplifier chip, shortening the RF connection path and reducing board-level assembly steps.

[0057] Optionally, after the low-noise amplifier chip flip-chip connection is completed, the connection status between the flip-chip interconnect bump 10 and the gold layer 9 can be confirmed by microscopic observation, electrical connection testing, or RF probe testing. For arrayed composite wafers, wafer-level inspection can also be performed before dicing to screen for module units with abnormal connections. This inspection process does not change the module structure but can improve the process controllability before subsequent separation and packaging.

[0058] Example 3 This embodiment, based on Embodiment 1, describes the application of the RF chip module layer 11 as a power amplifier chip. The power amplifier chip is also flip-chip connected to the pad area of ​​the IPD wafer via flip-chip interconnect bumps 10. The flip-chip interconnect bumps 10 are electrically connected to the gold layer 9. The three-dimensional self-curled inductor structure is connected to the corresponding port of the power amplifier chip through the metal interconnect path formed by the copper layer 8 and the metal connection area where the titanium layer 7 is located.

[0059] In this embodiment, the three-dimensional self-rolling inductor structure can be connected between the drain terminal and the power supply terminal of the power amplifier chip through a metal interconnect layer, or it can be connected to the input or output terminal of the power amplifier chip to form a bias inductor, input matching inductor, or output matching inductor in conjunction with the power amplifier chip. The specific connection relationship can be arranged according to the port distribution of the power amplifier chip and the layout of the IPD wafer, but the flip-chip interconnect bump 10 should be aligned and connected with the gold layer 9, and the three-dimensional self-rolling inductor structure should be connected to the corresponding port through the metal conductive pattern and the metal interconnect path.

[0060] Optionally, in power amplifier chip applications, the three-dimensional self-rolled inductor structure may include multiple self-rolled inductors. For example, two self-rolled inductors are connected in series between the drain terminal and the power supply terminal of the power amplifier chip, serving as drain choke inductors; one self-rolled inductor is connected in parallel to the input terminal of the power amplifier chip, serving as input matching inductor; and another self-rolled inductor is connected in series to the output terminal of the power amplifier chip, serving as output matching inductor. In one specific embodiment, the inductance of the self-rolled inductors can be selected from 5.3nH, 7nH, or 10nH, corresponding to a quality factor Q of 12.4 to 13.4. In actual design, the number, size, connection position, and metal interconnect path of the self-rolled inductors can be designed according to the operating frequency band, output power, input matching requirements, output matching requirements, and drain bias network of the power amplifier chip.

[0061] Figure 5 and Figure 4 This invention demonstrates that the wafer-level integration path can adapt to the layout connection requirements of different RF chip module layers 11. In power amplifier chip applications, the three-dimensional self-curling inductor structure can be placed around the chip or near the corresponding metal interconnect path, and connected to the corresponding port of the power amplifier chip through the pad area, thereby obtaining a compact power amplifier RF module structure.

[0062] Optionally, after the power amplifier chip completes the flip-chip interconnection, the layout of the number, relative position, and metal interconnect path of the three-dimensional self-rolling inductor structure can be adjusted according to the operating frequency band and port matching requirements of the power amplifier chip. This adjustment is an adaptation around the same wafer-level IPD integration path and does not change the main process line of first releasing the three-dimensional self-rolling inductor structure, then performing whole-wafer flip-chip interconnection, and finally local laser-modified separation.

[0063] Example 4 This embodiment provides a system-level radio frequency (RF) module and a composite wafer for fabricating the system-level RF module. The composite wafer formed before dicing includes an uncut IPD wafer, a three-dimensional self-rolling inductor structure, and an RF chip module layer 11. The uncut IPD wafer includes multiple arrayed module units, with a preset dicing channel between adjacent module units; the three-dimensional self-rolling inductor structure is disposed within each module unit and is formed by rolling up a low-frequency plasma-deposited silicon nitride layer 4 and a high-frequency plasma-deposited silicon nitride layer 5 after the germanium sacrificial layer 2 is removed; the RF chip module layer 11 is flip-chip connected to the pad area of ​​the corresponding module unit via flip-chip interconnect bumps 10.

[0064] like Figure 6As shown, when the composite wafer is in an uncuttered state, multiple module units can be arrayed on the same IPD wafer. Each module unit can form different types of heterogeneous integrated structures according to the different functions of the RF front-end circuit. For example, it can form a heterogeneous integrated structure 15 for power amplifier chips for power amplification, or a heterogeneous integrated structure 16 for low-noise receiver amplification. Each heterogeneous integrated structure is surrounded by RF probe pads 13 and DC probe pads 14. The RF probe pads 13 are used for contact with RF test probes, and the DC probe pads 14 are used for contact with DC test probes, thereby enabling wafer-level RF testing, DC bias testing, or connectivity testing of the corresponding module units before wafer separation. Through this arrangement, arrayed testing of different types of RF module units can be completed before composite wafer separation, which is beneficial for screening abnormal module units and improving the process controllability before subsequent wafer separation and packaging.

[0065] In the composite wafer, the pad area includes a metal interconnect structure formed by a titanium layer 7, a copper layer 8, and a gold layer 9. Flip-chip interconnect bumps 10 are electrically connected to the gold layer 9, and the titanium layer 7 is electrically connected to the metal conductive pattern in the three-dimensional self-curled inductor structure. Pre-defined cleaving paths are located between adjacent RF chip module layers 11, and are spaced apart from the flip-chip interconnect region where the flip-chip interconnect bumps 10 are located, and the curled-up suspended region where the three-dimensional self-curled inductor structure is located. This layout provides a clear path for subsequent laser refining and wafer separation, while the flip-chip interconnect region and the curled-up suspended region are avoided as functional areas.

[0066] Furthermore, the system-level RF module obtained after laser modification, cleavage separation, and UV film debonding includes an IPD substrate and an RF chip module layer 11. The IPD substrate includes a substrate 1 and a three-dimensional self-curling inductor structure and a pad region disposed on one side of the substrate 1; the RF chip module layer 11 is disposed on the side of the IPD substrate with the pad region and is electrically connected to the gold layer 9 in the pad region through flip-chip interconnect bumps 10. The three-dimensional self-curling inductor structure includes a curled support structure formed by the release and curling of a low-frequency plasma-deposited silicon nitride layer 4 and a high-frequency plasma-deposited silicon nitride layer 5, and a metal conductive pattern disposed on the curled support structure; a titanium layer 7 is formed in the pad region or the metal connection region and is electrically connected to the metal conductive pattern.

[0067] In this embodiment, the composite wafer is an intermediate product form before the separation of the system-level RF module. It retains the uncut IPD wafer, the three-dimensional self-curling inductor structure, and the flip-chip connected RF chip module layer 11.

Claims

1. A wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure, characterized in that, Includes the following steps: S1. An IPD wafer comprising a germanium sacrificial layer (2), a SiNx strain layer, a metal interconnect layer and a pad layer is formed on a substrate (1), wherein the SiNx strain layer comprises a low-frequency plasma-deposited silicon nitride layer (4) and a high-frequency plasma-deposited silicon nitride layer (5) stacked along the thickness direction, the metal interconnect layer comprises a titanium layer (7) and a copper layer (8), and the pad layer comprises a gold layer (9); S2. The IPD wafer is patterned, wherein the IPD wafer includes multiple arrayed module units, each module unit is provided with a self-rolling structure region and a pad region, and a preset dicing channel is reserved between adjacent module units; S3. The germanium sacrificial layer (2) is removed by dry etching with xenon difluoride, so that the low-frequency plasma-deposited silicon nitride layer (4) and the high-frequency plasma-deposited silicon nitride layer (5) are released and rolled up, forming a three-dimensional self-rolled inductor structure in the self-rolled structure region. S4. While the IPD wafer is in an uncut state, the RF chip module layer (11) with flip-chip interconnect bumps (10) is flip-chipped onto the pad area using the Die-to-Wafer flip-chip interconnect process, and the flip-chip interconnect bumps (10) are electrically connected to the gold layer (9) to form a composite wafer. S5. The composite wafer is attached to the UV film, and the composite wafer is laser modified along the preset dicing channel, so that the substrate (1) forms a laser modified area at a local position corresponding to the preset dicing channel. The preset dicing channel is located between adjacent module units and is spaced apart from the flip interconnect area where the flip interconnect bump (10) is located and the curled suspended area where the three-dimensional self-curling inductor structure is located on the plane projection. S6. Using the laser-modified region as the dicing guide position, the composite wafer is diced and separated, and the UV film is debonded to obtain an independent system-level radio frequency module.

2. The wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure according to claim 1, characterized in that: The IPD wafer further includes a first aluminum oxide layer (3) and a second aluminum oxide layer (6). The first aluminum oxide layer (3) is disposed between the germanium sacrificial layer (2) and the low-frequency plasma-deposited silicon nitride layer (4), and the second aluminum oxide layer (6) is disposed between the high-frequency plasma-deposited silicon nitride layer (5) and the metal interconnect layer.

3. The wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure according to claim 2, characterized in that: After the second aluminum oxide layer (6) is formed, the second aluminum oxide layer (6) and the SiNx strain layer below it are first patterned to define the planar outline of the self-curling structure region, the strain layer pattern, the fixed anchoring region and the metal connection region. The titanium layer (7) is formed in the metal connection area as an adhesion layer or transition connection layer, and the copper layer (8) is formed on the titanium layer (7), together with the titanium layer (7) to form a metal interconnect structure connecting the three-dimensional self-curling inductor structure and the pad area; The gold layer (9) is formed on the copper layer (8) and forms a pad surface layer at least in the pad area; After the metal interconnect layer and the pad layer are patterned, a release window communicating with the germanium sacrificial layer (2) is formed in the self-curling structure region.

4. The wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure according to claim 1, characterized in that: In S2, the SiNx strain layer, the metal interconnect layer and the pad layer are patterned by photolithography and etching processes, so that the metal interconnect layer forms an inductively conductive pattern in the self-curling structure region, and the gold layer (9) forms a pad surface layer in the pad region for connection with the flip-chip interconnect bump (10).

5. The wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure according to claim 1, characterized in that: In S3, the xenon difluoride dry etching enters from the release window of the self-curling structure region and removes the germanium sacrificial layer (2). The low-frequency plasma-deposited silicon nitride layer (4) and the high-frequency plasma-deposited silicon nitride layer (5) are released and curled after the germanium sacrificial layer (2) is removed, so that the metal conductive pattern disposed in the self-curling structure region forms a spatial curled conductive path. The titanium layer (7) is formed in the metal connection area and is electrically connected to the spatially coiled conductive path.

6. The wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure according to claim 1, characterized in that: In S4, the RF chip module layer (11) is picked up and transferred to the pad area of ​​the IPD wafer by a flip-chip nozzle (12). The flip-chip interconnect bump (10) is located on the side of the RF chip module layer (11) facing the IPD wafer and is aligned with the gold layer (9).

7. The wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure according to claim 1, characterized in that: In S4, the radio frequency chip module layer (11) is a low-noise amplifier chip or a power amplifier chip; When the RF chip module layer (11) is a low noise amplifier chip, the three-dimensional self-curling inductor structure is electrically connected to the low noise amplifier chip through the metal interconnect layer, and is connected to the corresponding port of the low noise amplifier chip as at least one of drain choke inductor, input matching inductor, output matching inductor or bias isolation inductor. When the RF chip module layer (11) is a power amplifier chip, the three-dimensional self-curling inductor structure is connected between the drain terminal and the power supply terminal, the input terminal or the output terminal of the power amplifier chip through the metal interconnect layer.

8. The wafer-level IPD RF module integration method based on a self-curling three-dimensional passive structure according to claim 1, characterized in that: In S5, the laser beam scans along the preset cutting path, causing the laser-modified region to extend along the preset cutting path; the laser-modified region, the flip-chip interconnection region, and the curled-up suspended region are spaced apart on the planar projection.

9. A system-level radio frequency module, characterized in that, include: IPD substrate, the IPD substrate includes a substrate (1) and a three-dimensional self-curling inductor structure and a pad area disposed on one side of the substrate (1); Radio frequency chip module layer (11) is disposed on the side of the IPD substrate having the pad area and is electrically connected to the gold layer (9) in the pad area through flip-chip interconnect bumps (10); The three-dimensional self-curling inductor structure includes a curled support structure formed by the release and curling of a low-frequency plasma-deposited silicon nitride layer (4) and a high-frequency plasma-deposited silicon nitride layer (5), and a metal conductive pattern disposed on the curled support structure. A titanium layer (7) is formed in the pad area or metal connection area and is electrically connected to the metal conductive pattern; The three-dimensional self-curling inductor structure is electrically connected to the radio frequency chip module layer (11) through the metal conductive pattern and the pad area.

10. A composite wafer for fabricating system-level radio frequency modules, characterized in that, include: An uncut IPD wafer, wherein the IPD wafer comprises multiple arrayed module units, and a preset dicing channel is provided between two adjacent module units; A three-dimensional self-curling inductor structure is disposed in each of the module units and is formed by curling a low-frequency plasma-deposited silicon nitride layer (4) and a high-frequency plasma-deposited silicon nitride layer (5) after the germanium sacrificial layer (2) is removed. Radio frequency chip module layer (11), wherein the radio frequency chip module layer (11) is flip-chip connected to the pad area of ​​the corresponding module unit through flip-chip interconnect bumps (10); The pad area includes a titanium layer (7), a copper layer (8) and a gold layer (9) stacked sequentially. The flip-chip interconnect bump (10) is electrically connected to the gold layer (9). The preset dicing channel is located between adjacent RF chip module layers (11) and is spaced apart from the flip-chip interconnect area where the flip-chip interconnect bump (10) is located and the curled suspended area where the three-dimensional self-curling inductor structure is located.

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