Panel construction

Abstract

This invention discloses a plate structure comprising a bridging plate, functional wafer units, gaps, and a filling material. The bridging plate defines a coefficient of thermal expansion (CTE) of no more than 10 ppm / °C along a horizontal plane and has channels. The functional wafer units are at least partially housed within the channels. Gaps extend between the functional wafer units and the bridging plate. Filler material is disposed within the gaps. By controlling the coefficient of thermal expansion of the bridging plate and integrating the functional wafer units within the channels, the plate structure of this invention effectively addresses thermal stress issues and improves structural integration.

Description

Technical Field

[0001] This invention relates to a plate structure that can be applied to semiconductor packaging or other electronic components. Background Technology

[0002] As electronic products trend towards thinner and smaller designs, semiconductor packaging technology is constantly evolving. While these technologies each have their own unique features, they still face numerous technical bottlenecks and challenges. The primary issue lies in the difference in the coefficient of thermal expansion (CTE) between different materials within the packaging structure. When electronic devices experience temperature changes during operation, the mismatch in thermal expansion between materials can lead to internal stress accumulation, resulting in reliability problems such as structural warping and interface delamination. Secondly, with the improvement of chip performance, traditional electrical interconnection methods are no longer sufficient to meet the demands of high-speed transmission. Long wire paths not only cause signal loss but may also introduce severe crosstalk interference, limiting the overall transmission bandwidth.

[0003] Furthermore, the purely electrical interconnect architecture limits the possibility of future development towards optoelectronic integration. In terms of packaging density, existing technologies often struggle to achieve high levels of functional integration within a limited space. At the process level, current packaging technologies generally require extremely high alignment precision and involve complex process steps, which not only affects yield but also increases production costs. The complex process flow also increases the potential risk of failure, impacting product stability and consistency.

[0004] In view of this, the industry urgently needs a new packaging structure that can simultaneously solve the above-mentioned technical challenges, effectively manage thermal stress, improve signal transmission efficiency, and increase integration density, so as to improve process feasibility and reliability. Summary of the Invention

[0005] The purpose of this invention is to provide a plate structure and one or more exemplary embodiments thereof, all of which are used to illustrate that the manufacturing method of the plate structure of this invention can take into account both the risk of thermal stress and the reduction of manufacturing costs.

[0006] To achieve the above objectives, the present invention provides a board structure comprising: a bridging board having a coefficient of thermal expansion (CTE) of not more than 10 ppm / °C along a horizontal plane, the bridging board having a channel; a functional wafer unit at least partially housed in the channel; a gap extending between the functional wafer unit and the bridging board; and a filler material filling the gap.

[0007] In some embodiments, the bridging plate is a single-layer plate.

[0008] In some embodiments, the bridging plate is a multilayer board.

[0009] In some embodiments, the bridging plate comprises glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, or polyimide (PI), or a combination of one or more of the above materials.

[0010] In some embodiments, the channel connects both sides of the bridge plate.

[0011] In some embodiments, the functional chip unit is housed in a channel, and the bridge board and the functional chip unit each have a defined thickness, with the thickness of the functional chip unit approaching the thickness of the bridge board.

[0012] In some embodiments, the coefficient of thermal expansion (CTE) of the bridging plate along the horizontal plane is not greater than 8 ppm / °C.

[0013] In some embodiments, the coefficient of thermal expansion (CTE) of the bridging plate along the horizontal plane is not greater than 4 ppm / °C.

[0014] In some embodiments, the functional wafer cells approach the filler material along the horizontal plane.

[0015] In some embodiments, the coefficient of thermal expansion (CTE) of the functional chip unit is defined along the horizontal plane; the ratio of the coefficient of thermal expansion of the bridge board to that of the functional chip unit is not less than 0.5.

[0016] In some embodiments, the coefficient of thermal expansion (CTE) of the functional chip unit is defined along the horizontal plane; the ratio of the coefficient of thermal expansion of the bridge board to that of the functional chip unit is not greater than 2.5.

[0017] In some embodiments, the filler material defines a coefficient of thermal expansion (CTE) along the horizontal plane; the coefficient of thermal expansion of the filler material is greater than the coefficient of thermal expansion of the bridging plate and the coefficient of thermal expansion of the functional chip unit.

[0018] In some embodiments, a functional chip unit includes one or more functional chips.

[0019] In some embodiments, the functional chip unit includes one or more bridge dies (BD), deep trench capacitors (DTC), voltage regulators (VR), integrated passive devices (IPD), electrical integrated circuits (EIC), photonic integrated circuits (PIC), or optoelectronic components, or combinations thereof.

[0020] In some embodiments, the optoelectronic element includes an optical transmitter and / or an optical sensor.

[0021] In some embodiments, the light emitter is a light-emitting diode (LED), an organic light-emitting diode (OLED), or a laser diode (LD).

[0022] In some embodiments, the plate structure further includes a material property layer located on one side of the bridging plate, at least partially covering the gap and connecting the filler material.

[0023] In some embodiments, at least two of the material property layer, filler material, and bridging plate contain the same material.

[0024] In some embodiments, the material property layer comprises polyimide (PI).

[0025] In some embodiments, the material property layer defines the coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the coefficient of thermal expansion of the material property layer and the coefficient of thermal expansion of the bridging plate is not greater than 1.3 ppm / °C.

[0026] In some embodiments, the material property layer defines the coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the coefficient of thermal expansion of the material property layer and the coefficient of thermal expansion of the bridging plate is not less than 0.7 ppm / °C.

[0027] In some embodiments, the material property layer connects to the bridging plate and is arranged discontinuously along the horizontal plane of the bridging plate.

[0028] In some embodiments, the material property layer connects to the bridging plate and is arranged in a planar manner along the horizontal plane of the bridging plate.

[0029] In some embodiments, the board structure further includes: a conductive element, independent of the channel, through which a bridging plate is disposed.

[0030] In some embodiments, the board structure further includes a layer structure that at least partially covers one side of the bridging board, the gap, and the functional wafer unit; wherein the layer structure and the functional wafer unit can communicate with each other via at least one of electrical signals and optical signals.

[0031] In some embodiments, the board configuration further includes: a conductive element, independent of the channel, passing through the bridging plate, and electrically connected to the layer structure.

[0032] In some embodiments, the layer structure is defined with a dielectric loss (Df) of no more than 0.006 at a frequency of 10 GHz.

[0033] In some embodiments, the layer structure spans and at least partially covers the gap.

[0034] In some embodiments, the layer structure includes a layer material and one or more communication layers bonded to the layer material; the communication layers or at least a portion of these communication layers span and at least partially cover the gap.

[0035] In some embodiments, the board configuration further includes another layer that at least partially covers the bridge board, the gap, and the other side of the functional wafer unit; wherein the other layer communicates with the functional wafer unit via at least one of electrical signals and optical signals.

[0036] In some embodiments, another layer is defined with a dielectric loss (Df) of no more than 0.006 at a frequency of 10 GHz.

[0037] In some embodiments, another layer of structure spans and at least partially covers the gap.

[0038] In some embodiments, another layer structure includes a layer material and one or more communication layers bonded to the layer material, the communication layers or at least a portion of these communication layers spanning and at least partially covering the gap.

[0039] In some embodiments, the layer structure includes a waveguide structure that couples to functional wafer units.

[0040] In some embodiments, another layer includes a waveguide structure that couples to a functional chip unit.

[0041] In some embodiments, the layer structure and the other layer structure are asymmetrical.

[0042] In some embodiments, the absolute difference ratio of the sum of the volume expansions of one layer structure and another layer structure within the plane of the bridging plate is not less than 30%.

[0043] In some embodiments, the functional chip unit includes one or more optical transmitters and / or one or more optical sensors.

[0044] In some embodiments, the light emitter and / or light detector are positioned toward the waveguide structure.

[0045] In some embodiments, the functional wafer unit has a linewidth of no more than 1 μm on the side facing the layer structure.

[0046] In some embodiments, the functional wafer unit has a line spacing of no more than 1 μm on the side facing the layer structure.

[0047] In some embodiments, the functional wafer unit has a linewidth of no more than 1 μm on the side facing the other layer structure.

[0048] In some embodiments, the functional wafer unit has a line spacing of no more than 1 μm on the side facing the other layer structure.

[0049] In some embodiments, the board structure further includes: a conductive element, independent of the channel, a bridging plate, an electrical connection layer structure, and another layer structure.

[0050] In some embodiments, the plate structure further includes: another material property layer located between the other layer structure and the bridging plate and connected to the filler material.

[0051] In some embodiments, the other material property layer is made of the same material as the filler material.

[0052] In some embodiments, another material property layer comprises polyimide.

[0053] In some embodiments, another material property layer connects to the bridging plate and is laid out in a consecutive and discontinuous manner along the horizontal plane of the bridging plate.

[0054] In some embodiments, another material property layer connects to the bridging plate and is laid out in an aplanar manner along the horizontal plane of the bridging plate.

[0055] In some embodiments, the bridging plate is a multilayer plate, including multiple layers of boards and one or more adhesive layers bonding these boards.

[0056] In some embodiments, the conductive element includes a plurality of secondary conductive elements passing through the plates and conductive material joining two adjacent secondary conductive elements in a direction perpendicular to the vertical plane.

[0057] In some embodiments, the bridging plate includes a conductive layer disposed on one or at least a portion of the plates, and the conductive material is electrically connected to the corresponding one or more secondary conductive elements through the conductive layer.

[0058] In some embodiments, the filler material may include silicon dioxide (SiO2), ceramics, glass ceramics, glass frit, glass powder, glass paste, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of the above materials.

[0059] In some embodiments, the material property layer may comprise silicon dioxide (SiO2), ceramic, glass ceramic, glass substrate, glass powder, glass paste, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of the above materials.

[0060] In some embodiments, the adhesive layer may comprise a glass substrate, glass powder, glass paste, or a combination of one or more of the above materials.

[0061] In some embodiments, the plate configuration further includes a temporary carrier plate that connects the bridging plate.

[0062] In some embodiments, the board configuration further includes a temporary carrier plate that connects the bridging board via a layered structure.

[0063] In some embodiments, the temporary carrier is or includes a glass substrate.

[0064] In some embodiments, the bridging plate defines one or more corners or side edges, and a material property layer is arranged in a planar manner along the horizontal plane of the bridging plate, covering at least one of the side edges.

[0065] In some embodiments, the bridging plate defines one or more corners or side edges and a chamfer disposed at one of the corners or side edges, and the material property layer is arranged in a planar manner along the horizontal plane of the bridging plate, covering the chamfer.

[0066] In some embodiments, the plate structure further includes: a conductive element, independent of the channel, passing through the bridging plate and the filler material and electrically connected to the layer structure.

[0067] To achieve the above objectives, the present invention provides a stacked structure, comprising: a packaging substrate; and the aforementioned board structure, stacked on the packaging substrate; wherein the functional chip units of the board structure communicate with the packaging substrate via at least one of electrical signals and optical signals.

[0068] In some embodiments, the packaging substrate comprises glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, polyimide (PI), bismaleimide triazine resin (BT), or FR4 substrate, or a combination of one or more of the above materials.

[0069] In some embodiments, the packaging substrate includes at least one of a waveguide structure and an electrical layer.

[0070] To achieve the above objectives, the present invention also provides an electronic device, comprising: a substrate; the aforementioned plate structure, stacked on the substrate; a plurality of electronic components disposed on one side of the plate structure, communicating with a functional chip unit via a layer structure using at least one of electrical signals and optical signals; and a plurality of externally conductive structures disposed on the other side of the plate structure, located between the plate structure and the substrate, and electrically connecting the plate structure and the substrate.

[0071] In some embodiments, the electronic components may be high-bandwidth memory (HBM), a switch chip, a neural processing unit (NPU), a tensor processing unit (TPU), a central processing unit (CPU), or a graphics processing unit (GPU), or a combination of one or more of the above components.

[0072] In some embodiments, one of the electronic components is a light sensing element, a photoelectric conversion element, or a combination of one or more of the above elements.

[0073] In some embodiments, one of the electronic components has a linewidth of no more than 1 μm on the side facing the layer structure.

[0074] In some embodiments, one of the electronic components has a line spacing of no more than 1 μm on the side facing the layer structure.

[0075] In some embodiments, the electronic device further includes a protective layer covering the electronic components and connecting them to the board structure.

[0076] The foregoing is merely illustrative and not intended to limit the invention. In addition to the illustrative embodiments, examples and features described above, other embodiments, examples and features of the invention will become clear from the accompanying drawings and the following detailed description. Attached Figure Description

[0077] Figure 1A This is a cross-sectional schematic diagram of the plate structure 100A according to the first embodiment of the present invention; Figure 1B This is a cross-sectional schematic diagram of plate structure 100B according to another embodiment of the present invention; Figure 1C This is a cross-sectional schematic diagram of the plate structure 100C according to another embodiment of the present invention; Figure 1D This is a cross-sectional schematic diagram of the plate structure 100D according to another embodiment of the present invention; Figure 1E This is a cross-sectional schematic diagram of plate structure 100E according to another embodiment of the present invention; Figure 2A This is a cross-sectional schematic diagram of the plate structure 100F according to an embodiment of the present invention; Figure 2B This is a cross-sectional schematic diagram of the plate structure 100G according to an embodiment of the present invention; Figure 2C This is a cross-sectional schematic diagram of the plate structure 100H according to an embodiment of the present invention; Figure 2D This is a cross-sectional schematic diagram of the plate structure 100I according to an embodiment of the present invention; Figure 2E This is a cross-sectional schematic diagram of the plate structure 100J according to an embodiment of the present invention; Figure 3A This is a cross-sectional schematic diagram of the plate structure 200A according to an embodiment of the present invention; Figure 3B This is a cross-sectional schematic diagram of the plate structure 200B according to an embodiment of the present invention; Figure 3C This is a cross-sectional schematic diagram of the plate structure 200C according to an embodiment of the present invention; Figure 3D This is a cross-sectional schematic diagram of the plate structure 200D according to an embodiment of the present invention; Figure 3E This is a cross-sectional schematic diagram of the plate structure 200E according to an embodiment of the present invention; Figure 4This is a cross-sectional schematic diagram of the stacked plate structure according to an embodiment of the present invention; Figure 5A This is a cross-sectional schematic diagram of electronic device I according to an embodiment of the present invention; Figure 5B This is a cross-sectional schematic diagram of electronic device II according to an embodiment of the present invention; Figure 5C This is a cross-sectional schematic diagram of electronic device III according to an embodiment of the present invention; Figure 5D This is a cross-sectional schematic diagram of electronic device IV according to an embodiment of the present invention; Figure 6 This is a cross-sectional schematic diagram of the electronic device V according to an embodiment of the present invention; Figures 7A to 7G This is a schematic diagram of the manufacturing method of the plate structure 100K according to an embodiment of the present invention; Figure 8A This is a cross-sectional schematic diagram of the plate structure 100L according to an embodiment of the present invention; Figure 8B This is a cross-sectional schematic diagram of the plate structure 100M according to an embodiment of the present invention; and Figure 8C This is a cross-sectional schematic diagram of the plate structure 100N according to an embodiment of the present invention. Detailed Implementation

[0078] The plate structure according to a preferred embodiment of the present invention will now be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals.

[0079] The advantages and features of the present invention, as well as the methods of implementing the invention, will be clearly explained in the following embodiments with reference to the accompanying drawings. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments described below. Rather, the embodiments disclosed below are only intended to make this specification clear and complete, and to fully convey the scope of the invention to those skilled in the art. The invention should be defined only by the scope of the claims; therefore, well-known constituent elements, operations, and techniques are not described in detail in the embodiments to avoid obscuring the technical features of the invention. Throughout the specification, identical or similar elements are represented by identical or similar element symbols. Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly or indirectly mechanically connected” to the other element, or “electrically connected” to the other element, and one or more intermediate elements may be inserted therein. It is further understood that in this specification, the terms “comprising” or “including” are used to specify the features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or components, or combinations thereof. The term “and / or” indicates the possibility of intersection or union. Unless otherwise defined, all terms (including technical and scientific terms) used in this specification shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Further, terms or words (e.g., terms or words as defined in the claims or common dictionaries) shall be interpreted as having the same meaning as they have in the description of the relevant art, and shall not be construed as having an ideal or overly rigorous meaning unless expressly defined in this specification.

[0080] Reference Figure 1A The diagram illustrates a board structure 100A according to a first embodiment of the present invention. Board structure 100A includes a bridging board 10, functional wafer units 20, a slot 30, and a filler material 40. The bridging board 10 defines a coefficient of thermal expansion (CTE) of no more than 8 ppm / °C along a horizontal plane (XY plane); the bridging board 10 has a channel 35. The functional wafer units 20 are at least partially accommodated in the channel 35. The slot 30 extends between the functional wafer units 20 and the bridging board 10. The filler material 40 fills the slot 30.

[0081] The bridging board 10 can be a single-layer board or a multi-layer board (e.g., a multilayer board). In some embodiments, the bridging board 10 may include an organic material, or at least one layer of the bridging board 10 may contain an organic material. In some embodiments, the bridging board 10 may contain glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, or polyimide (PI), or a combination of one or more of the above materials. As shown in the figure, the number of channels 35 is not limited to one, and the number of corresponding components also increases accordingly. Channels 35 may connect both sides of the bridging board 10, or at least one side of the bridging board 10, or may not connect both sides of the bridging board 10, and are not limited thereto.

[0082] The functional chip unit 20 includes one or more chips. The functional chip unit 20 can be housed in the channel 35 in a modular or non-modular form. The bridging plate 10 and the functional chip unit 20 each have a defined thickness, with the thickness of the functional chip unit 20 approaching the thickness of the bridging plate 10. Typically, it is also beneficial for subsequent processes to fully house the functional chip unit 20 within the channel 35; therefore, the thickness of the functional chip unit 20 is no greater than the thickness of the bridging plate 10. The functional chip unit 20 contacts the filler material 40 along a horizontal plane. The functional chip unit 20 includes one or more bridge dies (BD), deep trench capacitors (DTC), voltage regulators (VR), integrated passive devices (IPD), electrical integrated circuits (EIC), photonic integrated circuits (PIC), or optoelectronic components, or combinations of one or more of the above materials, but is not limited thereto. Optoelectronic components include optical transmitters and / or optical sensors. The light emitter is a light-emitting diode (LED), an organic light-emitting diode (OLED), or a laser diode (LD).

[0083] The filler material 40 may contain silicon dioxide (SiO2), ceramics, glass ceramics, glass frit, glass powder, glass paste, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of the above materials.

[0084] exist Figure 1B In the board structure 100B, the board structure 100B further includes a material property layer 60, located on at least one side of the bridging plate 10 and connected to the filler material 40; the material property layer 60 may at least partially cover the gap 30. The material property layer 60 may comprise glass, silicon dioxide (SiO2), ceramic, glass ceramic, glass dielectric, glass powder, glass paste, compound semiconductor material, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of the above materials. In one embodiment, at least two of the material property layer 60, the filler material 40, and the bridging plate 10 may comprise the same or different materials, such as polyimide or epoxy resin, silicone, etc.; but are not limited thereto. The material property layer 60 connects to the bridging plate 10 and is laid out discontinuously along the horizontal plane of the bridging plate 10; or laid out planarly along the horizontal plane of the bridging plate 10. For example... Figure 1B The material property layer 60 is discontinuously arranged along the horizontal plane of the bridging plate 10. In addition, the plate structure 100B also includes a conductive element 70, which is independent of the channel 35 and passes through the bridging plate 10; the conductive element 70 can be a single structure or a composite structure composed of multiple sub-elements.

[0085] exist Figure 1C In the plate structure 100C, two material property layers 60 and 60A are respectively disposed on opposite sides of the bridging plate 10. The conductive element 70A is independent of the channel 35 and passes through the bridging plate 10. The two material property layers 60 and 60A are discontinuously arranged along the horizontal plane of the bridging plate 10 and at least partially cover the channel 35.

[0086] exist Figure 1DIn the plate structure 100D, the material property layer 60B is arranged in a planar manner along the horizontal plane of the bridging plate 10. The material property layer 60B can be attached to the bridging plate 10 in the form of a thin plate or a thin film.

[0087] exist Figure 1E In the plate structure 100E, two material property layers 60B and 60C are respectively disposed on opposite sides of the bridging plate 10 and are arranged in a planar manner along the horizontal plane of the bridging plate 10.

[0088] All of the above implementation scenarios can be arranged and combined.

[0089] Figures 2A-2E Series and Figures 1A-1E The difference in this series lies in the addition of a layered structure. The following is a detailed explanation: Reference Figure 2A The diagram illustrates a board structure 100F according to a first embodiment of the present invention. The board structure 100F includes a bridging board 10, functional wafer units 20, a slot 30, a filler material 40, and a layer structure 50. The bridging board 10 defines a coefficient of thermal expansion (CTE) of no more than 8 ppm / °C along a horizontal plane (XY plane); the bridging board 10 has a channel 35 connecting its two sides. The functional wafer units 20 are at least partially housed in the channel 35. The slot 30 extends between the functional wafer units 20 and the bridging board 10. The filler material 40 fills the slot 30. The layer structure 50 at least partially covers one side of the bridging board 10, the slot 30, and the functional wafer units 20; wherein the layer structure 50 and the functional wafer units 20 can communicate via at least one of electrical signals and optical signals. In this embodiment, the layer structure 50 is located on the same side (bottom side) of the bridging board 10, the slot 30, and the functional wafer units 20.

[0090] The layer structure 50 spans and at least partially covers the gap 30. The layer structure 50 includes one or more layers of material, at least one layer being the same material as the bridging board 10. The layer structure 50 includes layer material and one or more communication layers bonded to the layer material. In some embodiments, the functional chip cell 20 has a linewidth of no more than 1 μm on the side facing the layer structure 50. The functional chip cell 20 has a line spacing of no more than 1 μm on the side facing the layer structure 50. The layer structure 50 defines a dielectric loss (Df) of no more than 0.006 at a frequency of 10 GHz. Figure 2A In the middle, the layer structure 50 includes a layer material and a communication layer 51 bonded to the layer material. The communication layer 51 is an electrical layer and is electrically connected to the functional chip unit 20.

[0091] The coefficient of thermal expansion (CTE) of the bridging plate 10 along the horizontal plane may not exceed 4 ppm / °C. Furthermore, the functional chip unit 20 may have a defined coefficient of thermal expansion (CTE) along this horizontal plane. In one embodiment, the ratio of the coefficient of thermal expansion of the bridging plate 10 to that of the functional chip unit 20 is not less than 0.5. In another embodiment, the ratio of the coefficient of thermal expansion of the bridging plate 10 to that of the functional chip unit 20 may be further defined as not exceeding 2.5. The filler material 40 may have a defined coefficient of thermal expansion (CTE) along the horizontal plane; the coefficient of thermal expansion of the filler material 40 is greater than both the coefficient of thermal expansion of the bridging plate 10 and the functional chip unit 20.

[0092] exist Figure 2B In the board structure 100G, the layer structure 50A includes a communication layer, which is a redistribution layer (RDL). Furthermore, the board structure 100G also includes a material property layer 60, located on at least one side of the bridging board 10 and connected to the filler material 40; the material property layer 60 may be located between the layer structure 50A and the bridging board 10, and may at least partially cover the gap 30. The material property layer 60 and the filler material 40 may be of the same material (e.g., materials of the same material configured for their respective independent processes, or a portion of the material property layer 60 extending from the filler material 40), and the material property layer 60 may also be of the same material as the bridging board 10 (e.g., materials of the same material configured for their respective independent processes); the material of the material property layer 60 or a combination thereof can be referred to the foregoing. The material property layer 60 may be located on the same side or a different side of the bridging board 10 as the layer structure 50A. The material property layer 60 connects to the bridging board 10 and is discontinuously arranged along the horizontal plane of the bridging board 10; or it may be planarly arranged along the horizontal plane of the bridging board 10. Figure 2B The material property layer 60 is discontinuously arranged along the horizontal plane of the bridging plate 10. In addition, the plate structure 100G also includes a conductive element 70, which is independent of the channel 35, passes through the bridging plate 10 and is electrically connected to the redistribution layer (RDL) of the layer structure 50A.

[0093] exist Figure 2CIn the board structure 100H, two material property layers 60 and 60A are respectively disposed on opposite sides of the bridging board 10. In this embodiment, the material property layer 60A is located between the bridging board 10 and the layer structure 50B. Furthermore, the layer structure 50B includes a communication layer, at least including a redistribution layer (RDL), and a plurality of conductive elements 70C that penetrate the layer structure 50B and are electrically connected to the functional chip unit 20. As previously described, the layer structure 50B includes one or more stacked layer materials and one or more communication layers bonded to the layer materials; the communication layer may include the redistribution layer (RDL) and conductive elements 70C electrically connected along the Z direction. The conductive elements 70A are electrically connected to the redistribution layer (RDL) of the layer structure 50B. In this embodiment, the conductive elements 70C are configured corresponding to the functional chip unit 20, and the redistribution layer (RDL) is configured at least to a portion of the functional chip unit 20 and the bridging board 10.

[0094] exist Figure 2D In the board structure 100I, the material property layer 60B is arranged in an aplanar manner along the horizontal plane of the bridging board 10. Furthermore, the layer structure 50C includes one or more stacked layer materials and one or more communication layers bonded to these layer materials; the communication layer includes at least an electrical layer and an optical layer; the electrical layer may be a redistribution layer (RDL) electrically connected to a conductive element 70A disposed on the bridging board 10, and the optical layer is a waveguide structure 55, which is coupled to the functional chip unit 20 through an optical channel 80.

[0095] exist Figure 2EIn the board structure 100J, two material property layers 60A and 60C are respectively disposed on opposite sides of the bridging board 10, and are arranged in a planar manner along the horizontal plane of the bridging board 10. Furthermore, the layer structure 50D includes one or more stacked layer materials and one or more communication layers bonded to these layer materials; the communication layer includes at least an electrical layer and an optical layer; the electrical layer may be a redistribution layer (RDL), electrically connected to a conductive element 70A disposed on the bridging board 10 and electrically connected to a conductive element 70B electrically connected to the functional chip unit 20; the optical layer is a waveguide structure 55 coupled to the functional chip unit 20 through an optical channel 80. In some embodiments, the material property layer 60 is connected to the layer structure 50D; the material property layer 60 and the layer material of the layer structure 50D may be different materials implemented in different steps, or they may be the same material implemented in the same step. In another embodiment, the material property layer 60 may have a defined coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the CTE of the material property layer 60 and the CTE of the bridging plate 10 is not greater than 1.3 ppm / °C. In another embodiment, the difference between the CTE of the material property layer 60 and the CTE of the bridging plate is not less than 0.7 ppm / °C. In some embodiments where the layer structure 50 is integrated into the material property layer 60, the CTE of the material property layer 60 may be interpreted as the equivalent CTE of the material property layer 60 and the layer structure 50, such as when the equivalent CTE of the bridging plate 10 is a multilayer plate, and the difference between the equivalent CTE of the material property layer 60 and the equivalent CTE of the bridging plate 10 is not greater than 1.3 ppm / °C; in another embodiment, the difference between the equivalent CTE of the material property layer 60 and the equivalent CTE of the bridging plate is not less than 0.7 ppm / °C. Please note that this description is not a necessary embodiment, but only to illustrate the equivalent coefficient of thermal expansion that can be uniformly derived from multiple layers or integration.

[0096] All of the above implementation methods can be arranged and combined.

[0097] Figures 3A-3E The series showcases the diversity of the bridge plate itself. Figure 3AIn the board structure 200A, the bridging board 10A is a multilayer board, including multiple layers of boards 220 and one or more adhesive layers 240 bonding these boards. The bridging board 10A also has an electrical layer 260 disposed on the outermost side of the boards 220. This electrical layer 260 can be configured as an independent component integrated with the bridging board 10A, or as a layer structure in conjunction with the bridging board 10A. For ease of understanding, taking the configuration of this electrical layer 260 integrated with the bridging board 10A as an example, the electrical layer 260 can be bonded to the bridging board 10A through the adhesive layer 240. The functional chip unit 20 is disposed within the channel of the bridging board 10A as described in the aforementioned embodiment. The board 220 is, for example, made of polyimide (PI), and the adhesive layer 240 may contain glass frit, glass powder, glass paste, or a combination of one or more of these materials.

[0098] exist Figure 3B In the plate structure 200B, the conductive element 70 passes through the bridging plate 10B and connects the upper and lower sides of the bridging plate 10B. Here, the conductive element 70 is a single structure and electrically connects the electrical layers 260 on the upper and lower sides.

[0099] exist Figure 3C In the plate structure 200C, the conductive element 70C passes through the bridging plate 10C, connecting the upper and lower sides of the bridging plate 10C. Here, the conductive element 70D is a composite structure that electrically connects the upper and lower electrical layers 260. The conductive element 70D includes multiple secondary conductive elements 72 passing through these plates 220 along the vertical direction Z of the vertical plane, as well as conductive material 74 that joins two adjacent secondary conductive elements 72.

[0100] exist Figure 3D In the plate structure 200D, the electrical layer 260 is not bonded to the bridging plate 10D by the adhesive layer 240 (the adhesive layer 240 adjacent to the electrical layer 260 does not exist). The conductive element 70E passes through the bridging plate 10D, connecting the upper and lower sides of the bridging plate 10D. Here, the conductive element 70E is a composite structure that electrically connects the upper and lower electrical layers 260. The bridging plate 10D includes one or more conductive layers 280, which are disposed on the inner surface of one or at least part of the plate 220. The conductive element 70E includes a plurality of secondary conductive elements 72A passing through these plates 220 along the vertical direction Z of the vertical plane, and conductive material 74A electrically connected to the corresponding one or more secondary conductive elements 72A through the conductive layer 280.

[0101] Figure 3E The plate structure 200E and Figure 3D The only difference between the 200D board structure and the 260 board structure is that the electrical layer 260 is arranged on one side of the bridging board 10E.

[0102] All of the above implementation methods can be arranged and combined.

[0103] Figure 4 This invention discloses a stacked structure, taking board structure 100H as an example but not limited to it, and further integrating it with packaging substrate 900. Board structure 100H is stacked on packaging substrate 900, and the functional chip unit 20 of board structure can communicate with packaging substrate 900 via at least one of electrical signals and optical signals. Packaging substrate 900 comprises glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, polyimide (PI), bismaleimide triazine resin (BT), or FR4 substrate, or a combination of one or more of the above materials. Packaging substrate 900 includes at least one of an optical layer and an electrical layer. The illustrations in this embodiment all use electrical signals as an example.

[0104] All of the above implementation methods can be arranged and combined.

[0105] Figure 5A and Figure 5B Disclosed electronic devices I and II include a board structure, a plurality of electronic components disposed on one side of the board structure, and a plurality of externally conductive structures disposed on the other side of the board structure.

[0106] like Figure 5AThe electronic device I includes a board structure 300A, a plurality of electronic components 200 disposed on one side of the board structure 300A, a plurality of externally conductive structures 310 disposed on the other side of the board structure 300A, and a protective layer 500 (not a necessary component) covering the electronic components 200 and connected to the board structure 300A. The board structure 300A includes a bridging board 10F, one or more functional chip units 20B, one or more slots 30A corresponding to the functional chip units 20B, one or more filling materials 40A corresponding to the functional chip units 20B, and two-layer structures 50A respectively disposed on both sides of the bridging board 10F. In some embodiments, the two-layer structure 50A is symmetrical; in this embodiment, the two-layer structure 50A is asymmetrical, meaning that it is asymmetrical in terms of electrical or non-electrical structure with the bridging plate as the central axis; here, it may include a redistribution layer (RDL) or a build-up layer, such as ABF (Ajinomoto Buildup Film), but is not limited to this method; for example, the absolute difference ratio of the total volume expansion of layer structure 50X and layer structure 50Y' within the plane of the bridging plate is not less than 30%; each layer structure is not limited to a single layer, the volume expansion of each layer material in the temperature change range, and the total volume expansion of the multilayer material in the same temperature change range; the two layer structures will have an absolute difference ratio, for example, with the difference as the numerator and the smaller volume expansion change as the denominator, this absolute difference ratio is greater than or equal to 30%. In this embodiment, the layer structure 50A is an electrical layer (both are redistributed layers, for example), the functional chip unit 20B is a single bridging chip, and the external conductive structure 310 is an under-bump metallurgy (UBM) layer and copper bumps, for example, disposed on the conductive element 70G and the functional chip unit 20B of the bridging board 10F, electrically connecting the layer structures 50A on opposite sides of the bridging board 10F. The layer structures 50A on both sides of the bridging board 10F have progressively increasing linewidths or line spacings. One side of the electronic component 200 facing the layer structure 50A has a linewidth of no more than 1 μm, and the other side of the electronic component 200 facing the layer structure 50A has a line spacing of no more than 1 μm.Electronic component 200 is a functional chip, which may be high-bandwidth memory (HBM), a switch chip, a neural processing unit (NPU), a tensor processing unit (TPU), a central processing unit (CPU), or a graphics processing unit (GPU), or a combination of one or more of the above components; or electronic component 200 may be a photosensitive element, a photoelectric conversion element, or a combination of one or more of the above components; these embodiments may also be arranged and combined.

[0107] like Figure 5BElectronic device II includes a board structure 300B, a plurality of electronic components 200 disposed on one side of the board structure 300B, a plurality of externally conductive structures 310 disposed on the other side of the board structure 300B, and a protective layer 500 (not an essential component) covering these electronic components 200 and connected to the board structure 300B. The board structure 300B includes a bridging board 10F, one or more functional chip units 20B, one or more slots 30A corresponding to these functional chip units 20B, one or more filling materials 40A corresponding to these functional chip units 20B, and layer structures 50A disposed on one side of the bridging board 10F and layer structures 50B on the other side, respectively. Layer structure 50A is an electrical layer (partially a redistribution layer, partially including multiple conductive elements 70F, for example), and layer structure 50B is an insulating layer, for example. Layer structure 50A and layer structure 50B, or both, are defined to have a dielectric loss (Df) of not more than 0.006 at a frequency of 10 GHz. The conductive elements 70F of the layer structure 50A are disposed at locations corresponding to the functional chip units 20B. Taking a single bridging chip as an example, the external conductive structure 310, using an under-ball metal layer (UBM) and copper bumps as examples, is disposed on the conductive elements 70G of the bridging board 10F and the functional chip unit 20B, electrically connecting the layer structure 50A on one side of the bridging board 10F to the external conductive structure 310 on the other side. The layer structure 50A on one side of the bridging board 10F has progressively increasing linewidths or spacings, with one electronic component 200 having a linewidth of no more than 1 μm on the side facing the layer structure 50A, and another electronic component 200 having a spacing of no more than 1 μm on the side facing the layer structure 50A. Electronic component 200 is a functional chip, which may be high-bandwidth memory (HBM), a switch chip, a neural processing unit (NPU), a tensor processing unit (TPU), a central processing unit (CPU), or a graphics processing unit (GPU), or a combination of one or more of the above components; or electronic component 200 may be a photosensitive element, a photoelectric conversion element, or a combination of one or more of the above components; these embodiments may also be arranged and combined.

[0108] Figure 5C and Figure 5DDisclosed electronic devices III and IV include board structures 300C and 300D, multiple electronic components disposed on one side of board structures 300A and 300B, multiple externally conductive structures 310 disposed on the other side of board structures 300C and 300D, and a packaging substrate 900 electrically connecting these externally conductive structures 310. Figure 5A and Figure 5B Compared to the disclosed electronic devices I and II, the difference lies in the addition of a packaging substrate 900 to electronic devices III and IV. In other words, board structures 300C and 300D respectively include board structures 300A and 300B and a packaging substrate 900. Similarly, the packaging substrate 900 comprises glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, polyimide (PI), bismaleimide triazine resin (BT), or FR4 board, or a combination of one or more of the above materials.

[0109] like Figure 6The electronic device V includes a board structure 300E, a plurality of electronic components 600 disposed on one side of the board structure 300E, a plurality of externally conductive structures 310A disposed on the other side of the board structure 300E, and a substrate 400A electrically connected to these externally conductive structures 310A. The board structure 300E includes a bridging board 10G, one or more functional chip units 20C, one or more slots (not shown) corresponding to these functional chip units 20C, one or more filling materials 40B corresponding to these functional chip units 20C, and two-layer structures 50G and 50H respectively disposed on both sides of the bridging board 10G. The layer structures 50G and 50H are single-layer electrical layers, and the functional chip unit 20C is represented by two functional chip units 20D and 20E. The external conductive structure 310A is represented by a copper bump. The conductive element 70H electrically connects the layer structures 50G and 50H on both sides of the bridging plate 10G. The substrate 400A is a multilayer structure of at least two layers 410 and 420, and includes an electrical layer 250A corresponding to the external conductive structure 310A, and a waveguide structure 55A corresponding to these functional chip units 20C. The functional chip unit 20E is a photoelectric conversion element array, including at least a light-emitting element array 20EA and a photosensitive element array 20EB. The functional chip unit 20D is a photoelectric conversion driving circuit. The electronic component 600 is a semiconductor main chip. The functional chip unit 20D is electrically connected to the functional chip unit 20E and the electronic component 600. Waveguide structure 55A can be directly or indirectly connected to board structure 300E and defines optical coupling region 55B, correspondingly coupled to light-emitting element array 20EA and photosensitive element array 20EB. The photoelectric conversion element array transmits and receives optical signals from waveguide structure 55A and is electrically driven by functional chip unit 20D to perform conversion between optical and electrical signals. Optical coupling region 55B may further be provided with micro-bump structure 444 to optimize coupling efficiency. In this embodiment, electronic component 600 defines a vertical direction, and at least a portion of electronic component 600, at least a portion of functional chip unit 20D, at least a portion of functional chip unit 20E, and at least a portion of waveguide structure 55A are arranged along the vertical direction of electronic component 600, or further arranged sequentially along this vertical direction. Figures 3A-3E The implementation can be combined with previous implementations, such as horizontally side-by-side or vertically stacked configurations of different functional chip units.

[0110] Figures 7A to 7G This paper discloses one method for fabricating the 100K plate structure described herein, but it is not a limitation. Figures 7A to 7CIn this process, one side of the bridging plate 10H is pre-attached to a carrier film 930 with a thin metal film 920 via a bonding sheet 910, while a sacrificial film 940 is provided on the other side of the bridging plate 10H. Laser drilling is performed from the other side of the bridging plate 10H, stopping at the thin metal film 920. A seed layer 950 is placed inside the hole, followed by electroplating. After electroplating forms a conductive element 960 to a certain extent, the carrier film 930 is removed, and an electrical layer 970 can be further placed on the thin metal film 920. Furthermore, the thin metal film 920 (and its electrical layer 970) undergo a patterning process. Figures 7D to 7G In this process, the semi-finished product with the carrier layer 930 removed is transferred to a temporary carrier board 980, which can be a rigid board, such as a glass substrate. Channels 35 are then formed on the bridging board 10H, and functional chip units 20 are placed within these channels 35, along with the filling material and material property layer (in this embodiment, this is integrated as epoxy molding compound molding, EMC molding) 990. Before, during, and after this epoxy molding process, optical / electrical communication-related processes can be performed on the functional chip units 20, and the surface of the epoxy molding package 990 is then ground to expose at least the electrical communication components (e.g., conductive elements 960 and pins 960A of the functional chip units 20). Finally, the temporary carrier board 980 can be removed to obtain the board structure 100K. It is worth noting that the commercially viable intermediate product structure includes at least the following: Figure 7G The bridging plate 10H and the temporary carrier plate 980 can be regarded as the intermediate structure of the bridging plate.

[0111] exist Figures 8A to 8CIn the plate structures 100L, 100M, and 100N, the bridging plate defines one or more corners or side edges, and a chamfer disposed at one of these corners or side edges. A material property layer is planarly disposed along the plane of the bridging plate, covering one or more bridging plates (bridging plates spliced ​​together) of these corners or side edges. In the plate structure 100L, the bridging plate 10J defines one or more outer corners 81, inner corners 82, or outer upper and lower side edges 84, outer peripheral side edges 85, and inner peripheral side edges 86; it is understood that the inner corner 82 and the inner peripheral side edge 86 are located at the channel 35. In this embodiment, a chamfer is disposed at one of the outer corners (marked 81A for easy distinction from the un-chamfered outer corner 81), and the material property layer 60D covers the chamfer 83. The material property layer 60D may further include at least one of the outer upper and lower side edges 84 and the outer peripheral side edge 85, particularly the outer peripheral side edge 85. The chamfer 83 of the bridging board 10J is only located at one of its outer corners 81A. Specifically, the layer structure 50G includes an electrical layer 260B and an optical layer (waveguide structure 55C), and the functional wafer unit 20 has photoelectric properties. In this embodiment, the chamfer 83 of the bridging board 10J is only located at the outer corner 81A relative to the layer structure 50G. In this embodiment, in addition to the layer structure 50G, the bridging board 10J may further include a layer structure 50J. These two layer structures 50G and 50J are respectively located on opposite sides of the bridging board 10J, and are asymmetrical. For example, the layer structure 50G is a redistribution layer (RDL), and the layer structure 50J is a build-up layer, but this is not a limitation.

[0112] In board structure 100M, the differences between bridging board 10K and bridging board 10J include: the chamfer 83 of bridging board 10K is located at the outer corners 81A on two opposite sides of bridging board 10K; the material property layer 60E covers the chamfer 83, and the material property layer 60E may further include at least one of the outer upper and lower side edges 84 and the outer peripheral side edge 85, particularly the outer peripheral side edge 85. Furthermore, in board structure 100L, the conductive element 70I is independent of the channel and directly passes through bridging board 10J, while in board structure 100M, the conductive element 70J further passes through the filling material 40C in bridging board 10K; in other words, in board structure 100M, the through-holes of bridging board 10K can first be filled with filling material 40C for the conductive element 70J to pass through, electrically connecting to layer structure 50H; layer structure 50H may also include electrical layer 260C and optical layer (waveguide structure 55D), and the functional chip unit 20 also has optoelectronic properties. Furthermore, in the plate structure 100M, the conductive element 70I is further perforated with a material property layer 60N that is connected to the bridging plate 10K.

[0113] In the board structure 100N, the differences between the bridging plate 10L and the bridging plate 10K include: the chamfer 83 of the bridging plate 10L is further disposed at the inner corner 82A of the bridging plate 10L; the material property layer 60E covers the chamfer 83, and the material property layer 60E may further include at least one of the outer upper and lower side edges 84 and the outer peripheral side edge 85, particularly the outer peripheral side edge 85. The chamfer 83 may also be further disposed in a through-hole in which the filler material 40D and the conductive element 70K are disposed. Here, the conductive element 70K is independent of the channel, passes through the bridging plate 10L and the filler material 40D and its material property layer 60F, and is electrically connected to the layer structure 50I. It is worth noting that the material property layer and the filler material may be formed simultaneously with the bridging plate, and then through-holes and channels are provided for the bridging plate, the material property layer, and the filler material before subsequent processes are performed. The material property layer and the filler material may be the same or different materials; furthermore, if combined... Figures 5A-5D In this series, the material property layer, filling material, and protective layer can be made of the same or different materials. Furthermore, the differences between bridge board 10L and bridge board 10K include: the functional chip unit 20F includes a first chip 20G and a second chip 20J; the first chip 20G is electrically connected to the electrical layer 260D of the layer structure 50I, and the second chip 20J is electrically connected to the electrical layer 260D of the layer structure 50I and the waveguide structure 55E.

[0114] As stated above, it should be understood that various embodiments of the present invention have been described in the specification for illustrative purposes, and various modifications can be made without departing from the scope and spirit of the invention. Therefore, the various embodiments of the present invention are not intended to limit the true scope and spirit of the invention.

[0115] The above description is illustrative only and not restrictive. Any equivalent modifications or alterations made without departing from the spirit and scope of this invention should be included within the scope of the appended claims.

Claims

1. A plate structure, comprising: The bridging plate has a coefficient of thermal expansion (CTE) defined along the horizontal plane of no more than 10 ppm / °C. The bridge plate has channels; Functional chip units, at least partially housed in the channel; The gap arises between the functional chip unit and the bridge board; as well as Filling material is used to fill the gap.

2. The plate construction as claimed in claim 1, wherein the coefficient of thermal expansion (CTE) of the bridging plate along the horizontal plane is not greater than 8 ppm / °C.

3. The board structure of claim 1, wherein the functional wafer unit defines a coefficient of thermal expansion (CTE) along the horizontal plane; the ratio of the coefficient of thermal expansion of the bridging board to the coefficient of thermal expansion of the functional wafer unit is not less than 0.5 and / or not greater than 2.

5.

4. The plate structure as described in claim 1, further comprising: A material properties layer is located on one side of the bridging plate, at least partially covering the gap and connecting the filler material.

5. The plate structure of claim 4, wherein the material property layer defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the coefficient of thermal expansion of the material property layer and the coefficient of thermal expansion of the bridging plate is not greater than 1.3 ppm / °C and / or not less than 0.7 ppm / °C.

6. The plate structure as described in claim 1, further comprising: A layered structure that at least partially covers the bridging plate, the gap, and one side of the functional chip unit; The layer structure and the functional chip unit are able to communicate with each other via at least one of electrical signals and optical signals.

7. The plate structure as described in claim 6, further comprising: Another layer of structure, at least partially covering the bridging plate, the gap, and the other side of the functional chip unit; The other layer communicates with the functional chip unit via at least one of electrical signals and optical signals.

8. The plate structure of claim 7, wherein the absolute difference ratio of the sum of the volume expansions of the two layer structures within the plane of the bridging plate is not less than 30%.

9. The board structure of claim 6, wherein the functional wafer unit has a linewidth of no more than 1 μm on the side facing the layer structure.

10. The plate construction of claim 4, wherein the bridging plate defines one or more corners or side edges, the material property layer is planarly arranged along the horizontal plane of the bridging plate, and the material property layer covers at least one of the side edges.

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