A packaging structure and a method of forming a packaging structure

Abstract

The application discloses a packaging structure and a forming method thereof. The packaging structure comprises a first inorganic passivation layer, a first semiconductor chip located on the top surface of the first inorganic passivation layer, and a surface of the first semiconductor chip away from the first inorganic passivation layer having a protruding connecting column, a second inorganic passivation layer located on the top surface of the first inorganic passivation layer, covering the first semiconductor chip and covering the side surface of the connecting column, and having a groove in the second inorganic passivation layer around the connecting column, and a third inorganic passivation layer located on the top surface of the second inorganic passivation layer, the third inorganic passivation layer filling the groove, and the top surface of the third inorganic passivation layer being flush with the top surface of the connecting column. The density of the first inorganic passivation layer and the third inorganic passivation layer is greater than the density of the second inorganic passivation layer. The warping range of the packaging structure is effectively reduced, and the stability of the packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of advanced packaging technology, and in particular to a packaging structure and a method for forming the packaging structure. Background Technology

[0002] In the field of semiconductor packaging technology, as electronic products continue to evolve towards higher integration, higher reliability and lower cost, in order to reduce packaging costs, improve packaging reliability and achieve higher density integration, 3D packaging structure has become one of the mainstream technology directions for advanced electronic device packaging due to its advantages such as high integration and miniaturization. 3D packaging structure can integrate more functional chips in a limited space and realize a complete system function in a single package.

[0003] In the fabrication process of 3D packaging structures, resin materials are usually used to encapsulate the chip. Since the coefficient of thermal expansion of the resin material is much greater than that of the chip, the 3D packaging structure is prone to warping or deformation under stress during the manufacturing process. This can lead to failure between electrical connection points within the 3D packaging structure, affecting the performance and lifespan of the 3D packaging structure and reducing its stability. Summary of the Invention

[0004] The purpose of this application is to provide a packaging structure and a method for forming the packaging structure, which can effectively reduce the warpage of the packaging structure and improve its stability.

[0005] To achieve the above objectives, this application first provides a packaging structure, including:

[0006] First inorganic passivation layer; A first semiconductor chip is located on the top surface of the first inorganic passivation layer, and the surface of the first semiconductor chip away from the first inorganic passivation layer has protruding connecting pillars. The second inorganic passivation layer is located on the top surface of the first inorganic passivation layer, and covers the first semiconductor chip and the side of the connecting post, and the second inorganic passivation layer around the connecting post has a groove. A third inorganic passivation layer is located on the top surface of the second inorganic passivation layer. The third inorganic passivation layer fills the groove, and the top surface of the third inorganic passivation layer is flush with the top surface of the connecting post. The density of the first inorganic passivation layer and the third inorganic passivation layer is greater than the density of the second inorganic passivation layer.

[0007] In some embodiments of this application, the materials of the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer are inorganic dielectric materials.

[0008] In some embodiments of this application, the stress adjustment range of the first inorganic passivation layer and the third inorganic passivation layer is greater than 500 MPa.

[0009] In some embodiments of this application, the materials of the first inorganic passivation layer and the third inorganic passivation layer include homogeneous or heterogeneous materials with poor water absorption.

[0010] In some embodiments of this application, the materials of the first inorganic passivation layer and the third inorganic passivation layer include one or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0011] In some embodiments of this application, the material of the second inorganic passivation layer includes silicon oxide.

[0012] In some embodiments of this application, it also includes: A metal pillar is located on the top surface of the first inorganic passivation layer around the first semiconductor chip. The top surface of the metal pillar is flush with the top surface of the connecting pillar, and the second inorganic passivation layer covers the side surface of the metal pillar.

[0013] In some embodiments of this application, the metal pillar and the connecting pillar are multilayer structures composed of one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni.

[0014] In some embodiments of this application, the number of connecting posts is multiple; The first semiconductor chip includes a through-hole interconnect structure, which is electrically connected to a portion of the connecting pillars, and the side of the first semiconductor chip that contacts the first inorganic passivation layer exposes the bottom surface of the through-hole interconnect structure.

[0015] In some embodiments of this application, it also includes: A circuit layer is located within the first semiconductor chip, and the connecting lines in the circuit layer are electrically connected to the connecting posts.

[0016] In some embodiments of this application, it also includes: The first wiring layer is located on the top surface of the third inorganic passivation layer and is electrically connected to the metal pillar and the connecting pillar.

[0017] In some embodiments of this application, the first redistribution layer includes: a first organic dielectric layer and a first metal wiring located within the first organic dielectric layer, wherein the first metal wiring is electrically connected to the metal post and the connecting post.

[0018] In some embodiments of this application, it also includes: The second semiconductor chip is flip-chipped onto the top surface of the first wiring layer and electrically connected to the first wiring layer. A molding layer is located on the top surface of the first redistribution layer and covers the second semiconductor chip.

[0019] In some embodiments of this application, it also includes: The second wiring layer is located on the bottom surface of the first inorganic passivation layer, and the second wiring layer is electrically connected to the metal pillar and the through-hole interconnect structure, respectively.

[0020] In some embodiments of this application, The first inorganic passivation layer has a plurality of first through holes corresponding to the metal pillar and the through hole interconnection structure, and the first through holes penetrate the top and bottom surfaces of the first inorganic passivation layer; The second redistribution layer includes: a second organic dielectric layer and a second metal wiring within the second organic dielectric layer, wherein the second metal wiring passes through the first via and is electrically connected to the metal pillar and the via interconnect structure.

[0021] In some embodiments of this application, the material of the second organic dielectric layer includes polyimide.

[0022] In some embodiments of this application, it also includes: The welding protrusions are electrically connected to the second metal wiring in the second rewiring layer.

[0023] In some embodiments of this application, it also includes: An organic coating layer covers the sides of the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer along the circumferential direction. The top surface of the organic coating layer is in contact with the bottom surface of the first redistribution layer, and the bottom surface of the organic coating layer is in contact with the top surface of the second redistribution layer.

[0024] This application also provides a method for forming a packaging structure, including: Provide the first carrier board; A first semiconductor chip is provided, the first semiconductor chip is mounted on the top surface of the first substrate, and the surface of the first semiconductor chip away from the first substrate has protruding connecting pillars. The first semiconductor chip has through-hole interconnection structures, and a plurality of the through-hole interconnection structures are electrically connected to a portion of the connecting pillars. A second inorganic passivation layer is formed on the top surface of the first carrier plate. The second inorganic passivation layer covers the first semiconductor chip and the side of the connecting post. The second inorganic passivation layer around the connecting post has a groove. A third inorganic passivation layer is formed on the top surface of the second inorganic passivation layer, the third inorganic passivation layer fills the groove, and the top surface of the third inorganic passivation layer is flush with the top surface of the connecting post. Remove the first carrier plate to expose the second inorganic passivation layer and the surface of the first semiconductor chip away from the third inorganic passivation layer; A first inorganic passivation layer is formed on the bottom surface of the second inorganic passivation layer, and the density of the first inorganic passivation layer and the third inorganic passivation layer is greater than the density of the second inorganic passivation layer.

[0025] In some embodiments of this application, the materials of the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer are inorganic dielectric materials.

[0026] In some embodiments of this application, the stress adjustment range of the first inorganic passivation layer and the third inorganic passivation layer is greater than 500 MPa.

[0027] In some embodiments of this application, the materials of the first inorganic passivation layer and the third inorganic passivation layer include homogeneous or heterogeneous materials with poor water absorption.

[0028] In some embodiments of this application, the materials of the first inorganic passivation layer and the third inorganic passivation layer include one or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0029] In some embodiments of this application, the material of the second inorganic passivation layer includes silicon oxide.

[0030] In some embodiments of this application, the formation of the first inorganic passivation layer is achieved using a chemical vapor deposition process.

[0031] In some embodiments of this application, before forming the second inorganic passivation layer on the top surface of the first carrier plate, the following steps are included: A metal pillar is provided and attached to the top surface of the first carrier plate on the periphery of the first semiconductor chip, wherein the top surface of the metal pillar is flush with the top surface of the connecting pillar. When a second inorganic passivation layer is formed on the top surface of the first carrier plate, the second inorganic passivation layer covers the side surface of the metal pillar.

[0032] In some embodiments of this application, A third inorganic passivation layer is formed on the top surface of the second inorganic passivation layer, and the method further includes: A third inorganic passivation layer is formed on the top surface of the second inorganic passivation layer using a chemical vapor deposition process; The top surface of the third inorganic passivation layer is thinned so that the top surface of the third inorganic passivation layer is flush with the top surfaces of the metal pillar and the connecting pillar.

[0033] In some embodiments of this application, after thinning the top surface of the third inorganic passivation layer, the method further includes: A first redistribution layer is formed on the top surface of the third inorganic passivation layer, and the first redistribution layer is electrically connected to the metal pillar and the connecting pillar.

[0034] In some embodiments of this application, it also includes: An organic coating layer is formed on the first carrier plate, and the organic coating layer covers the sides of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer along the circumferential direction of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer; A first redistribution layer is formed on the top surface of the third inorganic passivation layer and the organic coating layer. The top surface of the organic coating layer is in contact with the bottom surface of the first redistribution layer, and the bottom surface of the organic coating layer is in contact with the top surface of the first carrier board.

[0035] In some embodiments of this application, the first redistribution layer includes: a first organic dielectric layer and a first metal wiring located within the first organic dielectric layer, wherein the first metal wiring is electrically connected to the metal post and the connecting post; The formation process of the organic coating layer and the first redistribution layer includes: etching away portions of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer at their edges to form an annular groove surrounding the metal pillar and the first semiconductor chip; An organic material layer is formed on the top surface of the third inorganic passivation layer and in the annular groove. The organic material layer on the top surface of the third inorganic passivation layer serves as the first organic medium layer, and the organic material layer in the annular groove serves as the organic coating layer. A plurality of openings are formed in the first organic medium layer, the openings corresponding to the top surfaces of the metal pillar and the connecting pillar; The opening is filled with metal to form the first metal wiring.

[0036] In some embodiments of this application, after forming the first redistribution layer, the method further includes: A second semiconductor chip is provided, which is flip-chip mounted on the top surface of the first multi-wiring layer and is electrically connected to the first multi-wiring layer. A molding compound is formed on the top surface of the first redistribution layer, the molding compound covering the second semiconductor chip.

[0037] In some embodiments of this application, forming a second inorganic passivation layer on the top surface of the first carrier plate includes: A second inorganic passivation layer is formed using a chemical vapor deposition process. The formed second inorganic passivation layer covers the first semiconductor chip and the top and side surfaces of the metal pillar and the connecting pillar, and part of the top surface of the second inorganic passivation layer is lower than the top surface of the metal pillar and the connecting pillar.

[0038] In some embodiments of this application, forming a second inorganic passivation layer on the top surface of the first carrier plate includes: A second inorganic passivation layer is formed using a chemical vapor deposition process. The second inorganic passivation layer covers the first semiconductor chip and the metal pillar and the connecting pillar, and the top surface of the second inorganic passivation layer is higher than the top surface of the metal pillar and the connecting pillar. The second inorganic passivation layer between the metal pillars and between the metal pillars and the connecting pillars is etched away to form a groove, such that the top surface of the remaining second inorganic passivation layer at the bottom of the groove is lower than the top surface of the metal pillars and the connecting pillars, and the remaining second inorganic passivation layer on the side of the groove covers the side of the metal pillars and the connecting pillars.

[0039] In some embodiments of this application, After forming the first inorganic passivation layer on the bottom surface of the second inorganic passivation layer, the process further includes: A second redistribution layer is formed on the bottom surface of the first inorganic passivation layer, and the second redistribution layer is electrically connected to the metal pillar and the through-hole interconnect structure.

[0040] In some embodiments of this application, before forming the second redistribution layer on the bottom surface of the first inorganic passivation layer, the method further includes: A plurality of first through holes corresponding to the metal pillar and the through hole interconnection structure are formed in the first inorganic passivation layer, and the first through holes penetrate the top and bottom surfaces of the first inorganic passivation layer; The second redistribution layer includes a second organic dielectric layer and a second metal wiring located within the second organic dielectric layer, wherein the second metal wiring passes through the first via and is electrically connected to the metal pillar and the via interconnect structure.

[0041] The beneficial effects of this application are: The encapsulation structure and the method for forming the encapsulation structure of this application, wherein the encapsulation structure includes: a first inorganic passivation layer; A first semiconductor chip is located on the top surface of the first inorganic passivation layer, and the surface of the first semiconductor chip away from the first inorganic passivation layer has protruding connecting pillars. The second inorganic passivation layer is located on the top surface of the first inorganic passivation layer, and covers the first semiconductor chip and the side of the connecting post, and the second inorganic passivation layer around the connecting post has a groove. A third inorganic passivation layer is located on the top surface of the second inorganic passivation layer. The third inorganic passivation layer fills the groove, and the top surface of the third inorganic passivation layer is flush with the top surface of the connecting post. The density of the first inorganic passivation layer and the third inorganic passivation layer is greater than the density of the second inorganic passivation layer.

[0042] The aforementioned packaging structure of this application, firstly, since the first semiconductor chip is located on the top surface of the first inorganic passivation layer and the top surface of the first semiconductor chip is covered by the second inorganic passivation layer, and the top surface of the second inorganic passivation layer is provided with the third inorganic passivation layer, the materials of the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer are inorganic dielectric materials. Compared with the single-layer organic molding compound used in the prior art, the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer have smaller coefficients of thermal expansion, which can reduce the difference in the coefficients of thermal expansion between the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer and the first semiconductor chip. This effectively improves the thermal expansion coefficient of the encapsulation structure and reduces warpage. Furthermore, since the density of the first and third inorganic passivation layers is greater than that of the second inorganic passivation layer, they have excellent waterproof and moisture-proof properties. This allows the first and third inorganic passivation layers to serve as external support and protection, forming a fully encapsulated waterproof and moisture-proof barrier. Moreover, the inorganic dielectric material has high compatibility with the materials of the first semiconductor chip and the connecting pillar, strong interfacial bonding, and small difference in thermal expansion coefficients. This effectively avoids interfacial peeling and cracking caused by high and low temperature cycling and vibration, significantly improving the structural integrity of the encapsulation and reducing the path of moisture intrusion from interfacial gaps at the source.

[0043] Secondly, since the first inorganic passivation layer and the third inorganic passivation layer are located on the top and bottom surfaces of the second inorganic passivation layer, the first inorganic passivation layer and the third inorganic passivation layer serve as external support and protection. The first inorganic passivation layer and the third inorganic passivation layer, which have a higher density, directly block external loads such as mechanical impact and solder reflow, preventing them from being directly transmitted to the first semiconductor chip or other internal structures. The second inorganic passivation layer has a relatively lower density and absorbs impact energy, avoiding stress transmission to the first semiconductor chip. This results in the packaging structure having high mechanical strength and stability as a whole, effectively resisting deformation caused by external stress.

[0044] Furthermore, since the second inorganic passivation layer covers the sides of the connecting post and the subsequently installed metal post, it buffers the stress on the connecting post and the subsequently installed metal post in the circumferential direction, preventing the two ends of the subsequently installed metal post from being disconnected from the first redistribution layer and the second redistribution layer, and preventing the two ends of the connecting post from being disconnected from the first semiconductor chip and the first redistribution layer.

[0045] Finally, because the second inorganic passivation layer around the connecting post has a groove, meaning the portion of the second inorganic passivation layer covering the side of the connecting post is lower than the top surface of the connecting post, the third inorganic passivation layer can fill the groove, and the top surface of the third inorganic passivation layer is flush with the top surface of the connecting post. This allows the third inorganic passivation layer to be embedded inside the groove, forming a mechanically interlocked encapsulation structure with the second inorganic passivation layer. This significantly enhances the interfacial bonding force between the two inorganic passivation layers of different densities, thereby avoiding interlayer delamination defects caused by differences in thermal expansion coefficients and temperature cycling stress, ensuring the overall structural integrity and moisture barrier continuity of the passivation layer. Furthermore, it ensures the safety of the connecting post and subsequent installations. The entire side of the metal pillar is covered by a low-density second inorganic passivation layer, preventing the connecting pillar and the subsequently installed metal pillar from directly contacting the high-density third inorganic passivation layer. This effectively disperses stress concentration at the root and side of the connecting pillar and the subsequently installed metal pillar, thereby preventing the connecting pillar and the subsequently installed metal pillar from breaking or debonding from the chip and passivation layer interface during reliability tests such as thermal shock and temperature cycling. At the same time, after the third inorganic passivation layer fills the groove, it improves the flatness of the top surface of the connecting pillar and the subsequently installed metal pillar, ensuring full and uniform contact between the top surface of the connecting pillar and the first redistribution layer, reducing contact resistance, and improving electrical connection stability and signal transmission efficiency. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0047] Figure 1 This is a flowchart illustrating the method for forming the packaging structure provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure after providing a first carrier plate and an adhesive layer in the method of forming the encapsulation structure provided in some embodiments of this application; Figure 3 This is a schematic diagram of the structure after a first semiconductor chip, metal pillar, and connecting pillar are mounted on a first carrier board in a method for forming a packaging structure provided in some embodiments of this application. Figure 4 This is a schematic diagram of the structure after forming a second inorganic passivation layer on a first carrier plate in a method for forming a packaging structure provided in some embodiments of this application. Figure 5 This is a schematic diagram of the structure after forming a third inorganic passivation layer on the second inorganic passivation layer in the method of forming the packaging structure provided in some embodiments of this application; Figure 6 This is a schematic diagram of the structure after thinning the top surface of the third inorganic passivation layer in the method of forming the packaging structure provided in some embodiments of this application; Figure 7 This is a schematic diagram of the structure after the first redistribution layer is attached to the top surface of the third inorganic passivation layer in the method of forming the packaging structure provided in some embodiments of this application. Figure 8 This is a schematic diagram of the structure after the second semiconductor chip and the molding compound are mounted on the top surface of the first redistribution layer in the method of forming the packaging structure provided in some embodiments of this application. Figure 9 This is a schematic diagram of the structure after removing the first carrier plate in the method of forming the packaging structure provided in some embodiments of this application; Figure 10 This is a schematic diagram of the structure after the first inorganic passivation layer is formed on the bottom surface of the second inorganic passivation layer in the method of forming the packaging structure provided in some embodiments of this application; Figure 11 This is a schematic diagram of the structure in which a first through-hole is formed on a first inorganic passivation layer in a method for forming an encapsulation structure provided in some embodiments of this application; Figure 12 This is a schematic diagram of the structure after the second redistribution layer is attached to the bottom surface of the first inorganic passivation layer in the method of forming the packaging structure provided in some embodiments of this application. Figure 13 This is a schematic diagram of the structure after an organic coating layer is formed on the first carrier plate in a method for forming an encapsulation structure provided in another embodiment of this application; Figure 14 This is a schematic diagram of the structure in another embodiment of the present application, in which the organic overlay layer is bonded to the first and second wiring layers.

[0048] Explanation of reference numerals in the attached figures: 1: First inorganic passivation layer; 101: First via; 2: Second inorganic passivation layer; 21: Groove; 3: Third inorganic passivation layer; 31: Organic coating layer; 31a: Annular groove; 4: First semiconductor chip; 41: Through-hole interconnect structure; 42: Circuit layer; 51: Connecting post; 52: Metal post; 6: First redistribution layer; 61: First organic dielectric layer; 62: First metal wiring; 7: Second redistribution layer; 71: Second organic dielectric layer; 72: Second metal wiring; 8: Second semiconductor chip; 81: Molding layer; 82: Connecting protrusion; 9: Soldering protrusion; 10: First carrier board; 11: Adhesive layer. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects, and is not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise.

[0052] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with the other component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or electrical coupling, or they can be in electrical contact or electrical coupling through an intermediate component.

[0054] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0055] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0056] This application first provides a packaging structure, please refer to... Figure 12 ,include: First inorganic passivation layer 1; The first semiconductor chip is located on the top surface of the first inorganic passivation layer 1, and the surface of the first semiconductor chip 4 away from the first inorganic passivation layer 1 has a protruding connecting post 51. The second inorganic passivation layer 2 is located on the top surface of the first inorganic passivation layer 1, and covers the first semiconductor chip 4 and the side surface of the connecting post 51. The second inorganic passivation layer 2 around the connecting post 51 has a groove 21 (see reference). Figure 4 ); The third inorganic passivation layer 3 is located on the top surface of the second inorganic passivation layer 2, and the third inorganic passivation layer 3 fills the groove 21 (see reference). Figure 4 Furthermore, the top surface of the third inorganic passivation layer 3 is flush with the top surface of the connecting column 51; The density of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 is greater than the density of the second inorganic passivation layer 2.

[0057] In the aforementioned packaging structure of this application, firstly, since the first semiconductor chip 4 is located on the top surface of the first inorganic passivation layer 1 and the top surface of the first semiconductor chip 4 is covered by the second inorganic passivation layer 2, and the top surface of the second inorganic passivation layer 2 is provided with the third inorganic passivation layer 3, and the materials of the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 are inorganic dielectric materials, compared with the single-layer organic molding compound used in the prior art, the thermal expansion coefficients of the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 are smaller, which can reduce the thermal expansion coefficient between the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 and the first semiconductor chip 4. The difference in density effectively improves the thermal expansion coefficient of the encapsulation structure and reduces warpage. Furthermore, since the density of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 is greater than that of the second inorganic passivation layer 2, they have good waterproof and moisture-proof properties. This allows the first inorganic passivation layer 1 and the third inorganic passivation layer 3 to serve as external support and protection, forming a fully enclosed waterproof and moisture-proof barrier. Moreover, the inorganic dielectric material has high compatibility with the materials of the first semiconductor chip 4 and the connecting post 51, strong interfacial bonding, and small difference in thermal expansion coefficient, effectively avoiding interfacial peeling and cracking caused by high and low temperature cycling and vibration, greatly improving the structural integrity of the encapsulation body, and fundamentally reducing the path of moisture intrusion from the interfacial gaps.

[0058] Secondly, since the first inorganic passivation layer 1 and the third inorganic passivation layer 3 are located on the top and bottom surfaces of the second inorganic passivation layer 2, the first inorganic passivation layer 1 and the third inorganic passivation layer 3 serve as external support and protection. The highly dense first inorganic passivation layer 1 and the third inorganic passivation layer 3 directly block external loads such as mechanical impact and solder reflow, preventing them from being directly transmitted to the first semiconductor chip 4 or other internal structures. The second inorganic passivation layer 2 has a relatively low density and absorbs impact energy, preventing stress from being transmitted to the first semiconductor chip 4. This results in the packaging structure having high overall mechanical strength and stability, effectively resisting deformation caused by external stress.

[0059] Furthermore, since the second inorganic passivation layer 2 covers the sides of the connecting post 51 and the subsequently installed metal post 52, it buffers the stress on the connecting post 51 and the subsequently installed metal post 52 in the circumferential direction, prevents the two ends of the subsequently installed metal post 52 from being disconnected from the first redistribution layer and the second redistribution layer, and prevents the two ends of the connecting post 51 from being disconnected from the first semiconductor chip 4 and the first redistribution layer.

[0060] Finally, due to the groove 21 (see reference) in the second inorganic passivation layer 2 around the connecting post 51 Figure 4The portion of the second inorganic passivation layer 2 covering the side of the connecting post 51 is lower than the top surface of the connecting post 51, allowing the third inorganic passivation layer 3 to fill the groove 21 and with its top surface flush with the top surface of the connecting post 51. This allows the third inorganic passivation layer 3 to be embedded within the groove 21, forming a mechanically interlocked encapsulation structure with the second inorganic passivation layer 2. This significantly enhances the interfacial bonding between the two inorganic passivation layers of different densities, thus avoiding delamination defects caused by differences in thermal expansion coefficients and temperature cycling stress, ensuring the overall structural integrity and moisture barrier continuity of the passivation layer. Furthermore, it ensures that the entire side of the connecting post 51 and the subsequently installed metal post 52 is covered with a relatively low density. The high-density second inorganic passivation layer 2 covers the connecting post 51 and the subsequently installed metal post 52, preventing direct contact between them and the high-density third inorganic passivation layer 3. This effectively disperses stress concentration at the roots and sides of the connecting post 51 and the subsequently installed metal post 52, thereby preventing them from breaking or detaching from the chip and passivation layer interface during reliability tests such as thermal shock and temperature cycling. At the same time, after the third inorganic passivation layer 3 fills the groove 21, it improves the flatness of the top surface of the connecting post 51 and the subsequently installed metal post 52, ensuring sufficient and uniform contact between the top surface of the connecting post 51 and the first redistribution layer 6, reducing contact resistance, and improving electrical connection stability and signal transmission efficiency.

[0061] In some embodiments, the materials of the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 are inorganic dielectric materials.

[0062] Specifically, the materials of the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 are inorganic dielectric materials. Compared with organic encapsulation materials, they can reduce the difference in thermal expansion coefficients between the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 and the first semiconductor chip 4, thereby effectively improving the thermal expansion coefficient of the packaging structure and reducing warpage. Furthermore, the inorganic dielectric material has high compatibility with the materials of the first semiconductor chip 4, the metal pillar 52, and the connecting pillar 51, strong interface bonding, and small difference in thermal expansion coefficients, effectively avoiding interface peeling and cracking caused by high and low temperature cycling and vibration, significantly improving the structural integrity of the package, and fundamentally reducing the path of moisture intrusion from the interface.

[0063] In some embodiments, the stress adjustment range of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 is greater than 500 MPa.

[0064] In some embodiments, the materials of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 include homogeneous or heterogeneous materials with poor water absorption.

[0065] In some embodiments, the materials of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 include one or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0066] In some embodiments, the material of the second inorganic passivation layer 2 includes silicon oxide.

[0067] Specifically, the material of the second inorganic passivation layer 2 is silicon oxide, which reduces the probability of warping and deformation of the encapsulation structure. Silicon oxide is an inorganic material with the characteristics of temperature resistance, corrosion resistance, aging resistance, and UV resistance. It solves the problems of easy aging, yellowing, and delamination of organic plastic encapsulation materials used in the prior art, so that the buffering and encapsulation functions of the second inorganic passivation layer 2 remain stable for a long time and extend the service life of the encapsulation structure.

[0068] In a specific example, the first inorganic passivation layer 1 and the third inorganic passivation layer 3 are made of silicon oxide, and their coefficient of thermal expansion (CTE) during high-temperature processing is 3.0–4.0 ppm / ℃. The second inorganic passivation layer 2 is also made of silicon oxide, and its CTE during high-temperature processing is 5.0–7.0 ppm / ℃. The first semiconductor chip 4 has a CTE of 3.0 ppm / ℃ during high-temperature processing. In contrast, the CTE of organic encapsulation materials in the prior art during high-temperature processing is 15.0–20.0 ppm / ℃. Compared to organic encapsulation materials, the difference in CTE between the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 and the first semiconductor chip 4 is smaller, thereby effectively improving the CTE of the packaging structure and reducing warpage.

[0069] In another specific example, based on the tunability of silicon oxide, the second inorganic passivation layer 2 can be a dense structure, balancing buffering and moisture resistance to achieve basic protection. In yet another specific example, the second inorganic passivation layer 2 can be a loose, porous structure to enhance stress buffering capacity and suppress warping deformation of the encapsulation structure.

[0070] In some embodiments, it also includes: The metal pillar 52 is located on the top surface of the first inorganic passivation layer 1 around the first semiconductor chip 4. The top surface of the metal pillar 52 is flush with the top surface of the connecting pillar 51, and the second inorganic passivation layer 2 covers the side surface of the metal pillar 52.

[0071] The metal pillars 52 are attached to the top surface of the first inorganic passivation layer 1. The metal pillars 52 are arranged in a discontinuous array along the side of the first semiconductor chip 4. The metal pillars 52 can be arranged around the first semiconductor chip 4, or on one side of the first semiconductor chip 4. The metal pillars 52 can also be arranged densely at the four corners of the first semiconductor chip 4. The metal pillars are used to form rigid support in the edge area where stress is most concentrated in the packaging structure, suppressing the warping deformation of the packaging structure. The top surface of the third inorganic passivation layer 3 is flush with the top surfaces of the metal pillars 52 and the connecting pillars 51, ensuring stable electrical connection between the connecting pillars 51, the metal pillars 52 and other subsequent components, reducing contact resistance and improving signal transmission efficiency.

[0072] In some embodiments, the metal pillar 52 and the connecting pillar 51 are multilayer structures composed of one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni.

[0073] In some embodiments, please refer to Figure 12 and Figure 14 The number of the connecting posts 51 is multiple; The first semiconductor chip 4 includes a through-hole interconnect structure 41, which is electrically connected to a portion of the connecting posts 51, and the side of the first semiconductor chip 4 that contacts the first inorganic passivation layer 1 exposes the bottom surface of the through-hole interconnect structure 41.

[0074] Specifically, refer to Figure 11 When there are multiple connecting posts 51, multi-channel independent signal transmission is realized, allowing signals from different functional areas of the first semiconductor chip 4 to be output simultaneously, increasing the interconnection density several times. The addition of the through-hole interconnect structure 41 realizes vertical electrical interconnection of the chip, breaking the limitation of single surface interconnection, and enabling the three-dimensional packaging structure to achieve more functional signal integration in a limited space. The bottom surface of the through-hole interconnect structure 41 is exposed, reserving a channel for electrical interconnection on the back of the packaging structure. The first through-hole 101 of the first inorganic passivation layer 1 realizes the electrical connection between the first semiconductor chip 4 and the outside, realizing bidirectional electrical interconnection, adapting to the need for more chips or devices to be integrated on both sides of the three-dimensional packaging structure, and improving the scalability of the packaging structure. The through-hole interconnect structure 41 (TSV) is a mature technology for three-dimensional packaging. The fabrication of multiple connecting posts 51 can be achieved by existing photolithography and electroplating processes, without the need for additional special equipment, thus reducing production costs.

[0075] In some embodiments, it also includes: The circuit layer 42 is located within the first semiconductor chip 4, and the connecting lines in the circuit layer 42 are electrically connected to the connecting post 51.

[0076] In some embodiments, it also includes: The first rewiring layer 6 is located on the top surface of the third inorganic passivation layer 3, and is electrically connected to the metal pillar 52 and the connecting pillar 51.

[0077] In some embodiments, the first redistribution layer 6 includes a first organic dielectric layer 61 and a first metal wiring 62 located within the first organic dielectric layer 61, wherein the first metal wiring 62 is electrically connected to the metal post 52 and the connecting post 51.

[0078] In one example, the material of the first metal wiring 62 is a metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver.

[0079] In one embodiment, the first redistribution layer 6 may be a resin substrate, a silicon substrate, a printed circuit board (PCB), a redistribution layer (RDL), or a glass substrate. The first redistribution layer 6 may be a single-layer or multi-layer structure.

[0080] In some embodiments, it also includes: The second semiconductor chip 8 is flip-chip mounted on the top surface of the first redistribution layer 6 and electrically connected to the first redistribution layer 6. A molding layer 81 is located on the top surface of the first redistribution layer 6 and covers the second semiconductor chip 8.

[0081] In one example, reference Figure 8 The second semiconductor chip 8 is flip-chip mounted on the top surface of the first redistribution layer 6 via a plurality of connecting protrusions 82. One end of each connecting protrusion 82 is electrically connected to the first metal wiring 62 of the first redistribution layer 6, and the other end of each connecting protrusion 82 is electrically connected to the second semiconductor chip 8. Specifically, the molding compound 81 is used to protect the second semiconductor chip 8 and the connecting protrusions 82. The molding compound 81 is located on the top surface of the first redistribution layer 6 and covers the second semiconductor chip 8, as well as the connecting protrusions 82.

[0082] In one example, the first semiconductor chip 4 and the second semiconductor chip 8 may include logic chips and / or memory chips. In one example, the logic chip may include, but is not limited to, gate arrays, cell substrate arrays, embedded arrays, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), graphics processing units (GPUs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), logic integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In one example, the memory chip may include, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), resistive random access memory (RRAM), or non-volatile memory chips (such as flash memory).

[0083] In some embodiments, the material of the molding layer 81 may be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin with or without filler; or it may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer, or polyvinyl alcohol with filler. The filler may be inorganic or organic.

[0084] In one example, the process of forming the encapsulation layer 81 includes compression molding or transfer molding.

[0085] In some embodiments, it also includes: The second wiring layer 7 is located on the bottom surface of the first inorganic passivation layer 1, and the second wiring layer 7 is electrically connected to the metal pillar 52 and the through-hole interconnect structure 41 respectively.

[0086] In some embodiments, please refer to Figure 11 , The first inorganic passivation layer 1 has a plurality of first through holes 101 corresponding to the metal pillar 52 and the through hole interconnection structure 41, and the first through holes 101 penetrate the top surface and the bottom surface of the first inorganic passivation layer 1. The second redistribution layer 7 includes: a second organic dielectric layer 71 and a second metal wiring 72 within the second organic dielectric layer 71, wherein the second metal wiring 72 passes through the first via 101 and is electrically connected to the metal pillar 52 and the via interconnection structure 41.

[0087] In one example, the material of the second metal wiring 72 is a metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver.

[0088] In one embodiment, the second redistribution layer 7 may be a resin substrate, a silicon substrate, a printed circuit board (PCB), a redistribution layer (RDL), or a glass substrate. The second redistribution layer 7 may be a single-layer or multi-layer structure.

[0089] In some embodiments, the material of the second organic dielectric layer 71 includes polyimide.

[0090] In some embodiments, please refer to Figure 12 and Figure 14 It also includes: The welding protrusions 9 are electrically connected to the second metal wiring 72 in the second redistribution layer 7.

[0091] The solder bumps 9 are used for electrical connections between the second redistribution layer 7 and the subsequently mounted substrate or package. There can be multiple solder bumps 9, located on the side of the second metal wiring layer away from the first semiconductor chip. In some embodiments, the solder bumps 9 may include solder balls or metal pillars. In one example, when the solder bump 9 is a solder ball, the material of the solder bump 9 includes solder, which includes one or more of tin, tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. In another example, when the solder bump 9 is a metal pillar, the material of the solder bump 9 includes one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni.

[0092] In some embodiments, please refer to Figure 13 and Figure 14 It also includes: An organic coating layer 31 covers the sides of the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 along the circumferential direction. The top surface of the organic coating layer 31 is in contact with the bottom surface of the first redistribution layer 6, and the bottom surface of the organic coating layer 31 is in contact with the top surface of the second redistribution layer 7.

[0093] Specifically, the organic coating layer 31 covers the sides of the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3, preventing external moisture and dust from entering the first semiconductor chip 4 through the gaps on the sides of the three passivation layers, thus achieving all-dimensional moisture absorption protection; it seamlessly connects the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 into a whole, improving the rigidity and mechanical stability of the overall packaging structure; it prevents leakage and short circuit risks caused by the contact between the sides of the packaging structure and external devices, thus improving electrical insulation.

[0094] In one example, the organic coating layer 31 is an organic material, such as polyimide, adapted to the material of the second organic dielectric layer 71, such as epoxy resin or benzocyclobutene (BCB), and is prepared by processes such as coating, molding, or lamination. Alternatively, materials with a certain degree of elasticity, such as silicone rubber or polyurethane, can be used, formed by dispensing or potting processes to accommodate possible deformations in the encapsulation structure.

[0095] This application also provides a method for forming a packaging structure. Figure 1 This is a flowchart illustrating the method for forming the encapsulation structure provided in some embodiments of this application. (Refer to...) Figure 1 The method for forming the encapsulation structure includes the following steps: Step S101: Provide the first carrier board; Step S102: Provide a first semiconductor chip, mount the first semiconductor chip on the top surface of the first carrier board, and the surface of the first semiconductor chip away from the first carrier board has protruding connecting pillars. The first semiconductor chip has through-hole interconnection structures, and a plurality of the through-hole interconnection structures are electrically connected to a portion of the connecting pillars. Step S103: A second inorganic passivation layer is formed on the top surface of the first carrier plate. The second inorganic passivation layer covers the first semiconductor chip and the side of the connecting post, and the second inorganic passivation layer around the connecting post has a groove. Step S104: A third inorganic passivation layer is formed on the top surface of the second inorganic passivation layer. The third inorganic passivation layer fills the groove, and the top surface of the third inorganic passivation layer is flush with the top surface of the connecting post. Step S105: Remove the first carrier plate to expose the second inorganic passivation layer and the surface of the first semiconductor chip away from the third inorganic passivation layer; Step S106: A first inorganic passivation layer is formed on the bottom surface of the second inorganic passivation layer, wherein the density of the first inorganic passivation layer and the third inorganic passivation layer is greater than the density of the second inorganic passivation layer.

[0096] The method for forming the packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0097] First, refer to Figure 1 In conjunction with references Figure 2 Step S101 is performed to provide a first carrier board 10.

[0098] The first carrier plate 10 serves as a temporary process carrier, which is used to support and fix the first semiconductor chip 4, the metal pillar 52 and the second inorganic passivation layer 2 in the subsequent packaging process to ensure the smooth progress of the packaging process. Before the subsequent thinning, the first carrier plate 10 needs to be peeled off or removed.

[0099] In one example, the first carrier plate 10 may be one or more of the following: a glass plate, a silicon plate, a ceramic material plate doped with alumina or aluminum nitride.

[0100] Next, continue to refer to Figure 1 In conjunction with references Figure 3 In step S102, a first semiconductor chip 4 is provided and mounted on the top surface of the first carrier plate 10. The surface of the first semiconductor chip 4 away from the first carrier plate 10 has protruding connecting posts 51. The first semiconductor chip 4 has through-hole interconnection structures 41, and a plurality of the through-hole interconnection structures 41 are electrically connected to a portion of the connecting posts 51.

[0101] Specifically, the first semiconductor chip 4 is precisely mounted on the top surface of the first carrier board, using the first carrier board 10 as a unified positioning reference, effectively avoiding overall offset and dimensional deviation of the packaging structure. During the mounting stage of the first semiconductor chip 4, the precise electrical connection between the through-hole interconnect structure 41 and the connecting post 51 is completed. Compared to subsequent field docking, the processing precision of the mounting stage is higher, enabling precise one-to-one or one-to-many output of multi-channel signals. This reduces aliasing and crosstalk problems in multi-channel signal transmission, improves the stability and accuracy of signal transmission, ensures signal transmission accuracy, and avoids crosstalk failure.

[0102] In some embodiments, Mounting the first semiconductor chip 4 onto the top surface of the first carrier board 10 includes: An adhesive layer 11 is formed on the first carrier 10, and the first semiconductor chip 4 and the semiconductor chip 5 are temporarily bonded to the first carrier 10 by being attached to the adhesive layer 11. In one example, the adhesive layer may be formed by applying an adhesive or by a film lamination process.

[0103] In some embodiments, the adhesive is polyimide or titanium nitride.

[0104] In other embodiments, the adhesive is one of a reversible thermosetting resin, a thermoplastic elastomer, or a silicone resin containing photosensitive groups.

[0105] Next, continue to refer to Figure 1 In conjunction with references Figure 4 In step S103, a second inorganic passivation layer 2 is formed on the top surface of the first carrier plate 10. The second inorganic passivation layer 2 covers the first semiconductor chip 4 and the side of the connecting post 51, and the second inorganic passivation layer 2 around the connecting post 51 has a groove 21.

[0106] In some embodiments, before forming the second inorganic passivation layer 2 on the top surface of the first carrier plate 10, the following steps are included: A metal pillar 52 is provided and is attached to the top surface of the first carrier plate 10 around the first semiconductor chip 4. The top surface of the metal pillar 52 is flush with the top surface of the connecting pillar 51. When the second inorganic passivation layer 2 is formed on the top surface of the first carrier plate 10, the second inorganic passivation layer 2 covers the side surface of the metal pillar 52.

[0107] The metal pillars 52 are mounted on the top surface of the first carrier plate 10 surrounding the first semiconductor chip 4. The metal pillars have no physical contact with the first semiconductor chip 4 or the connecting pillars 51, preventing scratching or squeezing damage to the first semiconductor chip 4 and the connecting pillars 51 during mounting, and reserving sufficient space for subsequent fabrication processes. (Refer to...) Figure 4 This disperses localized stress concentrations caused by interfacial tension and thermal stress during the formation of the second inorganic passivation layer 2, effectively preventing warping and cracking of the second inorganic passivation layer 2 and improving the structural stability of the packaging structure. The top surface of the metal pillar 52 is flush with the top surface of the connecting pillar 51, and the metal pillar 52 and the connecting pillar 51 form an array interconnection. An electrical interconnection interface is added to the connecting pillar 51 of the first semiconductor chip 4, expanding the signal transmission channel and enabling the packaging structure to achieve multi-channel, multi-functional signal transmission, thus reducing processing costs.

[0108] In some embodiments, reference Figure 4 and Figure 5The formation of a second inorganic passivation layer 2 on the top surface of the first carrier plate 10 includes: A second inorganic passivation layer 2 is formed using a chemical vapor deposition process. The formed second inorganic passivation layer 2 covers the first semiconductor chip 4 and the top and side surfaces of the metal pillar 52 and the connecting pillar 51, and part of the top surface of the second inorganic passivation layer 2 is lower than the top surface of the metal pillar 52 and the connecting pillar 51.

[0109] In other embodiments, forming a second inorganic passivation layer 2 on the top surface of the first carrier plate 10 includes: A second inorganic passivation layer 2 is formed using a chemical vapor deposition process. The second inorganic passivation layer 2 covers the first semiconductor chip 4 and the metal pillar 52 and the connecting pillar 51, and the top surface of the second inorganic passivation layer 2 is higher than the top surface of the metal pillar 52 and the connecting pillar 51. The second inorganic passivation layer 2 is etched away between the metal pillars 52 and between the metal pillars 52 and the connecting pillar 51 to form a groove, such that the top surface of the remaining second inorganic passivation layer 2 at the bottom of the groove is lower than the top surface of the metal pillars 52 and the connecting pillar 51, and the remaining second inorganic passivation layer 2 on the side of the groove covers the side of the metal pillars 52 and the connecting pillar 51.

[0110] In some embodiments, the material of the second inorganic passivation layer 2 includes silicon oxide.

[0111] Next, continue to refer to Figure 1 In conjunction with references Figure 5 and Figure 6 In step S104, a third inorganic passivation layer 3 is formed on the top surface of the second inorganic passivation layer 2. The third inorganic passivation layer 3 fills the groove 21, and the top surface of the third inorganic passivation layer 3 is flush with the top surface of the connecting post 51.

[0112] In some embodiments, a third inorganic passivation layer 3 is formed on the top surface of the second inorganic passivation layer 2, including: refer to Figure 5 A third inorganic passivation layer 3 is formed on the top surface of the second inorganic passivation layer 2 using a chemical vapor deposition process. refer to Figure 6 The top surface of the third inorganic passivation layer 3 is thinned so that the top surface of the third inorganic passivation layer 3 is flush with the top surfaces of the metal pillar 52 and the connecting pillar 51.

[0113] In some embodiments, reference Figure 6 and Figure 7 After thinning the top surface of the third inorganic passivation layer 3, the method further includes: A first redistribution layer 6 is formed on the top surface of the third inorganic passivation layer 3, and the first redistribution layer 6 is electrically connected to the metal pillar 52 and the connecting pillar 51.

[0114] In some examples, the thinning can also employ mechanical polishing or chemical mechanical polishing (CMP) techniques. Mechanical polishing involves using polishing equipment to mechanically grind the surface, gradually removing material. Mechanical polishing or chemical mechanical polishing combines the effects of mechanical polishing and chemical etching to achieve high-precision planarization and thinning. The endpoint of the thinning support can be precisely controlled through optical detection or electrical contact detection to ensure that the top surfaces of the connecting post 51 and the metal post 52 are accurately exposed.

[0115] In some embodiments, reference Figure 13 and Figure 14 It also includes: An organic coating layer 31 is formed on the first carrier plate 10, and the organic coating layer 31 covers the sides of the first inorganic passivation layer 1, the second inorganic passivation layer 2 and the third inorganic passivation layer 3 along the circumferential direction. A first redistribution layer 6 is formed on the top surface of the third inorganic passivation layer 3 and the organic coating layer 31. The top surface of the organic coating layer 31 is in contact with the bottom surface of the first redistribution layer 6, and the bottom surface of the organic coating layer 31 is in contact with the top surface of the first carrier plate 10.

[0116] In some embodiments, reference Figure 7 The first redistribution layer 6 further includes: a first organic dielectric layer 61 and a first metal wiring 62 located within the first organic dielectric layer 61, wherein the first metal wiring 62 is electrically connected to the metal post 52 and the connecting post 51. The formation process of the organic coating layer 31 and the first redistribution layer 6 includes: etching away the edge portions of the first inorganic passivation layer 1, the second inorganic passivation layer 2 and the third inorganic passivation layer 3 to form an annular groove 31a surrounding the metal pillar 52 and the first semiconductor chip 4; An organic material layer is formed on the top surface of the third inorganic passivation layer 3 and in the annular groove 31a. The organic material layer on the top surface of the third inorganic passivation layer 3 serves as the first organic medium layer 61, and the organic material layer in the annular groove 31a serves as the organic coating layer 31. A plurality of openings are formed in the first organic medium layer 61, and the openings expose the top surfaces of the metal pillar 52 and the connecting pillar 51 respectively; The opening is filled with metal to form the first metal wiring 62.

[0117] In one example, the organic coating layer 31 is formed simultaneously with the first organic medium layer 61, and the organic coating layer 31 and the first organic medium layer 61 are made of the same material.

[0118] In another example, refer to Figure 14 After the organic coating layer 31 is formed, the first organic dielectric layer 61 is formed on the top surface of the second inorganic passivation layer 2 and the organic coating layer 31.

[0119] In one example, the organic coating layer 31 is an organic material, such as polyimide, adapted to the material of the second organic dielectric layer 71, such as epoxy resin or benzocyclobutene (BCB), and is prepared by processes such as coating, molding, or lamination. Alternatively, materials with a certain degree of elasticity, such as silicone rubber or polyurethane, can be used, formed by dispensing or potting processes to accommodate possible deformations in the encapsulation structure.

[0120] In some embodiments, reference Figure 8 After forming the first redistribution layer 6, it also includes: A second semiconductor chip 8 is provided, which is flip-chip mounted on the top surface of the first redistribution layer 6 and is electrically connected to the first redistribution layer 6. A molding compound 81 is formed on the top surface of the first redistribution layer 6, and the molding compound 81 covers the second semiconductor chip 8.

[0121] Next, continue to refer to Figure 1 In conjunction with references Figure 9 In step S106, the first carrier plate 10 is removed, exposing the second inorganic passivation layer 2 and the surface of the first semiconductor chip 4 away from the third inorganic passivation layer 3.

[0122] In some embodiments, removing the first carrier board 10 further includes: The first carrier plate 10 is removed using wet chemical immersion debonding, thermal slip debonding, or laser debonding methods.

[0123] Finally, continue to refer to Figure 1 In conjunction with references Figure 12 In step S107, a first inorganic passivation layer 1 is formed on the bottom surface of the second inorganic passivation layer 2, wherein the density of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 is greater than that of the second inorganic passivation layer 2.

[0124] In some embodiments, the materials of the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 are inorganic dielectric materials.

[0125] In some embodiments, the stress adjustment range of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 is greater than 500 MPa.

[0126] In a specific example, the stress of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 can be 410 MPa, 420 MPa, 450 MPa, 500 MPa, 550 MPa, or 600 MPa. The first and third inorganic passivation layers are prepared using chemical vapor deposition (CVD). By controlling process parameters such as deposition temperature, reactive gas ratio, radio frequency power, and deposition rate, the stress of the films of the first and third inorganic passivation layers 1 and 3 is kept within an adjustable range to adapt to the thermomechanical stress changes of the packaging structure during preparation and use, effectively balancing the stress distribution and preventing the packaging structure from warping, deforming, or separating due to stress imbalance.

[0127] In some embodiments, the materials of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 include homogeneous or heterogeneous materials with poor water absorption.

[0128] In some embodiments, the materials of the first inorganic passivation layer 1 and the third inorganic passivation layer 3 include one or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0129] In some embodiments, the formation of the first inorganic passivation layer 1 is achieved using a chemical vapor deposition process.

[0130] In a specific example, the first inorganic passivation layer 1 and the third inorganic passivation layer 3 are made of silicon nitride, and their coefficient of thermal expansion (CTE) during high-temperature processing is 3.0–4.0 ppm / ℃. The second inorganic passivation layer 2 is made of silicon oxide, and its CTE during high-temperature processing is 5.0–7.0 ppm / ℃. The first semiconductor chip 4 has a CTE of 3.0 ppm / ℃ during high-temperature processing. In contrast, the CTE of organic encapsulation materials in the prior art during high-temperature processing is 15.0–20.0 ppm / ℃. Compared to organic encapsulation materials, the difference in CTE between the first inorganic passivation layer 1, the second inorganic passivation layer 2, and the third inorganic passivation layer 3 and the first semiconductor chip 4 is smaller, thereby effectively improving the CTE of the packaging structure and reducing warpage.

[0131] In another specific example, based on the tunability of silicon oxide, the second inorganic passivation layer 2 can be a dense structure, balancing buffering and moisture resistance to achieve basic protection. In yet another specific example, the second inorganic passivation layer 2 can be a loose, porous structure to enhance stress buffering capacity and suppress warping deformation of the encapsulation structure.

[0132] In some embodiments, reference Figure 12 , After forming the first inorganic passivation layer 1 on the bottom surface of the second inorganic passivation layer 2, the method further includes: A second redistribution layer 7 is formed on the bottom surface of the first inorganic passivation layer 1, and the second redistribution layer 7 is electrically connected to the metal pillar 52 and the through-hole interconnect structure 41.

[0133] In some embodiments, reference Figure 11 Before the second redistribution layer 7 is formed on the bottom surface of the first inorganic passivation layer 1, the method further includes: A plurality of first through holes 101 corresponding to the metal pillar 52 and the through hole interconnection structure 41 are formed in the first inorganic passivation layer 1. The first through holes 101 penetrate the top surface and the bottom surface of the first inorganic passivation layer 1. The second redistribution layer 7 includes a second organic dielectric layer 71 and a second metal wiring 72 located within the second organic dielectric layer 71. The second metal wiring 72 passes through the first via 101 and is electrically connected to the metal pillar 52 and the via interconnect structure 41.

[0134] In some embodiments, reference Figure 12 and Figure 14 , Solder protrusions 9 are provided, and a plurality of said solder protrusions 9 are electrically connected to the second metal wiring 72 in the second rewiring layer 7.

[0135] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0136] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0137] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A packaging structure, characterized in that, include: First inorganic passivation layer; A first semiconductor chip is located on the top surface of the first inorganic passivation layer, and the surface of the first semiconductor chip away from the first inorganic passivation layer has protruding connecting pillars. The second inorganic passivation layer is located on the top surface of the first inorganic passivation layer, and covers the first semiconductor chip and the side of the connecting post, and the second inorganic passivation layer around the connecting post has a groove. A third inorganic passivation layer is located on the top surface of the second inorganic passivation layer. The third inorganic passivation layer fills the groove, and the top surface of the third inorganic passivation layer is flush with the top surface of the connecting post. The density of the first inorganic passivation layer and the third inorganic passivation layer is greater than the density of the second inorganic passivation layer.

2. The packaging structure according to claim 1, characterized in that, The materials of the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer are inorganic dielectric materials.

3. The packaging structure according to claim 2, characterized in that, The stress adjustment range of the first inorganic passivation layer and the third inorganic passivation layer is greater than 500 MPa.

4. The packaging structure according to claim 2, characterized in that, The materials of the first inorganic passivation layer and the third inorganic passivation layer include homogeneous or heterogeneous materials with poor water absorption.

5. The packaging structure according to claim 4, characterized in that, The materials of the first inorganic passivation layer and the third inorganic passivation layer include one or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

6. The packaging structure according to claim 4, characterized in that, The material of the second inorganic passivation layer includes silicon oxide.

7. The packaging structure according to claim 1, characterized in that, Also includes: A metal pillar is located on the top surface of the first inorganic passivation layer around the first semiconductor chip. The top surface of the metal pillar is flush with the top surface of the connecting pillar, and the second inorganic passivation layer covers the side surface of the metal pillar.

8. The packaging structure according to claim 7, characterized in that, The metal pillars and the connecting pillars are multilayer structures composed of one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni.

9. The packaging structure according to claim 8, characterized in that, The number of connecting posts is multiple; The first semiconductor chip includes a through-hole interconnect structure, which is electrically connected to a portion of the connecting pillars, and the side of the first semiconductor chip that contacts the first inorganic passivation layer exposes the bottom surface of the through-hole interconnect structure.

10. The packaging structure according to claim 1, characterized in that, Also includes: A circuit layer is located within the first semiconductor chip, and the connecting lines in the circuit layer are electrically connected to the connecting posts.

11. The packaging structure according to claim 9, characterized in that, Also includes: The first wiring layer is located on the top surface of the third inorganic passivation layer and is electrically connected to the metal pillar and the connecting pillar.

12. The packaging structure according to claim 11, characterized in that, The first rewiring layer includes: a first organic dielectric layer and a first metal wiring located within the first organic dielectric layer, wherein the first metal wiring is electrically connected to the metal post and the connecting post.

13. The packaging structure according to claim 11, characterized in that, Also includes: The second semiconductor chip is flip-chipped onto the top surface of the first interconnect layer and electrically connected to the first interconnect layer. A molding layer is located on the top surface of the first redistribution layer and covers the second semiconductor chip.

14. The packaging structure according to claim 9, characterized in that, Also includes: The second wiring layer is located on the bottom surface of the first inorganic passivation layer, and the second wiring layer is electrically connected to the metal pillar and the through-hole interconnect structure.

15. The packaging structure according to claim 14, characterized in that, The first inorganic passivation layer has a plurality of first through holes corresponding to the metal pillar and the through hole interconnection structure, and the first through holes penetrate the top and bottom surfaces of the first inorganic passivation layer; The second redistribution layer includes: a second organic dielectric layer and a second metal wiring within the second organic dielectric layer, wherein the second metal wiring passes through the first via and is electrically connected to the metal pillar and the via interconnect structure.

16. The packaging structure according to claim 15, characterized in that, The material of the second organic dielectric layer includes polyimide.

17. The packaging structure according to claim 15, characterized in that, Also includes: The welding protrusions are electrically connected to the second metal wiring in the second rewiring layer.

18. The packaging structure according to claim 15, characterized in that, Also includes: An organic coating layer covers the sides of the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer along the circumferential direction. The top surface of the organic coating layer is in contact with the bottom surface of the first redistribution layer, and the bottom surface of the organic coating layer is in contact with the top surface of the second redistribution layer.

19. A method for forming an encapsulation structure, characterized in that, include: Provide the first carrier board; A first semiconductor chip is provided, the first semiconductor chip is mounted on the top surface of the first substrate, and the surface of the first semiconductor chip away from the first substrate has protruding connecting pillars. The first semiconductor chip has through-hole interconnection structures, and a plurality of the through-hole interconnection structures are electrically connected to a portion of the connecting pillars. A second inorganic passivation layer is formed on the top surface of the first carrier plate. The second inorganic passivation layer covers the first semiconductor chip and the side of the connecting post. The second inorganic passivation layer around the connecting post has a groove. A third inorganic passivation layer is formed on the top surface of the second inorganic passivation layer, the third inorganic passivation layer fills the groove, and the top surface of the third inorganic passivation layer is flush with the top surface of the connecting post. Remove the first carrier plate to expose the second inorganic passivation layer and the surface of the first semiconductor chip away from the third inorganic passivation layer; A first inorganic passivation layer is formed on the bottom surface of the second inorganic passivation layer, and the density of the first inorganic passivation layer and the third inorganic passivation layer is greater than the density of the second inorganic passivation layer.

20. The method for forming the packaging structure according to claim 19, characterized in that, The materials of the first inorganic passivation layer, the second inorganic passivation layer, and the third inorganic passivation layer are inorganic dielectric materials.

21. The method for forming the packaging structure according to claim 20, characterized in that, The stress adjustment range of the first inorganic passivation layer and the third inorganic passivation layer is greater than 500 MPa.

22. The method for forming the packaging structure according to claim 20, characterized in that, The materials of the first inorganic passivation layer and the third inorganic passivation layer include homogeneous or heterogeneous materials with poor water absorption.

23. The method for forming the packaging structure according to claim 22, characterized in that, The materials of the first inorganic passivation layer and the third inorganic passivation layer include one or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

24. The method for forming the packaging structure according to claim 22, characterized in that, The material of the second inorganic passivation layer includes silicon oxide.

25. The method for forming the packaging structure according to claim 19, characterized in that, The formation of the first inorganic passivation layer is achieved using a chemical vapor deposition process.

26. The method for forming the packaging structure according to claim 19, characterized in that, Before forming the second inorganic passivation layer on the top surface of the first carrier plate, the process includes: A metal pillar is provided and attached to the top surface of the first carrier plate on the periphery of the first semiconductor chip, wherein the top surface of the metal pillar is flush with the top surface of the connecting pillar. When a second inorganic passivation layer is formed on the top surface of the first carrier plate, the second inorganic passivation layer covers the side surface of the metal pillar.

27. The method for forming the packaging structure according to claim 26, characterized in that, A third inorganic passivation layer is formed on the top surface of the second inorganic passivation layer, comprising: A third inorganic passivation layer is formed on the top surface of the second inorganic passivation layer using a chemical vapor deposition process; The top surface of the third inorganic passivation layer is thinned so that the top surface of the third inorganic passivation layer is flush with the top surfaces of the metal pillar and the connecting pillar.

28. The method for forming the packaging structure according to claim 27, characterized in that, After thinning the top surface of the third inorganic passivation layer, the method further includes: A first redistribution layer is formed on the top surface of the third inorganic passivation layer, and the first redistribution layer is electrically connected to the metal pillar and the connecting pillar.

29. The method for forming the packaging structure according to claim 27, characterized in that, Also includes: An organic coating layer is formed on the first carrier plate, and the organic coating layer covers the sides of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer along the circumferential direction of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer; A first redistribution layer is formed on the top surface of the third inorganic passivation layer and the organic coating layer. The top surface of the organic coating layer is in contact with the bottom surface of the first redistribution layer, and the bottom surface of the organic coating layer is in contact with the top surface of the first carrier board.

30. The method for forming the packaging structure according to claim 29, characterized in that, The first redistribution layer includes: a first organic dielectric layer and a first metal wiring located within the first organic dielectric layer, wherein the first metal wiring is electrically connected to the metal post and the connecting post; The formation process of the organic coating layer and the first redistribution layer includes: etching away portions of the first inorganic passivation layer, the second inorganic passivation layer and the third inorganic passivation layer at their edges to form an annular groove surrounding the metal pillar and the first semiconductor chip; An organic material layer is formed on the top surface of the third inorganic passivation layer and in the annular groove. The organic material layer on the top surface of the third inorganic passivation layer serves as the first organic medium layer, and the organic material layer in the annular groove serves as the organic coating layer. A plurality of openings are formed in the first organic medium layer, the openings corresponding to the top surfaces of the metal pillar and the connecting pillar; The opening is filled with metal to form the first metal wiring.

31. The method for forming the packaging structure according to claim 28 or 30, characterized in that, After forming the first redistribution layer, the method further includes: A second semiconductor chip is provided, which is flip-chip mounted on the top surface of the first multi-wiring layer and is electrically connected to the first multi-wiring layer. A molding compound is formed on the top surface of the first redistribution layer, the molding compound covering the second semiconductor chip.

32. The method for forming the packaging structure according to claim 26, characterized in that, Forming a second inorganic passivation layer on the top surface of the first carrier plate includes: A second inorganic passivation layer is formed using a chemical vapor deposition process. The formed second inorganic passivation layer covers the first semiconductor chip and the top and side surfaces of the metal pillar and the connecting pillar, and part of the top surface of the second inorganic passivation layer is lower than the top surface of the metal pillar and the connecting pillar.

33. The method for forming the packaging structure according to claim 26, characterized in that, Forming a second inorganic passivation layer on the top surface of the first carrier plate includes: A second inorganic passivation layer is formed using a chemical vapor deposition process. The second inorganic passivation layer covers the first semiconductor chip and the metal pillar and the connecting pillar, and the top surface of the second inorganic passivation layer is higher than the top surface of the metal pillar and the connecting pillar. The second inorganic passivation layer between the metal pillars and between the metal pillars and the connecting pillars is etched away to form a groove, such that the top surface of the remaining second inorganic passivation layer at the bottom of the groove is lower than the top surface of the metal pillars and the connecting pillars, and the remaining second inorganic passivation layer on the side of the groove covers the side of the metal pillars and the connecting pillars.

34. The method for forming the packaging structure according to claim 26, characterized in that, After forming the first inorganic passivation layer on the bottom surface of the second inorganic passivation layer, the process further includes: A second redistribution layer is formed on the bottom surface of the first inorganic passivation layer, and the second redistribution layer is electrically connected to the metal pillar and the through-hole interconnect structure.

35. The method for forming the packaging structure according to claim 34, characterized in that, Before forming the second redistribution layer on the bottom surface of the first inorganic passivation layer, the method further includes: A plurality of first through holes corresponding to the metal pillar and the through hole interconnection structure are formed in the first inorganic passivation layer, and the first through holes penetrate the top and bottom surfaces of the first inorganic passivation layer. The second redistribution layer includes a second organic dielectric layer and a second metal wiring located within the second organic dielectric layer, wherein the second metal wiring passes through the first via and is electrically connected to the metal pillar and the via interconnect structure.

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