An embedded half-bridge cell

By placing the power semiconductor chip on two planes and embedding a DC-Link capacitor in the half-bridge unit, the problems of low power density and poor heat dissipation in the prior art are solved by utilizing the interlayer structure and electrical and thermal conductivity, thereby achieving higher circuit performance and thermal management efficiency.

CN122421818APending Publication Date: 2026-07-17CRRC ZHUZHOU ELECTRIC LOCOMOTIVE RESEARCH INSTITUTE CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
CRRC ZHUZHOU ELECTRIC LOCOMOTIVE RESEARCH INSTITUTE CO LTD
Filing Date
2026-04-27
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

The large size of the DC-Link capacitor in the existing half-bridge unit results in low power density. The power semiconductor chip located on a single plane leads to large AC line inductance, large temperature difference, high heat loss and poor heat dissipation.

Method used

By employing an interlayer structure, the power semiconductor chip is placed on two planes, and the DC-Link capacitor is embedded inside the half-bridge unit. By utilizing the alternating stacking and vertical layout of the DC positive and negative conductive parts, a large capacitor, a small inductor, and a large heat capacity are constructed, thereby improving the conductivity and thermal conductivity.

Benefits of technology

It significantly improves the power density of the half-bridge unit, reduces inductance and temperature difference, enhances heat dissipation capability, and eliminates contact thermal resistance issues.

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Abstract

This invention provides an embedded half-bridge unit, comprising a first power semiconductor chip, a DC positive conductive portion, a DC negative conductive portion, a second power semiconductor chip, and an AC conductive portion. The first power semiconductor chip is located at the top of the embedded half-bridge unit, and the second power semiconductor chip is located at the bottom. A first extension layer and a second extension layer of the AC conductive portion extend in a parallel direction and are connected by a vertical main body portion. The protrusions of the DC positive conductive portion and the DC negative conductive portion extend in a direction perpendicular to the main body portion, and the protrusions of the DC positive conductive portion and the DC negative conductive portion are alternately stacked but not directly connected. The first extension layer is connected to the top of the first power semiconductor chip, and the uppermost protrusion of the DC positive conductive portion is connected to the bottom of the first power semiconductor chip. The lowermost protrusion of the DC negative conductive portion is connected to the top of the second power semiconductor chip, and the second extension layer is connected to the bottom of the second power semiconductor chip.
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