Semiconductor device and display device

Abstract

A display device with a high aperture ratio is provided. A high-definition display device is also provided. The display device includes first to third conductive layers, a first semiconductor layer, and first and second insulating layers. The first insulating layer has an island-like shape and includes a first surface located on the first conductive layer. The first surface is a portion of a side surface of the first insulating layer and has two or more regions with normal directions different from each other. The second conductive layer is located on the first insulating layer. The first semiconductor layer has a first portion in contact with the top surface of the first conductive layer, a second portion in contact with the top surface of the second conductive layer, and a third portion in contact with the first surface of the first insulating layer. The second insulating layer covers the third portion. The third conductive layer covers the third portion through the second insulating layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. Another aspect of the present invention relates to a transistor. Another aspect of the present invention relates to a display device including a transistor.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving these devices, and methods for manufacturing these devices. A semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Background Technology

[0003] As a type of display device, there are liquid crystal display devices that use liquid crystal elements as display elements. For example, active matrix liquid crystal display devices, in which pixel electrodes are arranged in a matrix and each pixel electrode is connected to a switching element, are used in various devices such as smartphones, tablets, displays, televisions, and digital signage.

[0004] Liquid crystal display devices are generally classified into two types: transmissive and reflective. A higher effective light-emitting area ratio (also known as aperture ratio) in the pixels of a liquid crystal display device results in a brighter display, which helps reduce power consumption; therefore, a higher aperture ratio is required.

[0005] For example, active matrix liquid crystal display devices are known that use transistors with metal oxide as the channel formation region as switching elements connected to the electrodes of each pixel. Patent Document 1 discloses a liquid crystal display device that uses transistors with metal oxide as the channel formation region to improve the aperture ratio.

[0006] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2018-189938. Summary of the Invention

[0007] The technical problem that the invention aims to solve Furthermore, one aspect of the present invention provides a transistor capable of miniaturization. One objective of one aspect of the present invention is to provide a transistor with excellent electrical characteristics. Additionally, one aspect of the present invention provides a transistor with a short channel length. Furthermore, one aspect of the present invention provides a transistor with a small footprint.

[0008] One objective of this invention is to provide a liquid crystal display device with a high aperture ratio. Another objective of this invention is to provide a liquid crystal display device with high resolution. Another objective of this invention is to provide a liquid crystal display device with low power consumption. Another objective of this invention is to provide a liquid crystal display device capable of high-speed driving. Finally, one objective of this invention is to provide a display device with high display quality.

[0009] One objective of this invention is to provide a transistor, display device, electronic device, etc., with a novel structure. Another objective of this invention is to provide a transistor, display device, electronic device, etc., with high reliability. One objective of this invention is to at least improve upon at least one of the problems of the prior art.

[0010] Note that the description of these objectives does not preclude the existence of other objectives. Also note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, claims, etc.

[0011] means of solving technical problems One aspect of the present invention is a semiconductor device comprising a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer has an island-like shape and includes a first surface located on the first conductive layer. The first surface is a portion of a side surface of the first insulating layer and has two or more regions with normal directions different from each other. The second conductive layer is located on the first insulating layer. The first semiconductor layer has a first portion contacting the top surface of the first conductive layer, a second portion contacting the top surface of the second conductive layer, and a third portion contacting the first surface of the first insulating layer. The second insulating layer covers the third portion of the first semiconductor layer. The third conductive layer covers the third portion of the first semiconductor layer through the second insulating layer.

[0012] Furthermore, in the above structure, the first surface of the first insulating layer preferably has two orthogonal planes on the first conductive layer. Additionally, the first surface of the first insulating layer preferably has a curved shape on the first conductive layer.

[0013] Furthermore, in the above structure, the end of the second insulating layer is preferably aligned with the third conductive layer.

[0014] Furthermore, in the above structure, a second semiconductor layer is preferably included. Additionally, the first insulating layer preferably has a second surface that is another part of its side surface and is located on the first conductive layer. In this case, it is preferable that the second semiconductor layer has a fourth portion in contact with the second surface, and the second insulating layer covers the fourth portion of the second semiconductor layer. In this case, the second semiconductor layer preferably has a fifth portion in contact with the top surface of the first conductive layer and a sixth portion in contact with the top surface of the second conductive layer.

[0015] Furthermore, in the above structure, it is preferable to further include a second semiconductor layer and a fourth conductive layer. Additionally, the first insulating layer preferably has a third surface that is another part of its side surface and is located on the fourth conductive layer. In this case, the second semiconductor layer preferably has a fifth portion that contacts the top surface of the fourth conductive layer, a sixth portion that contacts the top surface of the second conductive layer, and a seventh portion that contacts the third surface. Furthermore, the second insulating layer preferably covers the seventh portion of the second semiconductor layer.

[0016] Another aspect of the present invention is a display device comprising any of the aforementioned semiconductor devices and a liquid crystal element. The liquid crystal element includes a portion of a second conductive layer, liquid crystal, and a fifth conductive layer. The liquid crystal is located on the second conductive layer. The second conductive layer serves as a pixel electrode. The fifth conductive layer serves as a common electrode.

[0017] Furthermore, in the above structure, a third insulating layer is preferably included that covers the second conductive layer, the third conductive layer, and the second insulating layer.

[0018] In the above structure, the second conductive layer preferably has a region that does not overlap with the first insulating layer, and this region is preferably used as a pixel electrode.

[0019] Another aspect of the present invention is a display device comprising a first conductive layer, a third conductive layer, a first semiconductor layer, a first insulating layer, a second insulating layer, and a liquid crystal element. The first insulating layer has an island-like shape and includes a first surface that is part of its side surface and located on the first conductive layer. The first semiconductor layer has a first portion contacting the top surface of the first conductive layer, a third portion contacting the first surface of the first insulating layer, and an eighth portion located on the first insulating layer. The second insulating layer covers the third portion of the first semiconductor layer. The third conductive layer covers the third portion of the first semiconductor layer through the second insulating layer. The liquid crystal element includes a portion of the first semiconductor layer, liquid crystal, and a fifth conductive layer. The liquid crystal is located on the first semiconductor layer. A portion of the first semiconductor layer is used as a pixel electrode. The fifth conductive layer is used as a common electrode.

[0020] In the above structure, the first semiconductor layer preferably has a ninth portion that does not overlap with the first insulating layer, and this ninth portion is preferably used as a pixel electrode.

[0021] Invention Effects According to one aspect of the present invention, a transistor capable of miniaturization can be provided. Furthermore, a transistor with good electrical characteristics can be provided. Additionally, a transistor with a short channel length can be provided. Furthermore, a transistor with a small footprint can be provided.

[0022] According to one aspect of the present invention, a liquid crystal display device with a high aperture ratio can be provided. Additionally, a liquid crystal display device with high resolution can be provided. Furthermore, a liquid crystal display device with low power consumption can be provided. Furthermore, a liquid crystal display device capable of high-speed driving can be provided. Additionally, a display device with high display quality can be provided.

[0023] According to one aspect of the present invention, a transistor, display device, electronic device, etc., with a novel structure can be provided. According to one aspect of the present invention, a transistor, display device, electronic device, etc., with high reliability can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be improved.

[0024] Note that the description of these effects does not preclude the existence of other effects. Also note that one embodiment of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the description, drawings, claims, etc.

[0025] Brief description of the attached figures Figures 1A to 1C This is an example of the structure of a semiconductor device. Figures 2A to 2C This is an example of the structure of a semiconductor device. Figure 3A and Figure 3B This is an example of the structure of a semiconductor device. Figures 4A to 4E This is an example of the structure of a semiconductor device. Figures 5A to 5D2 This is an example of the structure of a semiconductor device. Figures 6A to 6E This is an example of the structure of a semiconductor device. Figures 7A to 7D This is an example of the structure of a semiconductor device. Figures 8A to 8D This is a diagram illustrating the manufacturing process of a semiconductor device. Figures 9A to 9C This is a diagram illustrating the manufacturing process of a semiconductor device. Figure 10A and Figure 10B This is an example of the structure of a display device. Figure 11A and Figure 11B This is an example of the structure of a display device. Figure 12A and Figure 12B This is an example of the structure of a display device. Figure 13A and Figure 13B This is an example of the structure of a display device. Figure 14A and Figure 14B This is an example of the structure of a display device. Figure 15A and Figure 15B This is an example of the structure of a display device. Figure 16A and Figure 16B This is an example of the structure of a display device. Figure 17A and Figure 17B This is an example of the structure of a display device. Figures 18A to 18C This is an example of the structure of a display device. Figure 19A , Figure 19C , Figure 19D This is a circuit diagram of the display device. Figure 19B It is a timing diagram. Figure 20 This is a block diagram of the touch panel module. Figures 21A to 21C This is a structural example of a touch panel module. Figures 22A to 22F This is an example of the structure of an electronic device. Figures 23A to 23G This is an example of the structure of an electronic device.

[0026] Methods of implementing the invention The embodiments will now be described with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0027] Note that in the structure of the invention described below, the same reference numerals are used across different figures to denote the same parts or parts having the same function, without omitting repeated descriptions. Furthermore, when denoteing parts with the same function, the same shading lines are sometimes used without additional reference numerals.

[0028] Note that in the various figures described in this specification, the size of the constituent elements, the thickness of the layers, and the area are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the figures.

[0029] The ordinal numbers such as "first" and "second" used in this specification are appended to avoid confusion of the constituent elements, and are not intended to limit the quantity.

[0030] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0031] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be used interchangeably.

[0032] Furthermore, in this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, there are no particular limitations on what constitutes an "element that has a certain electrical function," as long as it allows for the transmission and reception of electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0033] Note that in this specification, "electrical connection" does not include the case where two nodes are connected through insulators such as the dielectric of a capacitor, the gate insulating film of a transistor, and the interlayer insulating film.

[0034] Note that in this specification, the top surface shape of a constituent element refers to the edge shape of the constituent element when viewed from a plane. Furthermore, "viewed from a plane" means the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0035] In this specification, "generally consistent top surface shape" means that at least a portion of the edges of each layer in the stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, in reality, there are cases where the edges do not overlap, and sometimes the upper layer is located inside or outside the lower layer; in such cases, it can also be said that the "top surface shape is generally consistent".

[0036] In this specification and other materials, the terms "film" and "layer" may be interchanged. For example, sometimes "insulating layer" and "insulating film" may be interchanged.

[0037] (Implementation Method 1) This embodiment describes a structural example of a semiconductor device according to one aspect of the present invention. Hereinafter, a structural example of a transistor will be described as an example of a semiconductor device.

[0038] One embodiment of the transistor of the present invention includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The first electrode serves as one of a source electrode and a drain electrode, and the second electrode serves as the other of a source electrode and a drain electrode.

[0039] The transistor is disposed in a region including an end of an insulating layer configured as an island. More specifically, an insulating layer is disposed to cover a portion of a first electrode, and a second electrode is disposed on the insulating layer. Furthermore, the semiconductor layer has a portion contacting the top surface of the first electrode, a portion contacting the top surface of the second electrode, and a portion disposed along the side surface of the insulating layer. Additionally, a gate insulating layer is disposed to cover the aforementioned portion of the semiconductor layer disposed along the side surface of the insulating layer, and a gate electrode is disposed to cover the gate insulating layer.

[0040] In addition, the first electrode and the second electrode can be electrodes different from the semiconductor layer, and a portion of the semiconductor layer can also be used as the first electrode or the second electrode.

[0041] In a transistor with the above structure, the source and drain electrodes are located at different heights, so the current flowing through the semiconductor layer flows in the height direction. That is to say, it can be said that the channel length direction has a height (vertical) component, so the transistor of one aspect of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc.

[0042] Because the source electrode, semiconductor layer, and drain electrode can be arranged overlapping each other in the above transistors, the occupied area can be significantly reduced compared to so-called planar transistors (also known as lateral transistors, LFETs, etc.) where the semiconductor layer is arranged on a plane.

[0043] Furthermore, the semiconductor layer of the transistor is preferably disposed in two or more regions on the surface of the insulating layer, which serves as a spacer, where the normal directions are different from each other. As a specific example, the semiconductor layer can be disposed across two or more adjacent planes or along a portion having a curved shape. Thus, by disposing the semiconductor layer not only along one plane of the insulating layer but also along two or more planes or curved surfaces, the channel width can be increased while suppressing the increase in the transistor's occupied area. In other words, a miniature transistor with a large on-state current can be realized.

[0044] Furthermore, since the channel length of the transistor can be precisely controlled by the thickness of the insulating layer, the non-uniformity of the channel length can be minimized compared to planar transistors. Moreover, by thinning the insulating layer, transistors with extremely small channel lengths can be manufactured. For example, transistors with channel lengths of less than 2μm, less than 1μm, less than 500nm, less than 300nm, less than 200nm, less than 100nm, less than 50nm, less than 30nm, or less than 20nm but greater than 5nm, greater than 7nm, or greater than 10nm can be manufactured. Thus, transistors with extremely small channel lengths that cannot be achieved by existing mass production exposure equipment for flat panel displays (e.g., minimum linewidths of approximately 2μm or 1.5μm) can be realized. Furthermore, transistors with channel lengths less than 10nm can be achieved without using the very expensive exposure equipment used in the most advanced LSI technology.

[0045] Metal oxide (also known as oxide semiconductor) films with semiconductor properties are particularly preferred as semiconductor layers, thereby achieving both high performance and high productivity. In particular, crystalline oxide semiconductor films are more preferred, thereby enabling semiconductor layers to have high reliability.

[0046] The following illustrations provide more specific examples.

[0047] [Structure Example] Figure 1A This is a top view schematic diagram of a semiconductor device including transistor 10. Additionally, Figure 1B Showing the corresponding Figure 1A A schematic diagram of the cross-section of the cut-off line A1-A2 in the diagram. Figure 1C A schematic diagram of the cross section corresponding to the cut-off line B1-B2 is shown. Figure 2A This is a three-dimensional schematic diagram of transistor 10. Note that in the top view, some components (such as insulating layers) are not shown for ease of viewing.

[0048] Transistor 10 is disposed on insulating layer 11 on substrate (not shown). Transistor 10 includes semiconductor layer 21, insulating layer 22 serving as gate insulating layer, conductive layer 23 serving as gate electrode, conductive layer 24 serving as one of source electrode and drain electrode, and conductive layer 25 serving as the other of source electrode and drain electrode. Note that insulating layer 11 may be omitted if not required.

[0049] A conductive layer 24 is disposed on an insulating layer 11, and an insulating layer 41 is disposed to cover a portion of the conductive layer 24. The insulating layer 41 serves as a spacer and has an island-like shape. A conductive layer 25 is disposed on the insulating layer 41. The semiconductor layer 21 has a portion that contacts the top surface of the conductive layer 24, a portion that contacts the top surface of the conductive layer 25, a portion that contacts the side surface of the conductive layer 25, and a portion disposed along the side surface of the insulating layer 41. Here, an example is shown where the semiconductor layer 21 is disposed to contact the side surface of the insulating layer 41. In addition, the insulating layer 22 is disposed to at least cover the portion of the semiconductor layer 21 disposed along the side surface of the insulating layer 41. The insulating layer 22 covers not only the semiconductor layer 21 but also a portion of the top surface of the conductive layer 25, a portion of the side surface of the insulating layer 41 where the semiconductor layer 21 is not disposed, etc. The conductive layer 23 is disposed to at least cover the portion of the semiconductor layer 21 disposed along the side surface of the insulating layer 41, separated by the insulating layer 22. Here, an example is shown where the conductive layer 23 and the insulating layer 22 are formed with substantially the same top surface shape.

[0050] Additionally, an example is shown here where the conductive layer 25 and the insulating layer 41 are formed in a manner with substantially the same top surface shape. For example, since the conductive layer 25 and the insulating layer 41 can be formed using the same photoresist mask, the manufacturing process of the transistor 10 can be simplified.

[0051] The insulating layer 41 serves as an interlayer insulating film or spacer that insulates the conductive layer 24 from the conductive layer 25. Here, an example is shown where the side surface of the insulating layer 41 is substantially perpendicular to the surface to which it is formed (the top surface of the insulating layer 11 or the conductive layer 24), but this is not a limitation. For example, the side surface of the insulating layer 41 may also have a tapered shape. For example, the angle formed by the side surface of the insulating layer 41 and the surface to which it is formed may be 45 degrees or more and 90 degrees or less, preferably 60 degrees or more and 90 degrees or less, more preferably 75 degrees or more and 90 degrees or less. This angle may also be greater than 90 degrees, but it is preferred when it is less than 90 degrees as this improves the coverage of the semiconductor layer 21, the insulating layer 22, etc. When the angle formed by the side surface of the insulating layer 41 and the surface to which it is formed is 90 degrees, the thickness of the insulating layer 41 is consistent with the channel length of the transistor 10.

[0052] Semiconductor layer 21 can be made of various semiconductor materials, with oxide semiconductors, including metal oxides, being particularly preferred. By using oxide semiconductors formed under appropriate conditions, transistors with both large on-state current and extremely small off-state current can be realized at low cost. Below, unless otherwise specified, preferred structural examples of using oxide semiconductors for semiconductor layer 21 will be described.

[0053] The conductive layers 24 and 25 each have a structure in which their respective top surfaces are in contact with the semiconductor layer 21. Therefore, when the semiconductor layer 21 uses an oxide semiconductor, the following concern arises: due to heat or other factors during or after the deposition process of the semiconductor film that will become the semiconductor layer 21, the surfaces of the conductive layers 24 and 25 may be oxidized, forming an insulating oxide film between the conductive layers 24 and 25 and the semiconductor layer 21, thus increasing the contact resistance.

[0054] Therefore, at least the uppermost portion of conductive layer 24 and conductive layer 25 is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material. In particular, an oxide conductor containing a conductive oxide is preferred. This prevents an increase in contact resistance caused by surface oxidation of conductive layer 24 and conductive layer 25.

[0055] A portion of conductive layer 24 can be used as one of the source wiring and drain wiring. Similarly, a portion of conductive layer 25 can be used as the other of the source wiring and drain wiring. When one or both of conductive layers 24 and 25 are used for wiring, the resistance is preferably low. Therefore, it is preferable to use materials with higher conductivity than oxide conductors, such as metals, alloys, or their nitrides. In particular, a laminated structure comprising layers of this highly conductive material is preferably used as one or both of conductive layers 24 and 25, and preferably, at least the uppermost layer uses the aforementioned oxide conductor.

[0056] Figure 2B From Figure 2A The 3D view shown is a 3D view with the conductive layer 23 and insulating layer 22 removed. For example... Figure 2B As shown, the semiconductor layer 21 is disposed in such a manner that it covers the entire corner of the insulating layer 41 and the conductive layer 25. The portion of the semiconductor layer 21 disposed along the side of the insulating layer 41 is used as the channel formation region of the transistor 10. Furthermore, the width of the portion of the semiconductor layer 21 disposed along the insulating layer 41 in the direction orthogonal to the height direction is the channel width of the transistor 10. Figure 2B The channel width direction is indicated by a dashed arrow. Therefore, in this structural example, by utilizing the corner of the insulating layer 41, the area occupied by the transistor 10 under the condition of the same channel width can be smaller than that of the case where the semiconductor layer 21 is only provided on the plane of the side of the insulating layer 41.

[0057] Figure 2C From Figure 2B The perspective view shown is a perspective view with the semiconductor layer 21 removed. The area R on the side of the insulating layer 41 that contacts the semiconductor layer 21 is shaded. In addition, the area of ​​the conductive layer 25 that contacts the semiconductor layer 21 is shown in dashed lines.

[0058] The semiconductor layer 21 is preferably disposed across two or more regions with different normal directions in the side surface of the insulating layer 41. Figure 2C An example is shown where the side of the insulating layer 41 has two adjacent planes. Figure 2C The diagram shows points P and Q, encompassed by one surface and the other surface of two planes in region R. Furthermore, the normal vector n1 at point P and the normal vector n2 at point Q show different directions. When the two planes are orthogonal, the two normal vectors (normal vector n1 and normal vector n2) are also orthogonal. For example, the corner of insulating layer 41 refers to the boundary portion between the surface encompassing point P and the surface encompassing point Q. Figure 2C An example is shown where the corner of the insulating layer 41 is right-angled when viewed from a plane (i.e., the plane including point P is orthogonal to the plane including point Q). Note that, as shown later, the corner of the insulating layer 41 can also be a curved surface.

[0059] By employing the above structure, miniature transistors capable of carrying large currents can be realized. By using such transistors in the pixel circuits of display devices, display devices with extremely high resolution can be achieved. Furthermore, since the area occupied by the transistors used for pixels can be reduced, display devices with a high aperture ratio can be realized.

[0060] Figure 3A This is a variation of the above structure. The example shown above illustrates an example where the insulating layer 22 and the conductive layer 23 are processed in a manner whose top surface shapes are substantially identical; however, Figure 3 shows an example without this processing. The insulating layer 22 covers the conductive layer 25 in areas where the conductive layer 23 is not provided. Furthermore, although not shown here, the insulating layer 22 may also cover the insulating layer 41, the conductive layer 24, and the insulating layer 11, etc., in areas where the conductive layer 23 is not provided.

[0061] in addition, Figure 3B The example shown illustrates an example where the insulating layer 41 has a stacked structure in which insulating layers 41a, 41b, and 41c are stacked sequentially from one side of the insulating layer 11.

[0062] The semiconductor layer 21 is disposed in contact with the side of the insulating layer 41b. The insulating layer 41b is preferably an oxide insulating film. In particular, an oxide insulating film that releases oxygen upon heating is preferred. Furthermore, an insulating layer 41c that has oxygen-blocking properties (oxygen barrier properties) is preferably disposed on the insulating layer 41b. For example, as the insulating layer 41c, a film with a lower oxygen diffusion coefficient (less oxygen diffusion coefficient) compared to the insulating layer 41b is preferred. This prevents most of the oxygen contained in the insulating layer 41b from diffusing to the outside, thus preventing insufficient oxygen supply to the semiconductor layer 21. Moreover, the insulating layer 41b is preferably sandwiched between the oxygen-blocking insulating layers 41a and 41c. This confines the oxygen contained in the insulating layer 41b within the area surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21, preventing the oxygen in the insulating layer 41b from escaping and decreasing during processing, thereby allowing for more efficient oxygen supply to the semiconductor layer 21.

[0063] Silicon oxide or silicon oxynitride are typical examples of oxide insulating films that release oxygen upon heating.

[0064] As an insulating film with oxygen barrier properties, oxides, nitrides, or oxynitrides of silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium aluminate, yttrium oxide, yttrium oxynitride, gallium oxide, gallium-zinc oxide, etc., are preferred. In particular, the use of silicon nitride and aluminum oxide can achieve films with high oxygen barrier properties at low cost, and therefore are preferred.

[0065] The portion of semiconductor layer 21 that contacts insulating layer 41b is a region where oxygen vacancies are reduced, which can be considered an i-type region. On the other hand, the portion that does not contact insulating layer 41b is preferably an n-type region containing multiple charge carriers. For example, the portion of semiconductor layer 21 that contacts insulating layer 41b can be referred to as a channel forming region, and the region outside of this channel forming region can be referred to as a low-resistance region (also called a source region or drain region).

[0066] Next, the shape of each component of transistor 10 when viewed from a plane and the positional relationship of each component will be explained.

[0067] Figure 4A A top view schematic diagram of the transistor described below is shown. Here, for ease of understanding of the positional relationship between conductive layer 24, conductive layer 25, insulating layer 41, and semiconductor layer 21, conductive layer 23 and insulating layer 22 are omitted. Furthermore, in Figure 4A In the diagram, region 21AC, which serves as the channel forming region, is surrounded by a dashed line. More specifically, region 21AC refers to the area at the end of the insulating layer 41 and the conductive layer 25 that overlaps with the semiconductor layer 21.

[0068] Note that, including Figure 4AIn the following top view diagram, the insulating layer 22 and the conductive layer 23 are provided to at least cover the region 21AC, which serves as the channel forming region of the semiconductor layer 21, and the other regions can have any shape.

[0069] In addition, including Figure 4A The following top view shows an example where the top surface shape of the insulating layer 41 is substantially the same as the top surface shape of the conductive layer 25, but is not limited thereto. The insulating layer 41 may have areas not covered by the conductive layer 25, and the conductive layer 25 may also have portions extending beyond the edge of the insulating layer 41.

[0070] Furthermore, in including Figure 4A In the following top view diagram, to easily distinguish between conductive layer 24 and conductive layer 25, only the shaded line of conductive layer 24 is shown. Figure 1B The cross-sectional diagrams shown are different.

[0071] Although Figure 1A Examples are shown where the semiconductor layer 21 is disposed in such a way that it covers the entire top surface of the conductive layer 24, but the invention is not limited thereto. Figure 4A The top view schematic diagram shows an example where the semiconductor layer 21 covers a portion of the conductive layer 24. The conductive layer 24 has areas that are not covered by the semiconductor layer 21.

[0072] Figure 4B An example is shown where the semiconductor layer 21 is located inside the end of the conductive layer 24. In the region where the conductive layer 24 and the conductive layer 25 overlap via the insulating layer 41, there is a portion that does not overlap with the semiconductor layer 21. Thus, by simply changing the shape of the semiconductor layer 21, transistors with different channel widths can be fabricated.

[0073] Figure 4C An example is shown where the semiconductor layer 21 has a region that does not overlap with both the conductive layers 24 and 25. Therefore, the entire region on the side of the insulating layer 41 that overlaps with the conductive layer 24, as well as the region that overlaps with the semiconductor layer 21 but not with the conductive layer 24, can be used as region 21AC, thus enabling the realization of a transistor with a large channel width.

[0074] Figure 4D An example is shown where the semiconductor layer 21 is rectangular when viewed from a plane. In this case, the areas of the two planes overlapping the semiconductor layer 21 on the side of the insulating layer 41 are different. Thus, the shape of the semiconductor layer 21 is not limited to a square; it can also be a rectangle with a large aspect ratio. By making the semiconductor layer 21 different, transistors of various shapes can be manufactured, thus increasing the degree of design freedom.

[0075] Figure 4EAn example is shown in which the corners of each component are not square but curved. At this time, since the semiconductor layer 21 is provided along the curved portion of the side surface of the insulating layer 41, the region 21AC also has a portion that is circular arc-shaped when viewed from the plane. By making the side surface of the insulating layer 41 where the region 21AC is provided have a curved surface, the gate electric field applied to the semiconductor layer 21 is averaged, and thus a highly reliable transistor can be realized.

[0076] The example in which the semiconductor layer 21 is provided in the region including one corner of the side surface of the insulating layer 41 is shown above, and different examples will be described below.

[0077] Figure 5A An example is shown in which the semiconductor layer 21 is provided so as to cover two corners of the insulating layer 41. The region 21AC has a "匚" - shaped (bracket - shaped) form. Additionally, Figure 5B An example is shown in which the semiconductor layer 21 is provided so as to cover three convex surfaces and one concave surface of the side surface of the insulating layer 41. The larger the area of the side surface of the insulating layer 41 covered by the semiconductor layer 21, the larger the channel width of the transistor that can be formed. Additionally, the larger the number of corners of the insulating layer 41 in the region covered by the semiconductor layer 21, the larger the area of the side surface of the insulating layer 41 covered by the semiconductor layer 21. The shape of the region of the insulating layer 41 covered by the semiconductor layer 21 can be various shapes. For example, it can be a square, a rectangle, a circle, an ellipse, or a quadrangle with rounded corners, etc. In addition, regular polygons such as an equilateral triangle or a regular pentagon, and polygons other than regular polygons can also be used. Additionally, in the case of a concave polygon such as a star - shaped polygon where at least one interior angle exceeds 180 degrees, the channel width can be increased. Additionally, polygons with rounded corners, curves combining straight lines and curves, etc. can also be used.

[0078] Figure 5C1 An example is shown in which the insulating layer 41 and the conductive layer 25 have a shape combining a circular part and a rectangular part when viewed from the plane. Additionally, in Figure 5C2 only the edge of the semiconductor layer 21 is shown by a dotted line. The semiconductor layer 21 is provided so as to cover the circular part and a pair of straight parts of the side surface of the insulating layer 41 when viewed from the plane. Therefore, the region 21AC has an arc - shaped part and a pair of straight - shaped parts. By adopting the above - mentioned shape, a transistor with a large channel width while reducing the occupied area can be realized.

[0079] Figure 5D1 and Figure 5D2 An example is shown in which the insulating layer 41 and the conductive layer 25 have an annular part when viewed from the plane. In Figure 5D2 only the edge of the semiconductor layer 21 is shown by a dotted line. As Figure 5D2As shown, the circular portions of the insulating layer 41 and the conductive layer 25 are provided with circular openings reaching the conductive layer 24. The semiconductor layer 21 is provided such that it covers the side surface of the opening in the insulating layer 41. By adopting the above structure, a channel forming region can be formed not only in the outer edge of the insulating layer 41 but also on the side surface of the opening, thus achieving a channel width ratio... Figure 5C1 The example shown is a large transistor.

[0080] The example above shows a transistor using a single semiconductor layer; the example below illustrates the use of multiple semiconductor layers.

[0081] Figure 6A The diagram shows a structure comprising two semiconductor layers 21a and 21b. Semiconductor layers 21a and 21b are provided such that they respectively cover each of the two corners of the insulating layer 41 that overlap with the conductive layer 24. This forms two transistors: transistor 10a comprising semiconductor layer 21a and transistor 10b comprising semiconductor layer 21b. Transistor 10a and transistor 10b share a source electrode and a drain electrode. Furthermore, transistor 10a and transistor 10b may share a common gate electrode or may have separate gate electrodes.

[0082] Figure 6D Showing the corresponding Figure 6A The circuit diagram is shown here. An example is shown where transistors 10a and 10b share a gate electrode. Thus, Figure 6A The structure shown has two transistors connected in parallel.

[0083] Figure 6B The structure includes three semiconductor layers 21a, 21b, and 21c. Additionally, the insulating layer 41 and the conductive layer 25 have two protruding portions (parts 41p and 41q) when viewed from a planar perspective. Parts 41p and 41q each have a region overlapping with the conductive layer 24. Semiconductor layers 21a and 21b are provided such that they cover each of the two corners of part 41p, and semiconductor layers 21b and 21c are provided such that they cover each of the two corners of part 41q. Thus, transistors 10a, 10b, 10c, and 10d are formed, each having one of semiconductor layers 21a, 21b, and 21c. Transistors 10b and 10c share semiconductor layer 21b. The source and drain electrodes of the four transistors are common. In the four transistors, a common gate electrode can be provided for two or more transistors, or separate gate electrodes can be provided.

[0084] Figure 6E Showing the corresponding Figure 6B The circuit diagram is shown here. An example is shown where four transistors share a gate electrode. (Example follows) Figure 6E As shown, Figure 6B The structure shown has four transistors connected in parallel.

[0085] Figure 6C yes Figure 6B Examples of variations. Figure 6C The diagram shows a structure comprising four semiconductor layers (semiconductor layers 21a, 21b, 21c and 21d) and including transistors 10a, 10b, 10c and 10d, each having one of them. Figure 6C Examples are shown where the portions (parts 41p, 41q) of the conductive layer 25 and insulating layer 41 do not protrude.

[0086] The conductive layer 25 and the insulating layer 41 have regions overlapping with the conductive layer 24. The outermost semiconductor layers 21a and 21d of the four semiconductor layers are arranged to cover one of the two corners of the insulating layer 41 that overlap with the conductive layer 24. Furthermore, semiconductor layers 21b and 21c are arranged to cover the sides of the insulating layer 41 that overlap with the conductive layer 24, respectively. The sides of the insulating layer 41 covered by semiconductor layers 21b and 21c are approximately planar.

[0087] Note that the semiconductor layers 21a to 21d have the same shape, and the channel widths of transistors 10a and 10d are larger than those of transistors 10b and 10c, but this is not a limitation. By adjusting the shape of semiconductor layers 21a to 21d, the channel widths of the four transistors can also be made approximately the same.

[0088] The above shows an example of multiple transistors connected in parallel; the following describes an example of multiple transistors connected in series.

[0089] Figure 7A The structure shown is an example that includes two conductive layers (conductive layers 24a, 24b) below the insulating layer 41, but excludes the conductive layer 24, and includes two semiconductor layers (semiconductor layer 21a, semiconductor layer 21b). Figure 7A In this configuration, one corner of the insulating layer 41 and the conductive layer 25 overlaps with the conductive layer 24a and the semiconductor layer 21a, while the other corner overlaps with the conductive layer 24b and the semiconductor layer 21b. This forms a transistor 10a including the semiconductor layer 21a and a transistor 10b including the semiconductor layer 21b. Transistors 10a and 10b share one of their source and drain electrodes, while the other of the source and drain electrodes is provided independently. Transistors 10a and 10b may share a common gate electrode or have separate, independent gate electrodes.

[0090] Figure 7C , Figure 7D All correspond to Figure 7A The circuit diagram. Figure 7CThis illustrates a case where two transistors share a common gate electrode. Figure 7D This illustrates the case where the gate electrode is independently configured. For example... Figure 7C and Figure 7D As shown, transistors 10a and 10b are connected in series.

[0091] Notice, Figure 7A An example is shown that includes two semiconductor layers, 21a and 21b, but they can also be combined into a single semiconductor layer.

[0092] Figure 7B yes Figure 7A Examples of variations. In Figure 7B In this structure, two adjacent corners of the insulating layer 41 and conductive layer 25 overlap with the semiconductor layer 21a and conductive layer 24a, while the other two corners overlap with the semiconductor layer 21b and conductive layer 24b. By employing this structure, [the structure is compatible with...]. Figure 7A Compared to the example shown, the area occupied can be reduced.

[0093] In addition, Figure 7B In the structure shown, semiconductor layer 21a and semiconductor layer 21b can also be a single semiconductor layer. By adopting this structure, the distance between transistors can be reduced compared to using two island-shaped semiconductor layers, thus further reducing the occupied area.

[0094] [Components] <Substrate> Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can also be used. Furthermore, examples include substrates with conductive or semiconductor layers on insulating substrates, substrates with conductive or insulating layers on semiconductor substrates, and substrates with semiconductor or insulating layers on conductive substrates. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements (including transistors), light-emitting elements, and memory elements.

[0095] <Semiconductor layer> Semiconductor layer 21 preferably comprises metal oxide (oxide semiconductor).

[0096] Examples of metal oxides that can be used in semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In, Zn, Sn, or Al, and more preferably In or Zn.

[0097] Furthermore, the metal oxide preferably contains two or three elements selected from In, element M, and Zn. For example, In-M-Zn oxide, In-Zn oxide, In-M oxide, or M-Zn oxide can be used. Note that element M is a metallic or half-metallic element with a high bonding energy with oxygen, such as a metallic or half-metallic element with a higher bonding energy with oxygen than indium. Examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The metal oxide preferably contains one or more of the above elements, and particularly preferably contains one or more elements selected from Al, Ga, Y, and Sn. Here, in this specification, etc., "metallic element" sometimes includes half-metallic elements.

[0098] The atomic ratio of In in In-M-Zn oxides is preferably greater than or equal to the atomic ratio of M. Increasing the atomic ratio of indium in the metal oxide can improve the on-state current or field-effect mobility of transistors. Examples of suitable atomic ratios for the metal elements in In-M-Zn oxides include In:M:Zn ratios of 1:1:1, 1:1:1.2, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, 5:1:3, and 5:1:6, as well as compositions close to these ratios. Note that "close to" compositions include a range of ±30% of the desired atomic ratio.

[0099] In In-M-Zn oxides, the atomic ratio of In can also be less than the atomic ratio of element M. By increasing the atomic ratio of M in the metal oxide, the formation of oxygen vacancies can be suppressed. For example, examples of In:M:Zn atomic ratios of 1:3:2, 1:3:3, and 1:3:4, as well as compositions with ratios close to these, can be cited as In-M:Zn oxides.

[0100] The semiconductor layer 21 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-W oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-W-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. Furthermore, as oxides that do not contain In, Ga oxide, Zn oxide, Ga-Zn oxide, Ga-Sn oxide, Al-Zn oxide, Al-Sn oxide, etc., can also be used. Using a Zn-free material such as indium oxide improves the affinity with the LSI manufacturing process, and is therefore preferred. On the other hand, using a Zn-containing material easily improves crystallinity, and is therefore preferred.

[0101] In addition, metal oxides can replace indium or contain metal elements with larger atomic numbers other than indium. Since the greater the overlap of the orbitals of the metal element, the greater the carrier conduction in the metal oxide, the field-effect mobility of the transistor can sometimes be improved when the metal oxide contains metal elements with larger atomic numbers. For example, one or more metal elements belonging to the 5th period and the 6th period can be used. Specifically, examples include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu.

[0102] Furthermore, metal oxides can also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved. Examples include C, N, P, S, Se, F, Cl, Br, and H.

[0103] Elements that contribute to improved conductivity, such as In, show higher concentrations, resulting in higher mobility and conductivity. Examples of high-mobility materials include oxides with atomic ratios of In:Ga:Zn = 4:3:2, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:1:10, In:Sn:Zn = 20:1:10, In:Sn = 95:5, In:Sn = 90:10, and similar ratios. Conversely, materials with lower mobility than the aforementioned materials include oxides with atomic ratios of In:Ga:Zn = 1:3:2, 1:3:4, 2:2:1, 1:1:1, 1:1:2, or similar ratios.

[0104] Metal oxides can be formed using sputtering or ALD (Alternating Discharge) methods. Sputtering is preferred because it reduces impurity concentration. Furthermore, ALD offers excellent coverage, making it a preferred method. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. In particular, the zinc content in the deposited metal oxide can sometimes decrease to about 50% of the zinc content in the target material.

[0105] In this specification, the content of a certain metal element in a metal oxide refers to the proportion of the number of atoms of that element relative to the total number of atoms of the metal element contained in the metal oxide. For example, in a metal oxide containing metal element X, metal element Y, and metal element Z, the number of atoms of each of metal element X, metal element Y, and metal element Z contained in the metal oxide is A. X A Y A Z When the content of metallic element X is such that it can be expressed as A, the percentage of X in the composition of metal can be expressed as A. X / (A X +A Y +A Z Furthermore, the ratio of the number of atoms of metal elements X, Y, and Z in a metal oxide (atomic ratio) is expressed as B. X B Y B Z When the content of metallic element X is such that B is used, the percentage of X can be expressed as B. X / (B) X +B Y +B Z ).

[0106] For example, when using metal oxides containing In, transistors with high on-state current can be achieved by increasing the In content.

[0107] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability under forward bias can be realized. That is, a transistor with small fluctuations in the threshold voltage during PBTS (Positive Bias Temperature Stress) testing can be achieved. Furthermore, when using a Ga-containing metal oxide, the Ga content is preferably lower than the In content. Thus, a transistor with both high mobility and high reliability can be realized.

[0108] On the other hand, by increasing the Ga content, transistors with high reliability for light can be achieved. In other words, transistors with small threshold voltage variations during NBTIS (Negative Bias Temperature Illumination Stress) testing can be realized. Specifically, the band gap of metal oxides with a higher Ga atom count than those with a higher In atom count can be larger, thus reducing the threshold voltage variation during NBTIS testing of the transistor.

[0109] Furthermore, by increasing the zinc content to create a highly crystalline metal oxide, the diffusion of impurities in the metal oxide can be suppressed. This suppresses variations in the electrical characteristics of the transistor, thereby improving reliability.

[0110] Semiconductor layer 21 may also have a stacked structure comprising two or more metal oxides. The compositions of the two or more metal oxides contained in semiconductor layer 21 may be the same or substantially the same. By employing a stacked structure of metal oxides with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs. Note that a stacked structure of two or more metal oxides with different compositions can also be used. Furthermore, by utilizing the ALD method, metal oxides whose composition continuously varies in the thickness direction can be formed. Therefore, compared to using a film with a predetermined composition, not only can the range of design choices be expanded, but the formation of interface states, etc., between two layers with different compositions can also be prevented, thus improving electrical characteristics and reliability.

[0111] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (high conductivity) than the first layer in the second layer, i.e., the layer closest to the gate electrode. This allows for the formation of a normally-off transistor with a large on-state current. Therefore, both low power consumption and high performance can be achieved. Alternatively, a material with higher mobility than the second layer can also be used in the first layer, i.e., the layer in contact with the source and drain electrodes. This reduces the contact resistance between the semiconductor layer 21 and the source or drain electrode, thereby reducing parasitic resistance and allowing for the formation of a transistor with a large on-state current.

[0112] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material in the second layer with a higher mobility than the first and third layers. This allows for the realization of transistors with high on-state current and high reliability.

[0113] When the semiconductor layer 21 has a stacked structure, all layers can be deposited using the same deposition method, or different deposition methods can be combined. For example, sputtering and ALD methods can be combined to form the semiconductor layer 21 with a stacked structure. Here, in deposition methods such as sputtering, a mixed layer (also called mixing) is sometimes formed at the interface between the semiconductor layer and the surface to be formed. Therefore, by using ALD to deposit the first layer to suppress mixing and using sputtering to deposit the second layer to deposit a highly crystalline film, a transistor with both high reliability and high electrical characteristics can be realized. Furthermore, a three-layer structure using ALD to deposit the third layer can also be used. In addition, it is preferable to perform heat treatment after depositing the stacked film using a combination of ALD and sputtering methods. As a result, crystal growth sometimes occurs from the sputtered layer to the ALD-deposited layer, thereby forming a highly crystalline semiconductor layer as the entire stacked film.

[0114] Furthermore, when the semiconductor layer 21 adopts a stacked structure, a high-mobility material can be used on the side that contacts the source and drain electrodes. This reduces the contact resistance between the semiconductor layer 21 and the source or drain electrodes, thereby enabling the realization of a transistor with a large on-state current. In particular, in bottom contact structures (structures where semiconductor layers are disposed on the source and drain electrodes), the aforementioned contact resistance is sometimes higher compared to top contact structures (structures where source and drain electrodes are disposed on the semiconductor layer). Therefore, it is preferable to use a high-mobility material on the side that contacts the source and drain electrodes.

[0115] A crystalline metal oxide layer is preferably used as the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nano-crystal (nc) structure can be used. By using a crystalline metal oxide layer as the semiconductor layer 21, the defect state density in the semiconductor layer 21 can be reduced, thereby enabling a highly reliable semiconductor device.

[0116] The higher the crystallinity of the metal oxide layer used for semiconductor layer 21, the lower the defect state density in semiconductor layer 21 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0117] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field-effect mobility. Furthermore, the source-drain leakage current (hereinafter also called off-state current) of an OS transistor in the off state is extremely small, allowing it to retain the charge stored in the capacitor connected in series with the transistor for extended periods. In addition, the power consumption of semiconductor devices can be reduced by using OS transistors.

[0118] One aspect of the semiconductor device of the present invention can be used, for example, in a display device that uses a display element as a display element. When increasing the luminous brightness of the light-emitting element included in the pixel circuit of the display device, it is necessary to increase the current flowing through the light-emitting element. For this purpose, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Because the source-drain breakdown voltage of an OS transistor is higher than that of a silicon transistor (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, the luminous brightness of the light-emitting element can be increased by increasing the current flowing through it.

[0119] When operating in the saturation region, OS transistors, compared to Si transistors, allow for smaller changes in source-drain current in response to variations in the gate-source voltage. Therefore, by using OS transistors as driving transistors included in pixel circuits, the amount of current flowing through the light-emitting element can be precisely controlled. This allows for an increase in the grayscale of the pixel circuit. Furthermore, even with variations in the electrical characteristics of the light-emitting element (e.g., resistance) or non-uniformity in these characteristics, a stable current can still flow.

[0120] As described above, by using OS transistors as driving transistors included in pixel circuits, it is possible to achieve "suppression of black blur", "increase in light emission brightness", "multi-grayscale conversion", and "suppression of the effects of uneven manufacturing of light-emitting elements".

[0121] OS transistors exhibit minimal changes in electrical characteristics due to radiation exposure, meaning they possess high radiation tolerance and are suitable for environments where radiation exposure is possible. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be used in the pixel circuitry of X-ray flat panel detectors. Furthermore, OS transistors can be applied to semiconductor devices used in space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0122] Note that the semiconductor material that can be used in semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors composed of a single element or compound semiconductors can be used. Examples of semiconductors composed of a single element include Si (including single crystal, polycrystalline, microcrystalline, and amorphous) or Ge. Examples of compound semiconductors include GaAs and SiGe. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, or oxide semiconductors. These semiconductor materials may also contain impurities as dopants.

[0123] Alternatively, semiconductor layer 21 can also be made of a material with a layered crystalline structure. Materials with a layered crystalline structure exhibit high conductivity within their layers. Therefore, by using such a material with a layered crystalline structure in the channel formation region, a transistor with a large on-state current can be provided. Examples include graphene, silicene, and chalcogenides. Chalcogenides can be derived from transition elements such as Mo, W, Hf, or Zr. In this case, group 16 elements such as S, Se, and Te can be used as chalcogen elements.

[0124] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 21; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (polycrystalline semiconductors, microcrystalline semiconductors, or semiconductors in which a portion has crystalline regions) can be used. When using a crystalline semiconductor, the degradation of transistor characteristics can be suppressed, so it is preferred.

[0125] <Gate insulating layer> The insulating layer 22 is used as a gate insulating layer for a transistor, and can also be used as a dielectric layer for a capacitor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as the film in the insulating layer 22 that is at least in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used as the insulating layer 22. In addition, nitride insulating films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride can also be used as the insulating layer 22. Furthermore, the insulating layer 22 can also have a stacked structure, for example, it can have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0126] In this specification, etc., oxynitrides refer to materials with an oxygen content greater than a nitrogen content. Nitrogen oxides refer to materials with a nitrogen content greater than a oxygen content.

[0127] Furthermore, the insulating layer 22 is preferably made of an insulating material with a high relative permittivity (high-k), and preferably uses a laminate structure of a high-k material and a material with a dielectric strength greater than that high-k material. For example, as the insulating layer 22, an insulating film (also called ZAZ) sequentially laminated with zirconium oxide, alumina, and zirconium oxide can be used. Alternatively, an insulating film (also called ZAZA) sequentially laminated with zirconium oxide, alumina, zirconium oxide, and alumina can be used. Furthermore, an insulating film sequentially laminated with hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina can be used. By using an insulator with a high dielectric strength, such as alumina, the dielectric strength can be increased, thus suppressing electrostatic breakdown of the capacitor.

[0128] Furthermore, ferroelectric materials can also be used as the insulating layer 22. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X Metal oxides (where X is a real number greater than 0).

[0129] <Conductive Layer> Conductive layers 24 and 25 are in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, if a metal that is easily oxidized, such as aluminum, is used in the portion of conductive layer 24 or conductive layer 25 that is in contact with the semiconductor layer 21, insulating oxide (e.g., aluminum oxide) may form between the conductive layer 24 or conductive layer 25 and the semiconductor layer 21, potentially hindering their conduction. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material in at least the portion of conductive layer 24 and conductive layer 25 that is in contact with the semiconductor layer 21.

[0130] For example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferably used as conductive layers 24 and 25. The above materials are conductive materials that are not easily oxidized or that maintain conductivity even if oxidized, so they are preferred.

[0131] In addition, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. In particular, conductive oxides containing indium have high conductivity and are therefore preferred. Alternatively, the aforementioned oxide materials such as In-Ga-Zn oxide that can be used in semiconductor layer 21 can also be used in the conductive layer by increasing the carrier concentration.

[0132] For example, conductive layers 24 and 25 can be constructed using a single-layer structure of the conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and titanium nitride are stacked sequentially, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the conductive oxide film, or a two-layer structure in which the conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0133] The conductive layer 23 is used as the gate electrode, and various conductive materials can be used. For example, a metal element selected from Al, Cr, Cu, Ag, Pt, Ta, Ni, Ti, Mo, W, Hf, V, Nb, Mn, Mg, Zr, Be, In, Ru, Ir, Sr, La, etc., or an alloy containing that metal element, is preferably used as the conductive layer 23. Alternatively, nitrides or oxides of the aforementioned metals or alloys can be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0134] Alternatively, the conductive layer 23 may also use the nitrides and oxides that are applicable to the conductive layers 24 and 25 as described above.

[0135] Since conductive layers 23, 24, and 25 are also used for wiring, it is preferable to use a stack of low-resistance conductive materials. For example, the lower layer of conductive layers 24 and 25 may also use the low-resistance conductive material that can be used in conductive layer 23.

[0136] <Insulating layer> The insulating layer 41b can be used as an interlayer insulating film. For example, deposition methods such as sputtering or plasma CVD are preferred. In particular, when using sputtering, hydrogen gas is not required as the deposition gas, thereby achieving a film with extremely low hydrogen content. This suppresses the supply of hydrogen to the semiconductor layer 21, thus stabilizing the electrical characteristics of the transistor 10.

[0137] Since the insulating layer 41b contacts the channel formation region of the semiconductor layer 21, an oxide insulating film is preferably used. In particular, an oxide insulating film that releases oxygen upon heating is preferred. As the insulating layer 41b, the oxide insulating film described above, which can be used as a gate insulating layer, can be used.

[0138] Furthermore, since insulating layer 41b is used as an interlayer insulating layer, a deposition method that can be used at a higher deposition rate than other insulating layers is preferred. For example, as insulating layer 41, a silicon oxide film formed by plasma CVD using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) can also be used. This can improve productivity.

[0139] Insulating layers 41a and 41c are preferably made of materials that are less permeable to oxygen than insulating layer 41b, i.e., materials with oxygen-barrier properties. Insulating layers 41a and 41c can use the aforementioned oxygen-barrier insulating film. In particular, silicon nitride or aluminum oxide is preferred.

[0140] Furthermore, either insulating layer 41a or insulating layer 41c, and insulating layer 41b, may also use an insulating film containing the same elements (e.g., silicon oxide). In this case, an insulating film with a higher density than insulating layer 41b can be used, for example, an insulating film with a slow etching rate can be applied.

[0141] The insulating layers 41a and 41c are preferably made of films that are not easily diffused by hydrogen. By sandwiching the insulating layer 41b between the upper and lower parts of the insulating layer 41b by the insulating layers 41a and 41c, which are not easily diffused by hydrogen, hydrogen can be prevented from mixing into the insulating layer 41b that is in contact with the semiconductor layer 21 from the outside.

[0142] In particular, silicon nitride and silicon oxynitride have the characteristics of releasing very few impurities (such as water and hydrogen) and not easily allowing oxygen and hydrogen to permeate, so they are suitable for use as insulating layers 41a and 41c.

[0143] In addition, when the insulating layer 41 has a single-layer structure, the materials described above that can be used for the insulating layer 41b or the materials that can be used for the insulating layer 41a or the insulating layer 41b can be used.

[0144] Insulating layer 11 is used as a base insulating layer or an interlayer insulating layer. As insulating layer 11, the insulating material that can be used in insulating layer 41b or the insulating material that can be used in insulating layer 41a and insulating layer 41c can be used appropriately.

[0145] The above is an explanation of the constituent elements.

[0146] [Example of manufacturing method] The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. Here, it is described as an example. Figure 3B The structure shown.

[0147] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, CVD, vacuum evaporation, pulsed laser deposition (PLD), and ALD. CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD (TCVD). Furthermore, metal-organic chemical vapor deposition (MOCVD) is one type of thermal CVD method.

[0148] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, and doctor blade coating.

[0149] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is primarily used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0150] CVD methods can be categorized into plasma CVD (PECVD), thermal CVD, and photo CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and organometallic CVD.

[0151] By utilizing plasma-enhanced CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece can be reduced. Additionally, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0152] As an ALD method, one can use thermal ALD, which uses only thermal energy to react the precursors and reactants, or PEALD, which uses reactants excited by plasma.

[0153] Unlike sputtering, CVD and ALD are deposition methods that are less affected by the shape of the substrate and offer good step coverage. In particular, ALD exhibits excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0154] When using CVD (CVD), films of arbitrary composition can be deposited depending on the source gas flow rate ratio. Furthermore, for example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to deposition using multiple deposition chambers because the time required for transfer or pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0155] When using the ALD method, films of arbitrary composition can be deposited by alternately introducing different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing different precursors, films of arbitrary composition can be deposited. Furthermore, similar to the CVD method, films with continuously varying compositions can be deposited.

[0156] Furthermore, when processing thin films constituting semiconductor devices, photolithography and other methods can be used. In addition, nanoimprint lithography, sandblasting, and lift-off methods can be used to process the thin films. Furthermore, island-shaped thin films can also be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0157] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film through etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to process the film into the desired shape.

[0158] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can be employed. Extreme ultraviolet (EUV) light and X-rays can also be used as the light for exposure. Electron beams can also be used instead of the light used for exposure. When using EUV light, X-rays, or electron beams, extremely fine processing can be achieved, making them preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0159] When etching thin films, methods such as dry etching, wet etching, and sandblasting can be used. Wet etching is mainly suitable for isotropic etching. On the other hand, dry etching can perform both isotropic and anisotropic etching depending on the etching apparatus and etching conditions.

[0160] Figures 8A to 9C These are cross-sectional views of each step in the manufacturing process of the semiconductor device shown below. Figures 8A to 9C The left side is a cross-sectional view corresponding to A1-A2 in the top view of Figure 1. Figures 8A to 9C The right side is a cross-sectional view corresponding to B1-B2 in the top view of Figure 1.

[0161] First, an insulating layer 11 is formed on a substrate (not shown).

[0162] As a substrate, a substrate with heat resistance sufficient to withstand subsequent heat treatment can be used. When using an insulating substrate, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, organic resin substrates, etc., can be used. In addition, single-crystal semiconductor substrates or polycrystalline semiconductor substrates made of materials such as silicon or silicon carbide, compound semiconductor substrates such as silicon-germanium and gallium nitride, SOI substrates, etc., can also be used.

[0163] As the insulating layer 11, inorganic insulating films such as silicon oxide films and silicon oxynitride films can be used. The deposition of the insulating layer 11 can be performed using sputtering, CVD, MBE, PLD, ALD, etc. If the surface on which the insulating layer 11 is formed is not flat, it is preferable to perform planarization treatment after depositing the insulating layer 11 to make the top surface of the insulating layer 11 flat.

[0164] Next, a conductive film is deposited on the insulating layer 11, and a photoresist mask is formed on the conductive film. Unwanted portions of the conductive film are removed by etching, thereby forming the conductive layer 24. Figure 8A The conductive film that will become the conductive layer 24 can be deposited using deposition methods such as sputtering, CVD, and ALD.

[0165] As the conductive film that will become the conductive layer 24, it is preferable to adopt a laminated structure containing a film of a highly conductive metal or alloy and an oxide conductor stacked thereon.

[0166] Next, insulating layers 41a, 41b, and 41c are formed on the conductive layer 24 and the insulating layer 11. Figure 8B Insulating layers 41a, 41b, and 41c can be formed using sputtering, CVD, MBE, PLD, ALD, or other suitable methods, respectively. Here, it is preferable to use an insulating film whose composition or constituent elements are different from those of insulating layers 41a and 41c as insulating layer 41b.

[0167] Furthermore, the thicknesses of insulating layers 41a, 41b, and 41c affect the channel length of the transistor, so it is important to prevent uneven thicknesses of the insulating layers 41a, 41b, and 41c.

[0168] The insulating layer 41b is the film that subsequently contacts the semiconductor layer 21, so an oxide film is preferably used. This oxide film contains oxygen to the extent that oxygen is released upon heating and has a low hydrogen content. The insulating layer 41b can be deposited using deposition methods such as PECVD, sputtering, and ALD, with sputtering being particularly preferred. In particular, by using an oxygen-containing gas instead of a hydrogen-containing gas for deposition, an insulating layer 41b with extremely low hydrogen content and excess oxygen can be deposited. By depositing the insulating layer 41b in this way, oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0169] Alternatively, oxygen can be supplied to the insulating layer 41b after deposition and before deposition of the insulating layer 41c. Methods for supplying oxygen to the insulating layer 41b include heating in an oxygen atmosphere and plasma treatment in an oxygen atmosphere. Alternatively, an oxide film can be deposited on the insulating layer 41b using a sputtering method in an oxygen atmosphere to supply oxygen. This oxide film can then be removed. Alternatively, oxygen (including any one of oxygen radicals, oxygen atoms, and oxygen ions) can be supplied using ion implantation, ion doping, or plasma immersion ion implantation.

[0170] Next, a conductive film 25f is deposited on the insulating layer 41c. Figure 8C The conductive film 25f can be deposited using deposition methods such as sputtering, CVD, MBE, PLD, and ALD.

[0171] Similar to conductive layer 24, conductive film 25f preferably has a laminated structure consisting of a film containing a highly conductive metal or alloy and a film containing an oxide conductor stacked thereon.

[0172] Next, unwanted portions of the conductive film 25f, insulating layer 41c, insulating layer 41b, and insulating layer 41a are removed by etching, thus forming them into island shapes. Figure 8D At this point, a portion of the conductive layer 24 is exposed.

[0173] When processing insulating layers 41c, 41b, and 41a, the conductive film 25f can also be used as a hard mask. In this case, the conductive film 25f is first processed into an island shape using a photoresist mask. Then, the conductive film 25f can be used as a mask to sequentially etch insulating layers 41c, 41b, and 41a. Alternatively, the photoresist mask can be removed after etching the conductive film 25f, during etching of insulating layers 41c, 41b, and 41a, or after etching is complete.

[0174] Alternatively, the photoresist mask used in processing the conductive film 25f can be different from that used in processing the insulating layers 41c, 41b, and 41a. In this case, the conductive film 25f can be etched using different photoresist masks after processing the conductive film 25f, insulating layers 41c, 41b, and 41a. Alternatively, the insulating layers 41c, 41b, and 41a can be etched using different photoresist masks after etching the conductive film 25f.

[0175] Next, a heat treatment can be performed. The heat treatment can be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, in order to replenish the detached oxygen, it can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 can be reduced before depositing the semiconductor film that will become the semiconductor layer. As oxidizing gases, nitrogen oxides such as N2O (nitrous oxide or nitrous oxide), NO2 (nitrogen dioxide), and NO (nitric oxide) or gases containing O2 (oxygen) and O3 (ozone) can be used.

[0176] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment is preferably 1 ppb (0.001 ppm) or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 41 can be prevented as much as possible.

[0177] Next, a semiconductor film that will later become semiconductor layer 21 is deposited, and unwanted portions are removed by etching to form semiconductor layer 21. Figure 9A ).

[0178] The semiconductor film is preferably deposited using a deposition method with extremely high coverage to make it contact the side surface of the insulating layer 41. Typically, the ALD method is preferred for deposition. Alternatively, even when using sputtering, a uniform thickness can be deposited on the side surface of the insulating layer 41 by reducing the distance between the substrate surface and the sputtering target or by tilting the surfaces of the substrate surface and the sputtering target relative to each other.

[0179] Alternatively, the impurity concentration in the oxide semiconductor film can be reduced by performing microwave treatment in an oxygen-containing atmosphere during or after the deposition of the oxide semiconductor film. Examples of impurities include hydrogen and carbon. Microwave treatment can sometimes improve the crystallinity of the oxide semiconductor film. Here, microwave treatment refers, for example, to treatment using a device that includes a power source for generating high-density plasma using microwaves.

[0180] The semiconductor film is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water. In particular, a crystalline metal oxide film is preferably used as the semiconductor film.

[0181] When depositing metal oxide films using sputtering, oxygen gas and inert gases (e.g., helium, argon, xenon, etc.) can be mixed. Note that the higher the proportion of oxygen gas in the overall deposition gas (hereinafter also referred to as the oxygen flow ratio) during metal oxide film deposition, the higher the crystallinity of the metal oxide film can be, enabling the realization of transistors with high reliability. Conversely, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, enabling the realization of transistors with high on-state current.

[0182] When the substrate temperature is high during sputtering deposition of metal oxide films, a denser metal oxide film with higher crystallinity can be formed. On the other hand, as the substrate temperature decreases, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0183] As for the deposition conditions when depositing metal oxide films using sputtering, it is preferable to set the substrate temperature to above room temperature and below 250°C, more preferably above room temperature and below 200°C, and even more preferably above room temperature and below 140°C. For example, a substrate temperature above room temperature and below 140°C is preferred, which can improve productivity. When depositing metal oxide films at room temperature or without intentional heating, crystallinity can be reduced.

[0184] When depositing metal oxide films using the ALD method, thermal ALD or PEALD (Plasma Enhanced ALD) are preferred. Thermal ALD offers extremely high step coverage and is therefore preferred. Furthermore, PEALD not only offers high step coverage but also allows for low-temperature deposition, making it a preferred method as well.

[0185] For example, when using a metal oxide for semiconductor layer 21, a precursor containing the metal element constituting the metal oxide and an oxidant can be deposited using the ALD method.

[0186] For example, when depositing In-Ga-Zn oxide, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium and one containing both gallium and zinc.

[0187] As precursors containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0188] In addition, as gallium-containing precursors, trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III)acetylacetone, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)gallium, dimethylgallium chloride, diethylgallium chloride, gallium(III) chloride, etc. can be used.

[0189] In addition, zinc-containing precursors such as dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride can be used.

[0190] As an oxidant, ozone, oxygen, water, etc. can be used, for example.

[0191] Methods for controlling the composition of the obtained membrane include adjusting the flow rate ratio of the source gas, the time for the source gas to flow through, and the order in which the source gas flows through. By adjusting these parameters, membranes with continuously varying compositions can be deposited. Furthermore, two or more membranes with different compositions can be deposited consecutively.

[0192] By performing a heat treatment after the semiconductor film is formed, oxygen can be supplied to the semiconductor film from the insulating layer 41b. Furthermore, the heat treatment can remove hydrogen from the semiconductor film and water adsorbed on its surface. The heat treatment method can be found as described above.

[0193] Next, an insulating layer 22 is formed to cover the conductive layer 24, semiconductor layer 21, conductive layer 25, etc. The insulating layer 22 is preferably formed in a manner where its thickness is uniform along the side of the insulating layer 41; therefore, a deposition method with high coverage is preferred. Specifically, deposition methods such as ALD and CVD are preferred, with ALD being particularly preferred.

[0194] Next, a conductive film 23f is deposited on the insulating layer 22. Figure 9B Then, the unwanted portions of the conductive film 23f are removed by etching to form the conductive layer 23. Next, the portions of the insulating layer 22 not covered by the conductive layer 23 are removed by etching. Figure 9C ).

[0195] The conductive film that will become the conductive layer 23 is preferably formed using a deposition method with high coverage. Specifically, deposition methods such as ALD and CVD are preferred, and one or both of ALD and thermal CVD are particularly preferred. Alternatively, the conductive layer 23 can also be formed using sputtering.

[0196] Transistors can be manufactured through the above processes.

[0197] The above is an explanation of examples of manufacturing methods.

[0198] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0199] (Implementation Method 2) By using the vertical transistor shown in Embodiment 1 in a liquid crystal display device, the aperture ratio can be significantly increased compared to conventional liquid crystal display devices using horizontal transistors. This enables the realization of display devices with low power consumption, increased maximum brightness, good viewing angle characteristics, and high reliability.

[0200] More specifically, in one aspect of the present invention, by using vertical transistors, which allow for extremely small occupancy areas, in the pixels of a liquid crystal display device, a liquid crystal display device achieving both extremely high resolution and a high aperture ratio can be realized. Furthermore, the vertical transistors of one aspect of the present invention can shorten the channel length compared to conventional lateral transistors, allowing for the flow of a large current. Therefore, by using such transistors in a display device, a liquid crystal display device capable of high-speed driving and high display quality can be realized. Moreover, although the vertical transistors of one aspect of the present invention have a small channel length, their leakage current in the off state is extremely small. By using them in a liquid crystal display device, the potential written in the pixels can be maintained for a long time, reducing power consumption through low frame rate display.

[0201] As the second electrode of the transistor disposed on the insulating layer, an oxide conductive film is preferably used. This reduces the contact resistance between the semiconductor layer and the second electrode when an oxide semiconductor film is used as the semiconductor layer. Furthermore, the second electrode can also be a transparent oxide conductive film and serve as the pixel electrode of the liquid crystal element.

[0202] When using lateral transistors, contact holes are required to connect the source or drain electrode of the transistor to the pixel electrode. Furthermore, depending on the transistor structure, contact holes are sometimes used to connect the semiconductor layer to the source or drain electrode. Due to the uneven shape created by these contact holes, the liquid crystal alignment in and around the contact holes becomes disordered, rendering them unusable for display. This is one of the main reasons why it is difficult to improve the aperture ratio.

[0203] However, in one embodiment of the invention, since the second electrode of the transistor also serves as the pixel electrode, no contact hole is required, thereby increasing the aperture ratio. Furthermore, since no interlayer insulating layer is required between the semiconductor layer of the transistor and the second electrode, the connection between the semiconductor layer and the second electrode can be achieved without a contact hole, further increasing the aperture ratio.

[0204] Liquid crystal elements can be of various structures. Typically, transmissive liquid crystal elements using VA (Vertical Alignment), FFS (Fringe Field Switching), or IPS (In-Plane Switching) modes can be used. Furthermore, not only transmissive liquid crystal elements but also reflective or semi-transmissive liquid crystal elements can be used.

[0205] The following illustrations provide more specific examples.

[0206] [Example of a liquid crystal display device structure] Figure 10A A top view schematic diagram of the pixels 55 included in the liquid crystal display device shown below is presented. Additionally, Figure 10B A three-dimensional schematic diagram of a pixel is shown. Note that some components (liquid crystal, common electrode, etc.) are omitted here.

[0207] Pixel 55 comprises three subpixels (subpixels 56R, 56G, and 56B). Subpixel 56R is a red subpixel, subpixel 56G is a green subpixel, and subpixel 56B is a blue subpixel. Subpixels 56R, 56G, and 56B have the same structure, except for the color layer.

[0208] Sub-pixel 56R includes transistor 10. Sub-pixel 56R includes a portion of conductive layer 23, a portion of conductive layer 24, and conductive layer 25. Conductive layer 23 also serves as a gate line, conductive layer 24 also serves as a signal line, and conductive layer 25 also serves as a pixel electrode.

[0209] like Figure 10B As shown, a conductive layer 24 and an island-shaped insulating layer 41 are disposed on the insulating layer 11, and a conductive layer 25 is disposed on the insulating layer 41. The semiconductor layer 21 has a portion that contacts the top surface of the conductive layer 24, a portion that contacts the side surface of the insulating layer 41, and a portion that contacts the top surface of the conductive layer 25. Note that in Figure 10B In the diagram, the insulating layer 22 and the conductive layer 23 used as gate insulating layers are omitted.

[0210] By adopting Figure 10A and Figure 10BThe pixels shown enable high-definition display devices. For example, by forming the wiring widths of conductive layers 23 and 24 and the spacing between the two conductive layers 25 with minimal processing dimensions, a display device with extremely high resolution can be achieved. Figure 10A and Figure 10B In the structure shown, for example, when the minimum processing size is 1.5μm, a display device with both high aperture ratio and high resolution can be realized, that is, a resolution of 2117ppi and an aperture ratio (here, the ratio of the effective area of ​​the pixel electrode) of 44.7%.

[0211] Figure 11A and Figure 11B An example structure of pixels that can further achieve high resolution is shown. Here, the width of conductive layer 24 is the same as the width of the thickest part of conductive layer 25. By adopting this structure, for example, a display device with a resolution of 2822ppi and an aperture ratio of 28.8% can be achieved with a minimum processing size of 1.5μm.

[0212] [Example of cross-sectional structure] [Structure Example 1] Figure 12A A cross-sectional schematic diagram of a liquid crystal display device is shown. Figure 12A Showing the corresponding Figure 10A The cross section of the dotted line C1-C2 in the diagram. Figure 12A The display device shown includes a transistor 10 and a liquid crystal element 30 between the insulating layer 11 and the substrate 12.

[0213] Transistor 10 includes a semiconductor layer 21, an insulating layer 22, a conductive layer 23, a conductive layer 24a, a conductive layer 24b, and a conductive layer 25. Here, an example is shown where the conductive layer 24b is stacked on the conductive layer 24a and the top surface of the semiconductor layer 21 is in contact with the conductive layer 24b. Preferably, a low-resistance conductive film is used as the conductive layer 24a, and an oxide conductive film is used as the conductive layer 24b.

[0214] The liquid crystal element 30 includes a portion of the conductive layer 25, liquid crystal 31, and conductive layer 32. The conductive layer 25 serves as a pixel electrode. Additionally, the conductive layer 32 serves as a common electrode. The conductive layers 25 and 32 are preferably made of transparent conductive films, and more preferably of oxide conductive films.

[0215] Conductive layers 24a and 24b are stacked on insulating layer 11, and island-shaped insulating layers 41 (insulating layers 41a, 41b, and 41c) are provided to cover a portion of them. A conductive layer 25 is provided on insulating layer 41. Semiconductor layer 21 is provided to contact the top surface of conductive layer 24a, the side surface of insulating layer 41, and the top surface of conductive layer 25. Insulating layer 22 is provided to cover conductive layer 24b, semiconductor layer 21, conductive layer 25, and insulating layer 11, and a conductive layer 23 is provided on insulating layer 22. Conductive layer 23 is provided to cover a portion of semiconductor layer 21 along insulating layer 41 through insulating layer 22. Note that insulating layer 11 can also be a glass substrate.

[0216] Additionally, an insulating layer 42 is provided to cover both the conductive layer 23 and the insulating layer 22. The insulating layer 42 serves as a protective layer. The insulating layer 42 may use the insulating film described above that can be used for the insulating layer 41a or the insulating layer 41b.

[0217] An alignment film 35a is provided to cover the insulating layer 42, and an insulating layer 54 serving as a spacer is provided on the alignment film 35a. The insulating layer 54 is preferably provided in a portion that does not contribute to the display. The insulating layer 54 may be provided in a portion overlapping with the conductive layer 24a, a portion overlapping with the conductive layer 23, etc.

[0218] A coloring layer 51, a light-shielding layer 52, an insulating layer 53, a conductive layer 32, and an alignment film 35b are disposed on one side of the insulating layer 11 of the substrate 12. The alignment film 35b may also have a portion that contacts the insulating layer 54.

[0219] The portion where the light-shielding layer 52 is provided is a non-light-emitting area. In one embodiment of the present invention, the light-shielding layer 52 can be provided in the area covering the transistor 10, the conductive layer 23, and the conductive layer 24. In one embodiment of the present invention, since there is no contact hole connecting the pixel electrode and the transistor, the area of ​​the non-light-emitting area where the light-shielding layer 52 is provided can be significantly reduced compared to the existing structure.

[0220] The color layer 51, also known as a color filter, converts light from a light source such as a backlight into light that displays a specific color. For example, by using color layers 51 corresponding to red, green, and blue for each pixel (sub-pixel) as color layers, full-color display can be achieved. In addition to the above three colors, it is preferable to also provide pixels (sub-pixels) corresponding to colors such as yellow and white, thereby reducing power consumption.

[0221] Alternatively, a color conversion material that uses blue or violet light as a light source and converts the blue or violet light into other colors (e.g., red, green, etc.) can be used in the color layer 51. As the color conversion material, fluorescent materials, phosphorescent materials, or quantum dot-dispersed resin materials can be used. In this case, in order to absorb the light transmitted through the color conversion material, the color layer 51 preferably has a stacked structure in which the color conversion material and the color filter are layered from the backlight side.

[0222] The insulating layer 53 serves as a protective layer to prevent components contained in the coloring layer 51, etc., from diffusing into the liquid crystal 31. Additionally, the insulating layer 53 serves as a planarization film. The insulating layer 53 can be formed using a transparent organic resin.

[0223] The substrate with insulating layer 11 and the substrate 12 are bonded together by an adhesive layer (not shown) provided on the outside of the display section. The distance between the substrates is controlled by insulating layer 54, which serves as a spacer.

[0224] In one embodiment of the present invention, one of the source and drain electrodes of transistor 10 (specifically, the electrode located on the upper side) also serves as a pixel electrode of liquid crystal element 30. By adopting this structure, the manufacturing process can be significantly simplified compared to forming the electrodes separately, thereby reducing manufacturing costs. Furthermore, since the number of interlayer insulating films required can be reduced, scattering of light from the backlight can be mitigated, power efficiency is improved, and power consumption can be reduced.

[0225] Here, the pixel electrode of the liquid crystal element 30 is required to have high light transmittance. Furthermore, in the structure of the transistor 10, good electrical connection with the semiconductor layer 21 containing oxide semiconductor is required. Therefore, by using a transparent conductive metal oxide film as the conductive layer 25, not only high light transmittance can be achieved, but good electrical connection with the oxide semiconductor can also be ensured. Thus, by using a transparent conductive metal oxide film as the conductive layer 25, it can function as both the source and drain electrode of the transistor 10 and the pixel electrode.

[0226] Here, the liquid crystal element 30 is shown in a so-called VA mode, in which the pixel electrode is disposed on one side of the insulating layer 11, the common electrode is disposed on one side of the substrate 12, and an electric field is applied to the liquid crystal 31 in a direction parallel to the thickness direction. Note that the electrode arrangement method is not limited to this; an electric field can also be applied to the liquid crystal 31 in a direction perpendicular to the thickness direction.

[0227] The display device can be a normally black liquid crystal display device, such as a transmissive liquid crystal display device using vertical alignment (VA) mode. As a vertical alignment mode, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc. can be used.

[0228] In addition, liquid crystal element 30 can use liquid crystal elements employing various modes. For example, in addition to VA mode and FFS mode, liquid crystal elements employing TN (Twisted Nematic) mode, IPS mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, guest-host mode, etc., can also be used.

[0229] Here, a liquid crystal display device is a display device that uses polarized light and the optical modulation effect of liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by an electric field (horizontal, vertical, or tilted) applied to the liquid crystal. Liquid crystals that can be used as liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, and homogeneous phases depending on the conditions. Furthermore, either positive or negative liquid crystals can be used as liquid crystal materials; a suitable liquid crystal material can be selected based on the mode or design used.

[0230] Although Figure 12AAlthough not shown in the diagram, in the case of a transmissive liquid crystal, polarizers are respectively provided on the outer surface of the substrate with insulating layer 11 and the outer surface of substrate 12. Furthermore, a backlight is provided on the outer side of the substrate with insulating layer 11. In this case, the substrate 12 side is the display surface side.

[0231] Figure 12A This shows the structure where the insulating layer 22 covers the top surface of the conductive layer 25. Figure 12B An example is shown where the insulating layer 22 is processed such that its ends are aligned with the conductive layer 23. In this case, in the liquid crystal element 30, the insulating layer 22 is not provided between the conductive layer 25 and the liquid crystal 31, thereby increasing the intensity of the electric field experienced by the liquid crystal 31 from the conductive layer 25. Therefore, the driving voltage of the liquid crystal element 30 can be reduced, which is preferable.

[0232] [Structure Example 2] Figure 13A Showing the Figure 12A The example shown is an additional conductive layer 36 to the structure.

[0233] The conductive layer 36 is disposed in the area overlapping with the liquid crystal element 30. The conductive layer 36 can be formed by processing the same conductive film as the conductive layer 24b. The conductive layer 36 has the function of allowing visible light to pass through.

[0234] A MIM (Metal-Insulator-Metal) capacitor is formed by conductive layer 36, insulating layer 41, and conductive layer 25. This capacitor can be used as a storage capacitor for pixels. By setting a storage capacitor, the period during which the potential of conductive layer 25, which serves as a pixel electrode, can be maintained can be extended, thereby enabling low frame rate display.

[0235] [Structure Example 3] Figure 13B An example of a liquid crystal element 30 using IPS mode is shown.

[0236] The conductive layer 25, used as a pixel electrode, and the conductive layer 32, used as a common electrode, are both disposed on the insulating layer 41c. Preferably, the conductive layer 25 and the conductive layer 32 are formed by processing the same conductive film. Note that in... Figure 13B In the illustration, different shaded lines are applied to conductive layer 25 and conductive layer 32.

[0237] Both conductive layer 25 and conductive layer 32 have a comb-like top surface shape and are configured to interlock with each other.

[0238] [Structure Example 4] Figure 14A An example of a liquid crystal element 30 employing FFS mode is shown.

[0239] A conductive layer 32, serving as a common electrode, is disposed on the insulating layer 42. One or more openings (also referred to as slits) are provided in the conductive layer 32. The conductive layer 32 includes a conductive film that allows visible light to pass through.

[0240] The conductive layer 32 and the conductive layer 25 have an overlapping area separated by the insulating layer 22 and the insulating layer 42, which is used as a storage capacitor. Therefore, since there is no need to separately provide a storage capacitor, it is easy to increase the pixel's footprint and aperture ratio.

[0241] Figure 14B yes Figure 14A Examples of variations. Figure 14B An example is shown where the stacking order of conductive layer 32 and conductive layer 25 is interchanged.

[0242] A conductive layer 32 is disposed on an insulating layer 41c, and an insulating layer 43 is disposed thereto cover both the conductive layer 32 and the insulating layer 41c. A conductive layer 25 is disposed on the insulating layer 43, and an insulating layer 22 and an insulating layer 42 are disposed thereto cover the conductive layer 25. One or more slits are provided in the conductive layer 25.

[0243] exist Figure 14B In this process, the area where conductive layer 32 and conductive layer 25 overlap through insulating layer 43 is used as a storage capacitor.

[0244] [Structure Example 5] Figure 15A The structure shown is Figure 13A Examples of variations.

[0245] exist Figure 15A In this process, the portion of the insulating layer 41b that overlaps with the liquid crystal element 30 is removed by etching. That is, Figure 15A The structure shown has a portion in the region overlapping with the liquid crystal element 30 where a conductive layer 36, an insulating layer 41a, an insulating layer 41b, and a conductive layer 25 are sequentially stacked. Thus, with... Figure 13A Compared to the structure shown, the capacitance between conductive layer 36 and conductive layer 25 can be increased. In addition, by omitting the insulating layer 41b in the portion used as liquid crystal element 30, not only can the light transmittance be improved, but the number of interfaces in the path of light from the light source can also be reduced, thus suppressing the effects of interface reflection and interface scattering.

[0246] In addition, such as Figure 15B As shown, in addition to the insulating layer 41b, the portion of the insulating layer 41c that overlaps with the liquid crystal element 30 can also be etched. This not only further increases the capacitance between the conductive layer 36 and the conductive layer 25, but also improves the light transmittance, thereby further suppressing the effects of interface reflection and interface scattering.

[0247] [Structure Example 6] Figure 16A The structure shown is Figure 15A Examples of variations.

[0248] Figure 16A This diagram illustrates a structure where a portion of the semiconductor layer 21 serves as a pixel electrode, without the conductive layer 25. The semiconductor layer 21 has a portion that does not overlap with the insulating layer 41 and is used as a pixel electrode. A portion of the semiconductor layer 21 is disposed in the region overlapping with the conductive layer 36. The liquid crystal element 30 is composed of the semiconductor layer 21, liquid crystal 31, and the conductive layer 32. Furthermore, the storage capacitor is composed of the conductive layer 36, insulating layers 41a and 41c, and the semiconductor layer 21.

[0249] By adopting this structure, the conductive layer 25 can be omitted, thereby reducing the number of manufacturing steps in the display device. Furthermore, since there is no need to provide a contact portion between the conductive layer 25 and the semiconductor layer 21, the occupied area of ​​the transistors can be further reduced. Therefore, higher resolution or a higher aperture ratio can be achieved.

[0250] Figure 16B yes Figure 16A Examples of variations. Figure 16B An example is shown where the portion of insulating layer 22 not covered by conductive layer 23 is removed by etching.

[0251] [Structure Example 7] Figure 17A yes Figure 14B Examples of variations. Figure 17A An example is shown where the insulating layer 41b is removed by etching in the area overlapping with the liquid crystal element 30.

[0252] Furthermore, a conductive layer 32 is disposed on the insulating layer 11. The conductive layer 32 can be formed by processing the same conductive film as the conductive layer 24b. This reduces the number of manufacturing steps in the display device, making it preferable.

[0253] An insulating layer 41a and an insulating layer 41c are disposed on the conductive layer 32, and a conductive layer 25 is disposed on the insulating layer 41c. Note that the conductive layer 25 may be omitted and the semiconductor layer 21 may also be used as a pixel electrode. Alternatively, a structure may be adopted in which one of the insulating layers 41a and 41c is removed by etching, and either the insulating layer 41a or the insulating layer 41c is disposed between the conductive layer 32 and the conductive layer 25 (or the semiconductor layer 21).

[0254] [Structure Example 8] Figure 17B yes Figure 13B Examples of variations. Figure 17B An example is shown in which insulating layers 41a, 41b, and 41c are removed by etching in the area overlapping with the liquid crystal element 30.

[0255] The insulating layer 41c is provided to cover the side of the insulating layer 41b opposite to the side of the semiconductor layer 21. Furthermore, the insulating layer 41c has a region that contacts the insulating layer 41a. Thus, by employing a structure in which the semiconductor layer 21, the insulating layer 41a, and the insulating layer 41c surround the insulating layer 41b, oxygen diffusion contained in the insulating layer 41b can be suppressed, thereby increasing the amount of oxygen supplied to the semiconductor layer 21. This enables a display device with high reliability.

[0256] Conductive layer 25 and conductive layer 32 are disposed on insulating layer 11. Thus, by minimizing the presence of insulating layer in the area overlapping with liquid crystal element 30, the effects of interface reflection and interface scattering can be suppressed, which is therefore preferred.

[0257] The above illustrates an example of the structure of a display device.

[0258] At least a portion of the structural examples shown in this embodiment and the corresponding drawings can be appropriately combined with other structural examples or drawings.

[0259] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0260] (Implementation Method 3) In this embodiment, a display device incorporating a transistor according to one aspect of the present invention will be described.

[0261] Figure 18A The display device shown includes a pixel unit 502, a driving circuit unit 504, a protection circuit 506, and a terminal unit 507. Alternatively, a structure without the protection circuit 506 may be adopted.

[0262] The transistor of one aspect of the present invention can be used in the transistors included in one or both of the pixel section 502 and the driving circuit section 504. Furthermore, the protection circuit 506 can also use a transistor of one aspect of the present invention.

[0263] The pixel unit 502 includes a plurality of pixel circuits 501 configured in X rows and Y columns (where X and Y are independent natural numbers of 2 or more). Each pixel circuit 501 includes circuitry for driving display elements.

[0264] The drive circuit section 504 includes drive circuits for a gate driver 504a that outputs scan signals to gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to data lines DL_1 to DL_Y. The gate driver 504a may have a structure that includes at least a shift register. The source driver 504b may be composed of a shift register, a digital-to-analog converter, a latch circuit, etc.

[0265] Terminal section 507 refers to the section provided with terminals for inputting power, control signals, and image signals to the display device from external circuitry.

[0266] The protection circuit 506 is a circuit that keeps the wire connected to it in a conductive state with other wires when the wire to which it is connected is supplied with a potential outside a certain range. Figure 18A The protection circuit 506 shown is connected to various wirings, such as the gate line GL and data line DL. Note that in Figure 18A In order to distinguish the protection circuit 506 from the pixel circuit 501, a shaded line is added to the protection circuit 506.

[0267] Alternatively, the gate driver 504a and source driver 504b can be disposed on the same substrate as the pixel portion 502. Alternatively, an IC with a separately formed gate drive circuit or source drive circuit can be mounted on the substrate where the pixel portion 502 is disposed using a method such as COG (Chip on Glass). Alternatively, an FPC (Flexible Printed Circuit) with the IC mounted can be attached to the substrate using a method such as ACF (Anisotropic Conductive Film).

[0268] In particular, it is preferable that the pixel portion 502 and the gate driver 504a are manufactured on the same substrate using the same process. In this case, it is preferable to provide a transistor of one aspect of the present invention in both the pixel portion 502 and the gate driver 504a. Furthermore, when the source driver 504b uses an IC, it is preferable to provide a demultiplexer circuit on this substrate, thereby reducing the number of terminals on the IC. In this case, it is preferable to use a transistor of one aspect of the present invention in the demultiplexer circuit.

[0269] Figure 18B An example of the structure of a pixel circuit that can be used in pixel circuit 501 is shown.

[0270] Figure 18B The pixel circuit 501 shown includes a liquid crystal element 570, a transistor 550, and a capacitor 560. Furthermore, the pixel circuit 501 is connected to data lines DL_n, gate lines GL_m, and potential supply lines VL.

[0271] The vertical transistor of one aspect of the present invention can be used in transistor 550.

[0272] The potential of one electrode of a pair of electrodes in the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written. Alternatively, a common potential can be supplied to one electrode of a pair of electrodes in the liquid crystal element 570 of each of the multiple pixel circuits 501. Furthermore, a different potential can be supplied to one electrode of a pair of electrodes in the liquid crystal element 570 of each row of pixel circuits 501.

[0273] in addition, Figure 18C The pixel circuit 501 shown includes transistor 552, transistor 554, capacitor 562, and light-emitting element 572. Furthermore, the pixel circuit 501 is connected to data line DL_n, gate line GL_m, potential supply line VL_a, and potential supply line VL_b.

[0274] Furthermore, a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. Based on the potential applied to the gate of transistor 554, the current flowing through the light-emitting element 572 is controlled, thereby controlling the luminous intensity from the light-emitting element 572.

[0275] Next, a pixel circuit equipped with a memory for correcting the grayscale displayed by the pixels and a display device having the pixel circuit will be described.

[0276] Figure 19A A circuit diagram of pixel circuit 400 is shown. Pixel circuit 400 includes transistor M1, transistor M2, capacitor C1, and circuit 401. Furthermore, pixel circuit 400 is connected to wiring S1, wiring S2, wiring G1, and wiring G2.

[0277] The vertical transistor of one aspect of the present invention can be used as transistor M1 and transistor M2.

[0278] The gate of transistor M1 is connected to wiring G1, one of its source and drain is connected to wiring S1, and the other of its source and drain is connected to one electrode of capacitor C1. The gate of transistor M2 is connected to wiring G2, one of its source and drain is connected to wiring S2, and the other of its source and drain is connected to the other electrode of capacitor C1 and circuit 401.

[0279] Circuit 401 includes at least one display element. Here, the display element includes a liquid crystal element.

[0280] The node connecting transistor M1 and capacitor C1 is denoted as node N1, and the node connecting transistor M2 and circuit 401 is denoted as node N2.

[0281] The pixel circuit 400 can maintain the potential of node N1 by turning transistor M1 off. Furthermore, it can maintain the potential of node N2 by turning transistor M2 off. Moreover, by writing a predetermined potential to node N1 through transistor M1 while transistor M2 is off, the potential of node N2 can change in response to changes in the potential of node N1 due to capacitive coupling through capacitor C1.

[0282] Here, one or both of transistors M1 and M2 can be an oxide semiconductor transistor as shown in Embodiment 1. Because this transistor has a very small off-state current, the potential of node N1 or node N2 can be maintained for a long time. Furthermore, when the potential maintenance period of each node is short (specifically, when the frame rate is 30Hz or higher, etc.), a transistor using a semiconductor such as silicon can also be used.

[0283] [Example of a driver method] Next, refer to Figure 19B An example illustrating how the pixel circuit 400 works. Figure 19B This is a timing diagram of the pixel circuit 400. Note that, for ease of explanation, the effects of various resistances such as wiring resistance, parasitic capacitance, and transistor threshold voltage are not considered here.

[0284] exist Figure 19B In the work shown, a frame period is divided into period T1 and period T2. Period T1 is the period for writing potential to node N2, and period T2 is the period for writing potential to node N1.

[0285] [Period T1] During period T1, a potential that turns the transistor on is supplied to both wiring G1 and wiring G2. Additionally, a fixed potential V is supplied to wiring S1. ref Supply the first data potential V to wiring S2 w .

[0286] Node N1 is supplied with potential V from wiring S1 via transistor M1. ref Furthermore, node N2 is supplied with a first data potential V from wiring S2 via transistor M2. w Therefore, the potential difference V is maintained by capacitor C1. w -V ref The state.

[0287] [Period T2] Next, during period T2, wiring G1 is supplied with a potential that turns transistor M1 on, and wiring G2 is supplied with a potential that turns transistor M2 off. Wiring S1 is supplied with the second data potential V. dataIn addition, a predetermined constant potential can be supplied to wiring S2 or it can be left in a floating state.

[0288] Node N1 is supplied with the second data potential V from wiring S1 via transistor M1. data At this time, due to capacitive coupling through capacitor C1, the corresponding second data potential V... data The potential of node N2 changes by a value of dV. In other words, circuit 401 is input with the first data potential V. w The potential added together with the potential dV. Note that, although... Figure 19B The potential dV is shown to be a positive value, but it can also be a negative value. That is, the second data potential V... data It can also be compared to the potential V ref Low.

[0289] Here, the potential dV is primarily determined by the capacitance of capacitor C1 and the capacitance of circuit 401. When the capacitance of capacitor C1 is sufficiently greater than the capacitance of circuit 401, the potential dV becomes close to the second data potential V. data The potential.

[0290] As described above, since the pixel circuit 400 can combine two data signals to generate a potential supplied to the circuit 401 including the display element, grayscale correction can be performed within the pixel circuit 400.

[0291] Furthermore, the pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to the source driver connected to wiring S1 and wiring S2. For example, when using a light-emitting element, high dynamic range (HDR) display can be achieved. Furthermore, when using a liquid crystal element, overdriving can be implemented.

[0292] [Application Example] [Examples of using liquid crystal elements] Figure 19C The pixel circuit 400LC shown includes circuit 401LC. Circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0293] One electrode of the liquid crystal element LC is connected to node N2 and one electrode of capacitor C2, and the other electrode is connected to the supplied potential V. com2 The wiring connection. The other electrode of capacitor C2 is connected to the supplied potential V. com1 Wiring connections.

[0294] Capacitor C2 is used as a storage capacitor. Furthermore, capacitor C2 can be omitted when it is not needed.

[0295] Since the pixel circuit 400LC can provide a high voltage to the liquid crystal element LC, high-speed display can be achieved, for example, through overdrive, and liquid crystal materials with high driving voltage can be used. Furthermore, by providing a correction signal to wiring S1 or wiring S2, grayscale correction can be performed based on factors such as operating temperature and the degradation state of the liquid crystal element LC.

[0296] [Example of using light-emitting elements] Figure 19D The pixel circuit 400EL shown includes circuit 401EL. Circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0297] The gate of transistor M3 is connected to node N2 and one electrode of capacitor C2, and one of the source and drain terminals is connected to the supplied potential V. H The wiring connection is such that one of the source and drain electrodes is connected to one electrode of the light-emitting element EL. The other electrode of capacitor C2 is connected to the supplied potential V. com The wiring connection. The other electrode of the light-emitting element EL is connected to the supplied potential V. L Wiring connections.

[0298] Transistor M3 controls the current supplied to the light-emitting element EL. Capacitor C2 is used as a storage capacitor. Capacitor C2 can be omitted when not needed.

[0299] Furthermore, although the structure shown here has the anode side of the light-emitting element EL connected to the transistor M3, a structure with the cathode side connected to the transistor M3 can also be used. In this case, the potential V can be appropriately changed. H With potential V L The value of .

[0300] The pixel circuit 400EL can achieve HDR display by applying a high potential to the gate of transistor M3 to allow a large current to flow through the light-emitting element EL. In addition, by supplying a correction signal to wiring S1 or wiring S2, the non-uniformity of the electrical characteristics of transistor M3, light-emitting element EL, etc. can be corrected.

[0301] Note that this is not limited to Figure 19C and Figure 19D The circuit shown can also be constructed using additional transistors, capacitors, etc.

[0302] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0303] (Implementation Method 4) In this embodiment, a structural example of a touch panel module including a touch panel and an IC is described.

[0304] Figure 20 A block diagram of a touch panel module 6500 is shown. The touch panel module 6500 includes a touch panel 6510 and an IC 6520.

[0305] The touch panel 6510 includes a display unit 6511, an input unit 6512, a scan line driving circuit 6513, a sensor driving circuit 6503, and a detection circuit 6504. The display unit 6511 includes multiple pixels, multiple signal lines, and multiple scan lines, and has the function of displaying images. The input unit 6512 includes multiple sensor elements that sense the contact or proximity of a sensing object to the touch panel 6510, and is used as a touch sensor. The scan line driving circuit 6513 has the function of outputting scan signals to the scan lines in the display unit 6511.

[0306] The sensor drive circuit 6503 has the function of outputting a signal to drive the sensor element in the input section 6512. The sensor drive circuit 6503 may, for example, have a structure that combines a shift register circuit and a buffer circuit.

[0307] The detection circuit 6504 has the function of amplifying the output signal from the sensor element in the input section 6512 and outputting it to the AD conversion circuit 6507.

[0308] Here, although the display unit 6511 and the input unit 6512 are shown separately as the structure of the touch panel 6510 for ease of explanation, a so-called In-Cell type touch panel that combines the functions of displaying images and touch sensors can also be used.

[0309] As a type of touch sensor that can be used as the input unit 6512, a capacitive type can be used, for example. Among capacitive types, there are surface-type capacitive sensors and projection-type capacitive sensors. Among projection-type capacitive sensors, there are self-capacitance type and mutual-capacitance type. Mutual-capacitance type is preferred, as it allows for simultaneous multi-point detection.

[0310] Note that this is not the only limitation; various sensors capable of sensing the proximity, contact, or pressure of objects such as fingers or styluses can also be used in the input section 6512. For example, in addition to capacitive sensors, resistive film sensors, surface acoustic wave sensors, infrared sensors, optical sensors, and other types can also be used as sensors.

[0311] In-cell touch panels typically include hybrid-in-cell and full-in-cell types. A hybrid-in-cell type refers to a structure where electrodes constituting a touch sensor are provided on both the substrate supporting the display element and the opposing substrate, or on the opposing substrate. Conversely, a full-in-cell type refers to a structure where electrodes constituting a touch sensor are provided on the substrate supporting the display element. Using a full-in-cell type touch panel simplifies the structure of the opposing substrate, making it preferable. Especially in the full-in-cell type, by using the electrodes constituting the display element as well as the electrodes constituting the touch sensor, the manufacturing process is simplified, thereby reducing manufacturing costs, making it even more preferable.

[0312] The display unit 6511 preferably has extremely high resolutions such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K (3840×2160 pixels), and 8K (7680×4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display unit 6511 is preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 800 ppi or higher, even more preferably 1000 ppi or higher, and even more preferably 1200 ppi or higher. Such a display unit 6511 with high resolution and high definition can further improve realism, depth perception, etc.

[0313] IC6520 includes circuit unit 6501, signal line driver circuit 6502, and AD conversion circuit 6507. Circuit unit 6501 includes timing controller 6505 and image processing circuit 6506, etc.

[0314] The signal line driving circuit 6502 has the function of outputting an image signal (also known as a video signal) as an analog signal to the signal lines in the display unit 6511. For example, the signal line driving circuit 6502 may have a structure that combines a shift register, a digital-to-analog converter (DAC), a latch circuit, a buffer circuit, etc. In addition, the touch panel 6510 may include a demultiplexer circuit connected to the signal lines.

[0315] The AD conversion circuit 6507 has the function of converting the analog signal input from the detection circuit 6504 into a digital signal and outputting it to the circuit unit 6501. For example, the AD conversion circuit 6507 may include an analog-to-digital converter (ADC) and an amplifier circuit.

[0316] The image processing circuit 6506 in the circuit unit 6501 has the following functions: generating and outputting signals that drive the display unit 6511 of the touch panel 6510; generating and outputting signals that drive the input unit 6512; and analyzing the signals output from the input unit 6512 and outputting them to the CPU 6540.

[0317] As a more specific example, the image processing circuit 6506, for instance, has the function of generating image signals according to instructions from the CPU 6540. Furthermore, the image processing circuit 6506 has the function of performing signal processing on the image signals according to the specifications of the display unit 6511 to convert them into analog image signals, and supplying them to the signal line drive circuit 6502. In addition, the image processing circuit 6506 has the function of generating drive signals output to the sensor drive circuit 6503 according to instructions from the CPU 6540. The image processing circuit 6506 also has the function of analyzing the signal input from the detection circuit 6504 via the AD conversion circuit 6507 and outputting it as position information to the CPU 6540.

[0318] The timing controller 6505 has the following function: it generates signals (clock signals, start pulse signals, etc.) output to the scan line drive circuit 6513 and the sensor drive circuit 6503 based on synchronization signals in the image signals processed by the image processing circuit 6506, and outputs them. The timing controller 6505 may also have the function of generating signals that specify the timing of the output signals of the detection circuit 6504 and outputting them. Here, the timing controller 6505 preferably outputs signals that are synchronized with the signals output to the scan line drive circuit 6513 and the signals output to the sensor drive circuit 6503, respectively. In particular, it is preferable to separate the period for rewriting the pixel data of the display unit 6511 from the period for sensing in the input unit 6512. For example, the touch panel 6510 can be driven by dividing a frame period into a period for rewriting pixel data and a sensing period. Furthermore, for example, by setting two or more sensing periods within a frame period, detection sensitivity and detection accuracy can be improved.

[0319] The image processing circuit 6506 may include, for example, a processor. For instance, it may use a microprocessor such as a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit). These microprocessors may also be constructed from PLDs (Programmable Logic Devices) such as FPGAs (Field Programmable Gate Arrays) or FPAAs (Field Programmable Analog Arrays). The image processing circuit 6506 performs various data processing and program control by interpreting and executing instructions from various programs by the processor. The programs executed by the processor may be stored in the processor's memory area or in a separately configured storage device.

[0320] Furthermore, it is preferable that one or more of the display unit 6511, input unit 6512, scan line drive circuit 6513, sensor drive circuit 6503, and detection circuit 6504 included in the touch panel 6510 use transistors with extremely small off-state currents achieved by using oxide semiconductors in the channel forming region. Because the off-state current of this transistor is extremely small, by using this transistor as a switch to maintain the charge (data) flowing into the capacitor used as a storage element, long-term data retention can be ensured. Alternatively, this transistor can also be used in the circuit unit 6501 included in the IC 6520, the signal line drive circuit 6502, the AD conversion circuit 6507, or in an external CPU 6540, etc. For example, by applying this feature to the registers or cache memory of the image processing circuit 6506, the image processing circuit 6506 can be operated only when necessary, while previously processed information is stored in the storage element under other circumstances. Thus, the power supply to the image processing circuit 6506 can be cut off when the image processing circuit 6506 is not in use, which can realize normally-off computing. This enables low power consumption of the touch panel module 6500 and the electronic device on which the touch panel module 6500 is installed.

[0321] Note that although the circuit unit 6501 shown here includes a timing controller 6505 and an image processing circuit 6506, the image processing circuit 6506 itself or a circuit having some of the functions of the image processing circuit 6506 can also be placed outside the IC 6520. Alternatively, the CPU 6540 can perform all or part of the functions of the image processing circuit 6506. For example, the circuit unit 6501 can also be structured to include a signal line drive circuit 6502, a timing controller 6505, and an AD conversion circuit 6507.

[0322] Furthermore, although an example of IC 6520 including circuit unit 6501 is shown here, circuit unit 6501 may also be excluded from IC 6520. In this case, IC 6520 may adopt a structure including signal line driving circuit 6502 and AD conversion circuit 6507. For example, when multiple ICs are installed in the touch panel module 6500, multiple ICs 6520 without circuit unit 6501 can be configured by separately providing ICs including circuit unit 6501, or ICs including only IC 6520 and signal line driving circuit 6502 can be combined.

[0323] Thus, by combining the functions of the display unit 6511 driving the touch panel 6510 and the driving input unit 6512 into one IC, the number of ICs installed in the touch panel module 6500 can be reduced, thereby reducing costs.

[0324] Figure 21A , Figure 21B , Figure 21C This is a schematic diagram of a touch panel module 6500 with IC6520 installed.

[0325] Figure 21A The touch panel module 6500 shown includes a substrate 6531, a counter substrate 6532, multiple FPCs 6533, IC 6520, IC 6530, etc. Between the substrate 6531 and the counter substrate 6532 are a display unit 6511, an input unit 6512, a scan line driving circuit 6513, a sensor driving circuit 6503, and a detection circuit 6504. IC 6520 and IC 6530 are mounted on the substrate 6531 using a COG (Chip On Glass) mounting method or similar method.

[0326] IC6530 is an IC that includes only the signal line driver circuit 6502, or includes both the signal line driver circuit 6502 and circuit unit 6501, as described above in IC6520. Signals are supplied to IC6520 and IC6530 from the outside via FPC6533. Additionally, signals can be output from IC6520 or IC6530 to the outside via FPC6533.

[0327] Figure 21A An example structure is shown where two scan line drive circuits 6513 are arranged to sandwich the display unit 6511. A structure including IC 6520 and IC 6530 is also shown. This structure is suitable for applications requiring extremely high resolution for the display unit 6511.

[0328] Figure 21BAn example is shown with one IC6520 and one FPC6533 installed. Thus, by concentrating functionality into a single IC6520, the number of components can be reduced, making it preferable. Furthermore, Figure 21B An example is shown where the scan line drive circuit 6513 is arranged along one of the two short sides of the display section 6511, closer to the side of the FPC 6533.

[0329] Figure 21C An example structure of a PCB (Printed Circuit Board) 6534, including an image processing circuit 6506 and the like, is shown. ICs 6520 and 6530 on substrate 6531 are electrically connected to PCB 6534 via FPC 6533. Here, IC 6520 may not include the aforementioned image processing circuit 6506.

[0330] Note that in Figure 21A , Figure 21B and Figure 21C In this case, IC6520 and IC6530 can also be mounted on FPC6533 instead of on substrate 6531. For example, IC6520 and IC6530 can be mounted on FPC6533 using COF or TAB mounting methods.

[0331] like Figure 21A and Figure 21B As shown, the structure of arranging FPC6533, IC6520 (and IC6530), etc. on the short side of the display unit 6511 can achieve a narrow bezel, so it can be applied to electronic devices such as smartphones, mobile phones, or tablet terminals. Furthermore, as... Figure 21C The structure shown using PCB6534 can be applied to devices such as televisions, monitors, tablets, or notebook computers.

[0332] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0333] (Implementation Method 5) In this embodiment, an electronic device according to one aspect of the present invention will be described.

[0334] The electronic device of this embodiment includes a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made to achieve high definition and high resolution. Therefore, it can be used in the display units of various electronic devices.

[0335] Furthermore, the semiconductor device according to one aspect of the present invention can also be used in parts of an electronic device other than the display unit. For example, when the semiconductor device according to one aspect of the present invention is used in the control unit of an electronic device, low power consumption can be achieved, so it is preferred.

[0336] As electronic devices, in addition to large-screen electronic devices such as television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game machines such as pinball machines, other examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0337] In particular, because the display device according to one aspect of the present invention can improve clarity, it can be used in electronic devices that include a smaller display section. Examples of such electronic devices include watch-type and bracelet-type information terminal devices (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0338] The electronic device of this embodiment may include a sensor (which has the function of detecting, identifying or measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor or infrared radiation).

[0339] The electronic device of this embodiment can have various functions. For example, it can have the following functions: displaying various information (static images, dynamic images, text images, etc.) on the display unit; touch panel function; displaying calendar, date, or time, etc.; executing various software (programs); wireless communication function; reading programs or data stored in the storage medium; etc.

[0340] Figure 22A The electronic device 7000 shown is a portable information terminal device that can be used as a smartphone.

[0341] Electronic device 7000 includes a frame 7001, a display unit 7002, a power button 7003, a button 7004, a speaker 7005, a microphone 7006, a camera 7007, and a light source 7008, etc. The display unit 7002 has a touch panel function.

[0342] The display device according to one aspect of the present invention can be used in the display unit 7002.

[0343] Figure 22B This is a cross-sectional schematic diagram of one end of the microphone 7006, including the frame 7001.

[0344] A light-transmitting protective component 7010 is provided on one side of the display surface of the frame 7001. The display panel 7011, optical component 7012, touch sensor panel 7013, printed circuit board 7017, battery 7018, etc. are arranged in the space surrounded by the frame 7001 and the protective component 7010.

[0345] The display panel 7011, optical component 7012, and touch sensor panel 7013 are fixed to the protective component 7010 using an adhesive layer (not shown).

[0346] In the area outside the display unit 7002, a portion of the display panel 7011 is folded back, and this folded portion is connected to an FPC 7015. An IC 7016 is mounted on the FPC 7015. The FPC 7015 is connected to terminals provided on a printed circuit board 7017.

[0347] The display panel 7011 can be used with a display device according to one aspect of the present invention. This allows for the realization of an extremely lightweight electronic device. Furthermore, since the display panel 7011 is extremely thin, a large-capacity battery 7018 can be installed while minimizing the thickness of the electronic device. Additionally, by folding a portion of the display panel 7011 to provide a connection portion with the FPC 7015 on the back of the pixel section, a narrow-bezel electronic device can be achieved.

[0348] Figure 22C An example of a television device is shown. In the television device 7100, a display unit 7002 is assembled in a frame 7101. Here is shown the structure in which the frame 7101 is supported by a bracket 7103.

[0349] The display device according to one aspect of the present invention can be used in the display unit 7002.

[0350] Figure 22C The television device 7100 shown can be operated using the operation switch provided in the housing 7101 and the separately provided remote control 7111. Alternatively, a touch sensor may be provided in the display unit 7002, allowing operation of the television device 7100 by touching the display unit 7002 with a finger or similar object. The remote control 7111 may also include a display unit that displays information output from the remote control 7111. Channel and volume adjustments can be made using the operation keys or touch panel provided in the remote control 7111, and the images displayed on the display unit 7002 can also be manipulated.

[0351] Furthermore, the television device 7100 includes a receiver and a modem. It can receive general television broadcasts using the receiver. Moreover, it can connect to a wired or wireless communication network via the modem to conduct one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0352] Figure 22D An example of a notebook computer is shown. The notebook computer 7200 includes a chassis 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7002 is assembled in the chassis 7211.

[0353] The display device according to one aspect of the present invention can be used in the display unit 7002.

[0354] Figure 22E and Figure 22F Here is an example of digital signage.

[0355] Figure 22E The digital sign 7300 shown includes a frame 7301, a display unit 7002, and a speaker 7303. It may also include LEDs, operation buttons (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0356] Figure 22F A digital sign 7400 is shown mounted on a cylindrical column 7401. The digital sign 7400 includes a display section 7002 disposed along the curved surface of the column 7401.

[0357] exist Figure 22E and Figure 22F In this embodiment, a display device according to one aspect of the present invention can be used in the display unit 7002.

[0358] The larger the display unit 7002, the more information it can provide at once. A larger display unit 7002 is also more likely to attract attention, which can improve the effectiveness of advertising.

[0359] By using a touch panel for the display unit 7002, not only can static or dynamic images be displayed on the display unit 7002, but users can also operate it intuitively, making it preferable. Furthermore, when used to provide information such as route information or traffic information, intuitive operation enhances ease of use.

[0360] like Figure 22E and Figure 22FAs shown, digital signage 7300 or 7400 preferably connects wirelessly with information terminal devices 7311 or 7411, such as smartphones carried by the user. For example, advertising information displayed on display unit 7002 can be displayed on the screen of information terminal device 7311 or 7411. Furthermore, the display on display unit 7002 can be switched by operating information terminal device 7311 or 7411.

[0361] The game can be executed on the digital signage 7300 or 7400 using the screen of information terminal device 7311 or 7411 as the operating unit (controller). Thus, multiple users can participate in the game simultaneously and enjoy the experience.

[0362] Figures 23A to 23G The electronic device shown includes a frame 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of sensing, detecting, and measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0363] exist Figures 23A to 23G In this embodiment, a display device according to one aspect of the present invention can be used in the display unit 9001.

[0364] Figures 23A to 23G The electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, and text images, etc.) on a display unit; a touch panel function; displaying a calendar, date, or time, etc.; controlling processing using various software (programs); wireless communication function; reading and processing programs or data stored in a storage medium; etc. Note that the functions of the electronic device are not limited to the above functions, and it may have various functions. The electronic device may also include multiple display units. In addition, a camera or the like may be installed in the electronic device to give it the following functions: capturing still or moving images and storing the captured images in a storage medium (external storage medium or storage medium built into the camera); displaying the captured images on a display unit; etc.

[0365] The following is a detailed explanation. Figures 23A to 23G The electronic device shown.

[0366] Figure 23AThis is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used, for example, as a smartphone. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc., may also be included in the portable information terminal 9101. Furthermore, as a portable information terminal 9101, text or image information can be displayed on multiple surfaces. Figure 23A The image shows an example displaying three icons 9050. Furthermore, information 9051, shown as a dashed rectangle, can be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of received emails, SNS messages, or phone calls; the subject of the email or SNS message; the sender's name; the date; the time; remaining battery level; and radio wave strength. Alternatively, icons 9050 can be displayed in the same location where information 9051 is displayed.

[0367] Figure 23B This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can check information 9053 displayed in a position visible from above the portable information terminal 9102. For example, the user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining whether to answer a phone call.

[0368] Figure 23C This is a perspective view of a tablet terminal 9103. The tablet terminal 9103 can, for example, execute various application software such as mobile phone, email, and article reading and editing, music playback, network communication, and computer games. The tablet terminal 9103 includes a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the frame 9000; operation keys 9005 serving as operating buttons on the left side of the frame 9000; and a connection terminal 9006 on the bottom surface.

[0369] Figure 23D This is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Furthermore, the display surface of the display unit 9001 is curved, allowing display along its curved surface. Additionally, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. Furthermore, by utilizing the connection terminal 9006, the portable information terminal 9200 can transmit data or charge with other information terminals. Charging can also be performed wirelessly.

[0370] Figures 23E to 23G This is a perspective view showing the foldable portable information terminal 9201. Additionally, Figure 23E This is a 3D view of the portable information terminal 9201 in its unfolded state. Figure 23G It is a 3D image of the folded state. Figure 23F From Figure 23E status and Figure 23G The portable information terminal 9201 is a three-dimensional representation of the state transitioning between different states. In its folded state, it offers good portability, while in its unfolded state, it provides a large, seamless display area, resulting in excellent browsing capabilities. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. The display unit 9001 can be bent, for example, within a radius of curvature of 0.1 mm or more and 150 mm or less.

[0371] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0372] [Symbol Explanation] 10: Transistor, 10a: Transistor, 10b: Transistor, 10c: Transistor, 10d: Transistor, 11: Insulating layer, 12: Substrate, 21: Semiconductor layer, 21a: Semiconductor layer, 21AC: Region, 21b: Semiconductor layer, 21c: Semiconductor layer, 21d: Semiconductor layer, 22: Insulating layer, 23: Conductive layer, 23f: Conductive film, 24: Conductive layer, 24a: Conductive layer, 24b: Conductive layer, 25: Conductive layer, 25f: Conductive film, 30: Liquid crystal element, 31: Liquid crystal, 32: Conductive layer, 35a: Alignment film, 35b: Alignment film, 36: Conductive layer, 41: Insulating layer, 41a: Insulating layer, 41b: Insulating layer, 41c: Insulating layer, 41p: Partial, 41q : Part, 42: Insulating layer, 43: Insulating layer, 51: Coloring layer, 52: Light-shielding layer, 53: Insulating layer, 54: Insulating layer, 55: Pixel, 56B: Sub-pixel, 56G: Sub-pixel, 56R: Sub-pixel, 400: Pixel circuit, 400EL: Pixel circuit, 400LC: Pixel circuit, 401: Circuit, 401EL: Circuit, 401LC: Circuit, 501: Pixel circuit, 502: Pixel section, 504: Driving circuit section, 504a: Gate driver, 504b: Source driver, 506: Protection circuit, 507: Terminal section, 550: Transistor, 552: Transistor, 554: Transistor, 560: Capacitor, 562: Capacitor, 570: Liquid crystal element, 572 6500: Light-emitting element; 6501: Touch panel module; 6502: Circuit unit; 6503: Signal line driving circuit; 6504: Sensor driving circuit; 6505: Detection circuit; 6506: Timing controller; 6507: Image processing circuit; 6510: AD conversion circuit; 6511: Touch panel; 6512: Display unit; 6513: Scan line driving circuit; 6520: IC; 6530: IC; 6531: Substrate; 6532: Opposite substrate; 6533: FPC; 6534: PCB; 6540: CPU; 7000: Electronic device; 7001: Frame; 7002: Display unit; 7003: Power button; 7004: Button; 700... 5: Speaker; 7006: Microphone; 7007: Camera; 7008: Light Source; 7010: Protective Component; 7011: Display Panel; 7012: Optical Component; 7013: Touch Sensor Panel; 7015: FPC; 7016: IC; 7017: Printed Circuit Board; 7018: Battery; 7100: Television Unit; 7101: Frame; 7103: Stand; 7111: Remote Control Unit; 7200: Notebook Computer; 7211: Frame; 7212: Keyboard; 7213: Pointing Device; 7214: External Connection Port; 7300: Digital Signage; 7301: Frame; 7303: Speaker; 7311: Information Terminal Equipment; 7400: Digital Signage.7401: Column; 7411: Information terminal equipment; 9000: Frame; 9001: Display unit; 9002: Camera; 9003: Speaker; 9005: Operation keys; 9006: Connection terminal; 9007: Sensor; 9008: Microphone; 9050: Icon; 9051: Information; 9052: Information; 9053: Information; 9054: Information; 9055: Hinge; 9101: Portable information terminal; 9102: Portable information terminal; 9103: Tablet terminal; 9200: Portable information terminal; 9201: Portable information terminal.

Claims

1. A semiconductor device, comprising: First conductive layer; Second conductive layer; Third conductive layer; First semiconductor layer; First insulating layer; as well as Second insulating layer, The first insulating layer has an island-like shape and includes a first surface located on the first conductive layer. The first surface is a portion of the side surface of the first insulating layer and has two or more regions with normal directions that are different from each other. The second conductive layer is located on the first insulating layer. The first semiconductor layer has a first portion that contacts the top surface of the first conductive layer, a second portion that contacts the top surface of the second conductive layer, and a third portion that contacts the first surface of the first insulating layer. The second insulating layer covers the third portion of the first semiconductor layer. Furthermore, the third conductive layer covers the third portion of the first semiconductor layer through the second insulating layer.

2. The semiconductor device according to claim 1, The first surface of the first insulating layer has two orthogonal planes on the first conductive layer.

3. The semiconductor device according to claim 1, The first surface of the first insulating layer has a curved shape on the first conductive layer.

4. The semiconductor device according to claim 1, The end of the second insulating layer is aligned with the third conductive layer.

5. The semiconductor device according to claim 1, further comprising: Second semiconductor layer, The first insulating layer has a second surface that is another part of its side surface and is located on the first conductive layer. The second semiconductor layer has a fourth portion that contacts the second surface. Furthermore, the second insulating layer covers the fourth portion of the second semiconductor layer.

6. The semiconductor device according to claim 5, The second semiconductor layer has a fifth portion that contacts the top surface of the first conductive layer and a sixth portion that contacts the top surface of the second conductive layer.

7. The semiconductor device according to claim 1, further comprising: Second semiconductor layer; as well as Fourth conductive layer The first insulating layer has a third surface that is another part of its side surface and is located on the fourth conductive layer. The second semiconductor layer has a fifth portion that contacts the top surface of the fourth conductive layer, a sixth portion that contacts the top surface of the second conductive layer, and a seventh portion that contacts the third surface. Furthermore, the second insulating layer covers the seventh portion of the second semiconductor layer.

8. A display device, comprising: The semiconductor device according to any one of claims 1 to 7; as well as Liquid crystal components, The liquid crystal element includes a portion of the second conductive layer, liquid crystal, and a fifth conductive layer. The liquid crystal is located on the second conductive layer. The second conductive layer is used as a pixel electrode. Furthermore, the fifth conductive layer is used as a common electrode.

9. The display device according to claim 8, further comprising: A third insulating layer covering the second conductive layer, the third conductive layer, and the second insulating layer.

10. The display device according to claim 8, The second conductive layer has a region that does not overlap with the first insulating layer. And the region is used as the pixel electrode.

11. A display device, comprising: First conductive layer; Third conductive layer; First semiconductor layer; First insulating layer; Second insulating layer; as well as Liquid crystal components, The first insulating layer has an island-like shape and includes a first surface that is part of its side surface and is located on the first conductive layer. The first semiconductor layer has a first portion that contacts the top surface of the first conductive layer, a third portion that contacts the first surface of the first insulating layer, and an eighth portion located on the first insulating layer. The second insulating layer covers the third portion of the first semiconductor layer. The third conductive layer covers the third portion of the first semiconductor layer through the second insulating layer. The liquid crystal element includes a portion of the first semiconductor layer, liquid crystal, and a fifth conductive layer. The liquid crystal is located on the first semiconductor layer. A portion of the first semiconductor layer is used as a pixel electrode. Furthermore, the fifth conductive layer is used as a common electrode.

12. The semiconductor device according to claim 11, The first semiconductor layer has a ninth portion that does not overlap with the first insulating layer. And the ninth part is used as the pixel electrode.

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