自对准背侧沟道去除
By introducing back-side channel plugs and adjusting the number of channels in the semiconductor structure, the problems of power consumption optimization and capacitor edge limitation in nanosheet FET devices are solved, achieving efficient scaling and performance optimization of transistor structures.
CN122423328APending Publication Date: 2026-07-17INTERNATIONAL BUSINESS MACHINE CORPORATION
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2024-11-17
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing technologies face challenges in power consumption optimization and capacitor edge limitations when scaling transistor device dimensions, especially in nanosheet FET devices, where it is difficult to achieve power savings and performance optimization by scaling the RX width.
Method used
By introducing back-side channel plugs into the semiconductor structure, adjusting the number and structure of channels, and combining etching techniques to remove unnecessary gate and channel regions, the channel layer stacking is optimized to meet design requirements.
Benefits of technology
This achieves transistor structures that optimize performance and power consumption while reducing device footprint, thus meeting various design constraints.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN122423328A_ABST
Abstract
一种半导体结构，包括半导体层的第一堆叠、半导体层的第二堆叠以及在半导体层的第一堆叠正下方的背侧沟道插塞，其中半导体层的第一堆叠比半导体层的第二堆叠少至少一层。
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