Display device

Abstract

An embodiment of the present invention discloses a display device including a display area and a non-display area outside the display area. The display device includes: islands arranged in the display area and spaced apart from each other; bridging portions connecting adjacent islands; and wirings arranged in the bridging portions, wherein each wiring includes a first layer, and the first layer includes a first sub-layer comprising an alloy containing aluminum and rare earth elements and a second sub-layer comprising aluminum.

Description

Technical Field

[0001] The disclosed embodiments relate to a display device, such as a flexible display device. Background Technology

[0002] Due to the development of display devices designed to visually display electrical signals, various display devices with excellent characteristics such as thinness, lightness, and low power consumption have been introduced. For example, flexible display devices that can be folded or rolled up have been introduced. Recently, stretchable display devices that can be transformed into various shapes have been under research and development. Summary of the Invention

[0003] Technical issues The disclosed embodiments provide a flexible display device, such as a stretchable display device. However, the technical objectives are merely illustrative, and the scope of the embodiments is not limited thereto.

[0004] Solution to the problem In one aspect of the invention, a display device including a display area and a non-display area outside the display area includes: islands arranged in the display area and spaced apart from each other; bridging portions connecting adjacent islands; and wiring arranged in each of the bridging portions, wherein each of the wirings includes a first layer, the first layer including a first sublayer and a second sublayer, and the first sublayer including an alloy of aluminum (Al) and rare earth elements, and the second sublayer including aluminum.

[0005] In another aspect of the invention, the display device includes a display area and a non-display area outside the display area. The display device includes: islands disposed in the display area and each including a transistor and a light-emitting element electrically connected to the transistor; and bridging portions connecting adjacent islands, wherein each bridging portion includes wiring electrically connected to a transistor in any of the adjacent islands, the wiring including a first layer, and the first layer including a first sublayer and a second sublayer, the first sublayer including an alloy of aluminum and rare earth elements, and the second sublayer including aluminum.

[0006] Beneficial effects of the invention According to embodiments, a display device capable of preventing damage caused by stress concentration and stretching (extension) or contraction in various directions can be provided. However, the scope of the disclosure is not limited thereto. Attached Figure Description

[0007] Figure 1 This is a perspective view schematically showing a display device according to an embodiment.

[0008] Figure 2a and Figure 2b Each is shown Figure 1The perspective view of the display device shown is in a stretched state in a first direction.

[0009] Figure 2c It is shown Figure 1 The perspective view of the display device shown is in a stretched state in the second direction.

[0010] Figure 2d It is shown Figure 1 The perspective view of the display device shown is in a stretched state in the first and second directions.

[0011] Figure 2e It is shown Figure 1 The display device shown is a perspective view of a third-party stretched-up state.

[0012] Figure 3 This is a schematic plan view of a display device according to an embodiment.

[0013] Figure 4a It is part of the display device according to the embodiment. Figure 3 The enlarged plan view of part IV is shown in the figure.

[0014] Figure 4b It is part of a display device according to another embodiment. Figure 3 The enlarged plan view of part IV is shown in the figure.

[0015] Figure 4c It is a part of a display device according to yet another embodiment. Figure 3 The enlarged plan view of part IV is shown in the figure.

[0016] Figure 5 This is a schematic cross-sectional view showing a first island and a first bridging portion arranged in the display area of ​​a display device according to an embodiment.

[0017] Figures 6a to 6c Each is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment.

[0018] Figure 7a This is a schematic cross-sectional view of the light-emitting element of the display device according to an embodiment.

[0019] Figure 7b This is a schematic cross-sectional view of the light-emitting element of the display device according to an embodiment.

[0020] Figure 8a This is an enlarged plan view of the first island portion of the display device according to an embodiment.

[0021] Figure 8b This is a plan view showing the arrangement of wiring in the first bridging section of the display device according to an embodiment.

[0022] Figure 9 It shows along Figure 8a The cross section shown is taken along line I-I' and along Figure 8b The cross section shown is taken by line II-II'.

[0023] Figure 10 This is a cross-sectional view of the conductive layer forming the wiring or connection electrodes of the display device according to an embodiment.

[0024] Figure 11 This is a cross-sectional view of the conductive layer of a display device according to another embodiment.

[0025] Figure 12 This is a cross-sectional view of the conductive layer of a display device based on a comparative example.

[0026] Figure 13 This is a flowchart illustrating a method for manufacturing an alloy layer including a conductive layer according to an embodiment.

[0027] Figure 14 The microstructure of the alloy layer according to an embodiment is shown.

[0028] Figure 15 The microstructure of the conductive layer according to an embodiment is shown.

[0029] Figure 16 This is a graph showing the resistivity of the conductive layer according to an embodiment.

[0030] Figure 17 This is a graph showing the resistivity of the conductive layer according to the embodiments and comparative examples.

[0031] Figure 18 This is a graph showing the results of a tensile test on a conductive layer based on a comparative example.

[0032] Figure 19 This is a graph showing the results of a tensile test on the conductive layer according to an embodiment.

[0033] Figure 20 This is a graph showing the results of a tensile test on a conductive layer according to other embodiments.

[0034] Figures 21a to 21g Each is a perspective view schematically illustrating an embodiment of an electronic device including a display device according to an embodiment. Detailed Implementation

[0035] Best embodiment of the invention In an embodiment, each of the first sub-layer and the second sub-layer can be configured as multiple, and the first layer can have a structure in which the first sub-layer and the second sub-layer are stacked alternately.

[0036] In an embodiment, the two first sub-layers in the first sub-layer can be respectively disposed on the top and bottom of the first layer.

[0037] In an embodiment, the first sublayer may include an amorphous alloy layer.

[0038] In the embodiments, rare earth elements may include at least one of yttrium (Y), samarium (Sm), cerium (Ce) and lanthanum (La).

[0039] In the embodiments, the content of rare earth elements may be from 4 atomic percentages (at%) to 10 at, relative to the total atomic weight of the first sublayer.

[0040] In an embodiment, the ratio of the thickness of each of the first sublayers to the thickness of each of the second sublayers can be greater than 0 and not greater than 1.

[0041] In an embodiment, the resistivity of the first layer can be greater than 5.6 micro ohm-cm (μΩ·cm) and less than 11 micro ohm-cm (μΩ·cm).

[0042] In this embodiment, the elastic strain limit of the first layer can be at least 2.0%.

[0043] In an embodiment, the yield strength of the first layer can be from 0.8 gigapascals (GPa) to 1.2 GPa.

[0044] In an embodiment, each of the wirings may further include a second layer below the first layer and a third layer above the first layer, and the second and third layers may include materials different from those of the first layer.

[0045] In an embodiment, each of the islands may include: a transistor, including a semiconductor and a gate electrode; a light-emitting element electrically connected to the transistor; and an electrode disposed between the gate electrode and the light-emitting element, wherein the electrode may include a third sublayer and a fourth sublayer, the third sublayer comprising an alloy of aluminum and rare earth elements, and the fourth sublayer comprising aluminum.

[0046] Embodiments of the Invention The disclosure can be modified in various ways and can have various embodiments, and specific embodiments will be shown in the accompanying drawings and described in detail in the specific implementation. The effects and features of the disclosure, as well as the methods of implementing it, will become apparent with reference to the embodiments described in detail below and the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms.

[0047] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and when describing with reference to the drawings, the same or corresponding components will be given the same reference numerals, and repeated descriptions thereof will be omitted.

[0048] In the following embodiments, the terms first, second, etc. are not intended to be limiting, but are used to distinguish one component from another.

[0049] In the following embodiments, unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0050] In the embodiments below, the terms "comprising" or "having" are intended to imply the presence of the said feature or component, and do not exclude the possibility of adding one or more other features or components.

[0051] In the following embodiments, when a portion of a membrane, region, component, etc. is referred to as being on or above another portion, this includes not only the case where the portion is directly on the other portion, but also the case where other membranes, regions, components, etc. are arranged between the portion and the other portion.

[0052] In the accompanying drawings, the dimensions of components may be exaggerated or reduced for ease of illustration. For example, for ease of description, the dimensions and thicknesses of each structure shown in the drawings are arbitrary, and the disclosure is not limited to those shown.

[0053] In some embodiments, a particular process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously, or two consecutively described processes may be performed in the reverse order of their description.

[0054] As used here, "A and / or B" means A, B, or both A and B. Additionally, "at least one of A and B" means A, B, or both A and B.

[0055] In the following embodiments, membranes, regions, components, etc., are referred to as connections, including direct connections between membranes, regions, components, and / or indirect connections between membranes, regions, and components in which other membranes, regions, and components are arranged. For example, when membranes, regions, components, etc., are referred to herein as electrical connections, it means direct electrical connections between membranes, regions, components, etc., and / or indirect electrical connections with membranes, regions, components, etc., in which other membranes, regions, components, etc., are arranged between them.

[0056] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense that includes the three axes of a Cartesian coordinate system. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0057] As used herein, “about” or “approximately” includes the stated value and indicates that, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system), it is within an acceptable deviation for the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±10%, ±5%, or ±2% of the stated value.

[0058] Figure 1 This is a schematic perspective view of the display device 1 according to an embodiment. Figure 2a and Figure 2b Each is shown Figure 1 The perspective view of the display device 1 shown is in a stretched state in a first direction. Figure 2c It is shown Figure 1 The perspective view of the display device 1 shown is stretched in the second direction. Figure 2d It is shown Figure 1 The perspective view of the display device 1 shown is in a stretched state in the first and second directions. Figure 2e It is shown Figure 1 The view shown is a perspective view of the display device 1 stretched upwards from a third-party perspective.

[0059] Reference Figure 1 The display device 1 may include a display area DA and a non-display area NDA. The display area DA may include pixels. The display device 1 may be configured to provide a specific image by using light emitted from the pixels. The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may generally surround the display area DA.

[0060] The display device 1 can extend or retract in various directions. Due to external forces applied by external objects or the user, the display device 1 can extend in a first direction (e.g., the x-direction and / or the -x-direction). In embodiments, such as Figure 2a and Figure 2b As shown, the display area DA and / or non-display area NDA of the display device 1 can extend in a first direction (e.g., the x-direction and / or the -x-direction). For example, the display area DA and / or non-display area NDA can be as follows: Figure 2a As shown, it extends in the x-direction and the -x-direction, or it can be as follows: Figure 2b It extends in the x-direction while being fixed on one side of the display device.

[0061] The display device 1 can extend in a second direction (e.g., the y-direction and / or the -y-direction) by an external force applied by an external object or a user. In an embodiment, as... Figure 2cAs shown, the display area DA and / or non-display area NDA of the display device 1 can extend in the y-direction and the -y-direction. In another embodiment, the display area DA and / or non-display area NDA of the display device 1 can extend in the y-direction or the -y-direction while one side of the display device 1 is fixed.

[0062] Due to external forces exerted by external objects or a part of the human body, the display device 1 can extend in multiple directions, such as a first direction (e.g., the x-direction and / or -x-direction) and a second direction (e.g., the y-direction and / or -y-direction). Figure 2d As shown, the display area DA and / or non-display area NDA of the display device 1 can extend in the ±x and ±y directions.

[0063] Due to external forces exerted by external objects or a part of the human body, the display device 1 can extend in a third direction (e.g., the z-direction or the -z-direction). In an embodiment, Figure 2e A portion of the display device 1 (e.g., the area of ​​display region DA) is shown to protrude in the z-direction. In another embodiment, a portion of the display device 1 (e.g., the area of ​​display region DA) may protrude in the z-direction (or may be recessed in the z-direction).

[0064] although Figures 2a to 2e The display device 1 is shown extending upward in a first direction, a second direction, and / or a third direction, but the disclosure is not limited thereto. In another embodiment, the display device 1 may be deformed into an irregular shape, for example, it may be bent or twisted along two or more axes.

[0065] Figure 3 This is a schematic plan view of the display device 1 according to an embodiment.

[0066] Pixels can be arranged in the display area DA of the display device 1. Each pixel may include sub-pixels configured to emit light of different colors. Light-emitting elements corresponding to the sub-pixels can be arranged in the display area DA. Circuitry configured to provide electrical signals to the light-emitting elements arranged in the display area DA and to transistors electrically connected to the light-emitting elements can be located in a non-display area NDA near the display area DA. Gate driving circuitry GDC can be arranged in each of a first non-display area NDA1 and a second non-display area NDA2 arranged on both sides of the display area DA. Gate driving circuitry GDC may include a driver configured to provide electrical signals to the gate electrode of a transistor electrically connected to the light-emitting element. Although... Figure 3The diagram shows a gate drive circuit GDC arranged in each of the first non-display region NDA1 and the second non-display region NDA2, but the disclosure is not limited thereto. In another embodiment, the gate drive circuit GDC may be arranged in either the first non-display region NDA1 or the second non-display region NDA2.

[0067] The data drive circuit DDC can be arranged in a third non-display area NDA3 and / or a fourth non-display area NDA4 that connects the first non-display area NDA1 and the second non-display area NDA2. In an embodiment, Figure 3 The diagram shows a data drive circuit (DDC) arranged in a fourth non-display area (NDA4). In another embodiment, the data drive circuit (DDC) may be arranged in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0068] although Figure 3 The data driving circuit DDC is shown arranged in the fourth non-display area NDA4 of the display device 1, but the disclosure is not limited thereto. In another embodiment, the display device 1 may further include a flexible circuit board (not shown) electrically connected to the display device 1 via a terminal portion (not shown) arranged in the fourth non-display area NDA4, and the data driving circuit DDC may be disposed on the aforementioned flexible circuit board.

[0069] In some embodiments, the elongation rate of the non-display area NDA may not be greater than the elongation rate of the display area DA. In embodiments, the non-display area NDA may have different elongation rates depending on the region. For example, although the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3 may have substantially the same elongation rate, the elongation rate of the fourth non-display area NDA4 may be less than the elongation rate of each of the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3.

[0070] Figure 4a It is part of the display device 1 according to the embodiment. Figure 3 The enlarged plan view of part IV is shown in the figure.

[0071] Reference Figure 4a The display device 1 may include: a first island portion 11, which is separated from each other in a first direction (e.g., the x direction or the -x direction) and a second direction (e.g., the y direction or the -y direction) in the display area DA; and a first bridging portion 12, which connects the adjacent first island portions 11.

[0072] Each of the first island portions 11 can be connected to a first bridging portion 12. For example, each of the first island portions 11 can be connected to four first bridging portions 12. Two of the first bridging portions 12 can be arranged on both sides of the first island portion 11 in a first direction (e.g., the x-direction or the -x-direction), and the other two of the first bridging portions 12 can be arranged on both sides of the first island portion 11 in a second direction (e.g., the y-direction or the -y-direction). In an embodiment, the four first bridging portions 12 can be connected to the four sides of the first island portion 11 respectively. Each of the four first bridging portions 12 can be adjacent to each of the corners of the first island portion 11.

[0073] The first bridging portions 12 can be separated from each other by a first opening CS1 between the first bridging portions 12. In an embodiment, the first opening CS1 having a shape generally similar to the letter "H" and the first opening CS1 having a shape generally similar to the letter "I" can be arranged alternately and repeatedly in a first direction (e.g., the x direction and the -x direction) and a second direction (e.g., the y direction or the -y direction), wherein the shape similar to the letter "I" is obtained by rotating the aforementioned shape similar to the letter "H" by 90°. The two ends of each of the first bridging portions 12 can be respectively arranged to the first island portions 11 adjacent to each other, and one side of each of the first bridging portions 12 can be separated from one side of the first island portion 11 and / or one side of the other first bridging portion 12 by the first opening CS1.

[0074] In the non-display area NDA (e.g., Figure 4a In the first non-display area NDA1 shown, the display device 1 may include second island portions 21 that are separate from each other and second bridging portions 22 that connect the adjacent second island portions 21.

[0075] Each of the second island portions 21 may extend in a first direction (e.g., the x-direction or the -x-direction). The second island portions 21 may be spaced apart from each other in a second direction (e.g., the y-direction or the -y-direction) intersecting the first direction (e.g., the x-direction or the -x-direction). Each of the second island portions 21 may include a reference. Figure 3 The gate drive circuit GDC described (see Figure 3 ) driver.

[0076] The second bridging portion 22 may have a serpentine shape. The length of the second bridging portion 22 may be greater than the minimum distance between adjacent second island portions 21 in a second direction (e.g., the y-direction or the -y-direction). In an embodiment, the second bridging portion 22 may have a shape generally resembling the Greek letter "Ω" protruding in a first direction (e.g., the x-direction or the -x-direction). The second bridging portion 22 may be arranged between adjacent second island portions 21 and may be separated from each other.

[0077] The second bridging portions 22 between adjacent second island portions 21 can be separated from each other by a second opening CS2. Between adjacent second island portions 21, the second opening CS2 and the second bridging portions 22 can be arranged alternately in a first direction (e.g., the x-direction or the -x-direction). The second openings CS2 can have the same shape. Both ends of each of the second bridging portions 22 can be connected to adjacent second island portions 21, and one side of each of the second bridging portions 22 can be separated from one side of the second island portion 21 adjacent to it and / or one side of another second bridging portion 22.

[0078] Any of the second island portions 21 arranged in the first non-display area NDA1 can correspond to a first island portion 11 arranged in a row in the display area DA. For example, any of the second island portions 21 arranged in the first non-display area NDA1 can correspond to a first island portion 11 arranged in the i-th row and a first island portion 11 arranged in the i+1-th row (where i is a positive number). Although Figure 4a The second island portion 21 is shown to correspond to two rows of the first island portions 11, but the disclosure is not limited thereto. In another embodiment, any one of the second island portions 21 arranged in the first non-display area NDA1 may correspond to n rows of the first island portions 11 arranged in the display area DA (where n is a positive number of 3 or greater).

[0079] The non-display area NDA (e.g., the first non-display area NDA1) may include: a first sub-non-display area SNDA1, in which a second island portion 21 and a second bridging portion 22 are arranged; and a second sub-non-display area SNDA2, located between the first sub-non-display area SNDA1 and the display area DA. A third bridging portion 23 connecting the display area DA and the first sub-non-display area SNDA1 may be arranged in the second sub-non-display area SNDA2. One end of the third bridging portion 23 may be connected to the second island portion 21 and / or the second bridging portion 22, and the other end of the third bridging portion 23 may be connected to the first island portion 11 and / or the first bridging portion 12.

[0080] The third bridging portion 23 may have a serpentine shape. In an embodiment, the shape of the third bridging portion 23 may differ from the shapes of the first bridging portion 12 and the second bridging portion 22. In an embodiment, such as... Figure 4aAs shown, the third bridging portion 23 may have a shape generally resembling the Greek letter "Ω" protruding in a second direction (e.g., the y-direction or the -y-direction). The third bridging portions 23, adjacent to each other and arranged in the second direction (e.g., the y-direction or the -y-direction), may have a symmetrical structure; for example, one may protrude in the y-direction and the other in the -y-direction. Third openings CS3 and fourth openings CS4, with different shapes, may be repeatedly arranged between the third bridging portions 23. The width of the third bridging portion 23 may differ from the width of the first bridging portion 12 and the width of the second bridging portion 22. In an embodiment, the width of the third bridging portion 23 may be greater than the width of the first bridging portion 12 and less than the width of the second bridging portion 22.

[0081] Figure 4a The diagram shows that the second island portion 21 and the second bridging portion 22 in the non-display area NDA (e.g., the first non-display area NDA1) have shapes different from the shapes of the first island portion 11 and the first bridging portion 12 in the display area DA. According to another embodiment, the second island portion 21 and the second bridging portion 22 in the non-display area NDA may have the same shapes as the first island portion 11 and the first bridging portion 12 in the display area DA.

[0082] Figure 4b It is part of display device 1 according to another embodiment. Figure 3 The enlarged plan view of part IV is shown in the figure.

[0083] Reference Figure 4b The display device 1 includes: first island portions 11, which are separated from each other in the display area DA; and first bridging portions 12, which are separated from each other through first openings CS1 and each connects the adjacent first island portions 11. Figure 4b The structure of the display area DA shown above can be compared with the structure of the above reference. Figure 4a The structure of the described display area DA is the same.

[0084] The display device 1 may include a second island portion 21 and a second bridging portion 22 disposed in a non-display area NDA (e.g., a first non-display area NDA1). In an embodiment, the second island portion 21 and the second bridging portion 22 may have a shape substantially the same as that of the first island portion 11 and the first bridging portion 12.

[0085] The second island portions 21 can be separated from each other in a first direction (e.g., x-direction and -x-direction) and a second direction (e.g., y-direction and -y-direction) within the non-display area NDA (e.g., the first non-display area NDA1). Each of the second bridging portions 22 can connect adjacent second island portions 21. The second bridging portions 22 can be separated from each other through a second opening CS2 between the second bridging portions 22.

[0086] The second opening CS2 may have a shape substantially the same as that of the first opening CS1. For example, a second opening CS2 having a shape roughly similar to the letter "H" and a second opening CS2 having a shape roughly similar to the letter "I" may be arranged alternately and repeatedly in the non-display area NDA (e.g., the first non-display area NDA1). The two ends of each of the second bridging portions 22 may be connected to each of the second island portions 21 adjacent to the second bridging portion 22, and one side of each of the second bridging portions 22 may be separated from one side of the second island portion 21 adjacent to the second bridging portion 22 and / or one side of another second bridging portion 22 by the second opening CS2.

[0087] Each of the second island sections 21 can be connected to four second bridge sections 22. Each of the second island sections 21 may include a reference. Figure 3 The gate drive circuit GDC described (see Figure 3 ) driver.

[0088] The second island 21 arranged in any row of the first non-display area NDA1 can correspond to the first island 11 arranged in any row of the display area DA. For example, the second island 21 arranged in the i-th row in the first direction (e.g., the x-direction or the -x-direction) in the first non-display area NDA1 can correspond to the first island 11 arranged in the same row (e.g., the i-th row) in the display area DA (where i is a positive number).

[0089] Display device 1 may include a third bridging portion 23 disposed in a second sub-non-display area SNDA2 to connect display area DA and first sub-non-display area SNDA1. The non-display area NDA (e.g., the first non-display area NDA1) may include: a first sub-non-display area SNDA1, wherein a second island portion 21 and a second bridging portion 22 are disposed; and a second sub-non-display area SNDA2, including the third bridging portion 23 and located between the first sub-non-display area SNDA1 and the display area DA. The third bridging portion 23 may be substantially the same as the first bridging portion 12 and the second bridging portion 22. For example, the width of the third bridging portion 23 may be the same as the width of the first bridging portion 12 and the width of the second bridging portion 22.

[0090] Figure 4c It is a part of display device 1 according to yet another embodiment. Figure 3 The enlarged plan view of part IV is shown in the figure.

[0091] Reference Figure 4cThe display device 1 may include a first island portion 11 that is separated from each other in a first direction (e.g., the x direction or the -x direction) and a second direction (e.g., the y direction and the -y direction) and a first bridging portion 12 that connects the adjacent first island portions 11.

[0092] The first bridging portions 12 can be arranged separately from each other through the first opening CS1 between the first bridging portions 12. The first bridging portions 12 can have a serpentine shape. For example, as Figure 4c As shown, the first bridging portion 12 may have a shape roughly similar to the letter "S".

[0093] Each of the first island portions 11 can be connected to a first bridging portion 12. For example, each of the first island portions 11 can be connected to four first bridging portions 12. Two of the first bridging portions 12 can be arranged on both sides of the first island portion 11 in a first direction (e.g., the x-direction or the -x-direction), and the other two of the first bridging portions 12 can be arranged on both sides of the first island portion 11 in a second direction (e.g., the y-direction or the -y-direction). The four first bridging portions 12 can be connected to the four sides of the first island portion 11 respectively. Each of the four first bridging portions 12 can be adjacent to each of the corners of the first island portion 11.

[0094] In the non-display area NDA (e.g., Figure 4c In the first non-display area NDA1 shown in the figure, the display device 1 may include: second island portions 21, which are separated from each other in a first direction (e.g., the x direction or the -x direction) and a second direction (e.g., the y direction and the -y direction); and second bridging portions 22, which connect the second island portions 21 that are adjacent to each other.

[0095] The second bridging portions 22 can be separated from each other through the second opening CS2 between the second bridging portions 22. The second bridging portions 22 can have a serpentine shape. For example, as Figure 4c As shown, the second bridging portion 22 may have a shape generally resembling the letter "S". The size and / or width of the second bridging portion 22 may differ from the size and / or width of the first bridging portion 12. For example, the size and / or width of the second bridging portion 22 may be larger than the size and / or width of the first bridging portion 12. The radius of curvature of the circular portion of the second bridging portion 22 may differ from the radius of curvature of the circular portion of the first bridging portion 12. For example, the radius of curvature of the circular portion of the second bridging portion 22 may be larger than the radius of curvature of the circular portion of the first bridging portion 12.

[0096] Each of the second island portions 21 can be connected to a second bridging portion 22. Each of the second island portions 21 can be connected to four second bridging portions 22. Two of the second bridging portions 22 can be arranged on both sides of the second island portion 21 in a first direction (e.g., the x-direction or the -x-direction), and the other two of the second bridging portions 22 can be arranged on both sides of the second island portion 21 in a second direction (e.g., the y-direction or the -y-direction). In an embodiment, the four second bridging portions 22 can be connected to the four sides of the second island portion 21 respectively. Each of the second bridging portions 22 can be connected to the center portion of each side of the second island portion 21.

[0097] The second island portion 21 arranged in any row of the first non-display area NDA1 can correspond to the first island portion 11 arranged in multiple rows of the display area DA. For example, the second island portion 21 arranged in any row of the first non-display area NDA1 can correspond to the first island portion 11 arranged in the i-th row and the first island portion 11 arranged in the (i+1)-th row of the display area DA (where i is a positive number). In another embodiment, the second island portion 21 in any row can correspond to the first island portion 11 in n rows (where n is a positive number of 3 or greater).

[0098] The non-display area NDA (e.g., the first non-display area NDA1) may include: a first sub-non-display area SNDA1, in which a second island portion 21 and a second bridging portion 22 are arranged; and a second sub-non-display area SNDA2, located between the first sub-non-display area SNDA1 and the display area DA. A third bridging portion 23 connecting the display area DA and the first sub-non-display area SNDA1 may be arranged in the second sub-non-display area SNDA2. One end of the third bridging portion 23 may be connected to the second island portion 21, and the other end of the third bridging portion 23 may be connected to the first island portion 11. For example, one end of the third bridging portion 23 may be connected to the center portion of the side of the second island portion 21, and the other end of the third bridging portion 23 may be connected to the center portion of the side of the first island portion 11.

[0099] The third bridging portion 23 may have a serpentine shape. In an embodiment, the shape of the third bridging portion 23 may differ from the shape of the first bridging portion 12 and the second bridging portion 22. The width of the third bridging portion 23 may differ from the width of the first bridging portion 12 and the width of the second bridging portion 22. The width of the third bridging portion 23 may be greater than the width of the first bridging portion 12 and less than the width of the second bridging portion 22. The third opening CS3 and the fourth opening CS4, which have different shapes, may be arranged alternately between the third bridging portions 23 in a second direction (e.g., the y-direction or the -y-direction).

[0100] Figure 5This is a schematic cross-sectional view showing the first island portion 11 and the first bridging portion 12 arranged in the display area DA of the display device 1 according to an embodiment.

[0101] Reference Figure 5 The first island portion 11 and the first bridging portion 12 arranged in the display area DA can be arranged separately from each other, and the first opening CS1 is located between them. The first island portion 11 may include a light-emitting element LED and a circuit (e.g., a pixel driving circuit unit PC) configured to drive the light-emitting element LED and electrically connected to the light-emitting element LED, and the first bridging portion 12 may include wiring WL that are electrically connected to the pixel driving circuit units PC arranged in the adjacent first island portions 11 respectively.

[0102] In the first island portion 11, a buffer layer 111 comprising an inorganic insulating material can be disposed on the substrate 100, and a pixel driving circuit unit PC can be disposed on the buffer layer 111. An insulating layer IL comprising an inorganic insulator and / or an organic insulator can be disposed between the pixel driving circuit unit PC and the light-emitting element LED. The light-emitting element LED can be disposed on the insulating layer IL and can be electrically connected to the corresponding pixel driving circuit unit PC. The light-emitting element LED can emit light of different colors or the same color. In an embodiment, the light-emitting element LED can be configured to emit red light, green light, and blue light, respectively. In some embodiments, the light-emitting element LED can be configured to emit white light. In another embodiment, the light-emitting element LED can be configured to emit red light, green light, blue light, and white light, respectively.

[0103] Substrate 100 may include polymeric resins such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. In one embodiment, substrate 100 may include a monolayer comprising the aforementioned polymeric resin. In another embodiment, substrate 100 may have a multilayer structure comprising: a matrix layer comprising the aforementioned polymeric resin; and a barrier layer comprising an inorganic insulator. Substrate 100 comprising polymeric resin may be flexible, rollable, and bendable.

[0104] In an embodiment, Figure 5 The illustration shows three pixel driving circuit units (PCs) arranged in each of the first island portion 11, and three light-emitting elements (LEDs) connected to each of the pixel driving circuit units (PCs), but the disclosure is not limited thereto. In another embodiment, the number of pixel driving circuit units (PCs) and light-emitting elements (LEDs) arranged in the first island portion 11 may be one, two, or at least four.

[0105] The encapsulation layer 300 can be disposed on the light-emitting element LED and can protect the light-emitting element LED from external forces and / or moisture. The encapsulation layer 300 may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer 300 may include a structure in which an inorganic encapsulation layer including an inorganic insulator, an organic encapsulation layer including an organic insulator, and an inorganic encapsulation layer including an inorganic insulator are stacked. In another embodiment, the encapsulation layer 300 may include an organic material such as a resin. In some embodiments, the encapsulation layer 300 may include urethane epoxy acrylate. The encapsulation layer 300 may include a photosensitive material (e.g., a material such as a photoresist).

[0106] In the first bridging portion 12, an insulating layer IL including an organic insulator may be disposed on the substrate 100. When the display device 1 extends, unlike the first island portion 11, the first bridging portion 12, which has a relatively large degree of deformation, may not include the layer of inorganic insulating material in which cracks are prone to occur.

[0107] In one embodiment, the substrate 100 corresponding to the first bridging portion 12 may have the same stacking structure as the substrate 100 corresponding to the first island portion 11. In another embodiment, the substrate 100 corresponding to the first bridging portion 12 and the substrate 100 corresponding to the first island portion 11 may include polymer resin layers formed together in the same process. In yet another embodiment, the substrate 100 corresponding to the first bridging portion 12 may have a different stacking structure than the substrate 100 corresponding to the first island portion 11. In some embodiments, the substrate 100 corresponding to the first island portion 11 may have a multilayer structure, comprising: a matrix layer including a polymer resin; and a barrier layer including an inorganic insulator, and the substrate 100 corresponding to the first bridging portion 12 may have a polymer resin layer structure without a layer including the inorganic insulator.

[0108] As described above, the wiring WL of the first bridging portion 12 may include signal lines (e.g., gate lines and / or data lines, etc.) configured to provide electrical signals or voltage lines (e.g., drive voltage lines and / or initialization voltage lines, etc.) configured to provide voltage to transistors included in the pixel driving circuit unit PC of the first island portion 11. In one embodiment, the encapsulation layer 300 may also be disposed in the first bridging portion 12. In another embodiment, the encapsulation layer 300 may not be disposed in the first bridging portion 12.

[0109] Reference Figures 4a to 4c and Figure 5 The base 100 corresponding to the first island portion 11 and the base 100 corresponding to the first bridging portion 12 can be connected to each other. In other words, the above... Figures 4a to 4c The floor plan shown can be compared with Figure 5The plan view of the base 100 shown is substantially the same. In other words, the base 100 may include a region corresponding to the first island portion 11, a region corresponding to the first bridging portion 12, and an opening 100OP1 having the same shape as the first opening CS1.

[0110] Similarly, the encapsulation layer 300 corresponding to the first island portion 11 and the encapsulation layer 300 corresponding to the first bridging portion 12 can be connected to each other. For example, as described above... Figures 4a to 4c The plan view shown may be substantially the same as the plan view of the encapsulation layer 300. In other words, the encapsulation layer 300 may include a region corresponding to the first island portion 11, a region corresponding to the first bridging portion 12, and an opening 300OP1 having the same shape as the first opening CS1.

[0111] The circuit light-emitting element layer 200 between the substrate 100 and the encapsulation layer 300 may include a buffer layer 111, a pixel driving circuit unit PC, wiring WL, an insulating layer IL, and a light-emitting element LED. Similar to the substrate 100, the layer above it... Figures 4a to 4c The plan view shown may be substantially the same as the plan view of the circuit light-emitting element layer 200. In other words, the circuit light-emitting element layer 200 may include an opening 200OP1 having the same shape as the first opening CS1.

[0112] Figures 6a to 6c Each of these is an equivalent circuit diagram of a sub-pixel of the display device 1 according to an embodiment.

[0113] Reference Figure 6a The light-emitting element (LED) corresponding to the sub-pixel is electrically connected to the pixel driving circuit unit PC, and the pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel driving circuit unit PC may be electrically connected to signal lines and voltage lines. The signal lines may include gate lines (e.g., a first scan line SL1) and data lines DL, and the voltage lines may include a first voltage line VDDL.

[0114] The second transistor T2 can be electrically connected to the first scan line SL1 and the data line DL. The first scan line SL1 can provide a first scan signal GW to the gate electrode of the second transistor T2. The second transistor T2 can be configured to transmit a data signal Dm input from the data line DL to the first transistor T1 in response to the first scan signal GW input from the first scan line SL1.

[0115] The storage capacitor Cst can be electrically connected to the second transistor T2 and the first voltage line VDDL, and can be configured to store a voltage corresponding to the difference between the voltage transmitted from the second transistor T2 and the first power supply voltage VDD provided from the first voltage line VDDL.

[0116] The first transistor T1, acting as a driving transistor, can be configured to control the driving current flowing through the light-emitting element LED. The first transistor T1 can be connected to a first voltage line VDDL and a storage capacitor Cst. The first transistor T1 can be configured to control the driving current flowing from the first voltage line VDDL through the light-emitting element LED to correspond to the value of the voltage stored in the storage capacitor Cst. The light-emitting element LED can be configured to emit light of a specific brightness in response to the driving current. The first electrode of the light-emitting element LED can be electrically connected to the first transistor T1, and the second electrode of the light-emitting element LED can be electrically connected to a second voltage line VSSL configured to provide a second power supply voltage VSS.

[0117] although Figure 6a The illustration shows a pixel driving circuit unit PC comprising two transistors and a storage capacitor, but in another embodiment, the pixel driving circuit unit PC may include three or more transistors.

[0118] Reference Figure 6b The pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0119] The pixel driving circuit unit PC can be electrically connected to signal lines and voltage lines. Signal lines may include gate lines (e.g., first scan line SL1, second scan line SL2, third scan line SL3, and light emission control line EML) and data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a first voltage line VDDL.

[0120] The first voltage line VDDL can be configured to drive the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can be configured to drive the first initialization voltage Vint, which initializes the first transistor T1, to the pixel driving circuit unit PC. The second initialization voltage line VIL2 can be configured to drive the second initialization voltage Vaint, which initializes the first electrode of the light-emitting element LED, to the pixel driving circuit unit PC.

[0121] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 is configured to act as a driving transistor, receiving the data signal Dm in response to the switching operation of the second transistor T2, and providing driving current to the light-emitting element LED.

[0122] The second transistor T2, acting as a data writing transistor, is electrically connected to the first scan line SL1 and the data line DL. The second transistor T2 is also electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 is turned on in response to the first scan signal GW transmitted through the first scan line SL1 and performs a switching operation to transmit the data signal Dm from the data line DL to the first node N1.

[0123] The third transistor T3 is electrically connected to the first scan line SL1 and is also electrically connected to the light-emitting element LED via the sixth transistor T6. The third transistor T3 can be turned on in response to the first scan signal GW transmitted through the first scan line SL1 and can also enable the first transistor T1 to be diode-connected.

[0124] The fourth transistor T4, acting as the first initialization transistor, is electrically connected to the third scan line SL3 and the first initialization voltage line VIL1. The fourth transistor T4 is turned on in response to the third scan signal GI transmitted via the third scan line SL3, transmitting the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, and initializing the voltage at the gate electrode of the first transistor T1. The third scan signal GI may correspond to the first scan signal of another pixel driving circuit unit PC arranged in the row preceding the row containing the corresponding pixel driving circuit unit PC.

[0125] The fifth transistor T5 may include an operation control transistor, and the sixth transistor T6 may include a light emission control transistor. The fifth transistor T5 and the sixth transistor T6 are electrically connected to the light emission control line EML and are simultaneously turned on in response to the light emission control signal EM transmitted through the light emission control line EML, forming a current path such that the drive current can flow from the first voltage line VDDL toward the light-emitting element LED.

[0126] The seventh transistor T7, acting as the second initialization transistor, can be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be turned on in response to the second scan signal GB received through the second scan line SL2, and can initialize the first electrode of the light-emitting element LED by transmitting the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED.

[0127] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 may be electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 may be electrically connected to the first voltage line VDDL. The storage capacitor Cst may be configured to maintain the voltage applied to the gate electrode of the first transistor T1 by storing and maintaining a voltage corresponding to the difference between the voltages at the ends of the first voltage line VDDL and the gate electrode of each of the first transistors T1.

[0128] Reference Figure 6c The pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor Cst, and an auxiliary capacitor Ca.

[0129] The pixel driving circuit unit PC can be electrically connected to signal lines and voltage lines. The signal lines may include gate lines (e.g., first scan line SL1, second scan line SL2, third scan line SL3, and light emission control line EML) and data lines DL. The voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, a holding voltage line VSL, and a first voltage line VDDL.

[0130] The first voltage line VDDL can be configured to drive the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can be configured to drive the first initialization voltage Vint, which initializes the first transistor T1, to the pixel driving circuit unit PC. The second initialization voltage line VIL2 can be configured to drive the second initialization voltage Vaint, which initializes the first electrode of the light-emitting element LED, to the pixel driving circuit unit PC. The holding voltage line VSL can be configured to provide a holding voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) in the initialization and data write sections.

[0131] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and can be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 can be configured to act as a driving transistor, receiving the data signal Dm in response to the switching operation of the second transistor T2, and providing driving current to the light-emitting element LED.

[0132] The second transistor T2 is electrically connected to the first scan line SL1 and the data line DL, and is also electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8. The second transistor T2 is turned on in response to the first scan signal GW transmitted from the first scan line SL1, and performs a switching operation to transmit the data signal Dm transmitted from the data line DL to the first node N1.

[0133] The third transistor T3 is electrically connected to the first scan line SL1 and is also electrically connected to the light-emitting element LED via the sixth transistor T6. The third transistor T3 can be configured to compensate for the threshold voltage of the first transistor T1 by turning on in response to the first scan signal GW transmitted through the first scan line SL1 and causing the first transistor T1 diode to connect.

[0134] The fourth transistor T4 is electrically connected to the third scan line SL3 and the first initialization voltage line VIL1. It is turned on in response to the third scan signal GI transmitted via the third scan line SL3 and transmits the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, thereby initializing the voltage at the gate electrode of the first transistor T1. The third scan signal GI may correspond to the first scan signal of another pixel driving circuit unit PC arranged in the row preceding the row containing the corresponding pixel driving circuit unit PC.

[0135] The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are electrically connected to the light emission control line EML and are simultaneously turned on in response to the light emission control signal EM transmitted through the light emission control line EML, forming a current path so that the driving current can flow from the first voltage line VDDL toward the light-emitting element LED.

[0136] The seventh transistor T7, acting as the second initialization transistor, can be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 is turned on in response to the second scan signal GB transmitted through the second scan line SL2, transmitting the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED, and initializing the first electrode of the light-emitting element LED.

[0137] The ninth transistor T9 can be electrically connected to the second scan line SL2, the second electrode CE2 of the storage capacitor Cst, and the holding voltage line VSL. The ninth transistor T9 can be turned on in response to the second scan signal GB transmitted through the second scan line SL2, and can be configured to transmit the holding voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) in the initialization segment and the data write segment.

[0138] The eighth transistor T8 and the ninth transistor T9 can both be electrically connected to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst). In some embodiments, during the initialization and data writing sections, the eighth transistor T8 can be turned off and the ninth transistor T9 can be turned on, and during the light emission section, the eighth transistor T8 can be turned on and the ninth transistor T9 can be turned off. During the initialization and data writing sections, the second node N2, to which the holding voltage VSUS is transmitted, can be configured to improve the long-distance uniformity (“LRU”) of the display device 1 based on the voltage drop of the first voltage line VDDL.

[0139] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 is electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 is electrically connected to the eighth transistor T8 and the ninth transistor T9.

[0140] An auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the holding voltage line VSL, and the first electrode of the light-emitting element LED. The auxiliary capacitor Ca can be configured to store and maintain a voltage corresponding to the difference between the voltage of the first electrode of the light-emitting element LED and the voltage of the holding voltage line VSL while the seventh transistor T7 and the ninth transistor T9 are turned on, thereby preventing an increase in black brightness when the sixth transistor T6 is turned off.

[0141] Figure 7a This is a schematic cross-sectional view of the light-emitting element LED of the display device 1 according to an embodiment.

[0142] Reference Figure 7a According to an embodiment, the light-emitting element LED may include an organic light-emitting diode 220 comprising organic materials. The organic light-emitting diode 220 may include a first electrode 221 disposed on an insulating layer, a second electrode 225 facing the first electrode 221, and a light-emitting layer 223 between the first electrode 221 and the second electrode 225. A first functional layer 222 may be disposed between the first electrode 221 and the light-emitting layer 223, and a second functional layer 224 may be disposed between the light-emitting layer 223 and the second electrode 225.

[0143] The edge of the first electrode 221 may be covered by a dam layer BKL comprising an insulator. The dam layer BKL may be defined as an opening B-OP overlapping the central portion of the first electrode 221 in a plan view.

[0144] The first electrode 221 may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In another embodiment, the first electrode 221 may also include a layer comprising ITO, IZO, ZnO, AZO, or In2O3 below or above the aforementioned reflective layer.

[0145] The light-emitting layer 223 may include a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a specific color. The first functional layer 222 may include a hole transport layer (“HTL”) and / or a hole injection layer (“HIL”). The second functional layer 224 may include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”).

[0146] The second electrode 225 may include a conductive material with a small work function. In an embodiment, for example, the second electrode 225 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Optionally, the second electrode 225 may also include a layer comprising ITO, IZO, ZnO, AZO, or In2O3 on top of a (semi-)transparent layer containing the above-described materials.

[0147] Figure 7b This is a schematic cross-sectional view of the light-emitting element LED of the display device 1 according to an embodiment.

[0148] Reference Figure 7b According to the embodiments, the light-emitting element may include an inorganic light-emitting diode 230 comprising inorganic materials. The inorganic light-emitting diode 230 may include a first semiconductor layer 231, a second semiconductor layer 232, an intermediate layer 233 between the first semiconductor layer 231 and the second semiconductor layer 232, a first electrode 235 electrically connected to the first semiconductor layer 231, and a second electrode 238 electrically connected to the second semiconductor layer 232. The first electrode 235 and the second electrode 238 of the inorganic light-emitting diode 230 may be electrically connected to a first electrode pad (or "solder pad") 241 and a second electrode pad 242 disposed in the same layer, respectively.

[0149] In some embodiments, the first semiconductor layer 231 may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from those having In x Al y Ga 1-x-ySemiconductor materials with a composition of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) (e.g., GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN), and may be doped with p-type dopants such as Mg, Zn, Ca, Sr, Ba, etc.

[0150] The second semiconductor layer 232 may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from those having In... x Al y Ga 1-x-y Semiconductor materials with a composition of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) (e.g., GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN), and may be doped with n-type dopants such as Si, Ge, Sn, etc.

[0151] The intermediate layer 233, serving as a region for electron-hole recombination, transitions to a lower energy level as electrons and holes recombine, and can generate light with a corresponding wavelength. The intermediate layer 233 can be formed to include elements such as In... x Al y Ga 1-x-y The semiconductor material is composed of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) and can be formed as a single quantum well structure or a multiple quantum well (“MQW”) structure. Additionally, the intermediate layer 233 may include a quantum wire structure or a quantum dot structure.

[0152] although Figure 7b The illustration shows a first semiconductor layer 231 comprising a p-type semiconductor layer and a second semiconductor layer 232 comprising an n-type semiconductor layer, but the disclosure is not limited thereto. In another embodiment, the first semiconductor layer 231 may comprise an n-type semiconductor layer and the second semiconductor layer 232 may comprise a p-type semiconductor layer.

[0153] Figure 8a This is a plan view showing an enlarged image of the first island portion 11 of the display device 1 according to an embodiment, and Figure 8b This is a plan view showing the arrangement of wiring WL in the first bridging section 12 of the display device 1 according to an embodiment. Additionally, Figure 9 It shows along Figure 8a The cross section shown is taken along line I-I' and along Figure 8b The cross section shown is taken by line II-II'.

[0154] Reference Figure 8a The first island 11 arranged in the display area DA may include a light-emitting element and a pixel driving circuit unit PC electrically connected to the light-emitting element. As described above, the pixel driving circuit unit PC may include a transistor and at least one capacitor. Although Figure 8a The illustration shows three pixel driving circuit units (PCs) arranged in the first island portion 11, but the disclosure is not limited thereto. In other embodiments, the number of pixel driving circuit units (PCs) and light-emitting elements arranged in the first island portion 11 may be one, two, or four or more.

[0155] Reference Figure 9 The substrate 100 corresponding to the first island portion 11 may include a first substrate layer 101, a first barrier layer 102, a second substrate layer 103, and a second barrier layer 104. The first substrate layer 101 and the second substrate layer 103 may each comprise a polymer resin, such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. The first barrier layer 102 and the second barrier layer 104 may each comprise an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0156] A buffer layer 111 may be disposed on a substrate 100, and a pixel driving circuit unit PC may be disposed on the buffer layer 111. The buffer layer 111 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0157] A thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Although Figure 9 The illustration shows a top-gate thin-film transistor in which the gate electrode GE is disposed on the semiconductor layer Act and the gate insulating layer 113 is between the gate electrode GE and the semiconductor layer Act. However, according to another embodiment, the thin-film transistor TFT may include a bottom-gate thin-film transistor.

[0158] The semiconductor layer Act may include polycrystalline silicon. Optionally, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, and / or organic semiconductor, etc. The gate electrode GE may include a low-resistance metallic material. The gate electrode GE may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include multiple layers or a single layer comprising the aforementioned materials.

[0159] The gate insulating layer 113 between the semiconductor layer Act and the gate electrode GE may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide. The gate insulating layer 113 may comprise a single layer or multiple layers containing the aforementioned materials.

[0160] The source electrode SE and the drain electrode DE can be on the same layer (e.g., on the second interlayer insulating layer 117) and can comprise the same material. The source electrode SE and the drain electrode DE can each comprise a conductive material and can each comprise multiple layers or a single layer. The second interlayer insulating layer 117 can comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide, and can comprise a single layer or multiple layers containing the aforementioned materials.

[0161] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2 stacked on top of each other in a planar view, with a first interlayer insulating layer 115 located therebetween. In the planar view, the storage capacitor Cst may be stacked with a thin-film transistor (TFT). Regarding this, Figure 9 The diagram shows the gate electrode GE of the thin-film transistor TFT as the first electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not be stacked with the thin-film transistor TFT in a planar view. The storage capacitor Cst may be covered by a second interlayer insulating layer 117. The second electrode CE2 of the storage capacitor Cst may include a conductive material and may include multiple layers or a single layer. A first interlayer insulating layer 115 may be disposed between the gate insulating layer 113 and the second interlayer insulating layer 117. The first interlayer insulating layer 115 may include inorganic insulators such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide, and may include a single layer or multiple layers containing the aforementioned materials.

[0162] The inorganic insulating layer IOL on the substrate 100 may include, for example, a buffer layer 111, a gate insulating layer 113, a first interlayer insulating layer 115, and a second interlayer insulating layer 117.

[0163] A first organic insulating layer 119 may be disposed on a second interlayer insulating layer 117, and a second organic insulating layer 121 may be disposed on a first organic insulating layer 119. The first organic insulating layer 119 and the second organic insulating layer 121 may each comprise an organic insulator such as polyimide.

[0164] A second voltage line VSSL may be disposed on the second organic insulating layer 121, and a third organic insulating layer 123 may be disposed on the second organic insulating layer 121 and the second voltage line VSSL. The third organic insulating layer 123 may include an organic insulator such as polyimide. The second voltage line VSSL may include a conductive material and may include multiple layers or a single layer.

[0165] The first electrode pad 241 and the second electrode pad 242 can be disposed on the third organic insulating layer 123. The first electrode pad 241 can be electrically connected to the thin-film transistor (TFT) through a first connecting electrode CM1 between the first organic insulating layer 119 and the second organic insulating layer 121 and a second connecting electrode CM2 between the second organic insulating layer 121 and the third organic insulating layer 123. The inorganic light-emitting diodes 230 on the first electrode pad 241 and the second electrode pad 242 are as described above. Figure 7b The light-emitting diode (e.g., inorganic light-emitting diode 230) may be protected by an encapsulation layer 300, and the encapsulation layer 300 may include an inorganic encapsulation layer and / or an organic encapsulation layer, or may include an organic material such as a resin. Although Figure 9 The light-emitting diode is shown as a reference. Figure 7b The inorganic light-emitting diode 230 described herein may, in another embodiment, include the light-emitting diode as described above. Figure 7a The organic light-emitting diode 220 is described.

[0166] Reference Figure 8b The first bridging portion 12 may include wiring WLs electrically connected to pixel driving circuit units PCs arranged in adjacent first island portions 11. As described above, the wiring WLs may include signal lines (e.g., gate lines, data lines) or voltage lines (e.g., drive voltage lines, initialization voltage lines) configured to provide electrical signals to transistors included in the pixel driving circuit units PCs in the first island portions 11. Although Figure 8b The illustration shows that wiring WLs (e.g., first wiring WL1, second wiring WL2, and third wiring WL3) are provided in the first bridging portion 12, but the disclosure is not limited thereto. In another embodiment, only one wiring WL may be provided in the first bridging portion 12.

[0167] Reference Figure 9 According to an embodiment, the substrate 100 corresponding to the first bridging portion 12 may have the same stacking structure as the substrate 100 corresponding to the first island portion 11. In an embodiment, the substrate 100 corresponding to the first bridging portion 12 may include a first substrate layer 101, a first barrier layer 102, a second substrate layer 103, and a second barrier layer 104. In another embodiment, the substrate 100 corresponding to the first bridging portion 12 may have a different stacking structure than the substrate 100 corresponding to the first island portion 11. The substrate 100 corresponding to the first bridging portion 12 may have a structure including a first substrate layer 101 and a second substrate layer 103.

[0168] The inorganic insulating layer IOL may not be disposed on the substrate 100, and the insulating layer OL, the first organic insulating layer 119, and the second organic insulating layer 121 may be disposed on the substrate 100. The insulating layer OL may include an organic insulator such as polyimide. In embodiments, the insulating layer OL may have a thickness corresponding to the thickness of the inorganic insulating layer IOL. In some embodiments, the insulating layer OL may also be omitted.

[0169] Wiring WLs (e.g., first wiring WL1, second wiring WL2, and third wiring WL3) can be disposed in different layers but can be electrically connected to the same pixel driving circuit unit PC. For example, first wiring WL1 can be disposed between second organic insulating layer 121 and third organic insulating layer 123, second wiring WL2 can be disposed between first organic insulating layer 119 and second organic insulating layer 121, and third wiring WL3 can be disposed between insulating layer 100 and first organic insulating layer 119. However, the disclosure is not limited thereto, and in other embodiments, at least some of the first wiring WL1, second wiring WL2, and third wiring WL3 can be disposed in the same layer.

[0170] Figure 10 and Figure 11 This is a cross-sectional view of the conductive layer SCL that forms the wiring or connection electrodes of the display device according to an embodiment. Figure 12 This is a cross-sectional view of the conductive layer SCL' based on the comparative example.

[0171] Reference Figure 10 and Figure 11 The conductive layer SCL may include a first layer L1. In an embodiment, the first layer L1 may have a structure including multiple sublayers. The multiple sublayers may include a first sublayer AL and a second sublayer CL.

[0172] The first sublayer AL may include an alloy layer. The first sublayer AL may include an alloy of aluminum (Al) and rare earth elements. The first sublayer AL may include an amorphous alloy layer. The amorphous alloy may not include grain boundaries. The amorphous alloy may have a high elastic strain limit. In the amorphous alloy, a fully amorphous alloy can undergo elastic deformation without plastic deformation. In this specification, the amorphous alloy may include cases where the alloy is fully amorphous and cases where a nanocrystalline phase with a crystal size of only a few nanometers exists in a dispersed state within the amorphous phase.

[0173] The atomic radii of rare earth elements can be larger than those of aluminum (Al). The ratio of the difference between the atomic radii of aluminum and rare earth elements to the atomic radius of aluminum can be about 25% or greater. When this difference is about 25% or greater than the atomic radius of Al, crystallization due to the regular arrangement of atoms can be interrupted. The electronegativity of rare earth elements can be less than that of aluminum. The electronegativity of rare earth elements can be about 1.0 or greater but not greater than about 1.2. In embodiments, the rare earth element may include at least one of yttrium (Y), samarium (Sm), cerium (Ce), and lanthanum (La). Such rare earth elements can have excellent ability to form amorphous materials.

[0174] In an embodiment, the first sublayer AL may include layers with Al a M b The composition is a binary alloy. Here, M may include at least one rare earth element selected from yttrium (Y), samarium (Sm), cerium (Ce), and lanthanum (La). a and b each represent the content (at%) of each element relative to the total atomic weight of the first sublayer AL, and the sum of a and b may be 100. In embodiments, a may be at least about 90 but not more than about 96, and b may be at least about 4 but not more than about 10. In other words, relative to the total atomic weight of the first sublayer AL, the content of aluminum (Al) may be at least about 90 atomic percent (at%) but not more than about 96 at%, and the content of rare earth element M may be at least about 4 at% but not more than about 10 at%. When the aluminum and rare earth element M included in the first sublayer AL satisfy the above ranges, the first sublayer AL may include an amorphous alloy layer with excellent resistivity. When the aluminum content is less than about 90 at%, the resistivity of the first sublayer AL may increase. When the aluminum content is greater than about 96 at%, the first sublayer AL may not form an amorphous alloy layer. When the content of the first sublayer Al is less than about 4 at%, the first sublayer Al may not form an amorphous alloy layer. When the content of the rare earth element M is greater than about 10 at%, the resistivity of the first sublayer Al may increase. In embodiments, the first sublayer Al may include Al... a Y b Alloys with a composition of (90≤a≤96 and 4≤b≤10).

[0175] In some embodiments, the first sublayer Al may further comprise nickel (Ni) and / or cobalt (Co). Nickel and cobalt may be elements that stabilize the amorphous phase. In some embodiments, the first sublayer Al may comprise a ternary alloy or a quaternary alloy. In some embodiments, the first sublayer Al may comprise Al... a M b Ni c Co dThe composition is a quaternary alloy. Here, M may include at least one rare earth element selected from Y, Sm, Ce, and La. a, b, c, and d each represent the content (at%) of each element relative to the total atomic weight of the first sublayer Al, and the sum of a, b, c, and d may be 100. In some embodiments, a may be about 80 or greater but not greater than about 90, b may be about 5 or greater but not greater than about 10, c may be about 3 or greater but not greater than about 8, and d may be about 1 or greater but not greater than 3. In other words, relative to the total atomic weight of the first sublayer Al, the content of aluminum may be about 80 at% or greater but not greater than about 90 at%, the content of rare earth element M may be about 5 at% or greater but not greater than about 10 at%, the content of nickel may be about 3 at% or greater but not greater than about 8 at%, and the content of cobalt may be about 1 at% or greater but not greater than about 3 at%. In embodiments, the first sublayer Al may include Al 85 The composition of Y8Ni5Co2 alloy.

[0176] The second sublayer CL may include aluminum (Al). The second sublayer CL may include a pure aluminum layer. The second sublayer CL may include crystalline aluminum. Pure aluminum undergoes plastic deformation after elastic deformation and can have a relatively low elastic strain limit compared to the elastic strain limit of amorphous alloys. For example, pure aluminum can have a low elastic strain limit of about 0.2% to about 0.5%. Pure aluminum can have a strain limit of less than 10 microohms. centimeters (μΩ) It has a low resistivity of (cm).

[0177] The first layer L1 of the conductive layer SCL can have a structure in which a first sublayer AL and a second sublayer CL are stacked alternately. In an embodiment, Figure 10 The diagram shows an eleven-layer structure for the first layer L1, comprising six first sublayers AL1, AL2, AL3, AL4, AL5, and AL6, and five second sublayers CL1, CL2, CL3, CL4, and CL5. For clarity, the six first sublayers AL1, AL2, AL3, AL4, AL5, and AL6 will be referred to as sublayer 1-1 AL1, sublayer 1-2 AL2, sublayer 1-3 AL3, sublayer 1-4 AL4, sublayer 1-5 AL5, and sublayer 1-6 AL6, respectively, and the five second sublayers CL1, CL2, CL3, CL4, and CL5 will be referred to as sublayer 2-1 CL1, sublayer 2-2 CL2, sublayer 2-3 CL3, sublayer 2-4 CL4, and sublayer 2-5 CL5, respectively. The top and bottom layers of the first layer L1 may each comprise a first sublayer AL. For example, Figure 10 The diagram shows that the top layer of the first layer L1 is sublayer AL6 (1-6), and the bottom layer is sublayer AL1 (1-1). In other words, in the first layer L1, each of the second sublayers CL can be set between the first sublayers AL.

[0178] Sublayers 1-1 (AL1) to 1-6 (AL6) may each comprise the same material. Sublayers 1-1 (AL1) to 1-6 (AL6) may each comprise an alloy of aluminum and rare earth elements having the same composition. Additionally, sublayers 2-1 (CL1) to 2-5 (CL5) may each comprise the same material. Sublayers 2-1 (CL1) to 2-5 (CL5) may each comprise a pure aluminum layer.

[0179] To reduce the resistivity of the first layer L1, sublayers 1-1 (AL1) to 1-6 (AL6) can be set with substantially the same thickness. Sublayers 2-1 (CL1) to 2-5 (CL5) can also be set with substantially the same thickness.

[0180] although Figure 10 The illustration shows a first layer L1 with an eleven-layer structure, but the disclosure is not limited thereto. In another embodiment, the first layer L1 may include at least one second sublayer CL and at least two first sublayers AL disposed below and above the second sublayer CL. Considering the thickness of the first layer L1 used as wiring or electrodes, the first layer L1 may have a structure comprising three to twenty-five layers.

[0181] In an embodiment, the thickness of the first layer L1 can be from about 300 nanometers (nm) to about 1000 nm.

[0182] In this embodiment, the thickness of the first sublayer AL can be from about 30 nm to about 100 nm. Desiredly, the thickness of the first sublayer AL can be from about 40 nm to about 80 nm.

[0183] In an embodiment, the ratio of the thickness of the first sublayer AL to the thickness of the second sublayer CL can be less than about 2. Desiredly, the ratio of the thickness of the first sublayer AL to the thickness of the second sublayer CL can be greater than 0 and not greater than about 1. When the ratio of the thicknesses of the first sublayer AL and the second sublayer CL meets the desired range, the first layer L1 can have excellent resistivity characteristics (i.e., 11 μΩ·cm or less).

[0184] Reference Figure 10In an embodiment, the conductive layer SCL may include a lower barrier layer L2 below the first layer L1 and an upper barrier layer L3 on the first layer L1. The conductive layer SCL may have a structure in which the lower barrier layer L2, the first layer L1, and the upper barrier layer L3 are stacked sequentially. In an embodiment, the lower barrier layer L2 may include a second layer, and the upper barrier layer L3 may include a third layer. The lower barrier layer L2 and the upper barrier layer L3 may include materials different from the material of the first layer L1. The lower barrier layer L2 and the upper barrier layer L3 may each include a metallic material, a transparent conductive oxide, or a nitride. In an embodiment, the metallic material may include, for example, molybdenum (Mo), copper (Cu), titanium (Ti), nickel (Ni), chromium (Cr), tungsten (W), and alloys thereof (e.g., NiTi, CuTi, CuMn, and CuMg). The transparent conductive oxide may include, for example, indium tin oxide (ITO). The nitride may include, for example, titanium nitride (TiN). In an embodiment, the lower barrier layer L2 and the upper barrier layer L3 may include Ti or Mo. In this embodiment, the lower barrier layer L2 and the upper barrier layer L3 may have crystalline or amorphous microstructures. (Refer to...) Figure 11 In another embodiment, the conductive layer SCL may not include the lower barrier layer L2 and the upper barrier layer L3. The conductive layer SCL may consist only of the first layer L1.

[0185] The aforementioned conductive layer SCL structure can be applied to the wiring WL disposed in the first bridging portion 12. The wiring WL disposed in the first bridging portion 12 may include a first layer L1 having an alternating stacked structure of a first sublayer AL comprising an alloy including aluminum and rare earth elements and a second sublayer CL comprising aluminum. For example... Figure 9 The first wiring WL1, the second wiring WL2 and the third wiring WL3 shown may include a first layer L1 having a structure in which a first sublayer AL, comprising an alloy including aluminum and rare earth elements, and a second sublayer CL comprising aluminum are stacked alternately.

[0186] Reference Figure 12 In the comparative example, the wiring disposed in the first bridging portion can have a structure of conductive layer SCL'. The first layer L1' of conductive layer SCL' may not include a stacked structure containing sublayers. The first layer L1' may include an alloy of aluminum and rare earth elements, and may include an amorphous alloy layer. In this case, the first layer L1' can have a high elastic strain limit. The resistivity of the first layer L1' can be reduced by adjusting the content of aluminum and rare earth elements. However, the first layer L1' can have a high resistivity compared to the resistivity of a pure aluminum layer.

[0187] However, according to the embodiment, the wiring WL provided in the first bridging portion 12 may have a reference Figure 10 and Figure 11The structure of the conductive layer SCL is described. The first layer L1 of the conductive layer SCL may include a first sublayer AL containing an alloy of aluminum and rare earth elements and a second sublayer CL containing aluminum, and may have a structure in which the first sublayer AL and the second sublayer CL are alternately stacked. In this case, by alternately stacking the first sublayer AL and the second sublayer CL, which have different physical properties, [the structure is similar to / is designed for / etc.]. Figure 12 Compared to the resistivity of the first layer L1' shown, the first layer L1 can have an improved resistivity (i.e., a lower resistivity). In the embodiments, the first layer L1 can ensure a resistivity similar to the low resistivity of a pure aluminum layer while maintaining a high elastic strain limit.

[0188] In this embodiment, the resistivity of the first layer L1 can be less than about 11 μΩ·cm. More preferably, the resistivity of the first layer L1 can be greater than about 5 μΩ. cm and less than approximately 11 μΩ cm. More preferably, the resistivity of the first layer L1 can be greater than approximately 5.6 μΩ. cm and less than approximately 11 μΩ cm.

[0189] In this embodiment, the elastic strain limit of the first layer L1 can be at least about 2.0%. Desiredly, the elastic strain limit of the first layer L1 can be at least about 3.0%. More desirously, the elastic strain limit of the first layer L1 can be at least about 3.0% but not more than about 4.0%. Because the first layer L1 has a high elastic strain limit of at least about 2.0%, the design area of ​​the wiring WL can be reduced in the first bridging portion 12 having a serpentine shape. Furthermore, when tensile strength is applied to the first bridging portion 12 and the first bridging portion 12 extends in all directions, the risk of damaging the wiring WL can be reduced, and the lifespan of the wiring WL can be effectively increased.

[0190] In an embodiment, the yield strength of the first layer L1 may be at least about 0.7 gigapascals (GPa) but not more than about 1.5 GPa. Desiredly, the yield strength of the first layer L1 may be at least about 0.8 GPa but not more than about 1.5 GPa. More desirously, the yield strength of the first layer L1 may be at least about 0.8 GPa but not more than about 1.2 GPa.

[0191] In this embodiment, the structure of the conductive layer SCL can also be applied to the connection electrode disposed in the first island portion 11. The connection electrode can be disposed between the inorganic insulating layer IOL and the light-emitting element. The connection electrode can be disposed between the gate electrode GE of the thin-film transistor TFT and the light-emitting element, and can be electrically connected to the thin-film transistor TFT and / or the light-emitting element. For example, the connection electrode can be disposed between the inorganic insulating layer IOL and the first organic insulating layer 119. Optionally, the connection electrode can be disposed between the first organic insulating layer 119 and the second organic insulating layer 121. Optionally, the connection electrode can be disposed between the second organic insulating layer 121 and the third organic insulating layer 123. For example, the connection electrode may include... Figure 9 The source electrode SE, drain electrode DE, first connection electrode CM1, second connection electrode CM2, and second voltage line VSSL are shown. The connection electrodes arranged in the first island portion 11 may include a first layer L1 having a structure in which a first sublayer AL and a second sublayer CL are alternately stacked, wherein the first sublayer AL comprises an alloy of aluminum and rare earth elements, and the second sublayer CL comprises only aluminum. For example, the source electrode SE, drain electrode DE, first connection electrode CM1, second connection electrode CM2, and second voltage line VSSL may each include a first layer L1 having a structure in which a first sublayer AL and a second sublayer CL are alternately stacked, the first sublayer AL comprising an alloy of aluminum and rare earth elements, and the second sublayer CL comprising aluminum. In other embodiments, the structure of the conductive layer SCL may be applied only to the wiring WL arranged in the first bridging portion 12, and not to the connection electrodes arranged in the first island portion 11.

[0192] Figure 13 This is a flowchart illustrating a method for manufacturing an alloy layer including a conductive layer according to an embodiment, and Figure 14 The results of examining the microstructure of the alloy layer according to the embodiment using a transmission electron microscope (“TEM”) are shown. Figure 14 (a) shows an image pattern image. Figure 14 (b) shows the diffraction pattern image.

[0193] A method of manufacturing a display device may include the following steps: forming a first island portion 11 and a first bridging portion 12, wherein each first bridging portion 12 connects adjacent first island portions 11; and forming wiring WL arranged in the first bridging portion 12 (see... Figure 9 ).

[0194] As described above, the wiring WL arranged in the first bridging portion 12 may have a conductive layer SCL (see... Figure 10 The structure of the wiring WL arranged in the first bridging part 12 may each include a first sublayer AL of an alloy containing aluminum and rare earth elements (see Figure 10 ) and the second sublayer CL containing aluminum (see Figure 10 The wiring WL disposed in the first bridging portion 12 may each include a structure in which a first sublayer AL and a second sublayer CL are stacked alternately. The steps of forming the wiring WL may include forming the first sublayer AL (i.e., an alloy layer) and forming the second sublayer CL. In an embodiment, the steps of forming the first sublayer AL and the second sublayer CL may be performed by a sputtering method.

[0195] In an embodiment, the step of forming the first sublayer AL may include: designing an alloy of Al and rare earth elements (S110); forming a master alloy including Al and rare earth elements (S120); forming powder of the master alloy (S130); forming an alloy body by sintering the powder (S140); and depositing the first sublayer AL on a substrate by performing sputtering on the alloy body as a target (S150).

[0196] First, in S110, the elements and their contents in the alloy composition can be designed. The target composition can be designed based on the composition of the final formed first sublayer Al. In an embodiment, the final formed first sublayer Al may comprise a binary alloy and may have Al a M b The composition formula is as follows. Here, M may include at least one rare earth element selected from Y, Sm, Ce, and La. a and b may each refer to the content (at%) of each element relative to the total atomic weight of alloy layer L1, and the sum of a and b may be 100. In an embodiment, a may be at least about 90 but not more than about 96, and b may be at least about 4 but not more than about 10. In other words, relative to the total atomic weight of the first sublayer AL, the aluminum content may be at least about 90 at% but not more than about 96 at%, and the content of rare earth element M may be at least about 4 at% but not more than about 10 at%. In an embodiment, the first sublayer AL may include Al a Y b Alloys with a composition of (90≤a≤96 and 4≤b≤10).

[0197] Next, in S120, a master alloy can be formed using high-purity raw materials. For example, a vacuum induction melting (“VIM”) method can be used to form the master alloy.

[0198] In S130, a master alloy powder can be formed. The master alloy can be pulverized in a highly clean state. The powder can be formed using an atomization method (e.g., electrode induction gas atomization (“EIGA”) method). The particle size of the formed powder can be from about 30 micrometers (μm) to about 50 μm.

[0199] In S140, an alloy body can be formed by sintering powder. Sintering allows the formation of an alloy body with a uniform composition. For example, the alloy body can be formed using processes such as spark plasma sintering (“SPS”) and hot isostatic pressing (“HIP”). The alloy body can then be machined to a size suitable for a sputtering target.

[0200] In S150, a sputtering process can be performed on the alloy body used as a target. A first sublayer of Al can be deposited on the substrate using the sputtering process. For example, DC-magnetron sputtering can be used in the sputtering process.

[0201] The microstructure of the first sublayer AL can vary depending on the conditions of the sputtering process. For example, the microstructure of the first sublayer AL can vary depending on the temperature, power density, and the deposition on the sputtered substrate.

[0202] Reference Figure 14 As shown in (a) and (b) of the embodiments, the first sublayer AL is an amorphous alloy layer and has a columnar high-density microstructure. Compared with a first sublayer AL having a columnar microstructure, a first sublayer AL having a columnar high-density microstructure can have superior physical properties (e.g., mechanical properties).

[0203] Figure 15 This is a diagram illustrating the microstructure of the conductive layer SCL according to an embodiment. Figure 16 This is a graph showing the resistivity of the conductive layer SCL according to an embodiment. Figure 17 This is a graph showing the resistivity of the conductive layer SCL according to the embodiments and comparative examples.

[0204] Reference Figures 15 to 17 In each of Examples 1 to 7, a first layer L1 is formed in which a first sublayer Al and a second sublayer CL are alternately stacked, wherein the first sublayer comprises Al and rare earth elements, and the second sublayer CL comprises aluminum. More specifically, an amorphous alloy layer comprising Al and rare earth elements is formed as the first sublayer Al, and a pure crystalline Al layer is formed as the second sublayer CL. The first layer L1 having an eleven-layer structure is formed by alternately stacking six first sublayers Al and five second sublayers CL.

[0205] In Examples 1 to 7, a first layer L1 was formed by changing the type and content of rare earth elements included in the first sublayer AL, the thickness of the first sublayer AL, the thickness of the second sublayer CL, and the ratio of the thickness of the first sublayer AL to the thickness of the second sublayer CL, according to the conditions shown in Table 1.

[0206] [Table 1]

[0207] In Comparative Examples 1 to 3, an alloy layer comprising Al and rare earth elements was formed. More specifically, an amorphous alloy layer comprising Al and rare earth elements was formed. In Comparative Example 1, an Al alloy layer with a thickness of 600 nm and a composition of Al was formed. 94 An alloy layer of Al and Y in Y6 was formed. In Comparative Example 2, an Al alloy layer with a thickness of 600 nm was formed. 90 Y 10 An alloy layer of Al and Y was formed. In Comparative Example 3, an Al alloy layer with a thickness of 600 nm and a composition of Al was formed. 85 The alloy layer of Al, Y, Ni and Co in Y8Ni5Co2.

[0208] In Comparative Example 4, a pure crystalline Al layer was formed. More specifically, an Al layer with a thickness of 600 nm was formed.

[0209] In Comparative Example 5, a crystalline Al alloy layer (Al7075) is formed.

[0210] Figure 15 The results of TEM examination of the microstructure of the first layer L1 in Examples 3 and 7 are shown. Figure 15 (a) shows the microstructure in Example 7, and (b) shows the microstructure in Example 3.

[0211] Reference Figure 15 As can be seen, the first layer L1 in Examples 3 and 7 has a structure in which a first sublayer AL (i.e., an amorphous alloy layer) and a crystalline second sublayer CL are stacked alternately. More specifically, it can be seen that the first sublayer AL in Example 7 is completely amorphous. On the other hand, it can be seen that the first sublayer AL in Example 3 exists in the form of a nanocrystalline phase with a crystal size of only a few nanometers distributed in the amorphous phase.

[0212] Resistivity was measured for the first layer L1 in Examples 1 to 7, the alloy layers in Comparative Examples 1 to 3, and the Al layer in Comparative Example 4. The resistivity was measured using a 4-point probe (“4PB”) method. The results are shown below. Figure 16 and Figure 17 middle. Figure 16 The resistivity in Examples 1 and 2 is shown, and Figure 17 The resistivity in Examples 3 to 7 and Comparative Examples 1 to 4 is shown.

[0213] Reference Figure 16 and Figure 17 It can be seen that the resistivity (13.1 μΩ) in Examples 1 and 2 is... cm and 8.5μΩ The resistivity (cm) is lower than that in Comparative Example 1 (17.7 μΩ). The resistivity is low (cm). It can also be seen that the resistivity in Example 2 is less than 11 μΩ·cm, while the resistivity in Example 1 is at least 11 μΩ·cm. When the thickness of the first sublayer AL is reduced to at least a certain extent, electrons can be further scattered, and the resistivity of the first layer L1 can increase. To ensure a resistivity of less than 11 μΩ·cm, the thickness of the first sublayer AL can be at least 40 nm. Desiredly, the thickness of the first sublayer AL can be from about 40 nm to about 100 nm. More desirously, the thickness of the first sublayer AL can be from about 40 nm to about 80 nm.

[0214] Reference Figure 17 It can be seen that the resistivity (8.7 μΩ·cm) in Example 3 is smaller than that in Comparative Example 1 (17.7 μΩ·cm), the resistivity in Examples 4 to 6 (12.6 μΩ·cm, 9.9 μΩ·cm, and 7.2 μΩ·cm, respectively) is smaller than that in Comparative Example 2 (22.9 μΩ·cm), and the resistivity in Example 7 (10.9 μΩ·cm) is smaller than that in Comparative Example 3 (68.5 μΩ·cm). Similar to the resistivity (5.6 μΩ·cm) in Comparative Example 4, the resistivity in Examples 3, 5, and 7 (8.7 μΩ·cm, 9.9 μΩ·cm, and 10.9 μΩ·cm, respectively) is less than 11 μΩ·cm, while the resistivity in Comparative Examples 1 to 3 and Example 4 (17.7 μΩ·cm, 22.9 μΩ·cm, 68.5 μΩ·cm, and 12.6 μΩ·cm, respectively) is at least 11 μΩ·cm. Therefore, it can be confirmed that when the ratio of the thickness of the first sublayer to the thickness of the second sublayer is 1 or less, the first layer has a resistivity of less than 11 μΩ·cm. It is clear from the above examples and comparative examples that the resistivity varies depending on the thickness of the first sublayer, the ratio of the thickness of the first sublayer to the thickness of the second sublayer, and the content of aluminum relative to the total atomic weight of the first sublayer.

[0215] Figure 18 This is a graph showing the results of a tensile strength test on the conductive layer according to the comparative example. Figure 19 This is a graph showing the results of a tensile strength test on the conductive layer according to an embodiment, and Figure 20 This is a graph showing the results of a tensile strength test on a conductive layer according to other embodiments.

[0216] Tensile strength tests were performed on the first layer of Examples 3 to 7 and the alloy layer of Comparative Examples 1 to 5. The tensile strength tests were conducted as follows: test specimens were fabricated by patterning the first layer or alloy layer into a dog-bone shape using a focused ion beam (“FIB”) method, and in-situ measurements were performed on the test specimens using a SEM device equipped with an in-situ nanomechanical testing system (Picoindenter), and the experimental results were recorded. The results are shown in Table 2 and... Figures 18 to 20 middle. Figure 18 This is a graph showing the results of comparing Comparative Examples 1 to 3. Figure 19 The graph shows the results of comparing Examples 3, 5, and 7. Figure 20 The graph shows the results of comparing Examples 4, 5, and 6.

[0217] [Table 2]

[0218] Reference Figures 18 to 20 In Comparative Example 3, the completely amorphous test piece fractured while undergoing elastic deformation without plastic deformation, while the test pieces in Comparative Examples 1 and 2, which have nanocrystals dispersed in the amorphous phase, underwent plastic deformation after elastic deformation. The test pieces in Examples 3 to 7 each have a stacked structure comprising a first sublayer (i.e., an amorphous alloy layer) and a second sublayer (i.e., a crystalline metal layer), thus undergoing plastic deformation after elastic deformation.

[0219] Refer to Table 2 and Figures 18 to 20 It can be seen that the test specimens in Comparative Examples 1 to 3 have a high elastic strain limit greater than 3.0%, while the test specimens in Comparative Examples 4 and 5 have low elastic strain limits of 0.2% and 0.6%, respectively. It can also be seen that the test specimens in Examples 3 to 7 have elastic strain limits lower than those in Comparative Examples 1 to 3, but maintain a high elastic strain limit of at least 2.0% (ideally, at least 3.0%). It can be seen that the test specimens in Examples 3 to 7 have elastic strain limits at least ten times greater than those in Comparative Examples 4 and 5.

[0220] It can be seen that the yield strength in Comparative Examples 1 to 3 is at least 1.2 GPa, while the yield strengths in Comparative Examples 4 and 5 are 124 MPa and 503 MPa, respectively, which are relatively lower than those in other comparative examples or embodiments. It can also be seen that the yield strength in Examples 3 to 7 is a high yield strength of at least 0.8 GPa, while still lower than that in Comparative Examples 1 to 3. It can be seen that the yield strength in Examples 3 to 7 is at least eight times greater than that in Comparative Example 4.

[0221] Figures 21a to 21g Each is a perspective view schematically illustrating an embodiment of an electronic device including a display device according to an embodiment.

[0222] The display device 1 according to the foregoing embodiment can be used in various electronic devices that can provide images. Here, electronic device refers to a device that can use electricity and can provide a specific image.

[0223] Reference Figure 21a The display device according to the embodiment can be used in a wearable electronic device 3100 that can be worn by a part of a user's body. The wearable electronic device 3100 may include a main body 3110 and a display 3120 included in the main body 3110. The display device according to the embodiment can be used as the display 3120 of the wearable electronic device 3100. Figure 21a The wearable electronic device 3100 shown in the embodiment can be modified. In the embodiment, the wearable electronic device 3100 can be used as a smartwatch or a smartphone, depending on the user's choice.

[0224] Figure 21b A medical electronic device 3200 is illustrated. In an embodiment, the medical electronic device 3200 may include a body 3210 and a transmitter 3220. A display device according to an embodiment may be used as the transmitter 3220 of the medical electronic device 3200. The transmitter 3220 may emit light of a specific wavelength (e.g., infrared and / or visible light) toward a user's body. In an embodiment, the body 3210 may include an elastic fibrous material, and the transmitter 3220 may have a structure that can be worn by a user's body.

[0225] Figure 21cAn electronic device 3300 for education is illustrated. In an embodiment, the electronic device for education may include a display 3320 disposed in a frame 3310. A display device according to an embodiment may be used for the display 3320. Images such as undulating oceans, snow-covered mountains, or volcanoes with flowing lava can be provided through the display 3320, and in this case, the display 3320 may extend in the height direction (e.g., the z-direction) to reflect the height of the waves, mountains, or volcano. In some embodiments, the height of a portion of the display 3320 gradually changes in the direction along which the lava flows, so that the movement of the lava can be viewed in three dimensions. The electronic device 3300 for education may include a pin (or stroke unit 3330) disposed on the rear surface of the display 3320 such that the display 3320 extends in the height direction. As the pin 3330 moves in a third direction (e.g., the z-direction or the -z-direction), the image displayed in the display 3320 can be implemented to have three-dimensional height. Although referenced... Figure 21c An electronic device 3300 for educational purposes is described, but the use of the electronic device is not limited to this, as long as the electronic device provides specific image information.

[0226] Although reference Figures 21a to 21c The electronic devices shown herein describe electronic devices with variable shapes, but the disclosure is not limited thereto. As in the embodiments below, the display device according to the embodiments can be used in electronic devices in which the portion thereon on which an image can be displayed (e.g., a screen) is fixed.

[0227] Figure 21d A robot 3400 as an electronic device according to an embodiment is shown. The robot 3400 can be configured to identify movement or objects using a camera 3440 and to display specific images to a user via displays 3420 and 3430. In some embodiments, the display device according to the embodiment can extend in various directions as described above, and thus can be assembled to a main frame having a hemispherical shape; therefore, the robot 3400 can include displays 3420 and 3430 having hemispherical shapes.

[0228] Figure 21e A display device 3500 for a vehicle, as an electronic device according to an embodiment, is shown. The display device 3500 for a vehicle may include an instrument panel 3510, a central information display (“CID”) 3520, and / or a passenger display 3530. Since the display device according to the embodiment can extend in various directions, it can be used for the instrument panel 3510, the CID 3520, and / or the passenger display (i.e., the passenger display) 3530, regardless of the shape of the vehicle's interior frame.

[0229] although Figure 21eThe instrument panel 3510, CID 3520, and / or passenger display 3530 are shown to be separate from each other, but the disclosure is not limited thereto. In other embodiments, at least two components selected from the instrument panel 3510, CID 3520, and passenger display 3530 may be integrally connected.

[0230] In some embodiments, the display device 3500 for a vehicle may include a button 3540 for displaying a specific image. (See also...) Figure 21e The enlarged image shown shows that the hemispherical button 3540 may include an object 3542 that moves in the z-direction or -z-direction and provides a tactile feel for the button, and a display device disposed on the object 3542. In some embodiments, when the object 3542 has a three-dimensional circular surface, the display device may also have a three-dimensional circular surface.

[0231] Figure 21f An electronic device 3600 for advertising or exhibition is shown according to an embodiment. In some embodiments, the electronic device 3600 for advertising or exhibition may be mounted on a fixed structure 3610 (e.g., a wall or column). When the structure 3610 includes such... Figure 21f When the surface is rough as shown, the electronic device 3600 for advertising or exhibition can also be arranged along the rough surface of the structure 3610. In some embodiments, the electronic device 3600 for advertising or exhibition can be mounted on the structure 3610 by using a thermostatic film or the like.

[0232] Figure 21g An electronic device according to an embodiment is shown, including a controller 3700. The controller 3700 may include image-type buttons. For example, the controller 3700 may include a first button area 3720, a second button area 3730, and a third button area 3740, that is, some areas of the display 3710 that protrude in the z-direction or protrude in the -z-direction (or are recessed in the z-direction). In some embodiments, the first button area 3720 and the third button area 3740 may protrude in the z-direction, and the second button area 3730 may protrude in the -z-direction (or be recessed in the z-direction).

[0233] Although the invention has been described with reference to embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that these are merely examples and various changes and equivalent embodiments can be made therefrom. Therefore, the true scope of the invention should be defined by the technical concept of the appended claims.

Claims

1. A display device, the display device comprising a display area and a non-display area outside the display area, the display device comprising: Multiple islands are arranged in the display area and spaced apart from each other; Multiple bridging sections, each connecting adjacent island sections among the multiple island sections; as well as Multiple cablings are arranged in the multiple bridging sections. Each of the multiple wirings includes a first layer. The first layer includes a first sub-layer and a second sub-layer. The first sublayer comprises an alloy of aluminum (Al) and rare earth elements, and the second sublayer comprises aluminum.

2. The display device according to claim 1, wherein, Each of the first sub-layer and the second sub-layer is configured with a plurality of first sub-layers and a plurality of second sub-layers, and the first layer has a structure in which the plurality of first sub-layers and the plurality of second sub-layers are stacked alternately.

3. The display device according to claim 2, wherein, Two of the plurality of first sub-layers are respectively arranged on the top and bottom of the first layer.

4. The display device according to claim 1, wherein, The first sublayer includes an amorphous alloy layer.

5. The display device according to claim 1, wherein, The rare earth elements include at least one of yttrium (Y), samarium (Sm), cerium (Ce), and lanthanum (La).

6. The display device according to claim 1, wherein, The content of rare earth elements is 4 at% to 10 at% relative to the total atomic weight of the first sublayer.

7. The display device according to claim 2, wherein, The ratio of the thickness of each of the plurality of first sublayers to the thickness of each of the plurality of second sublayers is not greater than 1.

8. The display device according to claim 1, wherein, The resistivity of the first layer is greater than 5.6 μΩ·cm and less than 11 μΩ·cm.

9. The display device according to claim 1, wherein, The elastic strain limit of the first layer is at least 2.0%.

10. The display device according to claim 1, wherein, The yield strength of the first layer is 0.8 GPa to 1.2 GPa.

11. The display device according to claim 1, wherein, Each of the multiple wirings also includes a second layer below the first layer and a third layer above the first layer, and The second and third layers comprise materials different from those of the first layer.

12. The display device according to claim 1, wherein, Each of the plurality of islands includes: A transistor consists of a semiconductor and a gate electrode; Light-emitting element, electrically connected to the transistor; and An electrode is disposed between the gate electrode and the light-emitting element. The electrode comprises a third sublayer and a fourth sublayer, wherein the third sublayer comprises an alloy of aluminum and rare earth elements, and the fourth sublayer comprises aluminum.

13. A display device, the display device comprising a display area and a non-display area outside the display area, the display device comprising: Multiple islands are arranged in the display area, and each includes a transistor and a light-emitting element electrically connected to the transistor; as well as Multiple bridging sections, each connecting adjacent island sections among the multiple island sections, Each of the plurality of bridging sections includes wiring that is electrically connected to a transistor in any of the adjacent island sections. The wiring includes a first layer, and The first layer includes a first sublayer and a second sublayer, the first sublayer comprising an alloy of aluminum and rare earth elements, and the second sublayer comprising aluminum.

14. The display device according to claim 13, wherein, Each of the first sub-layer and the second sub-layer is configured with a plurality of first sub-layers and a plurality of second sub-layers, and the first layer has a structure in which the plurality of first sub-layers and the plurality of second sub-layers are stacked alternately.

15. The display device according to claim 14, wherein, Two of the plurality of first sub-layers are respectively arranged on the top and bottom of the first layer.

16. The display device according to claim 13, wherein, The rare earth elements include at least one of yttrium (Y), samarium (Sm), cerium (Ce), and lanthanum (La).

17. The display device according to claim 13, wherein, The content of rare earth elements is 4 at% to 10 at% relative to the total atomic weight of the first sublayer.

18. The display device according to claim 14, wherein, The ratio of the thickness of each of the plurality of first sub-layers to the thickness of each of the plurality of second sub-layers is greater than 0 and not greater than 1.

19. The display device according to claim 13, wherein, The resistivity of the first layer is greater than 5.6 μΩ·cm and less than 11 μΩ·cm.

20. The display device according to claim 13, wherein, The elastic strain limit of the first layer is at least 2.0%.

21. The display device according to claim 13, wherein, The yield strength of the first layer is 0.8 GPa to 1.2 GPa.

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