Method for determining an end current of a semiconductor device, determining system and storage medium

Abstract

The application discloses a method for determining the terminal current of a semiconductor device, a determination system and a storage medium. The method comprises determining the electric potential and carrier concentration in each grid; determining a plurality of doped regions and doped interfaces according to the relationship between the net doping concentration in each grid and zero, wherein the relationship between the net doping concentration of a plurality of grids in each doped region and zero is the same, and the common surface between adjacent doped regions is a doped interface; determining the interface current of the doped interface between adjacent doped regions based on the electric potential and carrier concentration of adjacent grids on both sides of the doped interface; and determining the terminal current of the semiconductor device according to the interface current flowing into the doped region and the interface current flowing out of the doped region. In this way, the current integration path can be transferred from the electrode contact boundary to the doped interface inside the semiconductor, so that the influence of the high-doping characteristics at the electrode contact boundary on the calculation accuracy of the terminal current is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method, system, and storage medium for determining the terminal current of a semiconductor device. Background Technology

[0002] Semiconductor power devices are widely used in high-voltage direct current transmission, power electronic converters, and grid-connected equipment for new energy sources. The terminal current of a semiconductor device is a crucial parameter. In related technologies, the contact-boundary integration (CBI) method is commonly used to calculate the terminal current: after obtaining the internal potential and carrier distribution of the device, the electron current density Jn and hole current density Jp, discretized using the Scharfetter-Gummel (SG) scheme of the finite volume method, are integrated along the electrode boundary to obtain the total electrode current.

[0003] However, in highly doped ohmic contact regions, when devices operate under low current or reverse bias conditions, the boundary current density given by the SG scheme is essentially represented by the difference between several extremely large fluxes. The terms An and Bn in the electron and hole current densities, along with Ap and Bp, are themselves very large, and their differences correspond to the actual physical current magnitude. In other words, the terminal current is a fraction obtained by subtracting several large numbers. In double-precision floating-point arithmetic, this type of subtraction is prone to significant loss of significant digits, resulting in the cancellation of large numbers and causing the calculated terminal current to be significantly affected by rounding errors, leading to low accuracy. Summary of the Invention

[0004] This application provides a method, system, and storage medium for determining the terminal current of a semiconductor device to solve at least some of the problems in the related art.

[0005] This application provides a method for determining the terminal current of a semiconductor device, including: The semiconductor device is discretized into a grid, and the physical model of carrier transport of the semiconductor device is solved in each grid to determine the potential and carrier concentration in each grid. Based on the relationship between the net doping concentration and zero in each grid, several doping regions and doping interfaces are determined, wherein the net doping concentration of multiple grids in each doping region has the same relationship with zero, and the common surface between adjacent doping regions is the doping interface. The interface current of the doped interface in the adjacent doped region is determined based on the potential and carrier concentration of the adjacent grids on both sides of the doped interface. The terminal current of the semiconductor device is determined based on the current conservation among the interface current flowing into the doped region, the interface current flowing out of the doped region, and the terminal current.

[0006] Optionally, the mesh discretization of the semiconductor device includes: The semiconductor device is discretized using finite volume Scharfta-Goumel. The physical model for carrier transport includes the Poisson equation and the carrier continuity equation; Solving the physical model of carrier transport in the semiconductor device includes solving the Poisson equation and the carrier continuity equation for the semiconductor device.

[0007] Optionally, the net doping concentration is the difference between the donor doping concentration and the acceptor doping concentration, and the relationship between the net doping concentration and zero includes the net doping concentration being greater than zero, the net doping concentration being less than zero, and the net doping concentration being equal to zero; the step of determining several doping regions and doping interfaces based on the relationship between the net doping concentration and zero in each grid includes: If the net doping concentration in adjacent grids has a different relationship with zero, the common surface between adjacent grids is defined as the doping interface; Using the doping interface as the boundary, multiple grids with the same net doping concentration relationship to zero are aggregated into the same doping region.

[0008] Optionally, the doped region with a net doping concentration greater than zero is the n-region, the doped region with a net doping concentration less than zero is the p-region, and the doped region with a net doping concentration equal to zero is the intrinsic region.

[0009] Optionally, determining the interface current of the doped interface of the adjacent doped region based on the potential and carrier concentration of the adjacent grids on both sides of the doped interface includes: The electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface are determined based on the potential and carrier concentration of adjacent grids on both sides of the doped interface. The interface current of the doped interface is obtained by integrating the electron current density flux, hole current density flux, and electric displacement current density flux in the normal direction of the doped interface.

[0010] Optionally, determining the electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface based on the potential and carrier concentration of adjacent grids on both sides of the doped interface includes: The electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface are determined based on the expression for electron current density flux and the hole current density flux, wherein, The expression for the electron current density flux is: ; The expression for the hole current density flux is: ; in, and Representing adjacent grids respectively and The electron current density flux and hole current density flux between them; It is the elementary charge; and These are the diffusion coefficients for electrons and holes, respectively; For grid and The effective distance in the normal direction of the doped interface; For grid , Electron concentration within; For grid , Hole concentration within; The potential of the corresponding grid; Thermoelectric voltage, Here is the Bernoulli function, defined as follows: and .

[0011] Optionally, the electric displacement current density flux is Where ε is the dielectric constant of the semiconductor device, The gradient of the electric potential, This represents the time derivative.

[0012] Optionally, after discretizing the semiconductor device into a grid, solving the physical model of carrier transport in each grid, and determining the potential and carrier concentration in each grid, the determination method further includes: The first coefficient in the calculation of the electron current density flux between adjacent grids on both sides of the electrode contact boundary is based on the potential and carrier concentration in the adjacent grids on both sides of the electrode contact boundary. The value and the second coefficient The third coefficient in the value of the hole current density flux between adjacent grids on both sides of the electrode contact boundary. The value and the fourth coefficient The value; If the first coefficient With the second coefficient The absolute value of the difference and the third coefficient The value and the fourth coefficient The sum of the absolute values ​​of the differences and the first coefficient Second coefficient Third coefficient Fourth coefficient If the ratio between the sums is less than a preset threshold, several doping regions and doping interfaces are determined based on the relationship between the net doping concentration in each grid and zero.

[0013] Another aspect of this application provides an apparatus for determining the terminal current of a semiconductor device, including a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement a method for determining the terminal current of the semiconductor device.

[0014] In another aspect, this application provides a storage medium storing a program that, when executed, implements a method for determining the terminal current of a semiconductor device.

[0015] Compared with related technologies, the method, system, and storage medium for determining the terminal current of a semiconductor device provided in this application determine several doped regions and doped interfaces based on the relationship between the net doping concentration and zero in each grid; and determine the interface current of the doped interface of adjacent doped regions based on the potential and carrier concentration of adjacent grids on both sides of the doped interface; and determine the terminal current of the semiconductor device based on the interface current flowing into the doped region, the interface current flowing out of the doped region, and the current conservation between the terminal currents. In this way, the current integration path can be shifted from the electrode contact boundary to the doped interface inside the semiconductor, avoiding the influence of the high doping characteristics at the electrode contact boundary on the calculation accuracy of the interface current, and thus affecting the calculation accuracy of the terminal current, which is beneficial to improving the calculation accuracy of the terminal current of the semiconductor device. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] Figure 1 This is a flowchart illustrating a method for determining the terminal current of a semiconductor device according to an embodiment of this application.

[0018] Figure 2 for Figure 1 A flowchart illustrating one embodiment of step 12 in the method for determining the terminal current of the semiconductor device shown.

[0019] Figure 3 for Figure 1 A flowchart illustrating one embodiment of step 13 in the method for determining the terminal current of the semiconductor device shown.

[0020] Figure 4This is a schematic diagram of the structure of the doped interface and doped region as defined in one embodiment of this application.

[0021] Figure 5 This is a schematic diagram illustrating the trend of terminal current calculation accuracy as a function of grid resolution.

[0022] Figure 6 This is a schematic diagram of the structure of the doped interface and doped region as defined in another embodiment of this application.

[0023] Figure 7 This is a single-pulse Buck test circuit topology that includes semiconductor devices.

[0024] Figure 8 This represents the waveforms of the current at the anode, cathode, and gate terminals as a function of time.

[0025] Figure 9 This is a logarithmic coordinate curve showing the change of the current conservation residual over time.

[0026] Figure 10 This is a structural block diagram of a device for determining the terminal current of a semiconductor device according to one embodiment of this application. Detailed Implementation

[0027] This application provides a method, system, and storage medium for determining the terminal current of a semiconductor device. The method, system, and storage medium for determining the terminal current of a semiconductor device according to this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features described in the following embodiments and implementations can be combined with each other.

[0028] Semiconductor power devices (such as integrated gate commutated thyristors (IGCTs) and insulated gate bipolar transistors (IGBTs) are widely used in high-voltage direct current (HVDC) transmission, power electronic converters, and grid-connected equipment for new energy sources. To evaluate the conduction and turn-off behavior of devices under actual operating conditions and their dynamic interaction with external circuits during the design phase, technical computer-aided design (TCAD) tools are commonly used in engineering to perform numerical simulations of the internal electric field distribution, carrier transport, and temperature field of the devices, and to conduct device-circuit co-simulation with circuit-level simulators. A typical approach is to establish the Poisson equation and carrier continuity equation based on a physical model of carrier transport, and then discretize these partial differential equations on a mesh using the finite-volume Scharfetter-Gummel (SG) scheme, thereby strictly satisfying current conservation at the control volume scale.

[0029] In such TCAD simulations and device-circuit co-simulations, device terminal currents are not only key observables for evaluating device physical behavior but also interface variables for coupling differential-algebraic equations of external circuits. In related technologies, the contact-boundary integration (CBI) method is widely used in industry and academia to calculate terminal currents: after obtaining the internal potential and carrier distribution of the device, the total electrode current is obtained by integrating along the electrode boundary at the ohmic contact boundary based on the electron current density Jn and hole current density Jp discretized by SG. This method is simple to implement and easy to integrate, and therefore adopted by most commercial or self-developed TCAD tools.

[0030] However, in highly doped ohmic contact regions, when devices operate under low current or reverse bias conditions, the boundary current density given by the SG scheme is essentially represented by the difference between several extremely large fluxes. The terms An and Bn in the electron and hole current densities, along with Ap and Bp, are themselves very large, and their differences correspond to the magnitude of the actual physical current. In other words, the terminal current is a fraction obtained by subtracting several large numbers. Under double-precision floating-point arithmetic, this type of subtraction of large numbers easily leads to significant loss of significant digits, resulting in the cancellation of large number subtractions. This causes the calculated terminal current to be significantly affected by rounding errors, making it difficult to reflect the local conservation properties guaranteed by finite volume discretization. The direct result is that even with significantly refined meshes or tightened Newton iteration convergence tolerances, the terminal current based on CBI still has significant current non-conservation residuals, and the algebraic sum of the electrode currents is difficult to reduce to a level of numerical accuracy.

[0031] In pure device simulation, small-amplitude non-conservation of terminal current can be handled through empirical judgment and special post-processing. However, in device-circuit coupled simulation, this problem is amplified: the terminal current calculated by TCAD is directly used as the current source or branch current in the circuit equations for solving. Its numerical non-conservation is equivalent to introducing spurious injection currents at circuit nodes, violating Kirchhoff's current law that the circuit topology should satisfy. For rigid, multi-timescale systems such as high-voltage, high-power converters, numerical noise in the terminal current can lead to residuals that are difficult to converge, frequent step size regressions, or even divergence in the circuit differential-algebraic equations during Newton iteration, seriously affecting the convergence and engineering usability of device-circuit co-simulation. Therefore, while maintaining the existing SG discrete framework and device physical model, how to improve the terminal current calculation strategy, avoid numerical ill-conditioning caused by large number subtraction at contact boundaries, restore the numerical conservation of terminal current, and improve the robustness of device-circuit coupled solutions has become an urgent technical problem to be solved in this field.

[0032] Please refer to Figure 1 , Figure 1This is a flowchart illustrating a method 10 for determining the terminal current of a semiconductor device according to an embodiment of this application.

[0033] like Figure 1 As shown, the method 10 for determining the terminal current of a semiconductor device provided in this application includes steps 11 to 14.

[0034] Step 11: Discretize the semiconductor device into a grid, solve the physical model of carrier transport in each grid, and determine the potential and carrier concentration in each grid. Step 12: Based on the relationship between the net doping concentration and zero in each grid, determine several doping regions and doping interfaces. In each doping region, the net doping concentration of multiple grids has the same relationship with zero, and the common surface between adjacent doping regions is the doping interface. Step 13: Determine the interface current of the doped region based on the potential and carrier concentration of the adjacent grids on both sides of the doped interface. Step 14: Determine the terminal current of the semiconductor device based on the current conservation among the interface current flowing into the doped region, the interface current flowing out of the doped region, and the terminal current.

[0035] The present application provides a method, system, and storage medium for determining the terminal current of a semiconductor device. The method 10 determines several doped regions and doped interfaces based on the relationship between the net doping concentration and zero in each grid. It then determines the interface current of the doped interface between adjacent doped regions based on the potential and carrier concentration of adjacent grids on both sides of the doped interface. Finally, it determines the terminal current of the semiconductor device based on the interface current flowing into the doped region, the interface current flowing out of the doped region, and the current conservation between terminal currents. This allows the current integration path to be shifted from the electrode contact boundary to the doped interface inside the semiconductor, avoiding the impact of high doping characteristics at the electrode contact boundary on the calculation accuracy of the interface current, and consequently, the calculation accuracy of the terminal current. It also avoids the undesirable numerical structure of subtracting multiple large numbers to obtain a small number in highly doped ohmic contact regions, significantly reducing the terminal current calculation error caused by the loss of significant bits in floating-point numbers. This reduces the terminal current conservation residual by several orders of magnitude, which is beneficial for improving the calculation accuracy of the terminal current of the semiconductor device.

[0036] In some embodiments, mesh discretization of a semiconductor device includes: The finite volume method Scharfta-Goumel discretization is used to discretize semiconductor devices. Finite volume method Scharfta-Goumel discretization is a dedicated spatial discretization technique for solving the physical model of semiconductor devices.

[0037] The finite volume method refers to dividing the three-dimensional or two-dimensional physical space of a semiconductor device into multiple non-overlapping control volumes, or grids, to ensure the conservation of physical quantities such as carrier concentration and potential within the grid, such as current conservation and charge conservation.

[0038] The physical model of carrier transport can be a drift-diffusion model, including the Poisson equation and the carrier continuity equation; solving the physical model of carrier transport in semiconductor devices includes solving the Poisson equation and the carrier continuity equation for semiconductor devices.

[0039] To address the strong coupling between the Poisson equation and the carrier continuity equation in semiconductor devices, the finite volume method adapts to the solution logic of the Scharfta-Goumer algorithm through specific grid node layout and boundary treatment, facilitating the solution of the Poisson equation and the carrier continuity equation in semiconductor devices, thereby determining the potential and carrier concentration in each grid.

[0040] In some embodiments, the net doping concentration is the difference between the donor doping concentration and the acceptor doping concentration. ,in, Donor doping concentration, This represents the acceptor doping concentration. The relationship between net doping concentration and zero includes net doping concentration greater than zero, net doping concentration less than zero, and net doping concentration equal to zero. When the current is greater than 0, free electrons are the majority carriers, and the number of free electrons is far greater than the number of holes. The current is mainly formed by the drift and diffusion of electrons. When the current is less than 0, holes are the majority carriers, and the number of holes is far greater than the number of free electrons. The current is mainly formed by the drift and diffusion of holes. When the doping concentration is 0, there are no significant majority carriers, and the electron and hole concentrations are approximately equal to the carrier concentration of the intrinsic semiconductor, resulting in weak conductivity. The doped region with a net doping concentration greater than zero is the n-region, the doped region with a net doping concentration less than zero is the p-region, and the doped region with a net doping concentration equal to zero is the intrinsic region.

[0041] The doping characteristics of semiconductor devices are determined during semiconductor design. The net doping concentration of each part of a semiconductor device is a fixed value. After the semiconductor device is discretized into a grid, the net doping concentration within each grid can be determined based on the net doping concentration of each part of the semiconductor device and the grid discretization method.

[0042] Please refer to Figure 2 , Figure 2 for Figure 1 This is a flowchart illustrating one embodiment of step 12 in method 10 for determining the terminal current of the semiconductor device. (See attached diagram.) Figure 2As shown, step 12 determines several doping regions and doping interfaces based on the relationship between the net doping concentration in each grid and zero, including steps 121 to 122.

[0043] Step 121: If the net doping concentration in adjacent grids has a different relationship with zero, the common surface between adjacent grids is determined as the doping interface. Step 122: Using the doping interface as the boundary, aggregate multiple grids with the same net doping concentration relative to zero into the same doping region.

[0044] Steps 121-122 are the key steps from discrete mesh to physical region partitioning. By first identifying the interface and then aggregating the regions, the computational mesh is transformed into doped regions with clear physical meaning, providing physical boundaries for subsequent interface current calculations.

[0045] In step 121, during the actual operation, all adjacent grids are traversed, and the relationship between their net doping concentration and zero is compared. If the relationship is different, the common surface of the two grids is defined as the doping interface. The relationship between net doping concentration and zero includes net doping concentration greater than zero, net doping concentration less than zero, and net doping concentration equal to zero. If the relationship between the net doping concentration and zero of adjacent grids is not the same, the common surface of the two adjacent grids is defined as the doping interface. In this way, the physical boundaries where the carrier type and concentration change abruptly in semiconductor devices, such as PN junctions and PI junctions, can be accurately located. These boundaries are critical regions for current transport and require separate calculation of interface current.

[0046] In step 122, using the doping interface identified in step 121 as the dividing boundary, all grids with the same net doping concentration relative to zero are grouped into the same doping region, ultimately forming three types of doping regions. n-type doped region: (The text abruptly ends here, so the translation stops as well.) The p-type doped region is formed by the aggregation of grids with a charge density greater than 0, where electrons are the majority carriers. The region is formed by the aggregation of grids with values ​​less than 0, where holes are the majority carriers. Intrinsic region: composed of... The grid is aggregated with 0 = 0, and there are no obvious majority carriers. In this way, discrete grids can be transformed into domain cells with consistent physical properties.

[0047] In summary, steps 121-122, by first finding the interface and then dividing the region, transform the discrete computational grid into a physical region consistent with the actual device structure, providing a precise boundary for subsequent interface current calculation. This serves as a crucial bridge connecting grid discretization and terminal current calculation, determining the accuracy and efficiency of the terminal current calculation.

[0048] Please refer to Figure 3 , Figure 3 for Figure 1 This is a flowchart illustrating one embodiment of step 13 in method 10 for determining the terminal current of the semiconductor device. (See attached diagram.) Figure 3 As shown, step 13, determining the interface current of the doped region based on the potential and carrier concentration of the adjacent grids on both sides of the doped interface, includes steps 131 and 132.

[0049] Step 131: Determine the electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface based on the potential and carrier concentration of the adjacent grids on both sides of the doped interface. Step 132: Integrate the electron current density flux, hole current density flux, and electric displacement current density flux in the normal direction of the doped interface to obtain the interface current of the doped interface.

[0050] Wherein, electron current density flux is the current density formed by electron transport across the interface, hole current density flux is the current density formed by hole transport across the interface, and electric displacement current density flux is the displacement current formed by the change of electric field (potential gradient changes with time) at the interface. In the embodiments of this application, firstly, the electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface are determined based on the potential and carrier concentration of adjacent grids on both sides of the doped interface. Then, the electric displacement current density flux is determined. Finally, the electron current density flux, hole current density flux, and electric displacement current density flux are integrated in the normal direction of the doped interface to obtain the interface current of the doped interface. The interface current of the doped interface is the sum of the integrals of the electron current density flux, hole current density flux, and electric displacement current density flux in the interface normal direction.

[0051] In this embodiment, the electron current density flux, hole current density flux, and electric displacement current density flux are integrated along the normal direction of the doped interface, avoiding the inaccuracy of the interface current and consequently the terminal current caused by the integration at the electrode boundary in related technologies. Because the magnitudes of the electron and hole current density fluxes on both sides of the doped interface are moderate, there is no loss of significant figures due to large number subtraction. Furthermore, this embodiment introduces the electric displacement current density to ensure that the interface current reflects the contribution of electric field changes under dynamic operating conditions such as device switching and voltage surges, further improving the accuracy of the interface current.

[0052] In some embodiments, step 131, determining the electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface based on the potential and carrier concentration of adjacent grids on both sides of the doped interface, includes: The electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface are determined based on the expression for electron current density flux and hole current density flux. The expression for electron current density flux is: ; The expression for hole current density flux is: ; in, and Representing adjacent grids respectively and The electron current density flux and hole current density flux between them; It is the elementary charge; and These are the diffusion coefficients for electrons and holes, respectively; For grid and The effective distance in the normal direction of the doped interface; For grid , Electron concentration within; For grid , Hole concentration within; The potential of the corresponding grid; Thermoelectric voltage, Here is the Bernoulli function, defined as follows: and .

[0053] In some embodiments, in step 132, the electric displacement current density flux is Where ε is the dielectric constant of the semiconductor device, The gradient of the electric potential, The time derivative is represented by the electric displacement current density flux, which describes the current density generated by the change of the electric field at the interface over time. The dielectric constant of a semiconductor device is an inherent electrical property of the semiconductor material, describing the material's ability to store charge, and is related to the material type. The electric potential is obtained by solving the physical model of carrier transport in the semiconductor device within each grid. The gradient of the electric potential describes the spatial rate of change of the potential (ψ) inside the semiconductor, reflecting the electric field strength, E = - ψ, the negative sign indicates that the direction of the electric field is opposite to the direction of the potential gradient.

[0054] In some embodiments, after discretizing the semiconductor device into a grid, solving the physical model of carrier transport in each grid, and determining the potential and carrier concentration in each grid, method 10 further includes: The first coefficient in the calculation of the electron current density flux between adjacent grids on both sides of the electrode contact boundary is based on the potential and carrier concentration in the adjacent grids on both sides of the electrode contact boundary. The value and the second coefficient The third coefficient in the value of the hole current density flux between adjacent grids on both sides of the electrode contact boundary. The value and the fourth coefficient The value; If the first coefficient With the second coefficient The absolute value of the difference and the third coefficient The value and the fourth coefficient The sum of the absolute values ​​of the differences and the first coefficient Second coefficient Third coefficient Fourth coefficient If the ratio between the sums is less than a preset threshold, several doping regions and doping interfaces are determined based on the relationship between the net doping concentration in each grid and zero.

[0055] If the first coefficient With the second coefficient The absolute value of the difference and the third coefficient The value and the fourth coefficient The sum of the absolute values ​​of the differences and the first coefficient Second coefficient Third coefficient Fourth coefficient If the ratio between the sums is less than a preset threshold, it indicates that the electron current density flux and hole current density flux between adjacent grids on both sides of the electrode contact boundary are too close. In this case, continuing to integrate at the electrode contact boundary to determine the interface current will result in inaccurate interface current.

[0056] Therefore, in the embodiments of this application, if the first coefficient With the second coefficient The absolute value of the difference and the third coefficient The value and the fourth coefficient The sum of the absolute values ​​of the differences and the first coefficient Second coefficient Third coefficient Fourth coefficient If the ratio between the sums is less than a preset threshold, step 12 of this patent application is executed to determine several doped regions and doped interfaces based on the relationship between the net doping concentration in each grid and zero. Following step 12, steps 13 and 14 are executed. Step 13 can improve the calculation accuracy of the interface current, and step 14, based on the improved accuracy of the interface current, can improve the calculation accuracy of the terminal current of the semiconductor device.

[0057] In some embodiments, step 14 determines the terminal current of the semiconductor device based on the current conservation among the interface current flowing into the doped region, the interface current flowing out of the doped region, and the terminal current. Specifically: for a boundary doped region connected to only one doped interface and one electrode, the current flowing out of the electrode of the doped region is set to be equal to the interface current; for an internal doped region connected to two or more doped interfaces, the sum of all interface currents flowing into the doped region is set to be equal to the current at the corresponding electrode of the doped region. Based on this, a set of equations is established, and by solving the set of equations, the mapping relationship between all electrode currents and each doped interface current is obtained, thereby achieving consistent reconstruction of the terminal current of a multi-terminal semiconductor device.

[0058] In some embodiments, the method 10 for determining the terminal current of a semiconductor device provided in this application can be used for semiconductor device-circuit coupled transient simulation. When performing semiconductor device-circuit coupled transient simulation, an implicit time integration scheme or a piecewise linearized circuit solver is used, and the terminal current obtained by the doping interface integration method is used as the input variable of the circuit differential-algebraic equation.

[0059] In summary, the method 10 for determining the terminal current of a semiconductor device provided in this application has the following beneficial effects: 1. Effectively avoids the problem of large number subtraction cancellation: By moving the current integration path from the electrode contact boundary to the internal doped interface, the undesirable numerical structure of "multiple large numbers subtracted to obtain a small number" in the highly doped ohmic contact region is avoided, which significantly reduces the terminal current calculation error caused by the loss of effective bits of floating point numbers, and reduces the terminal current conservation residual by several orders of magnitude.

[0060] 2. Significantly improves device-circuit coupling convergence: The terminal current determined by the semiconductor device terminal current determination method 10 provided in this application is more conserved and smooth in numerical terms, which significantly suppresses the spurious injection current introduced by terminal current noise, thereby reducing the residual fluctuation of circuit equations and the number of Newton iteration backoffs. In device-circuit coupling transient simulation, it can significantly improve convergence performance and avoid iterative divergence caused by ill-conditioned port current values.

[0061] 3. Maintaining the original discretization format and solution framework unchanged: The method 10 for determining the terminal current of semiconductor devices provided in this application improves upon the completion of SG discretization and device PDE solution by replacing the terminal current calculation strategy. It does not require modification of the original carrier transport physical model, mesh structure and nonlinear solver. It can be integrated into the existing TCAD or self-developed simulation platform by simply adding doping region partitioning, interface integration and KCL backtracking modules, resulting in low engineering porting costs.

[0062] 4. Adaptable to multi-terminal and complex device structures: By rationally dividing the doped region and calculating the interface current at all doped interfaces, and then establishing a unified linear relationship by combining Kirchhoff's current law, the method of this application can be naturally extended to multi-terminal power devices and two-dimensional and three-dimensional complex structure devices, and has good versatility and scalability.

[0063] 5. Improve overall simulation efficiency while ensuring accuracy: In the transient simulation example of high-voltage and high-power devices, the terminal current is calculated using the method of this application. Compared with the traditional CBI method, the number of Newton iterations and time step backs of the device-circuit coupled solver is significantly reduced while maintaining or improving the accuracy of terminal current calculation. The overall simulation time is shortened, and the unity of high-precision terminal current calculation and efficient co-simulation is achieved.

[0064] To verify the feasibility and effectiveness of the method 10 for determining the terminal current of a semiconductor device provided in this application, two specific cases are used for illustration.

[0065] Case 1 uses a one-dimensional PN junction model as the verification object to illustrate the improvement in the accuracy of terminal current calculation and grid convergence of the semiconductor device determination method 10 provided in this application under a simple device structure. Please refer to... Figure 4 , Figure 4 This is a schematic diagram of the structure of the doped interface and doped region as defined in one embodiment of this application. The total length of the PN junction device is 20 μm, with the left half being the P-region and the right half being the N-region. The absolute values ​​of the net doping concentration are both... Ideal ohmic contact boundary conditions are applied at both ends. The internal physical equations based on a carrier transport physics model are used, including the Poisson equation and the electron-hole continuity equations. Spatial discretization employs the finite-volume Scharfetter-Gummel (SG) scheme, conservatively discretizing the total current density within each control volume. Steady-state solutions or pseudo-time-progression to steady state are used to obtain the steady-state solution of the one-dimensional PN junction after nonlinear iterative convergence.

[0066] According to the semiconductor device terminal current determination method 10 provided in the embodiments of this application, based on the net doping distribution... The symbol is used to divide the entire PN junction into two doped regions: the left P-region and the right N-region. The common surface between two adjacent doped regions, i.e., the PN junction location, is defined as the doping interface. For the one-dimensional PN junction in this embodiment, only two doped regions and one doping interface are required.

[0067] After steady-state iterative convergence, this embodiment calculates the electron current density flux and hole current density flux at the doped interface of the PN junction based on the SG discretization results, and integrates along the doped interface to obtain the interface current. Subsequently, the P-region and N-region are considered as current-conserving control volumes, and Kirchhoff's current law is applied to the two doped regions: the interface current of one doped region is equal to or opposite to the current at its corresponding contact electrode, while the interface current of the other doped region satisfies a current balance relationship with its electrode current. By solving this set of simple linear relationships, the terminal currents at the anode and cathode ports can be reconstructed, thus realizing the terminal current calculation based on the doped interface.

[0068] To evaluate the advantages of the semiconductor device terminal current determination method 10 provided in this application embodiment compared to the traditional contact boundary integration (CBI) method, this embodiment, under the same physical model and numerical solution framework, uses both the CBI method and the semiconductor device terminal current determination method 10 provided in this application embodiment (hereinafter referred to as the doped interface integration (DII) method) to calculate the terminal current, and defines the relative error of the terminal current based on a high-precision reference solution. The relationship between the relative error of the terminal current and the number of grid cells is compared at a series of different grid resolutions (e.g., from tens of cells to thousands of cells). Please refer to... Figure 5 , Figure 5 This is a schematic diagram illustrating the trend of terminal current calculation accuracy as a function of grid resolution. (Example:) Figure 5 As shown, when using the traditional CBI method, the error decreases slightly with mesh refinement when the mesh is coarse. However, as the mesh continues to be refined, the relative error of the terminal current gradually approaches saturation, and the error no longer decreases significantly with mesh refinement. When using the doped interface integral (DII) method of this application, the relative error of the terminal current continues to decrease throughout the mesh refinement process, and the convergence trend is consistent with the theoretical convergence order of SG discretization on the internal control volume.

[0069] The results show that the terminal current determination method 10 provided in this embodiment effectively avoids the problem of numerical accuracy loss caused by large number subtraction in the contact area by shifting the current integration path from the ohmic contact boundary to the PN junction doped interface, restores the grid convergence of the SG format when used for terminal current calculation, and greatly improves the accuracy and robustness of terminal current calculation.

[0070] Case 2 uses an integrated gate commutated thyristor (IGCT) power device and its single-pulse test circuit as the object to verify the application effect of the method of this application in transient simulation of complex multi-terminal devices coupled with external circuits.

[0071] Please refer to Figure 6 , Figure 6The diagram shows the structure of the doped interface and doped region as defined in one embodiment of this application. This is based on the net doping distribution within the IGCT device. Its vertical structure is divided into four doped regions: a highly doped region on the anode side, a buffer layer region, a base region, and a doped region on the cathode side. The highly doped region on the anode side is... Figure 6 The doped region 4 and the buffer layer region are Figure 6 The doped region 3 and the base region are Figure 6 Doped region 2 in the cathode side is Figure 6 The device is divided into three doped regions. The doping interfaces between adjacent doped regions are defined as three doped interfaces. The anode, cathode, and gate of the device are connected to the external circuit via ohmic contacts. The internal physical model of carrier transport and the finite-volume SG discretization scheme are also used. The Poisson equation and carrier continuity equation are solved under a two-dimensional cross-sectional model. Implicit time-stepping methods can be used for time integration to meet the simulation requirements of highly nonlinear and rigid transient processes in high-voltage, high-power devices.

[0072] According to the doping interface integration method in this embodiment, after each time step or each nonlinear iteration converges, the fluxes of electron current, hole current, and displacement current in the normal direction are calculated only at the three doped interfaces, and the interfaces are integrated to obtain the interface current of each doped interface. Subsequently, the four doped regions are regarded as current-conserving control volumes, and Kirchhoff's current law is applied to each doped region. This constitutes a set of linear equations concerning the anode, cathode, and gate currents and the interface currents. By solving this set of equations, the terminal currents of the three electrodes can be obtained, realizing the unified reconstruction of the terminal currents of the multi-terminal IGCT device.

[0073] This method can be extended to any number of doped regions and any multi-terminal structure. By establishing a system of equations where the inflow current equals the outflow current for all doped regions, the mapping relationship between the current at each electrode and the internal interface current is obtained, thereby achieving consistent reconstruction of the terminal current in multi-terminal semiconductor devices. Using this method, this application can obtain terminal currents with higher accuracy and better numerical conservation without relying on the boundary flux data of numerical ill-conditioned ohmic contacts.

[0074] Please refer to Figure 7 , Figure 7 This is a single-pulse Buck test circuit topology that includes semiconductor devices. Figure 7 In the illustrated embodiment, the semiconductor device is an IGCT device. In some other embodiments, the semiconductor device may also be an insulated gate bipolar transistor (IGBT), a power MOSFET, or a combination thereof.

[0075] The single-pulse Buck test circuit topology includes a voltage source. V DCCurrent-limiting inductors, load resistors, and gate drive networks, etc. Current-limiting inductors ( L i This inductor is used to limit the rate of change of current. It helps smooth current spikes and limits the risk of high-frequency oscillations; current-limiting resistor ( R s This resistor is used to dissipate heat. L i The energy stored in it is converted into heat energy to prevent damage from inductors. L i Overvoltage caused by current changes; current-limiting capacitor ( C CL This capacitor is used to limit the influence of large inductance. L i The overvoltage caused by this circuit protects it from damage due to excessive voltage; current-limiting diode ( D CL This diode is used for conduction. L i The energy stored in the capacitor is dissipated through resistors and current-limiting capacitors to prevent overvoltage. Total parasitic inductance ( L CL This represents the total parasitic inductance of components in the circuit, including current-limiting capacitors, current-limiting diodes, IGCTs, and freewheeling diodes; it is the sum of the parasitic inductances of these components. (Load inductance) L load ) and load resistance ( R load These two components simulate the load in the circuit. The load inductance represents the inductive behavior of the load, and the load resistance represents its resistive characteristics, in which energy is dissipated; the freewheeling diode (FWD) allows current to flow and prevents voltage spikes from damaging the device when the IGCT is off.

[0076] The working principle of the single-pulse Buck test circuit topology is as follows: This circuit is essentially similar to a Buck converter, where the IGCT is controlled to turn on and off. When the IGCT is on, current flows through the circuit and transfers electrical energy to the load. When the IGCT is off, the freewheeling diode (FWD) allows current to continue flowing. L i The energy stored in it is passed through a current-limiting resistor ( R s ) and current limiting capacitor ( C CL Dissipation. Current-limiting diode ( D CL ) helps guide L iThe energy stored in the circuit is used to prevent overvoltage. Parasitic inductance simulates parasitic elements that arise from physical connections in a circuit, which affect the overall performance of the circuit.

[0077] The IGCT device is considered as a three-terminal nonlinear circuit element. Its terminal voltage and terminal current are coupled with the differential-algebraic equations of the external circuit through boundary conditions. In each time step, the circuit solver provides the terminal voltages, the device solver calculates the internal field quantities and doped interface currents based on the terminal voltages, and then the port current is reconstructed by the terminal current determination method 10 provided in this embodiment and returned to the circuit solver. The two are coupled and solved through Newton iteration or block iteration.

[0078] Under the unified simulation framework described above, this embodiment uses both the traditional CBI method and the doped interface integration method of this embodiment to calculate the terminal current of the IGCT device, and compares and analyzes the transient simulation results. Figure 8 The waveforms show the changes in current at the anode, cathode, and gate terminals over time. Figure 9 For current conservation residual A logarithmic coordinate curve that varies with time. Among them... , and These represent the magnitudes of the currents flowing out of the anode, cathode, and gate of the IGCT device, respectively. Figure 9 It can be seen that the method 10 for determining the terminal current of semiconductor materials provided in this application improves the calculation accuracy of terminal current conservation by two orders of magnitude compared with the traditional CBI method.

[0079] Another aspect of this application provides a device for determining the terminal current of a semiconductor device. Figure 10 This is a structural block diagram of a semiconductor device terminal current determination apparatus according to an embodiment of the present application. The semiconductor device terminal current determination apparatus includes a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements a semiconductor device terminal current determination method 10.

[0080] exist Figure 10 In the illustrated embodiment, the device 5 for determining the terminal current of the semiconductor device may include a storage medium 32, which may store a program that can be invoked by a processor 31, and may include a non-volatile storage medium. In some embodiments, the determining device 5 may include a memory 33 and an interface 34. In some embodiments, the determining device 5 may also include other hardware depending on the actual application.

[0081] This application, in another aspect, provides a storage medium storing a program that, when executed, implements a method 10 for determining the terminal current of a semiconductor device. In some embodiments, the program may take the form of a computer program product implemented on one or more storage media 32 (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing program code. The storage medium 32 includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented using any method or technology. The information may be computer-readable instructions, data structures, program modules, or other data. Examples of storage media 32 include, but are not limited to: phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0082] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0083] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for determining the terminal current of a semiconductor device, characterized in that, The determination methods include: The semiconductor device is discretized into a grid, and the physical model of carrier transport of the semiconductor device is solved in each grid to determine the potential and carrier concentration in each grid. Based on the relationship between the net doping concentration and zero in each grid, several doping regions and doping interfaces are determined, wherein the net doping concentration of multiple grids in each doping region has the same relationship with zero, and the common surface between adjacent doping regions is the doping interface. The interface current of the doped interface in the adjacent doped region is determined based on the potential and carrier concentration of the adjacent grids on both sides of the doped interface. The terminal current of the semiconductor device is determined based on the current conservation among the interface current flowing into the doped region, the interface current flowing out of the doped region, and the terminal current.

2. The method for determining the terminal current of a semiconductor device according to claim 1, characterized in that, The process of mesh discretizing the semiconductor device includes: The semiconductor device was discretized using the finite volume method Scharfta-Gummel scheme; The physical model for carrier transport includes the Poisson equation and the carrier continuity equation; Solving the physical model of carrier transport in the semiconductor device includes solving the Poisson equation and the carrier continuity equation for the semiconductor device.

3. The method for determining the terminal current of a semiconductor device according to claim 1, characterized in that, The net doping concentration is the difference between the donor doping concentration and the acceptor doping concentration. The relationship between the net doping concentration and zero includes the net doping concentration being greater than zero, the net doping concentration being less than zero, and the net doping concentration being equal to zero. The determination of several doping regions and doping interfaces based on the relationship between the net doping concentration and zero within each grid includes: If the net doping concentration in adjacent grids has a different relationship with zero, the common surface between adjacent grids is defined as the doping interface; Using the doping interface as the boundary, multiple grids with the same net doping concentration relationship to zero are aggregated into the same doping region.

4. The method for determining the terminal current of a semiconductor device according to claim 3, characterized in that, The doped region with a net doping concentration greater than zero is the n-region, the doped region with a net doping concentration less than zero is the p-region, and the doped region with a net doping concentration equal to zero is the intrinsic region.

5. The method for determining the terminal current of a semiconductor device according to claim 1, characterized in that, Determining the interface current of the doped region based on the potential and carrier concentration of adjacent grids on both sides of the doped interface includes: The electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface are determined based on the potential and carrier concentration of the adjacent grids on both sides of the doped interface. The interface current of the doped interface is obtained by integrating the electron current density flux, hole current density flux, and electric displacement current density flux in the normal direction of the doped interface.

6. The method for determining the terminal current of a semiconductor device according to claim 5, characterized in that, The step of determining the electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface based on the potential and carrier concentration of adjacent grids on both sides of the doped interface includes: The electron current density flux and hole current density flux between adjacent grids on both sides of the doped interface are determined based on the expression for electron current density flux and the hole current density flux, wherein, The expression for the electron current density flux is: ; The expression for the hole current density flux is: ; in, and Representing adjacent grids respectively and The electron current density flux and hole current density flux between them; It is the elementary charge; and These are the diffusion coefficients for electrons and holes, respectively; For grid and The effective distance in the normal direction of the doped interface; For grid , Electron concentration within; For grid , Hole concentration within; The potential of the corresponding grid; Thermoelectric voltage, Here is the Bernoulli function, defined as follows: .

7. The method for determining the terminal current of a semiconductor device according to claim 5, characterized in that, The electric displacement current density flux is Where ε is the dielectric constant of the semiconductor device, The gradient of the electric potential, This represents the time derivative.

8. The method for determining the terminal current of a semiconductor device according to claim 1, characterized in that, After discretizing the semiconductor device into a grid, solving the physical model of carrier transport in each grid, and determining the potential and carrier concentration in each grid, the determination method further includes: The first coefficient in the calculation of the electron current density flux between adjacent grids on both sides of the electrode contact boundary is based on the potential and carrier concentration in the adjacent grids on both sides of the electrode contact boundary. The value and the second coefficient The third coefficient in the value of the hole current density flux between adjacent grids on both sides of the electrode contact boundary. The value and the fourth coefficient The value; If the first coefficient With the second coefficient The absolute value of the difference and the third coefficient The value and the fourth coefficient The sum of the absolute values ​​of the differences and the first coefficient Second coefficient Third coefficient Fourth coefficient If the ratio between the sums is less than a preset threshold, several doping regions and doping interfaces are determined based on the relationship between the net doping concentration in each grid and zero.

9. A device for determining the terminal current of a semiconductor device, characterized in that, It includes a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for determining the terminal current of the semiconductor device as described in any one of claims 1-8.

10. A storage medium, characterized in that, The storage medium stores a program that, when executed, implements the method for determining the terminal current of the semiconductor device as described in any one of claims 1-8.

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