Satellite navigation chip system input clock pin CDM protection method and packaging structure

Abstract

The application provides a satellite navigation chip system input clock pin CDM protection method and packaging structure. The satellite navigation chip includes at least one system input clock pin, the method includes obtaining the chip power-on working state, chip pin electrical parameters and chip current consumption of the satellite navigation chip before and after CDM test, and determining the failed system input clock pin according to the changes of the above parameters before and after CDM test. A protection structure is arranged on the clock input path corresponding to the failed system input clock pin. In the case that the protection structure includes a protection resistor, the resistance value of the protection resistor is determined according to the CDM test voltage, the system input clock frequency, the crystal oscillator output impedance, the chip input capacitance and the packaging parasitic capacitance. Whether the protection structure meets the CDM protection requirement is determined through CDM test verification again, and the method can improve the CDM protection capability of the clock pin without reflowing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit reliability testing technology, specifically to a CDM protection method and packaging structure for the input clock pin of a satellite navigation chip system. Background Technology

[0002] Satellite navigation chips are widely used in communications, aviation, aerospace, military, and missile-borne / spaceborne equipment, requiring high reliability. Before deployment, chips typically undergo multiple reliability tests, with Electrostatic Discharge (CDM) testing being a crucial test for assessing their electrostatic discharge (ESD) immunity. For chips that have already been designed and fabricated, pin breakdown during CDM testing can prevent normal startup, potentially leading to issues such as no debug output, no interface response, and inability to locate internal states. The system input clock pin, in particular, serves as the fundamental clock input for chip startup and operation; a breakdown in this pin can prevent external clock signals from reaching the chip, potentially causing complete chip failure. Existing solutions typically require redesigning the internal circuitry, re-fabrication, or re-verification, which is time-consuming, costly, and impacts chip qualification and product delivery schedules. Furthermore, current methods lack rapid pin location techniques after CDM testing and effective solutions for reinforcing the system input clock pin without altering the chip's internal circuitry. Summary of the Invention

[0003] The purpose of this application is to provide a CDM protection method and packaging structure for the input clock pin of a satellite navigation chip system.

[0004] To achieve the above objectives, the first aspect of this application provides a CDM protection method for the input clock pin of a satellite navigation chip system. The satellite navigation chip includes at least one system input clock pin, and the method includes: Obtain the power-on operating status, pin electrical parameters, and current consumption of the satellite navigation chip before and after CDM testing; Based on the changes in the chip's power-on operating state before and after the CDM test, the changes in the chip's pin electrical parameters before and after the CDM test, and the changes in the chip's current consumption before and after the CDM test, the failed system input clock pin is identified. A protective structure is provided on the clock input path corresponding to the failed system input clock pin. The protective structure includes at least one of the following: an electrostatic discharge protection device connected between the clock input path and the ground terminal; a protective resistor connected in series between the external clock input terminal and the failed system input clock pin; wherein, when the protective structure includes a protective resistor, the resistance value of the protective resistor is determined based on the CDM test voltage, the system input clock frequency, the crystal oscillator output impedance, the chip input capacitance, and the package parasitic capacitance. The satellite navigation chip with the protective structure was tested and verified again by CDM. If the power-on working state of the satellite navigation chip after the CDM test and verification, the electrical parameters of the chip pins and the current consumption of the chip meet the preset conditions, it is determined that the protective structure meets the CDM protection requirements of the system input clock pin.

[0005] In this embodiment, the protective structure is disposed on the packaging substrate of the satellite navigation chip; A clock input node is provided on the packaging substrate, and an external clock input terminal is connected to the clock input node; In the case where the protective structure includes a ground electrostatic discharge (ESD) protection device, the ESD protection device is connected between the clock input node and the ground terminal; In cases where the protective structure includes a protective resistor, the protective resistor is connected between the clock input node and the failed system input clock pin.

[0006] In this embodiment, the chip pin electrical parameters include at least one of the following: pin-to-ground impedance, pin-to-power supply impedance, and pin leakage current parameters.

[0007] In this embodiment, the chip power-on operating state includes at least one of the following: chip startup state, debug interface output state, and communication interface response state.

[0008] In this embodiment of the application, determining the failed system input clock pin includes: Based on the changes in the electrical parameters of the chip pins before and after the CDM test, candidate failed pins are selected from at least one system input clock pin. Based on the changes in the chip pin electrical parameters of the candidate failed pins, as well as the changes in the chip power-on operating state and chip current consumption of the satellite navigation chip, the failed system input clock pin is determined from the candidate failed pins.

[0009] In this embodiment of the application, when a failed system input clock pin is determined, the clock output status of an external clock source is obtained; When an external clock source has a clock output and the satellite navigation chip does not respond after CDM testing, the failed system input clock pin is determined from the candidate failed pins.

[0010] In the embodiments of this application, when the protective structure includes a protective resistor, the resistance value of the protective resistor is 33Ω to 100Ω.

[0011] In this embodiment, the resistance of the protection resistor is 33Ω.

[0012] In this embodiment of the application, the preset conditions include: The satellite navigation chip can start normally; The chip's current consumption is within the preset current range; The electrical parameters of the chip pins are within the preset electrical parameter range.

[0013] A second aspect of this application provides a satellite navigation chip packaging structure, including a packaging substrate, a satellite navigation chip disposed on the packaging substrate, and a protective structure disposed on the packaging substrate. The satellite navigation chip includes at least one system input clock pin. The protective structure is installed on the clock input path corresponding to the target system input clock pin, which is one of at least one system input clock pin; The protective structure includes at least one of the following: an electrostatic discharge protection device connected between the clock input path and the ground terminal; and a protective resistor connected in series between the external clock input terminal and the target system input clock pin. In cases where the protective structure includes a protective resistor, the resistance value of the protective resistor is determined based on the CDM test voltage, the system input clock frequency, the crystal oscillator output impedance, the chip input capacitance, and the package parasitic capacitance.

[0014] This application identifies the failed system input clock pin based on changes in the chip's power-on operating state, pin electrical parameters, and current consumption before and after CDM testing. An electrostatic discharge (ESD) protection device and / or a protection resistor are then installed on the clock input path corresponding to the failed system input clock pin. This allows transient current during CDM testing to be discharged or limited, reducing the risk of transient current entering the system input clock pin and causing breakdown. After implementing the protection structure, CDM testing is performed again to verify that the protection structure meets the CDM protection requirements for the system input clock pin, provided that the chip's power-on operating state, pin electrical parameters, and current consumption meet preset conditions. This improves the reliability of the satellite navigation chip in passing CDM testing without redesigning the internal circuitry or re-fabrication, reducing chip rectification costs and shortening the rectification cycle.

[0015] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings: Figure 1 The schematic diagram illustrates a CDM protection method for the input clock pin of a satellite navigation chip system according to an embodiment of this application; Figure 2This illustration schematically shows a structural diagram of a satellite navigation chip packaging structure according to an embodiment of this application; 20. Packaging substrate; 30. Satellite navigation chip; 40. External clock source; 41. External clock input terminal; 42. Clock input node; 43. System input clock pin; 50. Static electricity protection devices to ground; 60. Protective resistors. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] Figure 1 This illustration schematically shows a flowchart of a CDM protection method for the input clock pin of a satellite navigation chip system according to an embodiment of this application. Figure 1 As shown in one embodiment of this application, a CDM protection method for the input clock pin of a satellite navigation chip system is provided, comprising the following steps: Step 102: Obtain the power-on operating status of the satellite navigation chip, the electrical parameters of the chip pins, and the current consumed by the chip before and after the CDM test; Step 104: Based on the changes in the chip's power-on operating state before and after the CDM test, the changes in the chip's pin electrical parameters before and after the CDM test, and the changes in the chip's current consumption before and after the CDM test, determine the failed system input clock pin. Step 106: Set up a protection structure on the clock input path corresponding to the failed system input clock pin. The protection structure includes at least one of the following: a ground electrostatic discharge protection device connected between the clock input path and the ground terminal; a protection resistor connected in series between the external clock input terminal and the failed system input clock pin; wherein, when the protection structure includes a protection resistor, the resistance value of the protection resistor is determined based on the CDM test voltage, the system input clock frequency, the crystal oscillator output impedance, the chip input capacitance, and the package parasitic capacitance. Step 108: Perform CDM test verification on the satellite navigation chip with the protection structure again. If the power-on working state of the satellite navigation chip after the CDM test verification, the electrical parameters of the chip pins, and the current consumption of the chip meet the preset conditions, it is determined that the protection structure meets the CDM protection requirements of the system input clock pin.

[0019] In one embodiment, the satellite navigation chip includes at least one system input clock pin. The chip's power-on operating state, pin electrical parameters, and current consumption are acquired before and after the CDM test. Based on the changes in the chip's power-on operating state, pin electrical parameters, and current consumption before and after the CDM test, the failed system input clock pin is identified. After identifying the failed system input clock pin, a protection structure is installed on the clock input path corresponding to the failed system input clock pin. The protection structure may include a ground electrostatic discharge (ESD) protection device connected between the clock input path and ground, a protection resistor connected in series between the external clock input and the failed system input clock pin, or both an ESD protection device and a protection resistor. When the protection structure includes a protection resistor, the resistance value is determined based on the CDM test voltage, system input clock frequency, crystal oscillator output impedance, chip input capacitance, and package parasitic capacitance. The satellite navigation chip with the protective structure was tested and verified again by CDM. If the power-on working state of the satellite navigation chip after the CDM test and verification, the electrical parameters of the chip pins and the current consumption of the chip meet the preset conditions, it is determined that the protective structure meets the CDM protection requirements of the system input clock pin.

[0020] The chip's power-on operating status can include whether the chip can start normally, whether there is debug output, whether the communication interface responds, and whether the chip can enter normal operating mode. Chip pin electrical parameters can include the impedance to ground, impedance to power supply, leakage current, and impedance change trends of the system input clock pin or other critical pins. Chip current consumption can include the quiescent current after power-on, current changes during startup, and operating current after entering the operating state. By comparing the above data before and after CDM testing, it can be determined whether chip failure is related to the system input clock pin. For example, before CDM testing, the satellite navigation chip can start normally, the impedance of the system input clock pin is within the normal range, and the chip's current consumption is also within the normal range; after CDM testing, the satellite navigation chip cannot start, the impedance of the system input clock pin is significantly reduced or leakage current increases, and the chip's current consumption is abnormal. This indicates that the system input clock pin is at risk of being damaged by the CDM test or has already failed.

[0021] The system input clock pin is the pin through which an external crystal oscillator, external TCXO, or other external clock source 40 inputs the system clock signal to the satellite navigation chip. The system input clock signal is the fundamental signal for chip startup and operation. When the system input clock pin experiences breakdown or leakage abnormalities due to CDM testing, the external clock signal may not be able to be input normally into the chip, resulting in the chip failing to start, having no debug output, or having no interface response. Therefore, this embodiment, through a comprehensive judgment of the chip's power-on operating state, chip pin electrical parameters, and chip current consumption, can locate the failure point even when the chip has no output and no debugging methods are available, avoiding misjudging the cause of failure based solely on a single test result. After identifying the failed system input clock pin, a protective structure can be set on the clock input path corresponding to the failed system input clock pin. The clock input path is the signal transmission path between the external clock input terminal and the system input clock pin. A ground electrostatic discharge (ESD) protection device is connected between the clock input path and the ground terminal to provide a discharge path for transient ESD during CDM testing, allowing the transient ESD current to be discharged to the ground terminal through the ESD protection device, reducing the current surge entering the system input clock pin. A protection resistor is connected in series between the external clock input and the failed system input clock pin to increase the transient impedance on the clock input path and limit the peak current entering the system input clock pin during CDM testing. The CDM protection capability of the system input clock pin can be enhanced by individually or in combination with ground ESD protection devices and protection resistors.

[0022] When the protective structure includes a protective resistor, the resistance value is determined based on the CDM test voltage, system input clock frequency, crystal oscillator output impedance, chip input capacitance, and package parasitic capacitance. The CDM test voltage is used to estimate the transient impact strength, the system input clock frequency is used to determine the clock edge and period requirements, and the crystal oscillator output impedance, chip input capacitance, and package parasitic capacitance are used to assess the impact of the protective resistor on the clock signal quality. A larger protective resistor value provides stronger limitation of transient current, but also slows down the clock signal rise time. A smaller protective resistor value has less impact on the clock signal, but reduces its ability to limit transient current. Therefore, when determining the protective resistor value, both CDM protection requirements and system input clock signal quality requirements must be met simultaneously.

[0023] For example, with a CDM test voltage of 250V, the current-limiting effect of the protection resistor can be estimated using I=V / R. When the protection resistor is 33Ω, the current estimated at 250V is less than the transient inrush current without a protection resistor in series; the current-limiting effect is further enhanced when the protection resistor is 100Ω. Simultaneously, it is necessary to estimate the clock rise time by considering the system input clock frequency, crystal oscillator output impedance, chip input capacitance, and package parasitic capacitance to determine whether the protection resistor will slow down the clock edge and affect the chip's clock signal recognition. If the system input clock frequency is 26MHz, a protection resistor selected in the range of 33Ω to 100Ω will meet the chip's input requirements for clock rise time. Considering both the CDM protection effect and clock signal quality, 33Ω can be chosen as the preferred resistance value for the protection resistor.

[0024] In this embodiment, after identifying the vulnerable system input clock pins through failed samples, a protective structure is installed on the corresponding clock input path of the same model of chip to be verified or an improved packaged sample. After completing the protective structure installation, the satellite navigation chip with the protective structure is subjected to CDM testing and verification again. After CDM testing and verification, the chip's power-on operating status, chip pin electrical parameters, and chip current consumption are re-acquired. If the satellite navigation chip can start normally, the chip pin electrical parameters do not show abnormal changes, and the chip current consumption is within the preset range, then it can be determined that the protective structure can meet the CDM protection requirements of the system input clock pins. In this way, external protection reinforcement can be performed on system input clock pins that have already experienced CDM test failure risks without redesigning the internal circuitry of the chip or re-fabricating the chip, enabling the satellite navigation chip to pass CDM testing and verification and meet the reliability requirements before subsequent use.

[0025] In one embodiment, the protective structure is disposed on the packaging substrate of the satellite navigation chip. The packaging substrate is used to connect the external clock input terminal and the system input clock pin inside the satellite navigation chip. By placing the protective structure on the packaging substrate, package-level protection reinforcement can be performed on the satellite navigation chip that has already been fabricated without changing the internal circuitry of the satellite navigation chip. Compared with redesigning the internal ESD structure of the chip, this method has the advantages of shorter rectification cycle, lower implementation cost, and suitability for improvements to already fabricated chips. A clock input node is provided on the packaging substrate, and the external clock input terminal is connected to the clock input node. The system clock signal output from the external clock source enters the packaging substrate through the external clock input terminal, is first transmitted to the clock input node, and then transmitted along the clock input path to the failed system input clock pin. The clock input node can serve as the connection location for ground electrostatic discharge protection devices and protection resistors, so that the clock input path forms electrostatic discharge and current limiting protection near the system input clock pin. When the protective structure includes a ground electrostatic discharge protection device, the ground electrostatic discharge protection device is connected between the clock input node and the ground terminal. When transient currents generated during CDM testing reach the clock input node, they can be discharged to ground via an ESD protection device, thereby reducing the transient current flowing to the system input clock pin. The ESD protection device can be a low-capacitance ESD device to reduce the impact on the rising and falling edges and signal integrity of the system input clock signal. When the protection structure includes a protection resistor, the protection resistor is connected between the clock input node and the failed system input clock pin. During normal operation, the external clock signal enters the clock input node from the external clock input terminal and is input to the failed system input clock pin via the protection resistor, enabling the satellite navigation chip to receive the system clock signal. During CDM testing or ESD events, the protection resistor increases the transient impedance between the clock input node and the system input clock pin, limiting the peak current entering the system input clock pin and thus reducing the risk of the system input clock pin being damaged. By setting a clock input node on the packaging substrate and connecting ground electrostatic discharge protection devices and protection resistors according to the specific form of the protection structure, transient current during CDM testing can be discharged or limited before entering the satellite navigation chip. This can improve the CDM protection capability of the system input clock pin without changing the internal structure of the satellite navigation chip, so that the satellite navigation chip can still meet the preset conditions such as normal startup, normal electrical parameters, and normal current consumption after CDM testing and verification.

[0026] In one embodiment, the chip pin electrical parameters include at least one of pin-to-ground impedance, pin-to-power supply impedance, and pin leakage current parameters. By obtaining the chip pin electrical parameters of the satellite navigation chip before and after CDM testing, it can be determined whether the system input clock pin has experienced breakdown, short circuit, increased leakage current, or abnormal impedance due to CDM testing. Pin-to-ground impedance is used to determine whether there is an abnormally low-impedance path between the system input clock pin and ground. Pin-to-power supply impedance is used to determine whether there is abnormal conduction between the system input clock pin and the power supply. Pin leakage current parameters are used to determine whether there is abnormal leakage current in the system input clock pin under power-on or bias conditions. Before CDM testing, the system input clock pin of the satellite navigation chip typically has relatively stable pin-to-ground impedance, pin-to-power supply impedance, and leakage current parameters. After CDM testing, if the pin-to-ground impedance, or pin-to-power supply impedance, or leakage current parameter of the system input clock pin decreases significantly, it indicates that the system input clock pin may have been affected by electrostatic discharge (ESD). In this case, by combining the chip's power-on operating state and chip current consumption, it can be further determined whether the failure location is the system input clock pin.

[0027] In one embodiment, the chip's power-on operating state includes at least one of the following: chip startup state, debug interface output state, and communication interface response state. The chip startup state is used to determine whether the satellite navigation chip can enter the normal startup process after power-on. The debug interface output state is used to determine whether the chip can output startup information, status information, or abnormal information through the debug interface. The communication interface response state is used to determine whether the chip can interact normally with the test equipment through the external communication interface. Before CDM testing, if the satellite navigation chip can start normally after power-on, the debug interface can output information, and the communication interface can generate a response, it indicates that the chip's overall operating state is normal. After CDM testing, if the satellite navigation chip cannot start normally, the debug interface has no output, and the communication interface has no response, it indicates that the chip has suffered a functional failure. Since the system input clock signal is the fundamental signal for chip startup and operation, when the external clock source 40 outputs normally, but the chip still cannot start or has no interface response, the chip pin electrical parameters and chip current consumption can be combined to further determine whether the system input clock pin is a failed pin.

[0028] In one embodiment, when determining the failed system input clock pin, candidate failed pins can be first screened from at least one system input clock pin based on changes in chip pin electrical parameters before and after CDM testing. Then, based on changes in the chip pin electrical parameters of the candidate failed pins, as well as changes in the power-on operating state and current consumption of the satellite navigation chip, the failed system input clock pin is determined from the candidate failed pins. Candidate failed pins are system input clock pins whose electrical parameters show abnormal changes after CDM testing. By first screening candidate failed pins and then confirming them in conjunction with the overall chip operating state, it is possible to avoid misjudging chip failures caused by other reasons as system input clock pin failures. During candidate failed pin screening, the impedance to ground, impedance to power supply, and leakage current parameters of each system input clock pin before and after CDM testing can be detected separately. If the impedance to ground, impedance to power supply, or leakage current parameter of a certain system input clock pin significantly decreases after CDM testing, it can be considered a candidate failed pin. If a satellite navigation chip includes multiple system input clock pins, such as a main system clock input pin, a backup system clock input pin, or clock input pins of different frequencies, the electrical parameters of each system input clock pin can be compared to identify one or more candidate failed pins. After identifying the candidate failed pins, further confirmation can be made by observing changes in the chip's power-on operating state and current consumption. For example, if the satellite navigation chip can start normally before CDM testing, the debug interface can output information, the communication interface can respond, and the chip's current consumption is within the normal range; but after CDM testing, the satellite navigation chip cannot start normally, the debug interface has no output, the communication interface has no response, the chip's current consumption is abnormal, and the impedance or leakage parameters of the candidate failed pin are abnormal, then the candidate failed pin can be identified as a failed system input clock pin.

[0029] In one embodiment, when a failed system input clock pin is identified, the clock output status of the external clock source 40 is acquired. The external clock source 40 can be a crystal oscillator, TCXO, or other clocking device capable of providing a system clock signal to the satellite navigation chip. The clock output status of the external clock source 40 can be acquired using an oscilloscope, frequency counter, or clock detection circuit on a test board to determine whether the external clock source 40 can output a clock signal normally.

[0030] After CDM testing, if the external clock source 40 still has a normal clock output, but the satellite navigation chip does not respond to startup, then the possibility that the external clock source 40 itself is faulty and causing the chip to fail to start can be ruled out. At this point, by combining the changes in the electrical parameters of the chip pins of the candidate faulty pins, the faulty system input clock pin can be identified from among the candidate faulty pins. By obtaining the clock output status of the external clock source 40, it is possible to avoid misjudging an abnormality in the external clock source 40 as a faulty chip clock input pin. In other words, only when the external clock source 40 can provide a normal clock signal, and the satellite navigation chip still does not respond to startup after CDM testing, should the changes in the electrical parameters of the candidate faulty pins be further considered to determine the failure location. This improves the accuracy of failure analysis.

[0031] In one embodiment, when the protection structure includes a protection resistor, the resistance value of the protection resistor is between 33Ω and 100Ω. The protection resistor is connected in series between the external clock input terminal 41 and the failed system input clock pin to limit the transient current entering the system input clock pin during CDM testing. If the resistance value of the protection resistor is too small, its limiting effect on transient current is insufficient; if the resistance value of the protection resistor is too large, it may slow down the rise edge of the system input clock signal, affecting the chip's recognition of the clock signal. Therefore, limiting the resistance value of the protection resistor to 33Ω to 100Ω can balance CDM protection capability and clock signal quality. With a CDM test voltage of 250V, the transient current can be estimated using the relationship between voltage and resistance. For example, a protection resistor of 33Ω can reduce the peak current entering the system input clock pin; a protection resistor of 100Ω further enhances the current limiting effect. Since CDM testing is a transient discharge process, the actual current is also affected by package parasitic parameters, test fixtures, chip internal structure, and the clamping capability of ESD protection devices. Therefore, this calculation is used to assist in determining the resistance range, and the final value still needs to be determined in conjunction with the actual CDM test verification results. When determining the resistance range, the system input clock frequency, crystal oscillator output impedance, chip input capacitance, and package parasitic capacitance also need to be considered. The protection resistor, chip input capacitance, and package parasitic capacitance will form an RC effect, increasing the clock signal rise time. If the clock frequency is low, the allowable rise time range is wider, and a larger protection resistor can be selected to enhance the current limiting effect; if the clock frequency is high, a smaller protection resistor needs to be selected to reduce the impact on the clock edge. For the system input clock of a satellite navigation chip, a resistance range of 33Ω to 100Ω can improve the CDM protection capability while ensuring that the system input clock signal meets the chip input requirements.

[0032] In one embodiment, the protection resistor has a resistance of 33Ω. 33Ω is the preferred resistance value for the protection resistor. This value achieves a good balance between limiting CDM transient current and maintaining the quality of the system input clock signal. Compared to larger resistance values, 33Ω has less impact on the rising and falling edges of the clock signal, reducing the risk of chip clock recognition anomalies due to edge slowing. Compared to smaller resistance values, 33Ω also increases the transient impedance on the clock input path, reducing the peak current entering the system input clock pin during CDM testing.

[0033] In practical applications, the external clock signal enters the package substrate through the external clock input terminal 41, and then passes through a 33Ω protection resistor to the system input clock pin. During normal operation, the 33Ω protection resistor does not significantly affect the transmission of the external clock signal, and the satellite navigation chip can still receive the required system clock signal. During CDM testing or electrostatic discharge (ESD) events, the 33Ω protection resistor limits transient current, reducing the current surge experienced by the system input clock pin.

[0034] In one embodiment, the preset conditions include the satellite navigation chip being able to start normally, the chip's current consumption being within a preset current range, and the chip pin electrical parameters being within a preset electrical parameter range. These preset conditions are used to determine whether the satellite navigation chip, after the protection structure is set, passes the CDM test verification, and to determine whether the protection structure meets the CDM protection requirements of the system input clock pin. The satellite navigation chip being able to start normally means that after CDM test verification, the chip can enter the normal startup process and execute preset functions. Normal startup can be confirmed through debug interface output, communication interface response, test board function test results, or chip operating status signals. If the chip can start normally after CDM test verification, it indicates that the system input clock signal can be received normally by the chip, and the system input clock pin has not been damaged due to the CDM test causing the chip to malfunction. The chip's current consumption being within the preset current range means that the chip's current value does not show abnormal increases or decreases during power-on, startup, and operation. If the chip's current consumption increases abnormally, it may indicate pin breakdown, short circuit, or leakage abnormalities; if the chip's current consumption decreases abnormally, it may indicate that the chip has not started normally or that the internal circuit has not entered the operating state. Therefore, the chip's current consumption can be used as a basis for judging whether the chip is working properly after CDM testing. Chip pin electrical parameters being within the preset range means that the impedance to ground, impedance to power supply, and leakage current of the system input clock pin or other critical pins are within normal ranges. If, after CDM testing, the impedance and leakage current parameters of the system input clock pin do not show abnormal changes, it indicates that the protection structure can reduce the impact of CDM testing on the system input clock pin. By using chip startup status, chip current consumption, and chip pin electrical parameters as preset conditions, the effectiveness of the protection structure can be judged from three aspects: functional state, current state, and pin electrical state. Only when all the above conditions are met can it be determined that the protection structure meets the CDM protection requirements for the system input clock pin.

[0035] This application also proposes a satellite navigation chip packaging structure, including a packaging substrate, a satellite navigation chip disposed on the packaging substrate, and a protective structure disposed on the packaging substrate. The satellite navigation chip includes at least one system input clock pin. The protective structure is disposed on the clock input path corresponding to the target system input clock pin, and the target system input clock pin is one of the at least one system input clock pin. The protective structure includes at least one of the following: an electrostatic discharge protection device 50 connected between the clock input path and the ground terminal; and a protective resistor 60 connected in series between the external clock input terminal 41 and the target system input clock pin. Wherein, when the protective structure includes the protective resistor 60, the resistance value of the protective resistor 60 is determined based on the CDM test voltage, the system input clock frequency, the crystal oscillator output impedance, the chip input capacitance, and the package parasitic capacitance.

[0036] Compared with existing technologies, this application proposes a CDM protection method for the input clock pin of a satellite navigation chip system. Based on the changes in the chip's power-on operating state, pin electrical parameters, and current consumption before and after CDM testing, the failed system input clock pin is identified. An electrostatic discharge (ESD) protection device 50 and / or a protection resistor 60 are installed on the clock input path corresponding to the failed input clock pin. This allows transient current during CDM testing to be discharged or limited, thereby reducing the risk of transient current entering the system input clock pin and causing breakdown. After setting the protection structure, CDM testing is performed again for verification. If the chip's power-on operating state, pin electrical parameters, and current consumption meet preset conditions, the protection structure is determined to meet the CDM protection requirements for the system input clock pin. This improves the reliability of the satellite navigation chip in passing CDM testing without redesigning the internal circuitry or re-faking the chip, reducing chip rectification costs and shortening the rectification cycle.

[0037] like Figure 2As shown, in one embodiment, the satellite navigation chip package structure includes a package substrate 20, a satellite navigation chip 30, and a protective structure disposed on the package substrate 20. The satellite navigation chip 30 is disposed on the package substrate 20. In one embodiment, the system input clock pin 43 of the satellite navigation chip 30 is the CLK pin through which an external clock source 40 inputs a system clock signal to the chip. The external clock source 40 can be a crystal oscillator or a TCXO. The system input clock frequency can be 26MHz. After CDM testing, the satellite navigation chip 30 fails to start normally, the debug interface has no output, and the communication interface has no response. By acquiring the chip's power-on operating state, chip pin electrical parameters, and chip current consumption before and after CDM testing, it can be determined that the system input clock pin 43 is abnormal after CDM testing. The chip pin electrical parameters can include the impedance to ground, impedance to power supply, and leakage current parameters of the system input clock pin 43. If the impedance to ground of the system input clock pin 43 decreases after CDM testing, the chip current consumption is abnormal, and the external clock source can still output a system clock signal, then it can be determined that the failed system input clock pin 43 is the CLK pin connected to the external clock source. After identifying the failed system input clock pin 43, a protective structure is installed on the clock input path corresponding to the failed system input clock pin 43. The protective structure includes a ground electrostatic discharge (ESD) protection device 50 connected between the clock input path and ground, and / or a protective resistor 60 connected in series between the external clock input terminal 41 and the failed system input clock pin 43. The ground ESD protection device 50 provides a ground discharge path for transient currents during CDM testing, allowing transient currents to preferentially discharge to ground. The protective resistor 60 increases the transient impedance on the clock input path, reducing the peak current entering the failed system input clock pin 43. Through discharge and current limiting, the risk of the system input clock pin 43 being damaged by the CDM test can be reduced. In one specific embodiment, the CDM test voltage is 250V. When the protective structure includes the protective resistor 60, the transient current entering the clock input path can be calculated first based on the CDM test voltage and the resistance value of the protective resistor 60. The calculation formula is I=V / R, where I is the estimated current, V is the CDM test voltage, and R is the resistance value of the protective resistor. When the protection resistor 60 is 33Ω, I = 250 / 33, which is approximately 7.576A. When the protection resistor 60 is 100Ω, I = 250 / 100, which is 2.5A. This shows that the protection resistor 60 can increase the impedance of the clock input path and reduce the transient current entering the system input clock pin 43 during CDM testing.

[0038] When determining the value of the protection resistor 60, it is also necessary to consider the system input clock frequency, crystal oscillator output impedance, chip input capacitance, and package parasitic capacitance to judge the clock signal quality. The protection resistor 60, along with the chip input capacitance and package parasitic capacitance, will create an RC effect, increasing the rise time of the system clock signal. A first-order RC model can be used to estimate the rise time; the calculation formula is as follows: ,in The rising time of the clock. This is the sum of the crystal oscillator output impedance, the protection resistor 60Ω, and the equivalent circuit resistance. This is the sum of the chip's input capacitance and the package's parasitic capacitance.

[0039] For example, the crystal oscillator output impedance is set to 30Ω, the chip input capacitance to 5pF, and the package parasitic capacitance to 2pF. It is 7pF. Without a 60Ω protection resistor in series, It is 30Ω. =2.2 × 30 Ω × 7 pF, approximately 0.46 ns. With a protection resistor of 60 Ω, It is 63Ω. =2.2 × 63 Ω × 7 pF, approximately 0.97 ns. With a protection resistor of 60 Ω and a resistance of 100 Ω, It is 130Ω. =2.2×130Ω×7pF, approximately 2.00ns. If the system input clock frequency is 26MHz, the corresponding clock period is approximately 38.46ns. Therefore, the clock rise times corresponding to 33Ω and 100Ω are both less than the preset proportion of the clock period, which meets the clock input requirements of system input clock pin 43. In actual verification, samples can be set up including only the ground ESD protection device 50, only the protection resistor 60, and both the ground ESD protection device 50 and the protection resistor 60. After CDM testing and verification of each sample, the chip's power-on operating status, chip pin electrical parameters, and chip current consumption are obtained. If the sample can start normally after CDM testing and verification, and the chip current consumption and chip pin electrical parameters are within the preset current range, then the corresponding protection structure meets the CDM protection requirements of system input clock pin 43.

[0040] In a preferred embodiment, the protective structure is disposed on the packaging substrate 20 of the satellite navigation chip 30. A clock input node 42 is disposed on the packaging substrate 20, an external clock input terminal 41 is connected to the clock input node 42, a ground electrostatic discharge (ESD) protection device 50 is connected between the clock input node 42 and ground, and a protection resistor 60 is connected between the clock input node 42 and the failed system input clock pin 43. The resistance value of the protection resistor 60 is preferably 33Ω. A 33Ω protection resistor has minimal impact on the rising edge of the system clock signal and can limit transient current during CDM testing. By providing the ground ESD protection device 50 and the 33Ω protection resistor on the packaging substrate, the CDM protection capability of the system input clock pin 43 can be improved without redesigning the internal circuitry of the chip or re-faking the chip, enabling the satellite navigation chip 30 to pass CDM testing and verification.

[0041] Figure 1 This is a flowchart illustrating a CDM protection method for the input clock pin of a satellite navigation chip system in one embodiment. It should be understood that, although... Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0042] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0043] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A CDM protection method for the input clock pin of a satellite navigation chip system, characterized in that, The satellite navigation chip includes at least one system input clock pin, and the method includes: Obtain the power-on operating status, pin electrical parameters, and current consumption of the satellite navigation chip before and after CDM testing; Based on the changes in the chip's power-on operating state before and after the CDM test, the changes in the chip's pin electrical parameters before and after the CDM test, and the changes in the chip's current consumption before and after the CDM test, the failed system input clock pin is determined. A protective structure is provided on the clock input path corresponding to the failed system input clock pin. The protective structure includes at least one of the following: an electrostatic discharge protection device connected between the clock input path and the ground terminal; and a protective resistor connected in series between the external clock input terminal and the failed system input clock pin. Wherein, when the protective structure includes the protective resistor, the resistance value of the protective resistor is determined based on the CDM test voltage, the system input clock frequency, the crystal oscillator output impedance, the chip input capacitance, and the package parasitic capacitance. The satellite navigation chip with the aforementioned protective structure is subjected to CDM testing and verification again. If the power-on working state of the satellite navigation chip after CDM testing and verification, the electrical parameters of the chip pins, and the current consumption of the chip meet the preset conditions, it is determined that the protective structure meets the CDM protection requirements of the system input clock pin.

2. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 1, characterized in that, The protective structure is disposed on the packaging substrate of the satellite navigation chip; A clock input node is provided on the packaging substrate, and the external clock input terminal is connected to the clock input node; When the protective structure includes the ground electrostatic discharge (ESD) protection device, the ground ESD protection device is connected between the clock input node and the ground terminal; When the protective structure includes the protective resistor, the protective resistor is connected between the clock input node and the failed system input clock pin.

3. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 1, characterized in that, The electrical parameters of the chip pins include at least one of the following: pin-to-ground impedance, pin-to-power supply impedance, and pin leakage current.

4. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 1, characterized in that, The chip's power-on operating state includes at least one of the following: chip startup state, debug interface output state, and communication interface response state.

5. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 1, characterized in that, The system input clock pin that is determined to be faulty includes: Based on the changes in the electrical parameters of the chip pins before and after the CDM test, candidate failed pins are selected from the at least one system input clock pin; Based on the changes in the chip pin electrical parameters of the candidate failed pins, as well as the changes in the chip power-on operating state and chip current consumption of the satellite navigation chip, the failed system input clock pin is determined from the candidate failed pins.

6. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 5, characterized in that, When the failed system input clock pin is identified, the clock output status of the external clock source is obtained; If the external clock source has a clock output and the satellite navigation chip does not respond after the CDM test, the failed system input clock pin is determined from the candidate failed pins.

7. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 1, characterized in that, When the protective structure includes the protective resistor, the resistance value of the protective resistor is from 33Ω to 100Ω.

8. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 7, characterized in that, The resistance of the protective resistor is 33Ω.

9. The CDM protection method for the input clock pin of a satellite navigation chip system according to claim 1, characterized in that, The preset conditions include: The satellite navigation chip can start normally; The current consumption of the chip is within a preset current range; The electrical parameters of the chip pins are within the preset electrical parameter range.

10. A satellite navigation chip packaging structure, characterized in that, The package includes a packaging substrate, a satellite navigation chip disposed on the packaging substrate, and a protective structure disposed on the packaging substrate, wherein the satellite navigation chip includes at least one system input clock pin; The protective structure is installed on the clock input path corresponding to the target system input clock pin, and the target system input clock pin is one of the at least one system input clock pins; The protective structure includes at least one of the following: an electrostatic discharge protection device connected between the clock input path and the ground terminal; and a protective resistor connected in series between the external clock input terminal and the input clock pin of the target system. Wherein, when the protective structure includes the protective resistor, the resistance value of the protective resistor is determined based on the CDM test voltage, the system input clock frequency, the crystal oscillator output impedance, the chip input capacitance, and the package parasitic capacitance.

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