Time base calibration method and system of sampling oscilloscope, electronic equipment and storage medium
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-23
- Publication Date
- 2026-07-21
Smart Images
Figure CN122430767A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of sampling oscilloscope technology, and in particular to a time base calibration method, system, electronic device, and storage medium for a sampling oscilloscope. Background Technology
[0002] Currently, in order to achieve eye diagram reconstruction of high-speed signals (optical or electrical signals), the time base control of high-speed equivalent sampling oscilloscopes needs to meet the requirements of large delay range and small step delay. However, the time base control of existing sampling oscilloscopes uses a single delay chip, which cannot take into account both large range and micro step in terms of hardware conditions, and cannot guarantee step accuracy in terms of software control, which easily produces phase error and results in poor sampling accuracy. Summary of the Invention
[0003] To address at least one of the aforementioned technical problems, this invention proposes a time base calibration method, system, electronic device, and storage medium for a sampling oscilloscope.
[0004] According to some embodiments of the present invention, a time base calibration method for a sampling oscilloscope is provided. The sampling oscilloscope includes a first delay chip and a second delay chip, wherein the step delay of the first delay chip is less than the step delay of the second delay chip. The method includes: controlling the sampling oscilloscope to sample a reference signal to obtain a plurality of first sampled signals; the delay control parameters of the first delay chips corresponding to the plurality of first sampled signals are the same, and the delay control parameters of the second delay chips corresponding to the plurality of first sampled signals are different; determining a first target control parameter based on the plurality of first sampled signals; the first target control parameter characterizes that the step delay of the first delay chip is equal to a target calibration. Delay control parameters under delay conditions; controlling the sampling oscilloscope to sample the reference signal to obtain multiple second sampled signals; the period lengths of the multiple second sampled signals are matched with each other, and the delay control parameters of the second delay chip corresponding to each of the multiple second sampled signals are different; based on the multiple second sampled signals, a second target control parameter is determined; the second target control parameter characterizes the delay control parameter of the first delay chip corresponding to the delay control parameter of the second delay chip; based on the first target control parameter and the second target control parameter, a target delay table is generated, and the target delay table characterizes the delay control parameters under the target calibration delay condition where the time base of the sampling oscilloscope is equal to the delay control parameters under the target calibration delay condition.
[0005] In some possible implementations, determining the first target control parameter based on the plurality of first sampling signals includes: determining the mapping relationship between the delay control parameters and the delay amount of the first delay chip based on the plurality of first sampling signals; extracting a plurality of step control parameter points from the mapping relationship based on the target calibration delay, and determining the plurality of step control parameter points as the first target control parameter.
[0006] In some possible implementations, determining the mapping relationship between the delay control parameters and the delay amount of the first delay chip based on the plurality of first sampled signals includes: extracting a target signal that meets preset waveform conditions from the plurality of first sampled signals; determining the delay amount corresponding to each point in the target signal based on the phase difference between each point in the target signal and the starting point; establishing an initial mapping relationship based on the delay control parameters corresponding to each point in the target signal and the delay amount corresponding to each point in the target signal; and smoothing the initial mapping relationship to obtain the mapping relationship between the delay control parameters and the delay amount of the first delay chip.
[0007] In some possible implementations, determining the second target control parameter based on the plurality of second sampled signals includes: determining the initial delay amount corresponding to the delay control parameter of the second delay chip corresponding to each second sampled signal based on the phase difference between the breakpoints of each second sampled signal and adjacent second sampled signals; adjusting the delay control parameter of the first delay chip based on the initial delay amount corresponding to the delay control parameter of each of the second delay chips until the delay between the breakpoints of two adjacent second sampled signals is equal to the target calibration delay; and determining the second target control parameter based on the adjusted delay control parameter of the first delay chip.
[0008] In some possible implementations, before determining the second target control parameter based on the adjusted delay control parameters of the first delay chip, the method further includes: adjusting the frequency of the reference signal until the breakpoint of the second sampled signal is located in the target signal interval; and adjusting the delay control parameters of the first delay chip until the delay between two adjacent breakpoints of the second sampled signal is equal to the target calibration delay.
[0009] In some possible implementations, after adjusting the delay control parameters of the first delay chip until the delay between the breakpoints of two adjacent second sampling signals is equal to the target calibration delay, the method further includes: adjusting the delay control parameters of the first delay chip until the delay between the breakpoints of two adjacent second sampling signals is less than a preset delay, wherein the preset delay is less than the target calibration delay.
[0010] In some possible implementations, before generating the target delay table based on the first target control parameter and the second target control parameter, the method further includes: controlling the sampling oscilloscope to sample the reference signal based on the first target control parameter and the second target control parameter to obtain a third sampled signal; when the difference between the frequency of the third sampled signal and the frequency of the reference signal is less than a preset difference threshold, and the breakpoint delay error of the third sampled signal is less than a preset error threshold, confirming the first target control parameter and the second target control parameter as valid control parameters; generating the target delay table based on the first target control parameter and the second target control parameter includes: generating the target delay table based on the valid control parameters.
[0011] According to some embodiments of the present invention, a time base calibration system for a sampling oscilloscope is also provided. The system includes a signal source module, a first delay chip, a second delay chip, a sampling module, and a control module. The signal source module, the first delay chip, the second delay chip, and the sampling module are connected in sequence. The control module is connected to the signal source module, the first delay chip, the second delay chip, and the sampling module, respectively. The control module is used to execute a time base calibration method for a sampling oscilloscope according to any one of the above embodiments.
[0012] According to some embodiments of the present invention, an electronic device is also provided, the electronic device including a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or at least one program being loaded and executed by the processor to implement a time base calibration method for a sampling oscilloscope as described in any of the above embodiments.
[0013] According to some embodiments of the present invention, a storage medium is also provided, wherein at least one instruction or at least one program is stored therein, the at least one instruction or at least one program being loaded and executed by a processor to implement a time base calibration method for a sampling oscilloscope as described in any of the above embodiments.
[0014] The implementation of this invention has the following beneficial effects: The sampling oscilloscope of the present invention is equipped with two delay chips, which can simultaneously meet the requirements of continuous fine stepping and wide range. Furthermore, a calibration scheme is set for each of the two delay chips, which can reduce errors and improve the accuracy of step delay calculation, thereby improving the accuracy and speed of time base calibration.
[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.
[0016] Other features and aspects of the invention will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0017] To more clearly illustrate the technical solutions and advantages in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A structural block diagram of a time base calibration system for a sampling oscilloscope according to an embodiment of the present invention is shown; Figure 2 A step diagram illustrating a time base calibration method for a sampling oscilloscope according to an embodiment of the present invention is shown. Figure 3 Waveform diagrams of a plurality of first sampled signals according to an embodiment of the present invention are shown; Figure 4 The initial mapping relationship between the delay amount and the delay control parameters according to an embodiment of the present invention is shown; Figure 5 This illustrates the mapping relationship between the smoothed delay amount and the delay control parameters according to an embodiment of the present invention; Figure 6 Waveform diagrams of a plurality of second sampled signals according to embodiments of the present invention are shown; Figure 7 The diagram shows waveforms of multiple second sampled signals adjusted based on a coarse value of delay according to an embodiment of the present invention. Figure 8 A waveform diagram of the breakpoint delay fine calibration of the second sampled signal according to an embodiment of the present invention is shown. Detailed Implementation
[0019] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0021] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0022] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0023] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.
[0024] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without certain specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order to highlight the spirit of the invention.
[0025] Figure 1 A structural block diagram of a time base calibration system for a sampling oscilloscope according to an embodiment of the present invention is shown. Figure 2 The diagram illustrates the steps of a time base calibration method for a sampling oscilloscope according to an embodiment of the present invention. Figure 3 Waveform diagrams of a plurality of first sampled signals according to embodiments of the present invention are shown. Figure 4 The initial mapping relationship between the delay amount and the delay control parameters according to an embodiment of the present invention is shown. Figure 5The diagram illustrates the mapping relationship between the smoothed delay amount and the delay control parameters according to an embodiment of the present invention. Figure 6 The diagram shows waveforms of a plurality of second sampled signals according to an embodiment of the present invention. Figure 7 The diagram shows waveforms of multiple second sampled signals adjusted based on a coarse delay value according to an embodiment of the present invention. Figure 8 A waveform diagram of the breakpoint delay fine calibration of the second sampled signal according to an embodiment of the present invention is shown.
[0026] Currently, to achieve eye diagram reconstruction of high-speed signals (optical or electrical signals), the time base control of high-speed equivalent sampling oscilloscopes needs to meet the requirements of a large delay range (e.g., 0~800 picoseconds) and a small step delay (e.g., 0.1 picoseconds). However, existing sampling oscilloscopes use a single delay chip for time base control, which cannot simultaneously handle large range and micro-stepping in terms of hardware. Wide-range delay chips have coarse step delays, while fine-stepping delay chips have insufficient range. In terms of software control, existing time base control methods cannot guarantee step accuracy and are prone to phase errors, resulting in poor sampling accuracy.
[0027] To address at least one of the aforementioned technical problems, embodiments of the present invention provide a time base calibration system for a sampling oscilloscope. Please refer to... Figure 1 The system includes a signal source module, a first delay chip, a second delay chip, a sampling module, and a control module. The signal source module, the first delay chip, the second delay chip, and the sampling module are connected in sequence. The control module is connected to the signal source module, the first delay chip, the second delay chip, and the sampling module. The control module controls the signal source module to emit a standard radio frequency signal as a reference signal. The control module controls the delay of the first delay chip and the second delay chip, enabling the sampling module to perform high-speed equivalent sampling of the signal from the signal source module.
[0028] In this embodiment, the sampling module includes a sample-and-hold circuit, an intermediate frequency (IF) amplifier circuit, and an ADC acquisition module (i.e., an analog-to-digital converter acquisition module). The sample-and-hold circuit acquires the signal at the sampling time, the IF amplifier circuit preprocesses the sampled signal, and the ADC acquisition module converts the sampled signal into a digital signal. The control module includes an FPGA (programmable gate circuit) delay control module, a firmware storage module, and a calibration calculation module. The FPGA delay control module is connected to the first delay chip and / or the second delay chip. The FPGA delay control module changes the delay size of the delay chip by switching the output signal. The firmware storage module stores the delay control parameters corresponding to the calibrated step delay control. The calibration calculation module analyzes and processes the sampled signal to obtain the delay control parameters corresponding to the precise step delay control, thereby achieving time base calibration.
[0029] In this embodiment, the first delay chip is a high-precision delay chip, and the second delay chip is a large-range delay chip. That is, the minimum step delay of the first delay chip is smaller than that of the second delay chip, and the range of the second delay chip is larger than that of the first delay chip. Based on the cooperation of the first and second delay chips, the requirements for both high precision and large range can be met simultaneously. Specifically, the first delay chip is used to achieve fine-step delay. When the delay amount reaches the range of the first delay chip, the step delay of the second delay chip is switched, and then the step delay of the first delay chip is rolled back, thereby achieving continuous fine-step delay increases while significantly improving the range of delay control.
[0030] In one specific implementation, both the first delay chip and the second delay chip are calibrated chips. At this time, the step delay of the first delay chip is T1, and the range of the first delay chip is K1*T1. The step delay of the second delay chip is T2, and the range of the first delay chip is K2*T2. The principle of delay control by the control module is as follows: after each signal point is acquired, the step of the first delay chip is incremented by one until the total delay reaches K1*T1. Then, the step of the second delay chip is incremented by one, and the step of the first delay chip is retracted, so that the total delay is K1*T1+T1, that is, the first delay chip needs to retract (T2-T1) / T1 steps.
[0031] The embodiments of the present invention do not limit the specific types of the first delay chip and the second delay chip, that is, they do not limit the control method of the delay chip, nor do they limit the range and step of the delay chip.
[0032] In one specific implementation, the first delay chip can be a voltage-controlled delay chip, i.e., the delay is controlled by DAC parameters, where DAC parameters refer to digital-to-analog converter parameters. The digital-to-analog converter converts digital signals into corresponding voltage signals, and the delay magnitude of the first delay chip varies under different voltage signals. The second delay chip can be a range-controlled delay chip, i.e., the delay is controlled by SPI ranges, where SPI ranges refer to the range data sent through the SPI communication line (Serial Peripheral Interface). It should be understood that the second delay chip can also use other communication protocols, and there are no limitations on this. Preferably, the delay range of the first delay chip can be 0~50 picoseconds, and the delay range of the second delay chip can be 0~1200 picoseconds. For ease of explanation, in the following embodiments, unless otherwise specified, the first delay chip is assumed to be a DAC voltage-controlled delay chip, and the second delay chip is assumed to be an SPI range-controlled delay chip.
[0033] The above embodiments have described a time base calibration system for a sampling oscilloscope according to the present invention. It should be understood that, in order to ensure the sampling and reconstruction of high-speed signals, the sampling oscilloscope requires precise time base control, that is, the delay between adjacent sampling points must remain consistent. As described above, fine-step delay is related to the first delay chip, therefore the first delay chip needs to be calibrated to ensure the consistency of its step delay. The second delay chip is used to amplify the measurement range. When the second delay chip increases its delay, the first delay chip needs to roll back its delay. To avoid inaccurate delay rollback of the first delay chip due to changes in the delay of the second delay chip, the second delay chip also needs to be calibrated to confirm the delay of the first delay chip corresponding to each delay level of the second delay chip.
[0034] To calibrate the aforementioned delay chip, this embodiment of the invention also provides a time base calibration method for a sampling oscilloscope. This method is applied to a time base calibration system for a sampling oscilloscope as described in the above embodiment. Please refer to... Figure 2 The method includes: Step S101: Control the sampling oscilloscope to sample the reference signal to obtain multiple first sampled signals.
[0035] In this embodiment, the reference signal is a standard sine wave signal generated by the signal source module. The delay control parameters of the first delay chips corresponding to the multiple first sampling signals are the same, while the delay control parameters of the second delay chips corresponding to the multiple first sampling signals are different.
[0036] Specifically, the first delay chip is controlled based on DAC parameters, with each DAC parameter corresponding to a delay amount. The DAC control range of the first delay chip is [N1, N2]. The second delay chip is controlled based on SPI levels, with each SPI level corresponding to a delay amount. The SPI control range of the first delay chip is [M1, M2]. Each first sampling signal includes multiple first sampling points. The delay control parameters corresponding to the multiple first sampling points are a combination of the control parameters of the two delay chips. That is, the delay control parameters corresponding to each first sampling point in the first first sampling signal are (M1, N1), (M1, N1+1), ..., (M1, N2), and the delay control parameters corresponding to each first sampling point in the second first sampling signal are (M1+1, N1), (M1+1, N1+1), ..., (M1+1, N2), and so on for the other first sampling signals.
[0037] Based on the above scheme, when controlling the sampling oscilloscope to sample the reference signal, first, the second delay chip is controlled to be in the M1 position, then the DAC parameters of the first delay chip are iterated to obtain the first first sampled signal. Next, the second delay chip is controlled to be in the M2 position, and the DAC parameters of the first delay chip are iterated to obtain the second first sampled signal. The above operation is repeated until all first sampled signals are obtained. The waveforms of multiple first sampled signals are as follows: Figure 3 As shown.
[0038] Step S102: Determine the first target control parameters based on multiple first sampling signals.
[0039] In this embodiment, the first target control parameter represents the delay control parameter when the step delay of the first delay chip is equal to the target calibration delay. For the traversal DAC parameters of the first delay chip, the delay difference corresponding to adjacent DAC parameters is not strictly equal. The function of step S102 is to extract multiple DAC parameters from the traversal DAC parameters to form the first target control parameter. The delay difference corresponding to adjacent parameters in the first target control parameter is equal, and its delay difference is equal to the target calibration delay. That is to say, the first target control parameter is the control parameter for the step delay, and the step delay is equal to the target calibration delay.
[0040] In one specific implementation, the range of DAC parameters traversed by the first delay chip (i.e., the DAC control interval in step S101) is [44932, 56000]. The delay difference between adjacent DAC parameters is about 0.004 picoseconds to 0.005 picoseconds, while the target calibration delay is 0.1 picoseconds. Therefore, the first target control parameter is a DAC parameter array. The delay difference between adjacent DAC parameters in the DAC parameter array is 0.1 picoseconds, and the difference between adjacent DAC parameters in the DAC parameter array is about 4 or 5. For example, the first target control parameter can be (44932, 44936, 44940, 44945, 44949, 44954, ...).
[0041] In this embodiment of the invention, the specific method for determining the first target control parameter includes: firstly, determining the delay amount corresponding to each of the traversed DAC parameters of the first delay chip, and then selecting DAC parameters with equal adjacent delay differences based on the delay amounts to form the first target control parameter. That is, the above-mentioned determination of the first target control parameter based on multiple first sampled signals includes: Step S1021: Based on multiple first sampling signals, determine the mapping relationship between the delay control parameters and the delay amount of the first delay chip.
[0042] Based on the above embodiments, it can be seen that for any first sampling signal, the multiple first sampling points contained in the signal correspond to the DAC parameters of the first delay chip respectively. That is, the first sampling signal contains information on the delay control parameters of the first delay chip. When the delay amount of the first sampling point (i.e. the starting point) corresponding to the starting DAC parameter is known, the delay amount of each point can be determined based on the relationship between each point and the starting point.
[0043] However, in practical applications, if the waveform of the first sampled signal is located in the peak-valley region of a sine wave, the amplitude error of the sampling module will be amplified into a phase error because the slope of the peak-valley region is close to 0, which in turn leads to distortion in the calculation of the delay amount of the corresponding DAC parameters.
[0044] To address the aforementioned issues, in some embodiments, it is necessary to extract signals from non-peak / valley regions of multiple first sampled signals to determine the mapping relationship, thereby improving the calibration accuracy of the first delay chip. Specifically, determining the mapping relationship between the delay control parameters and the delay amount of the first delay chip based on multiple first sampled signals includes: Step S10211: Extract the target signal that meets the preset waveform conditions from multiple first sampled signals.
[0045] In this embodiment, the preset waveform condition refers to the signal waveform starting point being within the effective slope range, and the signal waveform exhibiting an upward trend after the starting point. Based on this preset waveform condition, peak-valley errors can be avoided, thereby improving calibration accuracy. It is worth noting that the delay control parameters (i.e., levels) of the second delay chip corresponding to different first sampling signals are different. Therefore, the purpose of step S10211 is to select appropriate delay control parameters for the second delay chip to improve the calibration accuracy of the first delay chip.
[0046] In one specific embodiment, the effective slope interval in the aforementioned preset waveform conditions represents the normalized sine wave interval of [-0.95, 0.95]. That is, it is necessary to perform normalization processing on multiple first sampled signals respectively, and then select the starting point phase that falls within the effective slope interval of the sine wave of [-0.95, 0.95].
[0047] It is worth noting that when the waveform of the first sampled signal does not fall completely within the above-mentioned effective slope range, a segmented calibration method can be used. Specifically, the DAC parameter range of the first delay chip corresponding to the first sampled signal is [44932, 56000]. The DAC parameter range of the first delay chip corresponding to the part within the effective slope range is [44932, 51323]. Therefore, only the part of [44932, 51323] is calibrated, and then the above calibration steps are repeated to calibrate the part of [51323, 56000].
[0048] Step S10212: Based on the phase difference between each point in the target signal and the starting point, determine the delay amount corresponding to each point in the target signal.
[0049] In this embodiment, after normalizing the target signal, the signal values of each first sampling point are obtained, and the phase value of each first sampling point is obtained by arcsine calculation. Based on the phase value of the starting point, the delay amount corresponding to the starting point can be determined. Based on the phase difference between other points and the starting point, the delay amounts of other points can be determined. Specifically, since the period frequency of the reference signal is known, the period frequency of the target signal is known. When the phase difference between any point and the starting point is known, the delay difference of any point is calculated based on the following formula: Delay difference = Phase difference / 2π * Period. Therefore, the delay amount of any point is the sum of the delay difference and the delay amount of the starting point.
[0050] Step S10213: Establish an initial mapping relationship based on the delay control parameters corresponding to each point in the target signal and the delay amount corresponding to each point in the target signal.
[0051] Please refer to Figure 4 Since the delay amount at each point has been determined in step S10212, the initial mapping relationship can be obtained by establishing the curve relationship between the delay amount and the delay control parameter. The delay value in the figure is the delay amount.
[0052] Step S10214: Smooth the initial mapping relationship to obtain the mapping relationship between the delay control parameters and the delay amount of the first delay chip.
[0053] In this embodiment, as Figure 4 As shown, due to the error of the ADC acquisition module in the sampling module, the curve of the initial mapping relationship has obvious errors, making subsequent difference calculations impossible. Therefore, it is necessary to smooth the initial mapping relationship to obtain the mapping relationship between the delay control parameters of the first delay chip and the delay amount. The processed mapping relationship is as follows: Figure 5 As shown. It should be understood that this embodiment does not limit the specific method of smoothing. The appropriate smoothing method can be flexibly selected according to the actual needs of the scenario. For example, it can be smoothed by Lewis smoothing, or it can be smoothed by polynomial fitting, or other smoothing / fitting methods.
[0054] Step S1022: Extract multiple step control parameter points from the mapping relationship based on the target calibration delay, and determine the multiple step control parameter points as the first target control parameter.
[0055] In this embodiment, the step delay increment corresponding to multiple step control parameter points is the target calibration delay. That is, the step control parameter points are extracted from the mapping relationship according to the target calibration delay, and the resulting DAC parameter array is the first target control parameter.
[0056] In a further embodiment, after obtaining the mapping relationship, control parameters whose step delay increment is not equal to the target calibration delay can also be extracted. Since the step delay increment is related to the sampling resolution of the sampling oscilloscope, step S1022 can extract the control parameters corresponding to the first delay chip under different resolutions.
[0057] Step S103: Control the sampling oscilloscope to sample the reference signal to obtain multiple second sampling signals.
[0058] In this embodiment, the period lengths of the multiple second sampling signals are matched, and the delay control parameters of the second delay chip corresponding to each of the multiple second sampling signals are different. Specifically, the period length of the second sampling signal is 0.25 * Z times the period of the reference signal, where Z is a positive integer. Based on the above settings, the end point of the previous second sampling signal is close to the start point of the next second sampling signal. Based on the distance information between the two points, the delay amount corresponding to each level of the second delay chip can be determined.
[0059] In one specific implementation, the period length of each second sampled signal is 0.25 times the period length of the reference signal, and multiple second sampled signals are as follows: Figure 6 As shown. Correspondingly, when the control sampling oscilloscope samples the reference signal, it first extracts the local control array from the first target control parameters. The total delay of the local control array corresponds to 1 / 4 of the reference signal cycle. First, it controls the second delay chip to the M1 position, and then controls the first delay chip through the local control array to obtain the first second sampled signal. Next, it controls the second delay chip to the M2 position, and then controls the first delay chip through the local control array to obtain the second second sampled signal. The above operation is repeated until all second sampled signals are obtained.
[0060] Step S104: Determine the second target control parameters based on multiple second sampling signals.
[0061] In this embodiment, the second target control parameter represents the delay control parameter of the first delay chip corresponding to the delay control parameter of the second delay chip. Based on the above, the function of the second delay chip is to increase the range, while the first delay chip is used for step delay control. When the delay amount reaches the range of the first delay chip, the step delay of the second delay chip is switched, and then the step delay of the first delay chip is rolled back, thereby achieving continuous step delay increase. The rollback delay of the first delay chip corresponds to the increase in delay by the second delay chip. That is, it is necessary to determine the accurate delay amount of each range of the second delay chip to determine the rollback delay of the first delay chip when switching the range of the second delay chip. Therefore, the second target control parameter is the rollback delay control parameter of the first delay chip, and the second target control parameter corresponds to the delay amount of each range of the second delay chip.
[0062] In one specific implementation, the first delay chip has a range of 30 picoseconds and performs step delay control in increments of 0.1 picoseconds. The next delay level of the second delay chip corresponds to a delay of 20 picoseconds. When the total delay of the sampling oscilloscope reaches 30 picoseconds, the second delay chip switches to the next level, and the first delay chip needs to back up by 19.9 picoseconds, meaning its delay value becomes 10.1 picoseconds. This ensures that the total delay of the sampling oscilloscope is 30.1 picoseconds, after which the first delay chip continues its step delay control. Based on the above scheme, it can be seen that the control parameters of the first delay chip corresponding to the second delay chip level are the DAC parameters corresponding to 10.1 picoseconds.
[0063] In this embodiment of the invention, since the control parameters of the first delay chip corresponding to each second sampling signal are consistent, it is equivalent to the first delay chip having the same back-off delay after the second delay chip switches gears. Therefore, the second target control parameters corresponding to each gear of the second delay chip can be determined by the breakpoint distance between adjacent second sampling signals. Specifically, the above-mentioned determination of the second target control parameters based on multiple second sampling signals includes: Step S1041: Based on the phase difference between each second sampled signal and the breakpoint of the adjacent second sampled signal, determine the initial delay amount corresponding to the delay control parameter of the second delay chip corresponding to each second sampled signal.
[0064] In this embodiment, adjacent second sampling signals represent the signals where the second delay chip switches gears and the first delay chip rolls back a fixed delay. The breakpoint of the adjacent second sampling signals is the breakpoint of the second delay chip switching gears. By performing amplitude normalization processing on the breakpoints and calculating the phase difference of the breakpoints, the delay difference can be calculated. Based on the above scheme, a rough value of the delay amount that the second delay chip needs to roll back for each gear switching can be calculated. Due to calculation errors, this rough value of the delay amount needs further verification.
[0065] Step S1042: Based on the initial delay amount corresponding to the delay control parameters of the second delay chip, adjust the delay control parameters of the first delay chip until the delay between the breakpoints of two adjacent second sampling signals is equal to the target calibration delay.
[0066] In this embodiment, after obtaining a rough value for the delay, the first delay chip is adjusted based on this rough value. This ensures that when the second delay chip switches gears, the first delay chip reverts to a delay amount corresponding to the rough value. The adjusted multiple second sampling signals are as follows: Figure 7 As shown.
[0067] In the previous step, the rough value of the delay amount had a calculation error. In order to ensure that there is no breakpoint error after the second delay chip switches gears, it is also necessary to perform fine calibration on the breakpoint. The fine calibration method includes: based on the breakpoint relationship of adjacent second sampling signals, multiple additional sampling points are collected between the termination point of the previous second sampling signal and the start point of the next second sampling signal. The delay amount of the first delay chip corresponding to the multiple additional sampling points is different, and the delay amount of the first delay chip corresponding to the multiple additional sampling points corresponds to the traversal DAC parameters.
[0068] For details, please refer to Figure 8 After the termination point of the previous second sampling signal, the delay amount of the first delay chip is adjusted by traversing the DAC parameters, and an additional first number of sampling points are collected. Before the start point of the next second sampling signal, the delay amount of the first delay chip is adjusted by traversing the DAC parameters, and an additional second number of sampling points are collected. Based on the additional sampling points, the termination point of the previous second sampling signal and the start point of the next second sampling signal are matched respectively, so that the precise delay difference between the termination point of the previous second sampling signal and the start point of the next second sampling signal can be determined.
[0069] In some embodiments, after the fine calibration method, a breakpoint phase optimization method is further provided. The breakpoint phase optimization method further includes: adjusting the frequency of the reference signal until the breakpoint of the second sampled signal is located in the target signal interval; and adjusting the delay control parameters of the first delay chip until the delay between the breakpoints of two adjacent second sampled signals is equal to the target calibration delay.
[0070] In this embodiment, the target signal interval is the middle position of the waveform. Preferably, the target signal interval corresponds to the signal interval with the largest waveform slope. The reason for setting the breakpoint phase optimization in this embodiment is that, under the same delay value, the amplitude difference when the breakpoint is located in the target signal interval is greater than the amplitude difference when the breakpoint is located in the peak-valley region. Moving the breakpoint to the target signal interval and repeating the above fine calibration steps can further reduce the error and improve the accuracy of the second delay chip calibration.
[0071] In a further embodiment, the delay accuracy can be improved by switching the precision mode, i.e., by using a smaller step delay to improve accuracy. Specifically, after adjusting the delay control parameters of the first delay chip until the delay between the breakpoints of two adjacent second sampling signals is equal to the target calibration delay, the method further includes: adjusting the delay control parameters of the first delay chip until the delay between the breakpoints of two adjacent second sampling signals is less than a preset delay, and the preset delay is less than the target calibration delay.
[0072] In one specific implementation, after completing the time base calibration with a 0.1 picosecond step delay, the breakpoint error can be reduced to 0.05 picoseconds. Then, by switching to the high-precision mode of 0.025 picoseconds and re-performing the calibration steps, the breakpoint error can be further reduced from 0.05 picoseconds to 0.0125 picoseconds, and temperature drift and splicing errors can be eliminated.
[0073] Step S1043: Determine the second target control parameters based on the adjusted delay control parameters of the first delay chip.
[0074] In this embodiment, coarse calibration and fine calibration respectively can reduce the breakpoint error caused by the switching of the second delay chip, ensuring the accuracy of the sampling oscilloscope in sampling and reconstructing high-speed signals. Furthermore, by setting a precision enhancement method, temperature drift and splicing errors can be eliminated, further improving the accuracy of signal sampling and reconstruction and avoiding signal distortion.
[0075] Step S105: Based on the first target control parameter and the second target control parameter, generate a target delay table. The target delay table represents the delay control parameter when the time base of the sampling oscilloscope is equal to the target calibration delay.
[0076] In this embodiment, the first target control parameter represents the DAC parameter corresponding to the step delay control of the first delay chip according to the target calibration delay. The second target control parameter represents the SPI level information when the second delay chip switches between different levels and the DAC parameter corresponding to the back-off delay of the first delay chip for each level. The first target control parameter and the second target control parameter are combined to form a DAC+SPI combined delay table, i.e., the target delay table. The target delay table is processed according to the firmware storage compression format and loaded into the register in the FPGA delay control module for use at the sampling time.
[0077] In some embodiments, generating a target delay table based on a first target control parameter and a second target control parameter includes: generating a target delay table based on valid control parameters. Specifically, after the above calibration steps, the calibration results also need to be verified to ensure that the calibration results of the two delay chips are correct. Only the verified first target control parameter and the verified second target control parameter can be used as valid control parameters.
[0078] In some embodiments, frequency offset and breakpoint dual-dimensional verification are employed. Specifically, before generating the target delay table based on the first target control parameter and the second target control parameter, the method further includes: controlling a sampling oscilloscope to sample a reference signal based on the first target control parameter and the second target control parameter to obtain a third sampled signal; when the difference between the frequency of the third sampled signal and the frequency of the reference signal is less than a preset difference threshold, and the breakpoint delay error of the third sampled signal is less than a preset error threshold, the first target control parameter and the second target control parameter are confirmed as valid control parameters.
[0079] Based on the above scheme, the calibration is verified in two dimensions. On the one hand, the deviation between the frequency of the acquired waveform and the frequency of the signal source is verified. On the other hand, the breakpoint delay error when the second delay chip switches gears is verified. If both are qualified, the calibration is confirmed to be qualified. This can avoid local calibration overfitting and ensure that the time base calibration is accurate.
[0080] This invention also provides an electronic device, which includes a processor and a memory. The memory stores at least one instruction or at least one program, which is loaded and executed by the processor to implement a time base calibration method for a sampling oscilloscope as described in any of the above embodiments.
[0081] This invention also provides a storage medium storing at least one instruction or at least one program, which is loaded and executed by a processor to implement a time base calibration method for a sampling oscilloscope as described in any of the above embodiments.
[0082] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A time base calibration method for a sampling oscilloscope, characterized in that, The sampling oscilloscope includes a first delay chip and a second delay chip, wherein the step delay of the first delay chip is less than the step delay of the second delay chip; the method includes: The sampling oscilloscope is controlled to sample the reference signal to obtain multiple first sampled signals; the delay control parameters of the first delay chip corresponding to each of the multiple first sampled signals are the same, and the delay control parameters of the second delay chip corresponding to each of the multiple first sampled signals are different; Based on the plurality of first sampling signals, a first target control parameter is determined; the first target control parameter characterizes the delay control parameter when the step delay of the first delay chip is equal to the target calibration delay. The sampling oscilloscope is controlled to sample the reference signal to obtain multiple second sampled signals; the period lengths of the multiple second sampled signals are matched with each other, and the delay control parameters of the second delay chip corresponding to each of the multiple second sampled signals are different; Based on the plurality of second sampling signals, a second target control parameter is determined; the second target control parameter represents the delay control parameter of the first delay chip corresponding to the delay control parameter of the second delay chip; Based on the first target control parameter and the second target control parameter, a target delay table is generated, wherein the target delay table represents the delay control parameter when the time base of the sampling oscilloscope is equal to the target calibration delay.
2. The method according to claim 1, characterized in that, The step of determining the first target control parameter based on the plurality of first sampled signals includes: Based on the multiple first sampling signals, the mapping relationship between the delay control parameters and the delay amount of the first delay chip is determined; Based on the target calibration delay, multiple step control parameter points are extracted from the mapping relationship, and the multiple step control parameter points are determined as the first target control parameter.
3. The method according to claim 2, characterized in that, The step of determining the mapping relationship between the delay control parameters and the delay amount of the first delay chip based on the plurality of first sampling signals includes: Extract the target signal that meets the preset waveform conditions from the plurality of first sampled signals; Based on the phase difference between each point in the target signal and the starting point, the delay amount corresponding to each point in the target signal is determined; An initial mapping relationship is established based on the delay control parameters corresponding to each point in the target signal and the delay amount corresponding to each point in the target signal; The initial mapping relationship is smoothed to obtain the mapping relationship between the delay control parameters and the delay amount of the first delay chip.
4. The method according to claim 3, characterized in that, The determination of the second target control parameters based on the plurality of second sampled signals includes: Based on the phase difference between each second sampled signal and the breakpoint of the adjacent second sampled signal, the initial delay amount corresponding to the delay control parameter of the second delay chip for each second sampled signal is determined; Based on the initial delay amount corresponding to the delay control parameters of the second delay chip, the delay control parameters of the first delay chip are adjusted until the delay between the breakpoints of two adjacent second sampling signals is equal to the target calibration delay. The second target control parameters are determined based on the adjusted delay control parameters of the first delay chip.
5. The method according to claim 4, characterized in that, Before determining the second target control parameter based on the adjusted delay control parameters of the first delay chip, the method further includes: Adjust the frequency of the reference signal until the breakpoint of the second sampled signal is located in the target signal range; Adjust the delay control parameters of the first delay chip until the delay between two adjacent breakpoints of the second sampling signal is equal to the target calibration delay.
6. The method according to claim 5, characterized in that, After adjusting the delay control parameters of the first delay chip until the delay between two adjacent breakpoints of the second sampling signal is equal to the target calibration delay, the method further includes: Adjust the delay control parameters of the first delay chip until the delay between two adjacent breakpoints of the second sampling signal is less than a preset delay, wherein the preset delay is less than the target calibration delay.
7. The method according to claim 2, characterized in that, Before generating the target delay table based on the first target control parameters and the second target control parameters, the method further includes: Based on the first target control parameter and the second target control parameter, the sampling oscilloscope is controlled to sample the reference signal to obtain a third sampled signal; When the difference between the frequency of the third sampled signal and the frequency of the reference signal is less than a preset difference threshold, and the breakpoint delay error of the third sampled signal is less than a preset error threshold, the first target control parameter and the second target control parameter are confirmed as valid control parameters. The step of generating a target delay table based on the first target control parameters and the second target control parameters includes: Based on the effective control parameters, the target delay table is generated.
8. A time base calibration system for a sampling oscilloscope, characterized in that, The oscilloscope comprises a signal source module, a first delay chip, a second delay chip, a sampling module, and a control module, wherein the signal source module, the first delay chip, the second delay chip, and the sampling module are connected in sequence, and the control module is connected to the signal source module, the first delay chip, the second delay chip, and the sampling module respectively. The control module is used to execute a time base calibration method for a sampling oscilloscope according to any one of claims 1-7.
9. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or at least one program being loaded and executed by the processor to implement a time base calibration method for a sampling oscilloscope as described in any one of claims 1-7.
10. A storage medium, characterized in that, The storage medium stores at least one instruction or at least one program, which is loaded and executed by a processor to implement a time base calibration method for a sampling oscilloscope as described in any one of claims 1-7.