A high-speed configurable two-dimensional CFAR detector based on FPGA

Abstract

The application relates to a high-speed configurable two-dimensional CFAR detector based on an FPGA. The FPGA accelerator is used for completing two-dimensional CFAR detection; the chain FIFO queue is used for buffering and rearranging serially input distance-Doppler two-dimensional power matrix data to realize construction of a two-dimensional data window for parallel output; the background estimation unit is used for calculating reference cell data according to a two-dimensional cross window constructed with a to-be-detected cell as the center to obtain a background estimation value in a mean algorithm mode; the decision unit is used for target decision of the to-be-detected cell according to the background estimation value and a threshold coefficient T and outputting two-dimensional coordinates of the to-be-detected cell; and the OS detection unit is used for completing background estimation in an order statistics algorithm mode and target decision of the to-be-detected cell according to a sorting position and the threshold coefficient T and outputting two-dimensional coordinates of the to-be-detected cell. The application improves the overall processing speed, flexibility and configurability of two-dimensional CFAR detection.

Description

Technical Field

[0001] This invention belongs to the field of radar target detection technology, and specifically relates to a high-speed configurable two-dimensional CFAR detector based on FPGA. Background Technology

[0002] In the field of radar target detection technology, Constant False Alarm Rate (CFAR) detection is a commonly used target detection algorithm. Compared to one-dimensional CFAR, which processes only the range or Doppler dimension, two-dimensional CFAR can detect targets simultaneously in the range-Doppler plane, resulting in higher detection accuracy and stronger anti-jamming capabilities. It has become an important detection method in modern radar systems. Traditional two-dimensional CFAR algorithms are typically deployed on general-purpose processing platforms such as Digital Signal Processors (DSPs). However, with the continuous increase in the data scale and real-time requirements of radar systems, DSPs are gradually becoming insufficient in terms of throughput and power consumption. Field Programmable Gate Arrays (FPGAs), with their high flexibility, high energy efficiency, and high bandwidth, have been widely used in radar signal processing systems.

[0003] Two-dimensional CFAR typically constructs a two-dimensional sliding detection window centered on the cell under test. The size of the detection window varies depending on the application scenario, and the detection algorithm used also differs. Therefore, supporting configurable detection window size and configurable detection algorithm in the hardware structure places high demands on the versatility and complexity of FPGA design. Secondly, under large-scale detection window conditions, traditional data rearrangement structures based on chained First-In-First-Out (FIFO) queues require a long pre-filling time during the startup phase, thus reducing the overall system processing efficiency.

[0004] Therefore, how to achieve a configurable, flexible, and highly efficient two-dimensional CFAR detection structure is an important technical problem that this invention urgently needs to solve. Summary of the Invention

[0005] The purpose of this invention is to provide a high-speed, configurable two-dimensional CFAR detector based on FPGA. This invention achieves dynamic configurability of two-dimensional CFAR detection by configuring the detection mode, window size, and related parameters, and by combining a chained FIFO and sliding window structure to realize data processing. By adopting a chained FIFO with variable input port structure design in the two-dimensional CFAR data buffering and rearrangement process, the FIFO input position is dynamically adjusted according to the size of the reference unit and the protection unit, thereby reducing the pre-filling time in the data serial-to-parallel conversion process and improving the overall processing speed of two-dimensional CFAR detection.

[0006] To address the aforementioned technical problems, this invention provides a high-speed, configurable two-dimensional CFAR detector based on FPGA, comprising: The host computer is used to configure system parameters; An FPGA accelerator is used to perform two-dimensional CFAR detection; including: A chained FIFO queue is used to buffer and rearrange the range-Doppler two-dimensional power matrix data serially input from DDR to construct a two-dimensional data window for parallel output; and by dynamically adjusting the input port position of the chained FIFO queue according to the size of the reference unit and the protection unit, the pre-filling time during the serial-to-parallel conversion process is reduced. The background estimation unit is used to calculate the background estimate value by using a two-dimensional cross window constructed with the unit to be tested as the center in the mean-based algorithm CFAR mode. The decision unit is used to make a target decision on the unit under test based on the background estimate and the threshold coefficient T, and output its two-dimensional coordinate mark to the DDR. The OS detection unit is used to perform background estimation in the CFAR (Categorical Statistical Arithmetic) algorithm mode, and to make target decisions on the unit to be tested based on the sorting position and threshold coefficient T, and output its two-dimensional coordinates to the DDR (Database Memory).

[0007] Preferably, the system parameters include: reference unit size D, protection unit size P, number of points, number of pulses, threshold coefficient T, and sorting factor K; the system supports a maximum reference unit size M and a maximum protection unit size L.

[0008] Preferably, the chained FIFO queue includes: N FIFOs, a read / write control module, and a selector MUX1; the N FIFOs are sequentially connected end-to-end to generate a data column Q. RWhere N = 2M + 2L + 1, and every two adjacent FIFOs from the first FIFO to the M+Lth FIFO also include an access selector MUX1, which is used to access the read / write control module. At the same time, the read / write control module is accessed by the first FIFO. The read / write control module is used to input range-Doppler two-dimensional power matrix data, reference cell size D, and protection cell size P.

[0009] Preferably, the processing procedure of the chained FIFO queue includes: During the pre-filling stage, the input port position of the chain FIFO queue is determined according to the reference unit size D≤M and the protection unit size P≤L, and data is input from the M+LP-D+1th FIFO. The data is then transmitted to the subsequent FIFOs in sequence until the M+L+1th FIFO. Once the FIFO pre-filling is complete, output all the data in the FIFO to form the data column Q. R New input data continues to be written from the M+LP-D+1th FIFO to the chained FIFO queue, and shift operations are performed to transmit the data level by level until it is filled to the 2M+2L+1th FIFO. After the last data point enters the FIFO, the corresponding data column Q will continue to be output. R This continues until all data in all FIFOs has been output.

[0010] Preferably, the background estimation unit includes: The mean-based horizontal window detection unit is used to perform background estimation of the reference unit data in the horizontal direction of the cross-shaped window; it includes: an accumulator, a subtractor, a comparator OM1, buffers fifo1~fifo2, and registers reg1~reg2; the accumulator is used to input the data column Q in the horizontal direction. R Extract the intermediate test unit data and sum it up. Store the summed result in the buffer fifo1 and the register reg1 respectively. Subtract the current accumulated value obtained from the register reg1 from the historical accumulated value obtained from the buffer fifo1 by the subtractor. Store the right reference window data obtained by the subtraction into the buffer fifo2 and the register reg2 respectively. Compare the left reference window data obtained from the buffer fifo2 by the comparator OM1 with the right reference window data obtained from the register reg1. The mean-based vertical window detection unit is used to perform background estimation of the reference unit data in the vertical direction of the cross-shaped window; it includes adder 1, comparator OM2, and buffers FIFO3~FIFO4; the adder 1 is used to input the data column Q in the vertical direction. RThe extracted upper and lower reference unit data are summed by the upper and lower addition trees respectively, and the summation results are compared by the comparator OM2. The comparison results are stored in the buffer fifo3 and the register reg4 respectively. Selector MUX2 is used to perform maximum, minimum, or average calculations on the upper, lower, left, and right reference values ​​of the cross window according to the selected detection working mode and output the selected values. The buffer FIFO5 is used to cache the data of the unit under test before outputting it.

[0011] Preferably, the processing procedure of the background estimation unit includes: In the mean-based CFAR pattern, along the vertical direction, from data column Q... R Extract the upper and lower reference cell data and form a new 2M data set. The actual number of reference cells extracted is 2D. If 2D < 2M, fill the remaining positions with 0. For the extracted 2M data points, perform the summation of the upper addition tree of the first M data points and the summation of the lower addition tree of the last M data points respectively. Then, input the summation results up_sum and down_sum into comparator OM2 for comparison to obtain the larger value col_max and the smaller value col_min. The larger value col_max and the smaller value col_min are stored in the buffers fifo3~fifo4 respectively for caching, and then output simultaneously after the horizontal calculation is completed. Along the horizontal direction, from data column Q R Extract the intermediate data of the unit under test and input it into the accumulator to accumulate and sum to obtain the accumulated result; The accumulated result is stored in the buffer fifo1 and register reg1 respectively. After a delay of D clock cycles, the corresponding historical accumulated value in the buffer fifo1 is retrieved. The current accumulated value stored in register reg1 is subtracted from the historical accumulated value to obtain the right reference window data and right_sum, which are then stored in register reg2. The data from the right reference window is stored in the buffer fifo2 and retrieved after a delay of D+2P+1 clock cycles to obtain the data from the left reference window and left_sum. The data from the left reference window and left_sum are compared with the data from the right reference window and right_sum in the comparator OM1 to obtain the larger value row_max and the smaller value row_min in the horizontal direction. At the same time, the larger value col_max and the smaller value col_min in the vertical direction are read. Based on the selected detection mode, the upper, lower, left, and right reference values ​​of the cross window are calculated to obtain the maximum, minimum, or average value. Specifically, the larger values ​​row_max and col_max are taken as the largest, the smaller values ​​row_min and col_min are taken as the smallest, and the larger and smaller values ​​row_max and col_min are averaged to obtain the background estimate under the mean-based CFAR mode. At the same time, the data of the unit under test is buffered in the FIFO5 buffer and the amplitude data is output synchronously with the background estimate.

[0012] Preferably, the decision unit includes: a multiplier, a buffer FIFO6, a comparator OM3, a counter, and a selector MUX3. The multiplier multiplies the background estimate by a threshold coefficient T to generate a detection threshold, which is then compared with the amplitude data buffered in the buffer FIFO6 to the comparator OM3. When the amplitude data is greater than the detection threshold, the amplitude data is determined to be a valid target signal, and the valid flag is set to 1; otherwise, it is determined to be an invalid signal, and the valid flag is set to 0. The counter counts the addresses of the amplitude data to generate row and column position information synchronized with the timing of the amplitude data. When the detection result is valid, the selector MUX3 selects and outputs the amplitude data of the unit under test and its corresponding row and column position information; when the detection result is invalid, no corresponding data and position information are output.

[0013] Preferably, the OS detection unit includes: The OS horizontal window detection unit is used to sort the data of the horizontal reference unit of the cross window; it includes a shift register, a comparator OM4, and an adder 2; the shift register is used to input data from data column Q. Y The intermediate data extracted from the data column Q Y For data column Q R The data is obtained by multiplying it by the threshold coefficient T; the left and right reference cell data extracted from the shift register and the data from the data column Q are input through the comparator OM4. R Extract the intermediate data of the unit to be tested, compare it, and then output it to the second adder for addition tree summation; The OS vertical window detection unit is used to sort the reference unit data in the vertical direction of the cross-shaped window; it includes: comparator OM5, adder 3, and buffer FIFO8; the comparator OM5 is used to input from data column Q. Y The extracted upper and lower reference unit data, and the data from the data column Q RExtract the intermediate test unit data, compare it, and output it to the adder three for addition tree summation. Then output the summation result to the buffer fifo8 for caching. Buffer FIFO7 and counter 2, wherein buffer FIFO7 is used for input from the data column Q R The intermediate data of the unit under test, namely amplitude data, is extracted and output to comparators OM4~OM5, counter 2 and selector MUX4 after being buffered. Counter 2 is used to count the address of the amplitude data to generate row and column position information synchronized with the amplitude data timing. Adder 4, comparator OM6, and selector MUX4 are used to add the summation result of adder 2 to the summation result cached in buffer fifo8, and output the result to comparator OM6 for comparison with sorting factor K. When the comparison result is valid, the amplitude data and its corresponding row and column position information are selected and output through selector MUX4.

[0014] Preferably, the processing procedure of the OS detection unit includes: In ordered statistical model, the data column Q R Multiply by the threshold coefficient T to obtain the data column Q Y At the same time, the data column Q R The intermediate test unit data is stored in the buffer area FIFO7 and the corresponding test unit data, i.e. amplitude data, is output when the detection result is valid. Along the vertical direction, from data column Q Y Extract the upper and lower reference unit data and form a new 2M data. The number of extracted reference units is 2D. If 2D < 2M, fill the remaining positions with a fixed large number C. The extracted 2M data points are compared with the data of the unit under test. The comparison results are summed using an addition tree to obtain the vertical comparison sum col_comp_sum, which is then stored in the buffer fifo8. Along the horizontal direction, from data column Q Y Intermediate data is extracted and input into a shift register, which has a length of 2M+2L+1. Data is input from the first shift register and shifted backward in each clock cycle. Extract left and right reference cell data from the shift register and form new 2M data, wherein the number of extracted reference cells is 2D. If 2D < 2M, fill the remaining positions with a fixed large number C. The extracted data is compared with the data of the unit to be tested, and the comparison results are summed by an addition tree to obtain the comparison and row_comp_sum in the horizontal direction. Read the vertical comparison sum col_comp_sum stored in the buffer fifo8, and add it to the horizontal comparison sum row_comp_sum to obtain the total comparison sum comp_sum of the reference cells on the top, bottom, left and right sides of the cross window; The comparison sum comp_sum is compared with the ranking factor K. If the comparison sum comp_sum is greater than or equal to the ranking factor K, the unit under test is determined to be the target and its amplitude data and corresponding row and column position information are output. If the comparison sum comp_sum is less than the ranking factor K, no detection result is output.

[0015] This invention also provides a high-speed configurable two-dimensional CFAR detection method based on FPGA, employing a high-speed configurable two-dimensional CFAR detector based on FPGA as described above, comprising: Configure system parameters via a host computer; In the CFAR detection mode of the mean-based algorithm, the system first reads the input range-Doppler two-dimensional power matrix data from DDR, and generates a data column Q through a chained FIFO queue. R This enables the conversion of one-dimensional serial data into a two-dimensional data structure that outputs in parallel. Based on data column Q R Background estimation is performed to obtain the background estimation value corresponding to the unit under test. Target determination is performed based on the background estimation value, and the amplitude data of the detected target and its corresponding row and column position information are output. In the CFAR (Category-Ordered Statistical Algorithm) mode, the system reads the input range-Doppler two-dimensional power matrix data from DDR (Data Retrieval Memory) and generates a data column Q through a chained FIFO queue. R ; Based on data column Q R Simultaneously, background estimation and target decision processing are completed, thereby outputting the detection results to DDR.

[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention proposes an optimization strategy with variable input ports for a chained FIFO. By dynamically adjusting the FIFO input position based on the size of the reference and protection units, the pre-filling time of the chained FIFO can be significantly reduced when the detection window size is smaller than the maximum window size, thereby improving the overall processing speed of 2D CFAR detection. Furthermore, this invention adopts a 2D CFAR detection architecture based on a cross-window structure. Through reasonable module division, it achieves a unified hardware implementation of mean-based CFAR detection and ordered statistical OS-CFAR detection modes, improving the flexibility and configurability of the system structure. Attached Figure Description

[0017] Figure 1The diagram shows the structure of the high-speed configurable two-dimensional CFAR detector based on FPGA provided by this invention.

[0018] Figure 2 The diagram shows the chained FIFO queue structure provided by this invention.

[0019] Figure 3 The calculation process structure diagram of the background valuation unit provided by the present invention.

[0020] Figure 4 This is a structural diagram of the decision unit provided by the present invention.

[0021] Figure 5 The diagram shows the computational flow structure of the OS detection unit provided by this invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0023] like Figure 1 As shown, this embodiment of the invention specifically provides a high-speed configurable two-dimensional CFAR detector based on FPGA, including a host computer for configuring parameters and an FPGA accelerator for calculating two-dimensional CFAR. The FPGA accelerator includes a chained FIFO queue, a background estimation unit, a decision unit, and an ordered statistics (OS) detection unit.

[0024] The chained FIFO queue consists of N interconnected FIFOs, a selector MUX1, and a read / write control module. It is used to buffer and rearrange the serially input two-dimensional power matrix data, thus constructing a two-dimensional data window. MUX1 primarily enables configurable input port selection for the chained FIFO queue, dynamically determining which FIFO stage the input data enters the chained queue from based on the number of reference units D and protection units P. On one hand, MUX1 can select the output of the previous FIFO as the input to the current FIFO, allowing data to be transmitted step-by-step according to the chained FIFO structure. On the other hand, MUX1 can also select external input data as the input to the current FIFO, allowing input data to directly enter the chained FIFO queue from a specified FIFO position. The background estimation unit is used to perform background estimation in the mean-based CFAR mode. It mainly consists of a mean-based horizontal window detection unit, a mean-based vertical window detection unit, a selector MUX2, and a buffer FIFO5. The mean-based horizontal window detection unit consists of an accumulator, a subtractor, a comparator OM1, buffers FIFO1~FIFO2, and registers reg1~reg2, used to perform background estimation of the horizontal reference cell data of the cross-shaped window. The mean-based vertical window detection unit consists of an adder, a comparator OM2, and buffers FIFO3~FIFO4, used to perform background estimation of the vertical reference cell data of the cross-shaped window. The decision unit is used to make a target decision on the unit under test based on the background estimation result in the mean-type CFAR mode. It consists of a multiplier, a buffer FIFO6, a comparator OM3, a counter 1, and a selector MUX3. It generates a detection threshold by operating on the background estimation value and the threshold coefficient, and compares it with the unit under test to output the position and amplitude information of the target. The OS detection unit is used to perform background estimation and target determination in the ordered statistical class CFAR mode. It consists of an OS horizontal window detection unit and an OS vertical window detection unit, a buffer FIFO7, a counter 2, an adder 4, a comparator OM6, and a selector MUX4. The OS horizontal window detection unit consists of a shift register, a comparator OM4, and an adder 2, and is used to sort the reference cell data in the horizontal direction of the cross window. The OS vertical window detection unit consists of a comparator OM5, an adder 3, and a buffer FIFO8, and is used to sort the reference cell data in the vertical direction of the cross window. Based on the sorting result and threshold parameters, it makes a target determination on the target cell and outputs the target position and amplitude information in the OS mode.

[0025] Furthermore, the chained FIFO queue processing procedure includes the following steps: Step 11, pre-filling stage: Determine the input port position of the chain FIFO queue according to the reference unit size D£M (M is the maximum configuration range of the reference unit) and the protection unit size P£L (L is the maximum configuration range of the protection unit), and input data from the M+LP-D+1th FIFO. The data is transmitted to the subsequent FIFOs in sequence until the M+L+1th FIFO. Step 12: After the FIFO pre-filling is complete, output all the data in the FIFO to form data column Q. R ; where data column Q R Given the data sequence {Xn…X3,X2,X1}, new input data continues to be written from the M+LP-D+1th FIFO to the linked FIFO queue, and is transmitted level by level with the queue shift operation until it is filled to the 2M+2L+1th FIFO. Step 13: After the last data enters the FIFO, continue to output the corresponding data column Q. R This continues until all data in all FIFOs has been output.

[0026] Furthermore, the calculation process of the background estimation unit includes the following steps: Step 21, in the mean-based CFAR pattern, vertically, from data column Q R Extract the upper and lower reference unit data and form a new 2M data set. The actual number of reference units extracted is 2D. If 2D < 2M, fill the remaining positions with 0. Step 22: Perform tree summation on the first M data (called the upper end) and the last M data (called the lower end) of the extracted 2M data respectively, and input the summation results into the comparator to compare and obtain the larger and smaller values; Step 23: Based on the comparison results, store the larger and smaller values ​​into FIFOs respectively, and output them simultaneously after the horizontal calculation is completed; Step 24, in the horizontal direction, from data column Q R Extract intermediate test data and input it into an accumulator for summation; Step 25: Store the accumulated result in the buffer, retrieve the corresponding historical accumulated value after a delay of D clock cycles, subtract the historical accumulated value from the current accumulated value to obtain the right reference window data sum; Step 26: Store the right reference window data in the buffer, and retrieve it after a delay of D+2P+1 clock cycles to obtain the left reference window data. Step 27: Compare the data from the left and right reference windows to obtain the larger and smaller values ​​in the horizontal direction, and at the same time read the larger and smaller values ​​in the vertical direction; Step 28: Based on the selected detection mode, perform maximum, minimum or average calculations on the upper, lower, left and right reference values ​​of the cross window to obtain the background estimation value under the mean-based CFAR mode. At the same time, the data of the unit under test is cached in the buffer area and output synchronously with the background estimation value.

[0027] Furthermore, the calculation process of the decision unit includes the following steps: Step 31: In the mean-based CFAR mode, the background estimate is multiplied by the threshold coefficient T to obtain the detection threshold. Simultaneously, the data of the unit to be tested is input into a buffer for caching to ensure that it is output synchronously with the threshold after the calculation is completed. Step 32: Compare the detection threshold with the data of the unit under test. If the data of the unit under test is greater than the detection threshold, the data is determined to be a valid target signal, and the valid flag is set to 1; otherwise, it is determined to be an invalid signal, and the valid flag is set to 0. When the detection result is valid, the amplitude of the unit under test and its corresponding row and column position information are output simultaneously; when the detection result is invalid, the corresponding data and position information are not output.

[0028] Furthermore, the calculation process of the OS detection unit includes the following steps: Step 41, in ordered statistical mode, sort the data column Q R Multiply by the threshold coefficient T to obtain the data column Q Y At the same time, the data column Q R The intermediate test data is stored in the buffer area and the corresponding test unit data is output when the detection result is valid. Step 42, in the vertical direction, from data column Q Y Extract the upper and lower reference unit data and form a new 2M data. The number of extracted reference units is 2D. If 2D < 2M, fill the remaining positions with a fixed large number C. Step 43: Compare the extracted 2M data points with the unit under test, perform addition tree summation on the comparison results, and store the summation results in the cache area; Step 44, in the horizontal direction, from data column Q Y Intermediate data is extracted and input into a shift register, which has a length of 2M+2L+1. Data is input from the first register and shifted backward in each clock cycle. Step 45: Extract the left and right reference cell data from the shift register and form a new 2M data. The number of extracted reference cells is 2D. If 2D < 2M, fill the remaining positions with a fixed large number. Step 46: Compare the extracted data with the unit to be tested, and perform addition tree summation on the comparison results to obtain the comparison sum in the horizontal direction; Step 47: Read the vertical comparison sum stored in the buffer and add it to the horizontal comparison sum to obtain the total comparison sum of the reference cells in the top, bottom, left and right of the cross window; Step 48: Compare the comparison sum with the sorting factor K. When the comparison sum is greater than or equal to K, determine the unit to be tested as the target and output its amplitude and corresponding row and column position information; when the comparison sum is less than K, do not output the detection result.

[0029] The operation method of this embodiment is as follows: Before performing CFAR testing, the system parameters are first configured via a host computer, including the number of reference units D, the number of protection units P, the number of points, the number of pulses, the threshold coefficient T, and the sorting factor K. In mean-based CFAR testing mode, the system first reads the input two-dimensional power matrix data from the DDR and generates a data column Q through a chained FIFO queue. R This converts one-dimensional serial data into a two-dimensional data structure; subsequently, based on data column Q... R Background estimation is performed to obtain the estimated background value corresponding to the unit under test; further, target determination is performed based on the background estimation result, and the detected target amplitude and its corresponding location information are output. In ordered statistical OS-CFAR mode, the system first reads the input two-dimensional power matrix data from DDR, and generates a data column Q through a chained FIFO queue. R Subsequently, based on data column Q R Simultaneously, background estimation and target decision processing are completed in OS mode, thereby outputting detection results.

[0030] In this embodiment, the data input consists of 128 pulses, each containing 1024 data points, each data point being a 32-bit amplitude value. The data is input sequentially according to the pulse order. The detection window uses a cross-shaped structure, with a reference cell size D of 8 and a maximum supported reference cell size M of 40. The protection cell size P is 4, and a maximum supported protection cell size L of 16. The threshold coefficient T is set to 5, the sorting factor K is set to 24, and the CFAR detection modes include both Cell-Averaging (CA) CFAR mode and Ordered Statistical OS-CFAR mode.

[0031] like Figure 2 As shown, the maximum number of reference units M is 40, the maximum number of protection units L is 16, and the chained FIFO queue consists of 113 (2M+2L+1) FIFOs connected end-to-end. The chained FIFO queue processing includes the following steps: Step 11: In the pre-filling stage, the input two-dimensional power matrix data is input from the 45th FIFO in 32-bit floating-point form after the amplitude calculation is completed. The data is then transmitted to the subsequent FIFOs in sequence until the 57th FIFO. Step 12: When the 45th to 57th FIFOs are all filled with 1024 data points, the pre-filling stage ends, and the data from the 113 FIFOs are output to form data column Q. R New input data continues to be written from the 45th FIFO to the chained FIFO queue, and is transmitted level by level with the queue shift operation until the 113th FIFO is filled. Step 13: After the last data enters the FIFO, the system continues to output the corresponding data column Q. R This continues until all data in all FIFOs has been output.

[0032] like Figure 3 As shown, the calculation process of the background estimation unit includes the following steps: Step 21, in CA-CFAR mode, from data column Q in the vertical direction R Extract the upper and lower reference unit data and form a new set of 80 data points, of which 16 data points are actually extracted and the remaining 64 data points are padded with 0; Step 22: Perform tree summation on the first 40 data points (called the upper end) and the last 40 data points (called the lower end) of the extracted 80 data points respectively to obtain the sum of the upper window data and the sum of the lower window data and the sum of the lower window data. Then, input the summation results into the comparator for comparison. Step 23: Based on the comparison results, store the larger value col_max and the smaller value col_min into the buffer area respectively, and output them synchronously after the horizontal calculation is completed; Step 24, in the horizontal direction, from data column Q R Extract intermediate data and input it into an accumulator for summation; Step 25: Store the accumulated result in the buffer, retrieve the corresponding historical accumulated value after a delay of 8 clock cycles, subtract the historical accumulated value from the current accumulated value to obtain the data of the right reference window and right_sum; Step 26: Store the right reference window data in the buffer, and retrieve it after a 17-clock-cycle delay to obtain the left reference window data and left_sum; Step 27: Compare the data from the left and right reference windows to obtain the larger value row_max and the smaller value row_min in the horizontal direction, and at the same time read the larger value and the smaller value in the vertical direction; Step 28: Average the reference values ​​in the four directions of the cross window (top, bottom, left, and right), i.e., calculate the average of col_max, col_min, row_max, and row_min to obtain the background estimate in CA-CFAR mode. At the same time, the data of the unit under test is cached in the buffer area and output synchronously with the background estimate.

[0033] like Figure 4 As shown, the calculation process of the decision unit includes the following steps: Step 31: In CA-CFAR mode, the background estimate is multiplied by the threshold coefficient 5 to obtain the detection threshold. Simultaneously, the data of the unit to be tested is input into a buffer for caching to ensure that it is output synchronously with the threshold after the threshold calculation is completed. Step 32: Compare the detection threshold with the data of the unit under test. If the data of the unit under test is greater than the detection threshold, the data is determined to be a valid target signal, and the valid flag is set to 1; otherwise, it is determined to be an invalid signal, and the valid flag is set to 0. When the detection result is valid, the amplitude of the unit under test and its corresponding row and column position information are output simultaneously; when the detection result is invalid, the corresponding data and position information are not output.

[0034] like Figure 5 As shown, the calculation process of the OS detection unit includes the following steps: Step 41, in OS-CFAR mode, transfer data column Q R Multiply by a threshold coefficient of 5 to obtain the data column Q. Y At the same time, the data column Q R The intermediate data is stored in a FIFO buffer, and the corresponding test unit data is output when the detection result is valid. Step 42, in the vertical direction, from data column Q Y Extract the upper and lower reference unit data and form a new set of 80 data points, of which 16 are reference unit data points and the remaining 64 data points are filled with fixed large numbers. Step 43: Compare the 80 extracted data points with the unit under test, perform tree summation on the comparison results to obtain the vertical comparison sum col_comp_sum, and store the result in FIFO; Step 44, in the horizontal direction, from data column Q Y Intermediate data is extracted and input into a shift register, which is 113 in length. The data is input from the first register cell and shifted backward in each clock cycle. Step 45: Extract the left and right reference cell data from the shift register and form a new set of 80 data, of which 16 reference cell data are extracted and the remaining 64 data are padded with a fixed large number. Step 46: Compare the extracted data with the unit to be tested, and perform addition tree summation on the comparison results to obtain the horizontal comparison and row_comp_sum; Step 47: Read the vertical comparison sum stored in the buffer and add it to the horizontal comparison sum to obtain the total comparison sum of the reference cells in the top, bottom, left and right of the cross window, comp_sum; Step 48: Compare the comparison sum with the sorting factor 24. When the comparison sum is greater than or equal to 24, determine that the unit to be tested is the target and output its amplitude and corresponding row and column position information; when the comparison sum is less than 24, no detection result is output.

[0035] The following experimental results illustrate the speed improvement of the proposed chain-type FIFO input port variable optimization strategy compared to the traditional fixed input port scheme. Table 1 shows the comparison of the running time of the proposed scheme and the traditional fixed input from the first port scheme under different detection window sizes (the sum of the reference unit and the protection unit).

[0036] Table 1. Comparison of pre-filling time and overall testing time between this solution and the traditional solution. 3 291.84 20.48 947.2 675.84 6 291.84 35.84 947.2 691.2 12 291.84 66.56 947.2 721.92 18 291.84 97.28 947.2 752.64 24 291.84 128 947.2 783.36 30 291.84 158.72 947.2 814.08 36 291.84 189.44 947.2 844.8 56 291.84 291.84 947.2 947.2 In the experiment, a fixed-size 128×1024 distance-Doppler matrix was used as input data, with 128 pulses, each containing 1024 data points. The FPGA operating clock frequency was set to 200MHz. Under the same experimental conditions, different detection window parameters were tested, and the system's prefill time and overall detection time were statistically analyzed.

[0037] Experimental results show that, compared with the traditional fixed input port structure, the variable input port strategy of the chain FIFO proposed in this invention can significantly reduce the pre-filling time of the chain FIFO queue under small window conditions, thereby effectively reducing the overall detection time and improving the processing efficiency of two-dimensional CFAR detection.

[0038] It should be noted that the specific algorithm and process sequence in this application are not limited to those described above, and can be modified according to specific circumstances. The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-speed configurable two-dimensional CFAR detector based on FPGA, characterized in that, include: The host computer is used to configure system parameters; The system parameters include: reference unit size D, protection unit size P, number of points, number of pulses, threshold coefficient T, and sorting factor K; the system supports a maximum reference unit size M and a maximum protection unit size L. An FPGA accelerator is used to perform two-dimensional CFAR detection; including: A chained FIFO queue is used to buffer and rearrange the range-Doppler two-dimensional power matrix data serially input from DDR to construct a two-dimensional data window for parallel output; and by dynamically adjusting the input port position of the chained FIFO queue according to the size of the reference unit and the protection unit, the pre-filling time during the serial-to-parallel conversion process is reduced. The background estimation unit is used to calculate the background estimate value by using a two-dimensional cross window constructed with the unit to be tested as the center in the mean-based algorithm CFAR mode. The decision unit is used to make a target decision on the unit under test based on the background estimate and the threshold coefficient T, and output its two-dimensional coordinate mark to the DDR. The OS detection unit is used to perform background estimation in the CFAR (Categorical Statistical Arithmetic) algorithm mode, and to make target decisions on the unit to be tested based on the sorting position and threshold coefficient T, and output its two-dimensional coordinates to the DDR (Database Memory). The chained FIFO queue includes: N FIFOs, a read / write control module, and a selector MUX1; the N FIFOs are sequentially connected end-to-end to generate a data column Q. R Where N = 2M + 2L + 1, and every two adjacent FIFOs from the first FIFO to the M+Lth FIFO also include an access selector MUX1, which is used to access the read / write control module. At the same time, the read / write control module is accessed by the first FIFO. The read / write control module is used to input range-Doppler two-dimensional power matrix data, reference cell size D, and protection cell size P. The processing procedure of the chained FIFO queue includes: During the pre-filling stage, the input port position of the chain FIFO queue is determined according to the reference unit size D≤M and the protection unit size P≤L, and data is input from the M+LP-D+1th FIFO. The data is then transmitted to the subsequent FIFOs in sequence until the M+L+1th FIFO. Once the FIFO pre-filling is complete, output all the data in the FIFO to form the data column Q. R New input data continues to be written from the M+LP-D+1th FIFO to the chained FIFO queue, and shift operations are performed to transmit the data level by level until it is filled to the 2M+2L+1th FIFO. After the last data point enters the FIFO, the corresponding data column Q will continue to be output. R Continue until all data in all FIFOs has been output; The background estimation unit includes: The mean-based horizontal window detection unit is used to perform background estimation of the reference unit data in the horizontal direction of the cross-shaped window; it includes: an accumulator, a subtractor, a comparator OM1, buffers fifo1~fifo2, and registers reg1~reg2; the accumulator is used to input the data column Q in the horizontal direction. R The intermediate test unit data is extracted and accumulated. The accumulated sum is stored in the buffer fifo1 and the register reg1 respectively. The current accumulated value obtained from the register reg1 is subtracted from the historical accumulated value obtained from the buffer fifo1 by the subtractor. The right reference window data obtained by the subtraction is stored in the buffer fifo2 and the register reg2 respectively. The left reference window data obtained from the buffer fifo2 by the comparator OM1 is compared with the right reference window data obtained from the register reg1. The mean-based vertical window detection unit is used to perform background estimation of the reference unit data in the vertical direction of the cross-shaped window; it includes adder 1, comparator OM2, and buffers FIFO3~FIFO4; the adder 1 is used to input the data column Q in the vertical direction. R The extracted upper and lower reference unit data are summed by the upper and lower addition trees respectively, and the summation results are compared by the comparator OM2. The comparison results are stored in the buffer fifo3 and the register reg4 respectively. Selector MUX2 is used to perform maximum, minimum, or average calculations on the upper, lower, left, and right reference values ​​of the cross window according to the selected detection working mode and output the selected values. The buffer FIFO5 is used to buffer the data of the unit under test before outputting it. The decision unit includes a multiplier, a buffer FIFO6, a comparator OM3, a counter, and a selector MUX3. The multiplier multiplies the background estimate by a threshold coefficient T to generate a detection threshold, which is then compared with the amplitude data buffered in the FIFO6 buffer and input to the comparator OM3. If the amplitude data is greater than the detection threshold, it is determined to be a valid target signal, and the valid flag is set to 1; otherwise, it is determined to be an invalid signal, and the valid flag is set to 0. The counter counts the addresses of the amplitude data to generate row and column position information synchronized with the amplitude data timing. When the detection result is valid, the selector MUX3 selects and outputs the amplitude data of the unit under test and its corresponding row and column position information; when the detection result is invalid, no corresponding data or position information is output. The processing procedure of the background estimation unit includes: In the mean-based CFAR pattern, along the vertical direction, from data column Q... R Extract the upper and lower reference cell data and form a new 2M data set. The actual number of reference cells extracted is 2D. If 2D < 2M, fill the remaining positions with 0. For the extracted 2M data points, perform the summation of the upper addition tree of the first M data points and the summation of the lower addition tree of the last M data points respectively. Then, input the summation results up_sum and down_sum into comparator OM2 for comparison to obtain the larger value col_max and the smaller value col_min. The larger value col_max and the smaller value col_min are stored in the buffers fifo3~fifo4 respectively for caching, and then output simultaneously after the horizontal calculation is completed. Along the horizontal direction, from data column Q R Extract the intermediate data of the unit under test and input it into the accumulator to accumulate and sum the data to obtain the accumulated result; The accumulated result is stored in the buffer fifo1 and register reg1 respectively. After a delay of D clock cycles, the corresponding historical accumulated value in the buffer fifo1 is retrieved. The current accumulated value stored in register reg1 is subtracted from the historical accumulated value to obtain the right reference window data and right_sum, which are then stored in register reg2. The data from the right reference window is stored in the buffer fifo2 and retrieved after a delay of D+2P+1 clock cycles to obtain the data from the left reference window and left_sum. The data from the left reference window and left_sum are compared with the data from the right reference window and right_sum in the comparator OM1 to obtain the larger value row_max and the smaller value row_min in the horizontal direction. At the same time, the larger value col_max and the smaller value col_min in the vertical direction are read. Based on the selected detection mode, the upper, lower, left, and right reference values ​​of the cross window are calculated to obtain the maximum, minimum, or average values. Specifically, the larger values ​​row_max and col_max are taken as the largest, the smaller values ​​row_min and col_min are taken as the smallest, and the larger values ​​row_max and row_min are averaged, and the larger values ​​col_max and col_min are averaged to obtain the background estimate under the mean-based CFAR mode. At the same time, the data of the unit under test is buffered in the FIFO5 buffer and the amplitude data is output synchronously with the background estimate. The OS detection unit includes: The OS horizontal window detection unit is used to sort the data of the horizontal reference unit of the cross window; it includes a shift register, a comparator OM4, and an adder 2; the shift register is used to input data from data column Q. Y The intermediate data extracted from the data column Q Y For data column Q R The data is obtained by multiplying it by the threshold coefficient T; the left and right reference cell data extracted from the shift register and the data from the data column Q are input through the comparator OM4. R Extract the intermediate data of the unit to be tested, compare it, and then output it to the second adder for addition tree summation; The OS vertical window detection unit is used to sort the reference unit data in the vertical direction of the cross-shaped window; it includes: comparator OM5, adder 3, and buffer FIFO8; the comparator OM5 is used to input from data column Q. Y The extracted upper and lower reference unit data, and the data from the data column Q R Extract the intermediate test unit data, compare it, and output it to the adder three for addition tree summation. Then output the summation result to the buffer fifo8 for caching. Buffer FIFO7 and counter 2, wherein buffer FIFO7 is used for input from the data column Q R The intermediate data of the unit under test, namely amplitude data, is extracted and output to comparators OM4~OM5, counter 2 and selector MUX4 after being buffered. Counter 2 is used to count the address of the amplitude data to generate row and column position information synchronized with the amplitude data timing. The system consists of adder 4, comparator OM6, and selector MUX4. Adder 4 adds the summation result of adder 2 to the summation result cached in buffer FIFO8, and outputs the result to comparator OM6 for comparison with sorting factor K. When the comparison result is valid, selector MUX4 selects and outputs the amplitude data and its corresponding row and column position information. The processing procedure of the OS detection unit includes: In ordered statistical model, the data column Q R Multiply by the threshold coefficient T to obtain the data column Q Y At the same time, the data column Q R The intermediate test unit data is stored in the buffer area FIFO7 and the corresponding test unit data, i.e. amplitude data, is output when the detection result is valid. Along the vertical direction, from data column Q Y Extract the upper and lower reference unit data and form a new 2M data. The number of extracted reference units is 2D. If 2D < 2M, fill the remaining positions with a fixed large number C. The extracted 2M data points are compared with the data of the unit under test. The comparison results are summed using an addition tree to obtain the vertical comparison sum col_comp_sum, which is then stored in the buffer fifo8. Along the horizontal direction, from data column Q Y Intermediate data is extracted and input into a shift register, which has a length of 2M+2L+1. Data is input from the first shift register and shifted backward in each clock cycle. Extract left and right reference cell data from the shift register and form new 2M data, wherein the number of extracted reference cells is 2D. If 2D < 2M, fill the remaining positions with a fixed large number C. The extracted data is compared with the data of the unit to be tested, and the comparison results are summed by an addition tree to obtain the comparison and row_comp_sum in the horizontal direction. Read the vertical comparison sum col_comp_sum stored in the buffer fifo8, and add it to the horizontal comparison sum row_comp_sum to obtain the total comparison sum comp_sum of the reference cells on the top, bottom, left and right sides of the cross window; The comparison sum comp_sum is compared with the ranking factor K. If the comparison sum comp_sum is greater than or equal to the ranking factor K, the unit under test is determined to be the target and its amplitude data and corresponding row and column position information are output. If the comparison sum comp_sum is less than the ranking factor K, no detection result is output.

2. A high-speed configurable two-dimensional CFAR detection method based on FPGA, employing the high-speed configurable two-dimensional CFAR detector based on FPGA as described in claim 1, characterized in that, include: Configure system parameters via a host computer; In the CFAR detection mode of the mean-based algorithm, the system first reads the input range-Doppler two-dimensional power matrix data from DDR, and generates a data column Q through a chained FIFO queue. R This enables the conversion of one-dimensional serial data into a two-dimensional data structure that outputs in parallel. Based on data column Q R Background estimation is performed to obtain the background estimation value corresponding to the unit under test. Target decision is made based on the background estimation value, and the amplitude data of the detected target and its corresponding row and column position information are output. In the CFAR (Category-Ordered Statistical Algorithm) mode, the system reads the input range-Doppler two-dimensional power matrix data from DDR (Data Retrieval Memory) and generates a data column Q through a chained FIFO queue. R ; Based on data column Q R Simultaneously, background estimation and target decision processing are completed, thereby outputting the detection results to DDR.

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