Digital time converter, control method and electronic device

Abstract

The application provides a digital time converter, a control method and an electronic device, the digital time converter comprising: N delay modules, each delay module being cascaded in turn; each of the first N-1 delay modules comprising two groups of delay units, the last delay module comprising at least one group of delay units, the delay time of each delay unit being consistent; wherein the first group of delay units of the first delay module keeps a gating state; the first group of delay units of each intermediate delay module is connected in one-to-one correspondence with the second group of delay units of the previous delay module and is controlled by a corresponding bit digital control signal; the second group of delay units of each intermediate delay module is connected in one-to-one correspondence with the first group of delay units of the next delay module and is controlled by a corresponding bit digital control signal. The application only improves from the circuit and control technology level, thereby improving the linearity of the link, without additional algorithm and resource overhead, effectively reducing the design cost of the high linearity digital time converter, and having high practical value.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and in particular to a digital time converter, control method, and electronic device. Background Technology

[0002] A Digital-to-Time Converter (DTC) is an electronic circuit module whose core function is to precisely adjust the time delay or phase shift of the output signal relative to the input signal based on the input digital control signal. In current circuit design, digital modules such as all-digital phase-locked loops (ADPLLs), clock and data recovery circuits (CDRs), and direct phase modulators in polarity or out-of-phase transmitters are widely used, and DTCs play a crucial role in these applications. The phase error of a DTC directly affects the spectral characteristics and error vector amplitude of the transmitter, and also significantly impacts the phase error of the all-digital PLL and clock and data recovery circuits. Therefore, achieving high-resolution and high-linearity DTCs has always been a research hotspot both domestically and internationally. For example, the nonlinearity of DTCs is one of the main factors causing fractional spurious emissions in all-digital PLLs; therefore, a high-linearity DTC can effectively suppress such spurious emissions and improve the overall system performance. However, high-linearity DTCs typically require additional auxiliary circuits or algorithms for calibration, often significantly increasing the design complexity of the circuit and system.

[0003] Patent CN109358485A discloses a digital time converter control method, device, electronic device, and storage medium. It converts binary control information into thermometer-coded information, selects capacitor units in a capacitor array, and encodes them using array, row, and column information segments to form three-dimensional coordinate values ​​to obtain capacitor unit information. This achieves the superposition of total capacitance information, thereby reducing nonlinearity. However, this method increases system complexity and requires additional computing power and resources to control DTC capacitor selection. Patent CN112054800A discloses a digital time conversion method, digital time converter, and digital phase-locked loop. It employs Dynamic Element Matching (DEM) technology to randomly select delay units in the thermometer-coded structure of the digital time converter. The delay units are selected based on historical control word conditions to achieve different delays for the same delay control word, disrupting the fixed pattern of the original control data flow and thus reducing nonlinearity. This method not only requires significant additional computing resources but also uses several delay units with different delays, making it impossible to simultaneously achieve a wide DTC delay range and high-precision delay resolution. Patent CN118074679A discloses a method to enhance the linearity of a multi-level digital control delay line (DTC) through redundancy and randomization. For binary code-controlled DTC circuits, it utilizes the characteristic that the maximum value of the INL (Input Linear Limit) occurs at the intermediate code position of each delay stage by introducing an offset stage and an additional stage. Random codes are generated based on the required time delays of each DTC stage. This reduces the probability of the control code falling at the intermediate code position and keeps the landing point as far away from the intermediate code position as possible, thereby improving INL and fractional spurious emissions. However, this technique also requires additional resources to generate random codes, increasing the system complexity.

[0004] Therefore, the need for a novel digital time converter link control technology to improve the linearity of the delay link of the digital time converter and enhance the overall performance of the circuit without increasing the design complexity of the circuit or system algorithm has become one of the urgent problems to be solved by those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a digital time converter, control method and electronic device to solve the problems of complexity, requirement of additional algorithms and resource overhead in the prior art for high linearity digital time converter systems.

[0007] To achieve the above and other related objectives, the present invention provides a digital time converter, the digital time converter comprising:

[0008] There are N delay modules, with their inputs and outputs cascaded sequentially. The input of the first-stage delay module receives a clock signal. The first N-1 stages of delay modules each include two sets of delay units, and the last stage of delay modules includes at least one set of delay units. The delay time of each delay unit is the same. N is a natural number greater than or equal to 2.

[0009] In this module, the first set of delay units of the first-stage delay module remains in the selected state; the first set of delay units of the intermediate-stage delay module is connected to the second set of delay units of the preceding-stage delay module in a one-to-one correspondence and is controlled by the corresponding bit digital control signal; the second set of delay units of the intermediate-stage delay module is connected to the first set of delay units of the following-stage delay module in a one-to-one correspondence and is controlled by the corresponding bit digital control signal.

[0010] Optionally, each group of delay units contains the same number of delay units.

[0011] Optionally, the last-stage delay module also includes a second set of delay units; the second set of delay units of the last-stage delay module remains disconnected.

[0012] Alternatively, each delay module includes a ramp generator, a threshold comparator, and multiple delay units;

[0013] The ramp generator receives the input signal and converts the transition edge of the input signal into a corresponding ramp signal;

[0014] Each delay unit is connected to the output terminal of the ramp generator and is selected or disconnected based on the control of the corresponding bit digital control signal;

[0015] The threshold comparator is connected to the output of each delay unit and is used to compare the delayed voltage with the threshold voltage and output the comparison result.

[0016] Alternatively, the ramp generator can be implemented using an inverter structure.

[0017] Alternatively, the ramp generator includes a first PMOS transistor, a first NMOS transistor, a first resistor, and a second resistor;

[0018] The source of the first PMOS transistor is connected to the power supply voltage; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor via the first resistor and the second resistor in sequence; the source of the first NMOS transistor is grounded; the gates of the first PMOS transistor and the first NMOS transistor are connected together as the input terminal of the ramp generator, and the connection node of the first resistor and the second resistor serves as the output terminal of the ramp generator.

[0019] Alternatively, each delay unit is a switched capacitor, and the capacitance value of each switched capacitor is equal.

[0020] Alternatively, each delay unit includes an inverter and a capacitor;

[0021] The input terminal of the inverter receives the corresponding bit digital control signal, and the output terminal is connected to the lower plate of the capacitor;

[0022] The upper plate of the capacitor is connected to the output terminal of the ramp generator.

[0023] Alternatively, the threshold comparator is implemented using an inverter, which flips the threshold as the threshold voltage.

[0024] Alternatively, the threshold comparator includes a second PMOS transistor and a second NMOS transistor;

[0025] The source of the second PMOS transistor is connected to the power supply voltage; the gates of the second PMOS transistor and the second NMOS transistor are connected together as the input terminal of the threshold comparator; the drains of the second PMOS transistor and the second NMOS transistor are connected together as the output terminal of the threshold comparator; the source of the second NMOS transistor is grounded.

[0026] To achieve the above and other related objectives, the present invention also provides a digital time conversion control method, which is implemented using the aforementioned digital time converter. The digital control signal is a thermometer code, and linearity is improved by mutual compensation of delay units in different levels controlled by the same digital control signal.

[0027] To achieve the above and other related objectives, the present invention also provides an electronic device, which includes at least the above-described digital time converter.

[0028] Optionally, the electronic device is a digital phase-locked loop, a clock and data recovery module, or a direct phase modulator.

[0029] As described above, the digital time converter, control method, and electronic device of the present invention have the following beneficial effects:

[0030] 1. The digital time converter, control method and electronic device of the present invention only improve and optimize from the circuit level and control technology level, without the need for additional algorithms and resource overhead.

[0031] 2. The digital time converter, control method, and electronic device of the present invention, for a digital time converter controlled by a thermometer code, controls half of the capacitors of two adjacent delay modules together, and utilizes the characteristics of the delay unit itself to compensate for its own nonlinearity, thereby optimizing the nonlinearity of the overall digital time conversion link and improving linearity.

[0032] 3. The digital time converter, control method and electronic device of the present invention do not affect the scalability, delay range and delay resolution of the digital time conversion link, and do not require additional circuits or algorithms, effectively reducing the design cost of high linearity digital time converters and having high practical value. Attached Figure Description

[0033] Figure 1 The diagram shown is a structural schematic of the digital time converter of the present invention.

[0034] Figure 2 The diagram shown is a structural schematic of the delay module of the present invention.

[0035] Figure 3 The diagram shown is a structural schematic of the 16-bit digital time converter of the present invention.

[0036] Figure 4 The diagram shown illustrates the working principle of the digital time converter of this invention.

[0037] Figure 5 The diagram shows a schematic of a digital time converter formed by a 16-bit digitally controlled delay circuit.

[0038] Figure 6 The diagram shows a digital time converter formed by cascading two 8-bit digital time delay circuits.

[0039] Figure 7 This diagram shows a comparison of the delay curves for three different architectures of 16-bit digital time converters.

[0040] Figure 8 This diagram shows a comparison of the INL curves (linearity) of three different architectures of 16-bit digital time converters.

[0041] Figure 9 This diagram shows a comparison of the INL curves (linearity) of three different architectures of 128-bit digital time converters.

[0042] Component designation explanation

[0043] 1-Digital time converter; 10-Delay module; 11, 12, 13, 1N, 1N-First to Nth level delay modules; 1a-Ramp generator; 1b-Delay unit; 1c-Threshold comparator; 2-Numerically controlled delay circuit; 3-Digital time converter; 4-Digital time converter. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please see Figures 1-9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] like Figure 1 As shown, the present invention provides a digital time converter 1, which includes:

[0047] There are N delay modules 10, with the input and output terminals of each delay module 10 cascaded in sequence. The input terminal of the first-stage delay module 11 receives the clock signal. The first N-1 stages of delay modules each include two sets of delay units, and the last stage of delay module 1N includes at least one set of delay units. The delay time of each delay unit is consistent (equal or within a preset range). N is a natural number greater than or equal to 2.

[0048] In this module, the first set of delay units of the first-stage delay module 11 remains in the selected state; the first set of delay units of the intermediate-stage delay module is connected to the second set of delay units of the preceding-stage delay module in a one-to-one correspondence and is controlled by the corresponding bit digital control signal DTC Code; the second set of delay units of the intermediate-stage delay module is connected to the first set of delay units of the following-stage delay module in a one-to-one correspondence and is controlled by the corresponding bit digital control signal DTC Code.

[0049] Specifically, to ensure consistency among the delay modules (improving performance consistency and design efficiency), in this embodiment, the structures and parameters of each delay module 10 are identical, including but not limited to the same number of delay units. In this case, the last-stage delay module 1N also includes two sets of delay units, and the second set of delay units in the last-stage delay module 1N remains disconnected. In practical use, the second set of delay units may not be provided in the last-stage delay module 1N, which will not be elaborated upon here.

[0050] like Figure 2 As shown, as an example, each delay module 10 includes a ramp generator 1a, a threshold comparator 1c, and multiple delay units 1b; in this example, each delay module 10 includes 16 delay units, which can be set as needed in actual use, and the number of delay units is not less than 2.

[0051] The ramp generator 1a receives the input signal Input and converts the transition edge of the input signal Input into a corresponding ramp signal. In one example, the ramp generator 1a is implemented using an inverter structure. As an example, the ramp generator 1a includes a first PMOS transistor PM1, a first NMOS transistor NM1, a first resistor R1, and a second resistor R2. The source of the first PMOS transistor PM1 is connected to the power supply voltage VDD, and its drain is connected to the first terminal of the first resistor R1. The source of the first NMOS transistor NM1 is grounded to GND, and its drain is connected to the first terminal of the second resistor R2. The gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 are connected together as the input terminal of the ramp generator 10. The second terminals of the first resistor R1 and the second terminals of the second resistor R2 are connected together as the output terminal of the ramp generator 10. When the input signal Input is high, the first PMOS transistor PM1 is turned off and the first NMOS transistor NM1 is turned on. The output of the ramp generator 1a is discharged through the second resistor R2 and the first NMOS transistor NM1, generating a falling edge with a certain slope. When the input signal Input is low, the first PMOS transistor PM1 is turned on and the first NMOS transistor NM1 is turned off. The output of the ramp generator 1a is pulled up through the first PMOS transistor PM1 and the second resistor R2, generating a rising edge with a certain slope. The slope is mainly determined by the resistance values ​​of the first resistor R1 and the second resistor R2, and can be set as needed. In other examples, it can also be set such that a high level of the input signal Input corresponds to a rising edge of the output, and a low level of the input signal Input corresponds to a falling edge of the output. Any circuit structure that can generate a ramp signal based on the input signal is applicable to this invention and is not limited to this embodiment.

[0052] Each delay unit 1b is connected to the output of the ramp generator 1a and is selected or disconnected based on the corresponding bit digital control signal DTCCode. In one example, each delay unit 1b is a switched capacitor, and the capacitance value of each switched capacitor is equal (denoted as Cu). As an example, each delay unit 1b includes an inverter Inv and a capacitor C. The input of the inverter Inv receives the corresponding bit digital control signal DTC Code, and its output is connected to the lower plate of the capacitor C. The upper plate of the capacitor C is connected to the output of the ramp generator 1a. When the corresponding bit digital control signal DTC Code is 1, the lower plate of the capacitor C is at a low level (GND), and the capacitor C is selected and connected to the output of the ramp generator 1a; when the corresponding bit digital control signal DTC Code is 0, the lower plate of the capacitor C is at a high level (VDD), the capacitor C is not selected, and the electrical connection with the output of the ramp generator 1a is disconnected. In practical applications, any circuit structure that can provide delay based on the corresponding bit digital control signal DTC Code is applicable to this invention, and will not be described in detail here.

[0053] The threshold comparator 1c is connected to the output of each delay unit 1b, and is used to compare the delayed voltage with the threshold voltage and output the comparison result Output. In one example, the threshold comparator 1c is implemented using an inverter, which flips the threshold voltage as the threshold voltage. As an example, the threshold comparator 1c includes a second PMOS transistor PM2 and a second NMOS transistor NM2. The source of the second PMOS transistor PM2 is connected to the power supply voltage VDD; the source of the second NMOS transistor NM2 is grounded to GND; the gates of the second PMOS transistor PM2 and the second NMOS transistor NM2 are connected together as the input of the threshold comparator 1c; the drains of the second PMOS transistor PM2 and the second NMOS transistor NM2 are connected together as the output of the threshold comparator 1c. When the delayed voltage is greater than the conduction threshold of the second NMOS transistor NM2, the second NMOS transistor NM2 is turned on, and the comparison result Output is low; when the delayed voltage is less than the conduction threshold of the second PMOS transistor PM2, the second PMOS transistor PM2 is turned on, and the comparison result Output is high. Inverter-type threshold comparators (ICs) are prone to introducing nonlinearity. Numerous studies suggest that this nonlinearity typically stems from variations in the input ramp slope and fluctuations in the inverter's flip-threshold voltage. This nonlinearity can be optimized using the digital time converter structure and control method of this invention. Of course, other structures that are less prone to introducing nonlinearity can also be used to further improve linearity. Any circuit structure capable of performing the comparison function is applicable to this invention, and will not be elaborated upon here.

[0054] It should be noted that any circuit structure capable of generating a delay signal corresponding to a digital control signal is applicable to the delay module 10 of the present invention, and is not limited to this embodiment.

[0055] like Figure 1 As shown, the delay modules 10 are cascaded sequentially. The input of the first-stage delay module 11 serves as the input of the digital time converter 1. The input of the subsequent delay module 10 is connected to the output of the preceding delay module 10. The output of the last-stage delay module 1N serves as the output of the digital time converter 1. In one example, each group of delay units contains the same number of delay units 1b; for example, each group includes 8 delay units. In practical use, the number of delay units in each group can be adjusted as needed, ensuring a one-to-one correspondence between the interconnected delay units. Further details are omitted here.

[0056] Specifically, such as Figure 3 As shown, with N set to 3, each delay module 10 includes 16 delay units, with 8 delay units forming a group. In this case, the 9-16 bit switched capacitors of the first-stage delay module 11 are connected one-to-one with the 1-8 bit switched capacitors of the second-stage delay module 12, and are controlled simultaneously by the 0-7 bit digital control signal DTC Code<7:0>. Similarly, the 9-16 bit switched capacitors of the second-stage delay module 12 are connected one-to-one with the 1-8 bit switched capacitors of the third-stage delay module 13 (the last stage), and are controlled simultaneously by the 8-15 bit digital control signal DTC Code<15:8>. The 1-8 bit switched capacitors of the first-stage delay module 11 are fixedly connected to a high potential; the 9-16 bit switched capacitors of the third-stage delay module 13 are fixedly connected to a low potential (or no 9-16 bit switched capacitors are set).

[0057] The present invention also provides a digital time conversion control method, which is implemented using the digital time converter 1 of the present invention. The digital control signal DTC Code is a thermometer code, and the linearity is improved by mutual compensation of delay units in different levels controlled by the same digital control signal.

[0058] Specifically, in this invention, if only the front-stage delay units controlled by the same digital control signal are considered (i.e., the first group of delay units in the subsequent delay module 10 is ignored), then the digital control signal DTC Code sequentially controls each delay unit, such as... Figure 4As shown, in this case, the actual delay curve is DTC actual delay 1, and the ideal delay is DTC ideal delay 1. The difference between the actual delay curve and the ideal delay can be used to characterize the nonlinearity of DTC. If only the subsequent delay unit controlled by the same digital control signal is considered (i.e., the second set of delay units of the preceding delay module 10 is ignored), the actual delay curve moves from DTC actual delay 1 to the position of DTC actual delay 2 in the figure. The actual delay curve of the present invention should be formed by superimposing DTC actual delay 1 and DTC actual delay 2, and the Code0 of the actual delay curve of the present invention starts from code8 of DTC actual delay 1. The compensated actual delay is shown as the red curve in the figure. Further, taking a digital time converter with 16 capacitors as an example, from Figure 4 As can be seen, the difference between the actual DTC delay 1 and the actual DTC delay 2 of this invention gradually increases from code 0 to code 8, and gradually decreases from code 8 to code 15, indicating that they can compensate for each other. If the delay change from code 8 to code 16 were linear, the method proposed in this invention could perfectly compensate for it. In reality, the delay change is non-linear, but the method proposed in this invention can still compensate for most of the non-linearity. Therefore, the actual delay after compensation will more closely match the ideal DTC delay 2 of this invention.

[0059] The performance of the digital time converter 1 of the present invention will be described below. For comparison, the following provides... Figure 3 , Figure 5 and Figure 6 The digital time converter shown is an example. Wherein, Figure 3 The digital time converter 1 of the present invention has the capacitance value of each capacitor set to Cu. Figure 5 A 16-bit digital time converter 3 consisting of a numerically controlled delay circuit 2 is provided. Its internal structure is the same as that of the delay module 10 of the present invention, including 16 delay units (each digital control signal corresponds to one delay unit), wherein the capacitance value of each capacitor is set to 2Cu. Figure 6 A digital time converter 4 is provided, formed by cascading two 8-bit digital controlled delay circuits 2. The internal structure of each digital controlled delay circuit 2 is the same as the delay module 10 of this invention, each including eight delay units (one delay unit corresponding to each bit of digital control signal), wherein the value of each capacitor is set to 2Cu. These three architectures of digital time converters have the same delay accuracy and the same delay coverage. The nonlinearity of the above three architectures is modeled as follows: Figure 7 As shown, the blue fitted curve is Figure 5 The actual latency curve of the architecture, the blue dashed line represents... Figure 5 The ideal latency curve for the architecture; the red fitted curve is... Figure 6 The actual latency curve of the architecture, the red dashed line represents... Figure 6The ideal latency curve for the architecture; the green fitted curve is Figure 3 The actual latency curve of the architecture (in this invention), the green dashed line represents... Figure 3 The ideal delay curve of the architecture; as can be seen from the delay, the actual delay generated by the control architecture proposed in this invention is closest to the ideal delay. Figure 8 As shown, the blue fitted curve is Figure 5 The difference curve between the actual latency and the ideal latency of the architecture (Integral Non-Linearity, INL), with the red fitted curve as an example. Figure 6 The curve showing the difference between the actual latency and the ideal latency of the architecture, with the green fitted curve representing this. Figure 3 The difference curve between the actual delay and the ideal delay of the architecture clearly shows that the control architecture proposed in this invention has an advantage in linearity performance, with its INL curve peak being significantly lower than the other two architectures.

[0060] Furthermore, at the circuit level, all three architectures are extended to 128-bit digital control signals. The architecture of this invention is formed by cascading 17 stages of 16-bit switched capacitor delay modules (the first 8 capacitors of the first stage are fixed to a high potential, and the last 8 capacitors of the last stage are fixed to a low potential), with the capacitance value set to Cu. The DTC architecture A consists of 8 stages... Figure 5 The 16-bit digital time converter shown is formed by cascading three stages, with the capacitor value set to 2Cu; the DTC architecture B consists of 8 stages, such as... Figure 6 The digital time converter shown is formed by cascading four circuits, with the capacitor value set to 2Cu. The circuit level of the above three architectures is simulated, as follows: Figure 9 As shown, the control architecture proposed in this invention can significantly reduce the difference between actual and ideal delays and improve overall linearity.

[0061] The present invention also provides an electronic device, which includes at least the digital time converter 1 of the present invention. This electronic device includes, but is not limited to, a digital phase-locked loop, a clock and data recovery module, or a direct phase modulator, which will not be described in detail here.

[0062] In summary, this invention provides a digital time converter, a control method, and an electronic device. The digital time converter includes: N delay modules, with the input and output terminals of each delay module cascaded sequentially. The input terminal of the first-stage delay module receives a clock signal. The first N-1 stages of delay modules each include two sets of delay units, and the last stage delay module includes at least one set of delay units. The delay time of each delay unit is consistent. N is a natural number greater than or equal to 2. The first set of delay units in the first-stage delay module remains in a selected state. The first set of delay units in the intermediate-stage delay module is connected one-to-one with the second set of delay units in the preceding stage delay module and is controlled by the corresponding bit digital control signal. The second set of delay units in the intermediate-stage delay module is connected one-to-one with the first set of delay units in the following stage delay module and is controlled by the corresponding bit digital control signal. The digital time converter, control method, and electronic device of this invention only improve and optimize at the circuit and control technology levels, without requiring additional algorithms or resource overhead. For the digital time converter controlled by thermometer codes, half the capacitors of two adjacent delay modules are controlled together. Utilizing the inherent characteristics of the delay units, they mutually compensate for their own nonlinearities, thereby optimizing the nonlinearity of the overall digital time conversion link. This does not affect the scalability or delay resolution of the digital time conversion link, nor does it require additional circuitry or algorithms, effectively reducing the design cost of high-linearity digital time converters and possessing high practical value. It significantly improves the linearity of the digital time conversion link without sacrificing the overall delay range and accuracy of the digital time converter, further reducing circuit and system design costs. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A digital time converter, characterized in that, The digital time converter includes: There are N delay modules, with their inputs and outputs cascaded sequentially. The input of the first-stage delay module receives a clock signal. The first N-1 stages of delay modules each include two sets of delay units, and the last stage of delay modules includes at least one set of delay units. The delay time of each delay unit is the same. N is a natural number greater than or equal to 2. In this module, the first set of delay units of the first-stage delay module remains in the selected state; the first set of delay units of the intermediate-stage delay module is connected to the second set of delay units of the preceding-stage delay module in a one-to-one correspondence and is controlled by the corresponding bit digital control signal; the second set of delay units of the intermediate-stage delay module is connected to the first set of delay units of the following-stage delay module in a one-to-one correspondence and is controlled by the corresponding bit digital control signal.

2. The digital time converter according to claim 1, characterized in that: Each group of delay units contains the same number of delay units.

3. The digital time converter according to claim 1, characterized in that: The final stage delay module also includes a second set of delay units; the second set of delay units in the final stage delay module remains disconnected.

4. The digital time converter according to any one of claims 1-3, characterized in that: Each delay module includes a ramp generator, a threshold comparator, and multiple delay units; The ramp generator receives the input signal and converts the transition edge of the input signal into a corresponding ramp signal; Each delay unit is connected to the output terminal of the ramp generator and is selected or disconnected based on the control of the corresponding bit digital control signal; The threshold comparator is connected to the output of each delay unit and is used to compare the delayed voltage with the threshold voltage and output the comparison result.

5. The digital time converter according to claim 4, characterized in that: The ramp generator is implemented using an inverter structure.

6. The digital time converter according to claim 5, characterized in that: The ramp generator includes a first PMOS transistor, a first NMOS transistor, a first resistor, and a second resistor; The source of the first PMOS transistor is connected to the power supply voltage; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor via the first resistor and the second resistor in sequence; the source of the first NMOS transistor is grounded; the gates of the first PMOS transistor and the first NMOS transistor are connected together as the input terminal of the ramp generator, and the connection node of the first resistor and the second resistor serves as the output terminal of the ramp generator.

7. The digital time converter according to claim 4, characterized in that: Each delay unit is a switched capacitor, and the capacitance value of each switched capacitor is equal.

8. The digital time converter according to claim 7, characterized in that: Each delay unit includes an inverter and a capacitor; The input terminal of the inverter receives the corresponding bit digital control signal, and the output terminal is connected to the lower plate of the capacitor; The upper plate of the capacitor is connected to the output terminal of the ramp generator.

9. The digital time converter according to claim 4, characterized in that: The threshold comparator is implemented using an inverter, which flips the threshold value to obtain the threshold voltage.

10. The digital time converter according to claim 9, characterized in that: The threshold comparator includes a second PMOS transistor and a second NMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage; the gates of the second PMOS transistor and the second NMOS transistor are connected together as the input terminal of the threshold comparator; the drains of the second PMOS transistor and the second NMOS transistor are connected together as the output terminal of the threshold comparator; the source of the second NMOS transistor is grounded.

11. A digital time conversion control method, characterized in that, The digital time conversion control method is implemented using a digital time converter as described in any one of claims 1-10, wherein the digital control signal is a thermometer code, and linearity is improved by mutual compensation between delay units in different levels controlled by the same digital control signal.

12. An electronic device, characterized in that, The electronic device includes at least one of the following: a digital time converter as described in any one of claims 1-10.

13. The electronic device according to claim 12, characterized in that: The electronic device is a digital phase-locked loop, a clock and data recovery module, or a direct phase modulator.

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