A multi-detector synchronous driving correction processing method

Abstract

The application discloses a kind of multi-probe synchronous drive correction processing methods, utilize the consistency, stability of hardware second pulse signal sent by satellite platform, the interval between adjacent hardware second pulse signal measured by high-frequency clock signal CLK is used as the reference of this FPGA probe drive signal second time correction;Obtain the deviation of this FPGA measurement second time relative to FPGA standard second time by calculation, avoid the dramatic change of frame frequency by the way of being evenly distributed to second time section;Adopt dichotomic calculation method to obtain correction parameter C, realize the compensation of time deviation by compensation counter cnt_div, and then reduce the cumulative synchronization error of probe drive signal;High-frequency clock signal CLK is used to measure the interval between adjacent hardware second pulse signal, to reduce measurement error;Design hardware second pulse reference measurement, the whole process of correction drive signal generation is in the same clock domain CLK, to avoid the risk of introducing new error across clock domain.

Description

Technical Field

[0001] This invention belongs to the field of electronic information technology, and specifically relates to a method for synchronous driving correction of multiple detectors. Background Technology

[0002] In recent years, the size of a single infrared detector array has been limited by material dimensions and is approaching physical limits. Meanwhile, the business needs of remote sensing mapping, disaster reduction, natural resources and other technical fields have placed higher demands on wide-swath and high-resolution infrared images. Multi-detector stitching and synchronous driving technology have become the inevitable choice to break through the limitations of resolution and field of view.

[0003] To achieve efficient and independent control of each detector, an independent detector driver circuit is designed for each detector in the engineering process. The driver circuit is controlled by an FPGA to generate the driving timing. Due to the limitation of board size, the driving of multiple detectors needs to be implemented by multiple boards. This design architecture introduces a new problem: the time deviation caused by the independence of the crystal oscillators of each driver board.

[0004] The FPGA generates a counter based on the local crystal oscillator to control the generation of drive timing. However, due to factors such as manufacturing process and temperature drift, the output frequency of the crystal oscillator has a slight deviation, measured in ppm. This slight deviation accumulates over imaging time, becoming particularly prominent in long-duration imaging tasks. Therefore, effectively reducing the accumulated error of multi-detector synchronous drive has become a key issue in multi-detector drive design. Summary of the Invention

[0005] The purpose of this invention is to utilize the consistency and stability of the hardware second pulse signal transmitted by the satellite platform, and to use software means to correct the counter generated by the local crystal oscillator of the FPGA, thereby effectively reducing the accumulated error of multi-detector synchronous drive, and providing a multi-detector synchronous drive correction processing method.

[0006] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0007] A multi-detector synchronous drive correction processing method includes the following steps:

[0008] Step 1: Determine the calibration design parameters, including: the clock period Tmc (in ns) of the low-frequency clock MC driven by the detector, the upper limit time value Th (in ns) of the calibration deviation threshold, and the lower limit time value Tl (in ns) of the calibration deviation threshold.

[0009] Furthermore, the clock period Tclk (in ns) of the high-frequency clock CLK and the clock period Tmc of the low-frequency clock MC for receiving and measuring the second pulse must satisfy the following relationship: Tmc = n × Tclk, where n is a positive integer;

[0010] Furthermore, the calculation relationship between the CLK clock cycle Tclk and the local clock count threshold Sparam is as follows: Sparam = 1000000000 / Tclk, rounded down;

[0011] Furthermore, the calculation relationship between the upper limit count value THREh and the upper limit time value Th of the start correction deviation threshold is as follows: THREh = Th / Tclk, rounded down;

[0012] Furthermore, the calculation relationship between the lower limit count value THREl for initiating the correction deviation threshold and the lower limit time value Tl for initiating the correction deviation threshold is as follows: THREl = Tl / Tclk, rounded down;

[0013] Furthermore, the calculation relationship between the upper bound parameter Hpram of the binary calculation module and the upper limit time value Th of the start-up correction deviation threshold is as follows: Hpram = 1000000000 / Th, rounded down;

[0014] Step 2: The second pulse receiving and measurement module receives the hardware second pulse signal sent by the satellite platform, and latches the local clock count value Sre at the falling edge of each hardware second pulse. After receiving the second pulse and completing the count value latching, the counter is cleared and a new round of counting measurement begins.

[0015] Step 3: The time compensation calculation module compares the values ​​of Sre, Sparam, THREh, and THREl to calculate the time compensation value. and time compensation direction flag_add;

[0016] Furthermore, in step 3, there are three scenarios: 1) If the local clock count value of the second pulse Sre > the upper limit of the correction deviation threshold THREh, it indicates that the second pulse signal is abnormal at this time. The second pulse abnormality handling mechanism is activated, no correction is performed, and the time compensation value is output. 1) If the local clock count value Sre is less than the lower limit of the correction deviation threshold THREl, it indicates that the local clock is relatively accurate and no correction is needed. Output the time compensation value. 0; 3) The local clock count value Sre is between the upper limit of the start-up correction deviation threshold THREh and the lower limit of the start-up correction deviation threshold THREl (the boundary is inclusive). If the local clock count value Sre ≥ the local clock count threshold Sparam, it means that the local clock is counting faster at this time, and the time compensation value is calculated. Output a negative time compensation flag_add=0; otherwise, it indicates that the local clock is running slowly, and the time compensation value is calculated. =Sparam-Sre, output time compensation direction is positive flag_add=1;

[0017] Step 4: The binary calculation module implements iterative calculation of the correction parameter C using the bisection method. After the bisection iteration ends, C = lower bound L is output. The number of iterations K of the bisection iterative calculation satisfies the following relationship: ;

[0018] Furthermore, the initial input to the binary calculation module has a lower bound L = 1 and an upper bound H = Hpram;

[0019] Furthermore, the calculation process of the binary calculation module is as follows: Take M as the result of shifting the sum of L + H + 1 one bit to the right, and calculate P = M × , where P is the product corresponding to the trial value M of the correction parameter. By comparing P with Sparam, it is determined whether the trial value M of the correction parameter is correct;

[0020] Furthermore, compare and determine the upper bound H and the lower bound L of the iterative input to the binary calculation module. If P ≥ Sparam, the lower bound L remains unchanged and the upper bound H = M - 1; otherwise, the lower bound L = M and the upper bound H remains unchanged;

[0021] Step 5: The counter compensation and driving timing generation module performs a compensation correction operation for one single CLK clock cycle by controlling the counter cnt_div to hold and increment by 2 every time it counts C;

[0022] [[ID=2O]]Furthermore, the compensation correction operation is completed by controlling cnt_div. There are three cases for the control of cnt_div: 1) When the compensation correction is triggered, if the time compensation direction is positive, the count value of cnt_div remains unchanged for one clock cycle; 2) When the compensation correction is triggered, if the time compensation direction is negative, the count value of cnt_div increments by 2 for one clock cycle; 3) When no compensation correction is performed, cnt_div counts cyclically from 0 to n - 1;

[0023] Furthermore, there are two cases for triggering the compensation correction operation: 1) In the case of flag_ctrl = 1, if trigger = 0 and cnt_div < n - 2, the compensation correction is triggered; 2) In the case of flag_ctrl = 0, if cnt_ctrl_add > 0 and trigger = 0 and cnt_div < n - 2, the compensation correction is triggered, and cnt_ctrl_add decrements by 1;

[0024] Furthermore, in the triggering of the compensation correction operation, the generation method of the flag_ctrl signal is as follows: Under the CLK clock, count cnt_add. When the count reaches C - 1, set flag_ctrl = 1 and clear the cnt_add counter. Clear the cnt_add counter at the falling edge of each hardware second pulse, and set flag_ctrl = 0 at other times. The cnt_add counter increments by 1;

[0025] Further, in the triggering of the compensation and correction operation, the trigger signal is generated as follows: when cnt_ctrl ≥ Nframe - Nexposal and cnt_mc = n - 1, set trigger = 1; otherwise, trigger = 0, where Nexposal is the exposure time count value.

[0026] Further, in the generation of the trigger signal, the cnt_ctrl signal is generated as follows: the satellite platform broadcasts the frame period count value Nframe and the start command frame to the FPGA through the serial port. Multiple FPGAs receive the start command frame simultaneously and count cnt_ctrl under the CLK clock. cnt_ctrl increments by 1 when cnt_div = n - 1, and cycles from 0 to Nframe - 1.

[0027] Further, in the triggering of the compensation and correction operation, the cnt_ctrl_add signal is the count to be corrected, and there are four cases for its control: 1) When flag_ctrl = 1, if trigger = 1, no compensation and correction is performed temporarily, and the count to be corrected cnt_ctrl_add increments by 1; 2) When flag_ctrl = 1, if trigger = 0 and n - 1 ≥ cnt_div ≥ n - 2, no compensation and correction is performed temporarily, and the count to be corrected cnt_ctrl_add increments by 1; 3) When flag_ctrl = 0, if cnt_ctrl_add > 0, trigger = 0, and cnt_div < n - 2, compensation and correction is performed, and cnt_ctrl_add decrements by 1; 4) In other cases, cnt_ctrl_add remains unchanged.

[0028] Step 6: The detector low-frequency clock MC is generated by dividing the high-frequency clock CLK of the second pulse reception and measurement by n. For the even division case where n is even, the counter cnt_mc cycles from 0 to n - 1 to generate the clock signal by n division. For the odd division case where n is odd, two complementary signals with a duty cycle of 60% and 40% are generated using different counting combinations of the counter, and the n-divided clock signal with a duty cycle of 50% is synthesized and output through ODDR dual-edge sampling. The trigger signal is the detector drive signal INT, and the other drive signals of the detector are generated according to the trigger signal.

[0029] The second pulse reception and measurement module, the time compensation calculation module, the binary calculation module, and the counter compensation and drive module are connected in sequence and are all generated by the FPGA of the corresponding detector imaging circuit.

[0030] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0031] 1. This invention fully utilizes the consistency and stability of the hardware second pulse signal. It uses a high-frequency clock signal (CLK) to measure the interval between adjacent hardware second pulse signals as a reference for the second-time correction of the FPGA detector drive signal. Then, it compensates for time deviations through a compensation counter. The deviations in this invention mainly consist of the deviation from measuring the interval between adjacent hardware second pulse signals using the high-frequency clock (CLK) and the deviation from the average compensation calculation, totaling less than 4Tclk (in nanoseconds). This reduces the deviation of the crystal oscillator output frequency reflected in the detector drive signal from the microsecond (µs) level to the nanosecond level, effectively reducing the timing deviation caused by clock drift of the FPGA time counters in each imaging circuit. This provides a new technical means for achieving synchronous drive of multiple spaceborne detectors.

[0032] 2. The present invention designs an FPGA software solution that does not require additional hardware to add a synchronization control module or replace it with a more expensive temperature-compensated crystal oscillator. The design is simple and economical.

[0033] 3. This invention has good compatibility, and each detector and imaging circuit can work independently. The design fully considers the expansion required for subsequent increases in the number of detectors, without the need to spend effort redesigning the system architecture. Attached Figure Description

[0034] Figure 1 This is a hardware platform composition diagram applicable to the multi-detector synchronous drive correction processing method of the present invention;

[0035] Figure 2 This is an FPGA design block diagram of the multi-detector synchronous drive correction processing method of the present invention. Detailed Implementation

[0036] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Those skilled in the art should understand that these embodiments are merely used to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0037] like Figure 1 , Figure 2 As shown, this embodiment provides a multi-detector synchronous drive correction processing method. The application scenario of this embodiment is that two FPGAs drive two infrared detectors to work and output video analog signals. The satellite platform outputs hardware second pulse signals to the two FPGAs and sends frame period count values ​​and start commands to the two FPGAs through serial ports. The FPGA selected is the JFM4VSX55RT device of Fudan Microelectronics JFM4V series, and the crystal oscillator selected is Haichuang ZA715CB-100MHz. The drive signals of the selected infrared detectors include low-frequency clock MC and exposure signal INT.

[0038] This embodiment specifically implements the synchronous drive correction process described in this invention through the following process:

[0039] Step 1: Determine the calibration design parameters, including: the clock period Tmc of the low-frequency clock driven by the detector is 100ns, the upper limit time value Th of the start calibration deviation threshold is 50000ns, and the lower limit time value Tl is 1000ns;

[0040] Based on the low-frequency clock MC driven by the detector, the clock period Tmc of the high-frequency clock CLK for second pulse reception and measurement is determined to be 10ns. From n=Tmc / Tclk, n is 10.

[0041] The local clock count threshold Sparam is calculated to be 100000000, the upper limit count value of the start correction deviation threshold THREh is 5000, the lower limit count value of the start correction deviation threshold THREl is 100, and the upper limit parameter Hpram of the binary calculation module is 200000.

[0042] Step 2: The second pulse receiving and measurement module receives the hardware second pulse signal sent by the satellite platform, and latches the count value Sre under the clock CLK at the falling edge of each hardware second pulse; after each second pulse is received and the count value is latched, the counter is cleared and a new round of counting measurement begins.

[0043] Step 3: The time compensation calculation module compares the values ​​of Sre, Sparam, THREh, and THREl to calculate the time compensation value. and time compensation direction flag_add;

[0044] There are three scenarios in step 3: 1) If the local clock count value of the second pulse Sre is greater than the upper limit of the start correction deviation threshold THREh, it indicates that the second pulse signal is abnormal. The second pulse abnormality handling mechanism is activated, no correction is performed, and the time compensation value is output. 1) If the local clock count value Sre is less than the lower limit of the start-up correction deviation threshold THREl, it indicates that the local clock timing is relatively accurate at this time, and no correction is required. Output the time compensation value. 0; 3) The local clock count value Sre is between the upper limit of the start-up correction deviation threshold THREh and the lower limit of the start-up correction deviation threshold THREl (the boundary is inclusive). If the local clock count value Sre is greater than or equal to the local clock count threshold Sparam, it indicates that the local clock is timing faster at this time, and the time compensation value is calculated. =Sre-Sparam, output time compensation direction is negative. flag_add=0, otherwise, it indicates that the local clock is running slowly, and the time compensation value is calculated. =Sparam-Sre, output time compensation direction is positive flag_add=1;

[0045] Step 4: The binary search calculation module implements the binary search method iterative calculation of the correction parameter C. After the binary search method iteration is completed, the output is C=L. The number of iterations for the binary search method iterative calculation is K=20.

[0046] Divide the standard one-second Sparam time into equal time compensation values. Each time segment has a duration C, which is used to indicate when the timing correction module counts to C and performs a correction. The correction time represented by the equal remainder is less than the clock period Tclk of the high-frequency clock for second pulse reception and measurement. Furthermore, the correction processing of the equal remainder may be affected by the measurement error of the high-frequency clock Sre for second pulse reception and measurement, which may lead to incorrect compensation direction. Therefore, this invention does not process the equal remainder.

[0047] The binary search method is simple to implement in hardware, requiring 20 iterations. The steps are as follows: Initially input the binary search module with a lower bound L=1 and an upper bound H=Hpram; take M as the result of L+H+1, right-shifted by 1 bit, and calculate P=M× Compare and determine the upper bound H and lower bound L of the iterative input binary search module. If P≥Sparam, the lower bound L remains unchanged and the upper bound H=M-1; otherwise, the lower bound L=M and the upper bound H remains unchanged, and proceed to the next iteration.

[0048] Step 5: The present invention, through... The compensation is distributed evenly over a time interval of one second. The counter compensation and drive timing generation module can achieve one compensation per single CLK clock cycle by controlling the counter cnt_div to maintain and increment by 2 every count C, thus avoiding drastic changes in frame rate caused by concentrated compensation.

[0049] The counter counts cnt_add under the CLK clock. When it reaches C-1, flag_ctrl is set to 1 and the counter is cleared. The counter is cleared at the falling edge of each hardware second pulse. At other times, flag_ctrl is set to 0 and the counter increments by 1.

[0050] The satellite platform broadcasts the frame period count value Nframe and the start command frame to the FPGA via the serial port. The two FPGAs simultaneously receive the start command frame and count cnt_ctrl under the CLK clock. cnt_ctrl increments by 1 when cnt_div=n-1, and counts cyclically from 0 to Nframe-1.

[0051] When cnt_ctrl ≥ Nframe - Nexposal and cnt_mc = n - 1, set trigger = 1; otherwise, set trigger = 0. Here, Nexposal is the exposure time count value.

[0052] There are two cases for the trigger of compensation correction: 1) When flag_ctrl = 1, if trigger = 0 and cnt_div < n - 2, the compensation correction is triggered; 2) When flag_ctrl = 0, if cnt_ctrl_add > 0, trigger = 0 and cnt_div < n - 2, the compensation correction is triggered, and cnt_ctrl_add is decremented by 1;

[0053] The compensation correction operation is completed by controlling cnt_div. There are three cases for the control of cnt_div: 1) When the compensation correction is triggered, if the time compensation direction is positive, the count value of cnt_div remains unchanged for one clock cycle; 2) When the compensation correction is triggered, if the time compensation direction is negative, the count value of cnt_div is incremented by 2 for one clock cycle; 3) When no compensation correction is performed, cnt_div counts cyclically from 0 to n - 1;

[0054] There are four cases for the control of the count to be corrected, cnt_ctrl_add: 1) When flag_ctrl = 1, if trigger = 1, the compensation correction is not performed temporarily, and the count to be corrected, cnt_ctrl_add, is incremented by 1; 2) When flag_ctrl = 1, if trigger = 0 and n - 1 ≥ cnt_div ≥ n - 2, the compensation correction is not performed temporarily, and the count to be corrected, cnt_ctrl_add, is incremented by 1; 3) When flag_ctrl = 0, if cnt_ctrl_add > 0, trigger = 0 and cnt_div < n - 2, the correction is performed, and cnt_ctrl_add is decremented by 1; 4) In other cases, cnt_ctrl_add remains unchanged;

[0055] Step 6: The detector low-frequency clock MC is generated by the counter cnt_mc counting cyclically from 0 to n - 1 and divided by n in the high-frequency clock CLK clock domain of the second pulse reception and measurement. n is 10, and the MC clock period is 100 ns; the trigger signal is the detector drive signal INT.

[0056] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the present invention.

Claims

1. A method for synchronous driving correction processing of multiple detectors, characterized in that: It includes the following steps: Step 1: Determine the calibration design parameters, including: the low-frequency clock MC clock period Tmc of the detector drive, the upper limit time value Th of the start calibration deviation threshold, and the lower limit time value Tl of the start calibration deviation threshold; the high-frequency clock CLK clock period Tclk for the second pulse reception and measurement, and the low-frequency clock MC clock period Tmc need to satisfy the following relationship: Tmc = n × Tclk, where n is a positive integer; Step 2: The second pulse reception and measurement module receives the hardware second pulse signal sent by the satellite platform, and at the falling edge of each hardware second pulse, latches the local clock count value Sre. After each reception of the hardware second pulse and completion of the count value latching, the counter is cleared and a new round of counting measurement starts; Step 3: The time compensation calculation module compares the local clock count value Sre, the local clock count threshold Sparam, the upper limit count value of the start correction deviation threshold THREh, and the lower limit count value of the start correction deviation threshold THREl to calculate the time compensation value. and time compensation direction flag_add; Step 4: The bisection calculation module implements the bisection method iterative calculation of the correction parameter C. After the bisection method iteration is completed, the output is C = lower bound L. The number of iterations K of the bisection method iterative calculation satisfies the following relationship: The initial input binary search module has a lower bound L=1 and an upper bound H=Hpram; where Hpram is the upper bound parameter of the binary search module. Step 5: The counter compensation and drive timing generation module performs a single CLK clock cycle compensation and calibration operation every C counts by controlling the counter cnt_div to hold and increment by 2; Step 6: The detector low-frequency clock MC is generated by the counter cnt_mc counting in a loop from 0 to n - 1 and performing n-frequency division in the high-frequency clock CLK clock domain of the second pulse reception and measurement.

2. The multi-detector synchronous drive correction processing method according to claim 1, characterized in that: The calculation relationship between the CLK clock period Tclk and the local clock count threshold Sparam is as follows: Sparam = 1000000000 / Tclk, rounded down; The calculation relationship between the upper limit time value Th of the start calibration deviation threshold is as follows: THREh = Th / Tclk, rounded down; The calculation relationship between the lower limit time value Tl of the start calibration deviation threshold is as follows: THREl = Tl / Tclk, rounded down; The calculation relationship between the upper bound parameter Hpram of the binary calculation module and the upper limit time value Th of the start calibration deviation threshold is as follows: Hpram = 1000000000 / Th, rounded down.

3. The multi-detector synchronous drive correction processing method according to claim 1, characterized in that: In step 3, there are three scenarios: 1) If the local clock count value of the second pulse Sre > the upper limit of the start correction deviation threshold THREh, it indicates that the second pulse signal is abnormal at this time. The second pulse abnormality handling mechanism is activated, no correction is performed, and the time compensation value is output. 1) If the local clock count value Sre is less than the lower limit of the correction deviation threshold THREl, it indicates that the local clock is relatively accurate and no correction is needed. Output the time compensation value. 0; 3) The local clock count value Sre is between the upper limit of the start-up correction deviation threshold THREh and the lower limit of the start-up correction deviation threshold THREl, and the boundary is inclusive. If the local clock count value Sre ≥ the local clock count threshold Sparam, it indicates that the local clock is timing faster at this time, and the time compensation value is calculated. Output a negative time compensation flag_add=0; otherwise, it indicates that the local clock is running slowly, and the time compensation value is calculated. The output time compensation direction is positive, flag_add=1.

4. The multi-detector synchronous drive correction processing method according to claim 1, characterized in that: In step 4, the binary search module performs the following calculation: Take M as the result of L+H+1, shift it right by 1 bit, and calculate... , where P is the product corresponding to the trial value M of the correction parameter. The correctness of the trial value M of the correction parameter is determined by comparing P with Sparam. Compare and determine the upper bound H and the lower bound L of the iterative input binary calculation module. If P ≥ Sparam, the lower bound L remains unchanged and the upper bound H = M - 1; otherwise, the lower bound L = M and the upper bound H remains unchanged.

5. The multi-detector synchronous drive correction processing method according to claim 1, characterized in that: In Step 5, the compensation and calibration operation is completed by controlling cnt_div. There are three cases for the control of cnt_div: 1) When triggering the compensation and calibration, if the time compensation direction is positive, keep the count value of cnt_div unchanged for one clock cycle; 2) When triggering the compensation and calibration, if the time compensation direction is negative, the count value of cnt_div increments by 2 for one clock cycle; 3) When not performing the compensation and calibration, cnt_div counts in a loop from 0 to n - 1; There are two cases for triggering the compensation and calibration operation: 1) In the case of flag_ctrl = 1, if trigger = 0 and cnt_div < n - 2, trigger the compensation and calibration; 2) In the case of flag_ctrl = In the triggering of the compensation and correction operation, the flag_ctrl signal is generated as follows: Under the CLK clock, the cnt_add counter is incremented. When the count reaches C - 1, flag_ctrl is set to 1, and the cnt_add counter is cleared. The cnt_add counter is cleared at the falling edge of each hardware second pulse, and flag_ctrl is set to 0 at other times. The cnt_add counter is incremented by 1. In the triggering of the compensation and correction operation, the trigger signal is generated as follows: When cnt_ctrl ≥ Nframe - Nexposal and cnt_mc = n - 1, trigger is set to 1; otherwise, trigger is set to 0, where Nexposal is the exposure time count value. In the generation of the trigger signal, the cnt_ctrl signal is generated as follows: The satellite platform broadcasts the frame period count value Nframe and the start command frame to the FPGA through the serial port. Multiple FPGAs receive the start command frame simultaneously and count cnt_ctrl under the CLK clock. cnt_ctrl is incremented by 1 when cnt_div = n - 1, and counts cyclically from 0 to Nframe - 1. In the triggering of the compensation and correction operation, the cnt_ctrl_add signal is the count to be corrected, and there are four cases for its control: 1) When flag_ctrl = 1, if trigger = 1, the compensation and correction are not performed temporarily, and the count to be corrected cnt_ctrl_add is incremented by 1; 2) When flag_ctrl = 1, if trigger = 0 and n - 1 ≥ cnt_div ≥ n - 2, the compensation and correction are not performed temporarily, and the count to be corrected cnt_ctrl_add is incremented by 1; 3) When flag_ctrl = 0, if cnt_ctrl_add > 0, trigger = 0, and cnt_div < n - 2, the compensation and correction are performed, and cnt_ctrl_add is decremented by 1; 4) In other cases, cnt_ctrl_add remains unchanged.

6. The multi-detector synchronous drive correction processing method according to claim 1, characterized in that: In step 6, for the even - division case where n is even, a counter is directly used to generate an n - division clock signal with a 50% duty cycle; for the odd - division case where n is odd, different counting combinations of the counter are used to generate two complementary signals with duty cycles of 60% and 40%, and an n - division clock signal with a 50% duty cycle is synthesized through ODDR dual - edge sampling. The trigger signal is the detector drive signal INT, and the remaining detector drive signals are generated based on the trigger signal.

7. A multi - detector synchronous drive correction processing method according to claim 1, characterized in that: The second - pulse receiving and measuring module, the time compensation calculation module, the binary calculation module, and the counter compensation and drive module are connected in sequence, and are all generated by the FPGA of the corresponding detector imaging circuit.

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