Industrial IO module and dynamic configuration method thereof based on adaptive identification

Abstract

The application relates to the field of industrial automation, and provides an industrial IO module and a dynamic configuration method thereof based on adaptive identification, which comprises the following steps: S1, multi-dimensional fingerprint construction; S2, cascaded deep detection; S3, topological feature matching; S4, dynamic parameter metering; and S5, table-driven chain configuration. Through the above steps, without relying on a special hardware identification circuit and without increasing additional GPIO pins, only by analyzing the behavior characteristics of the existing functional chips on the communication bus, the specific model of an integrated digital IO module can be automatically identified, and the whole software module chain is dynamically configured through a table-driven mechanism according to the identification result, so that a set of firmware covers the whole series of products.

Description

Technical Field

[0001] This invention relates to the field of industrial automation technology, specifically to an industrial I / O module and its dynamic configuration method based on adaptive recognition. Background Technology

[0002] Industrial automation distributed digital I / O systems are a core component of industrial fieldbus control systems, primarily used to connect field sensors, actuators, and upper-level controllers to acquire and output digital signals. These systems mostly employ a distributed architecture, distributing I / O modules across the industrial field. They communicate with the controller via fieldbuses such as PROFINET and EtherCAT, significantly reducing field cabling and improving system scalability and maintainability. Digital I / O modules can be functionally categorized into digital input modules (DI), digital output modules (DO), DI / DO hybrid modules, and enhanced modules with diagnostics and alarms. They are responsible for acquiring equipment switching status and driving actuators such as valves and relays, serving as key units for field signal acquisition and control output in industrial automation.

[0003] In industrial automation distributed digital I / O systems, existing technologies for I / O module model identification and configuration mainly fall into three categories. The first is a model-specific firmware solution, where dedicated firmware is developed and maintained for different I / O module models, and the corresponding program is burned into the production process according to the model. The second is a hardware-specific pin encoding method, which uses dedicated GPIO pins on the PCB and generates hardware codes using pull-up or pull-down resistors. The firmware reads the pin level combination during power-up to determine the module model. The third is a communication feature code traversal identification method, which relies on a pre-defined chip communication feature library to send feature commands to the bus and determine the chip type based on the chip's returned information, thereby completing hardware identification.

[0004] All three traditional solutions described above have significant drawbacks. The first type, the model-specific independent firmware solution, leads to a rapid increase in the number of firmware versions as product models grow, significantly increasing development and maintenance costs. It also complicates production line management processes, is prone to firmware flashing errors, and cannot achieve compatibility between multiple module models with a single firmware. The third type, the communication feature code traversal identification method, is used to identify unknown chip models but only supports single-chip granularity identification, lacking multi-dimensional feature fusion and module-level topology matching capabilities.

[0005] The second type of hardware-specific identification pin encoding method is the most commonly used and mature technical solution in the existing technology. For example, the invention patent with authorization announcement number CN11404773B, "Distributed Control System IO Module Hardware Address Adaptive Identification Method and System," describes a distributed control system IO module hardware address adaptive identification method and system. The identification method includes the following steps: arranging IO module bases in sequence and cascading them together, inserting two IO modules into each IO module base slot, so that each IO module base corresponds to two IO hardware addresses; automatically sorting the base slot addresses by designing hardware circuits in the IO module bases and cards; and identifying different addresses by address shifting between upper-level and lower-level IO bases. This invention is not affected by network failures or loss of controller-IO communication, and can reliably ensure the correct identification of distributed control system IO module hardware addresses. However, this type of technology is limited by the scarcity of pin resources on the PCB and MCU of industrial I / O modules, with no spare GPIOs available for identification and encoding; the encoding space is also limited, and model expansion requires continuous occupation of hardware pins; it cannot distinguish dynamic configuration differences such as whether modules in the same series have alarm functions; it can only detect static levels, cannot assess the health status of the chip, and is difficult to identify abnormalities such as cold solder joints and damage, which can easily lead to mismatch between software configuration and actual hardware.

[0006] In summary, existing technologies cannot achieve automatic model identification and adaptive configuration of integrated digital I / O modules purely in software without adding dedicated identification hardware or occupying additional GPIO pins. Especially for cascaded DO driver chips, there is a lack of reliable cascade depth detection and link integrity verification methods, and automatic configuration is also impossible after identifying the hardware device. Summary of the Invention

[0007] The purpose of this invention is to provide an industrial I / O module and its dynamic configuration method based on adaptive identification. Without relying on dedicated hardware identification circuits or adding extra GPIO pins, it automatically identifies the specific model of the integrated digital I / O module by analyzing the behavior characteristics of existing functional chips on the communication bus. Based on the identification results, it dynamically configures the entire software module chain through a table-driven mechanism, so as to achieve a single firmware covering the entire product series.

[0008] To achieve the above objectives, the present invention proposes the following technical solution: The first aspect includes an industrial I / O module and its dynamic configuration method based on adaptive recognition, comprising the following steps: S1 Multidimensional Fingerprint Construction: Perform batch reading of multiple registers on the DI acquisition chip to obtain the fingerprint triplet F=(S,C,D) composed of the status register, configuration register, and fault status register. After multiple rounds of consistency verification, determine the existence of the chip and the hardware health status, and count the number of valid DI chips N_DI. S2 Cascade Depth Probing: Performs multiple rounds of incrementally increasing feature code injection into the DO cascade link, accurately measures the cascade depth N_DO based on the overflow inflection point of the shift register, and completes the link integrity verification through echo verification; S3 Topology Feature Matching: Combine (N_DI, N_DO, Alarm) into a topology feature key and match it precisely with the preset topology feature table to determine a unique product ID; S4 dynamic parameter calculation: Dynamically calculate the number of SPI transmission bytes, DMA buffer length, and IO data frame length based on N_DI and N_DO; S5 table-driven chained configuration: Using the product ID as an index, the system queries the overall product configuration table and combines this with dynamically calculated parameters to complete the integrated initialization and logic channel mapping of DI acquisition, DO output, fault detection, protocol stack, and MCU peripherals. Without adding dedicated identification hardware or occupying additional GPIO identification pins, it obtains multi-dimensional topological characteristics of functional chips solely through SPI bus behavior analysis, autonomously identifies IO module models, and achieves fully software-chain adaptive configuration through a combination of table-driven and dynamic parameter calculation.

[0009] Furthermore, the fingerprint triplet determination rule in step S1 is as follows: If F = (0xFF, 0xFF, 0xFF), then there is no chip at that location. If all three registers are not 0xFF and the configuration register is within the default value range, the chip is considered to exist normally. If the register value is 0xFF or the configuration value is abnormal, the chip is determined to be faulty and a hardware fault flag is generated. After multiple rounds of consistent data collection, N_DI was confirmed to have valid values ​​of 0, 2, and 4.

[0010] Furthermore, step S2 employs a combined detection algorithm of multi-round progressive depth measurement and echo verification, specifically including: injecting 1-4 bytes of feature code step by step; when the readback data first shows a non-zero feature code, the cascaded depth is equal to the current round - 1; after the depth is determined, a position code verification code is written, and then a push code is used to push out and compare with the readback data to verify that each chip functions normally; all-zero data latching is performed before and after detection. Safe recovery is achieved through all-zero latching, avoiding malfunctions of industrial actuators.

[0011] Furthermore, in step S3, the topology feature key includes the number of DI chips, the DO cascade depth, and the alarm function flag Alarm; precise table lookup matching is used, and if N_DI or N_DO is odd, a hardware fault is determined, an abnormal interrupt is triggered, and the fault code is recorded.

[0012] Furthermore, step S4 dynamic calculation includes: calculating the number of output refresh bytes B_out = N_DO × K based on the DO depth N_DO, where K is the single-chip bit width coefficient; calculating the number of input acquisition bytes B_in = N_DI × J based on the number of DIs N_DI, where J is the single-chip bit width coefficient; allocating a DMA ring buffer based on the maximum values ​​of B_out and B_in, configuring the DMA transfer count register, and adapting to the current hardware topology.

[0013] Furthermore, step S5, the table-driven chain configuration, includes: loading the number of channels, the number of chips, alarm bytes, and protocol stack data length parameters from the product configuration master table; initializing DI filter parameters, DO output mode, and fault diagnosis strategy; and constructing an IO mapping table that maps the logical channels called by the upper layer to specific physical chips and their corresponding bit offsets in their registers through mapping relationships, thereby realizing hardware and software address translation. During runtime, the business logic only accesses the logical channel number.

[0014] Furthermore, it also includes an abnormal diagnosis mechanism in step S6: if the detection depth is inconsistent with the standard depth in the configuration table, locate the breakpoint chip, restrict the abnormal channel control authority, the system enters safe mode and reports fault alarm information.

[0015] Secondly, the present invention also includes an industrial I / O module, comprising: a microcontroller (MCU) connected to a DI / DO function chip via an SPI bus that has no dedicated GPIO pins for hardware model identification; a DI acquisition circuit containing multiple cascaded DI chips, equipped with a status register, configuration register, and fault status register that can be read in batches; a DO driver circuit containing multiple cascaded shift registers without independent addresses, forming a closed-loop readback detection link; and a non-volatile memory storing a product configuration master table, a topology feature table, and firmware program; the MCU is configured to perform multi-dimensional fingerprint acquisition, cascaded depth detection, topology feature matching, dynamic parameter calculation, and table-driven chain configuration, enabling adaptive operation of the entire series of I / O modules without dedicated identification hardware.

[0016] As can be seen from the above technical solutions, the technical solutions of the present invention have achieved the following beneficial effects: Compared to existing methods such as independent firmware burning, hardware pin encoding identification, and communication feature code traversal query, this technical solution achieves integrated extraction and accurate matching of multi-dimensional topological features, including the depth of cascaded chip links without independent addressing capabilities, chip presence, hardware health status, and alarm functions, without requiring dedicated identification hardware, occupying additional GPIO encoding pins, relying on host computer configuration, or maintaining multiple firmware sets. It utilizes a combined detection algorithm of DI multi-register fingerprint triple detection and DO cascaded link multi-round progressive depth measurement and echo verification. Furthermore, it incorporates table-driven parameter lookup and dynamic... The system calculates SPI byte count, DMA buffer, and logical channel mapping, enabling fully software-chain autonomous adaptive configuration. It also features power-on hardware diagnostics, fault chip location, secure zero-output latching, and fault degradation operation capabilities. This solves the shortcomings of traditional hardware coding in recognizing dynamic functions and chip health, overcomes the limitations of communication traversal methods in adapting to cascaded structures and lacking topology fusion recognition, and completely eliminates the problems of multiple firmware maintenance and production line programming errors. It enables a single firmware set to achieve adaptive operation of a full range of industrial I / O modules, including pure DI, pure DO, hybrid I / O, alarm-equipped, and direction-configurable modules, without hardware modifications.

[0017] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below can be considered part of the inventive subject matter of this disclosure, provided that such concepts do not contradict each other.

[0018] The foregoing and other aspects, embodiments, and features of the teachings of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description

[0019] The accompanying drawings are not drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the invention will now be described by way of example and with reference to the accompanying drawings, wherein: Figure 1 This is a hardware architecture diagram of an industrial I / O module and its dynamic configuration method based on adaptive recognition, according to the present invention.

[0020] Figure 2 This is a flowchart illustrating the workflow of an industrial I / O module and its dynamic configuration method based on adaptive recognition, according to the present invention.

[0021] Figure 3This is a flowchart of a multi-register fingerprint signature detection process for an industrial I / O module and its dynamic configuration method based on adaptive recognition, according to the present invention.

[0022] Figure 4 This is a diagram illustrating the dynamic parameter calculation and I / O address mapping structure of an industrial I / O module and its dynamic configuration method based on adaptive identification, according to the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art to which this invention pertains.

[0024] The terms "first," "second," and similar words used in the specification and claims of this patent application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, unless the context clearly indicates otherwise, the singular forms of "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" encompasses the features, integrals, steps, operations, elements, and / or components listed following "comprising" or "including," and do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0025] like Figure 1 , Figure 2As shown, this invention discloses an adaptive identification and dynamic configuration method for industrial I / O modules based on multi-dimensional topological fingerprinting. Without adding dedicated identification hardware or occupying additional GPIO identification pins, it obtains multi-dimensional topological features of functional chips solely through SPI bus behavior analysis, autonomously completing I / O module model identification. It achieves fully software-chain adaptive configuration through a combination of table-driven and dynamic parameter calculation, including multi-dimensional fingerprint construction, cascade depth probing, topological feature matching, dynamic parameter calculation, and table-driven chain configuration steps. Multi-dimensional fingerprint construction involves performing batch multi-register readings of the DI acquisition chip to obtain fingerprint triples and determine the chip's existence and health status. Cascade depth probing uses an injection-overflow-echo algorithm to inject feature codes level by level and uses echo verification to ensure link integrity, performing full-zero latching for safe recovery before and after probing. Topological feature matching combines the number of DI chips, DO cascade depth, and alarm flags as feature keys for precise table lookup and triggers fault diagnosis for abnormal values. Dynamic parameter calculation automatically determines the number of SPI transmission bytes, DMA buffer length, and I / O based on the number of DI and DO chips. The data frame length and table-driven chain configuration are based on the product configuration master table to complete the initialization of each functional module and establish the mapping relationship between logical channels and physical addresses. At the same time, the present invention also includes an anomaly diagnosis mechanism, which can locate the faulty chip and realize degraded operation. The whole method does not require independent firmware, hardware pin coding, or communication feature code traversal. It can realize the adaptive adaptation of a single firmware to the entire series of hardware topologies. The present invention also discloses a corresponding industrial IO module, which consists of an MCU, a DI acquisition circuit, a DO driver circuit, and a non-volatile memory. It does not set up a dedicated identification GPIO and can autonomously execute all the above identification and configuration processes.

[0026] The following are specific embodiments of the present invention: Example 1:

[0027] After the system is powered on, it will enter a complete initialization process. First, it will perform multi-register fingerprint signature detection on the DI acquisition chip cascade chain. For each possible chip location, it will read the values ​​of the status register, configuration register, and fault status register, construct the corresponding fingerprint triplet, and judge it according to three levels: non-existent, normal existence, and abnormal existence. This acquisition process will be executed continuously for multiple rounds. Only when the results of multiple rounds are consistent will the final judgment result be confirmed, and then the number of normally existing DI chips and the health status of each chip will be obtained. After completing the DI chip probing, the depth measurement of the DO driver chip cascade chain continues. First, the entire cascade chain is cleared to establish a clean and stable initial state. Then, multiple rounds of incremental feature code injection operations are performed. After each round of injection, the data is read back and the overflow inflection point is detected to accurately determine the actual depth of the cascade. After the depth is determined, echo verification is carried out. Position-encoded feature codes are written into the cascade chain, and then pushed out using push codes and data comparison is performed to confirm the integrity and reliability of the link. Before and after all probing operations, a safety recovery operation is performed, writing all-zero data into the cascade chain and latching it to prevent unexpected actions from the output pins. Finally, the accurate number of DO chips and the link integrity indicator are obtained.

[0028] After DI and DO chip detection is completed, auxiliary feature signal detection continues. By reading the GPIO pin level status corresponding to the alarm detection circuit and judging the level stability, it is determined whether the module has an alarm function. At the same time, test commands are written to the interface with DI / DO configurable function and the response is detected to determine whether the module is an enhanced configurable model, thus obtaining the alarm function flag and the enhanced function flag. After all detection is completed, the number of DI chips, DO cascade depth and alarm flag are combined into a topology feature key. A precise lookup and matching is performed in the pre-stored topology feature table. If a successful match is found, the corresponding product series is determined. Combined with the auxiliary detection results, different sub-models are further distinguished, and finally a unique product ID is obtained. If the detected value is not within the legal range, or the actual detection depth is inconsistent with the preset standard depth in the product configuration table, it is determined that a hardware abnormality has occurred. The system automatically enters safe mode, locates the specific chip location of the link interruption, records the fault code in the system log, restricts the system to only open control permissions to the channel of the normal link, and reports a diagnostic alarm code containing specific abnormal information.

[0029] Once the product ID is determined, the system uses that ID as an index to query the product configuration table, retrieving all configuration parameters corresponding to the current model at once. Based on the identified number of DI chips and the DO cascading depth, the system dynamically calculates the number of SPI transmission bytes, DMA buffer length, and IO data frame length. It also calculates the number of bytes required for output refresh based on the DO cascading depth, the number of bytes required for input acquisition based on the number of DI chips, and dynamically allocates the size of the MCU's internal ring buffer based on the maximum value of the acquisition and refresh byte counts. Finally, it configures the DMA controller's transmission count register to match the number of bytes in the current hardware topology. After completing the parameter calculations, the initialization of each functional module is performed sequentially along the software module chain. First, the DI acquisition module is initialized, calculating the total number of channels based on the number of DI bytes and DI chips. The corresponding number of SPI drivers are initialized, and an independent filter instance is created for each channel. Next, the DO output module is initialized, determining the total number of channels based on the number of DO bytes and DO chips. The cascaded SPI driver parameters and channel output modes are configured. Then, the fault detection module is initialized, determining whether to enable the full alarm function and protocol stack reporting mechanism based on the number of alarm bytes. At the same time, the LED indicator module is initialized. Finally, the protocol stack parameter configuration is completed, setting the uplink and downlink data frame lengths, the parameter configuration area size, and the device description string, so that the entire protocol stack automatically adapts to the data format of the current product.

[0030] During initialization, an I / O mapping table is constructed synchronously. This table contains logical channel numbers, physical chip indexes, and bit offsets. Based on the identified product model ID, the corresponding mapping rules are loaded. If a compact topology is identified, logical channels 0 to 7 are mapped to the lower 8 bits of the first DO chip. If an extended topology is identified, logical channels 0 to 7 are mapped to the first DO chip, and logical channels 8 to 15 are mapped to the second DO chip. At runtime, the business logic layer only calls the logical channel numbers, and the underlying driver automatically converts them to physical addresses based on the I / O mapping table for read and write operations. All software modules complete initialization only based on configuration parameters, dynamic calculation results, and mapping relationships, without needing to be aware of specific product model information. After the entire initialization process is completed, the system officially enters the main runtime loop.

[0031] The DI chip multi-register fingerprint signature detection relies on the SPI bus. Multiple DI chips are cascaded and share the same chip select signal. Data is shifted and transmitted sequentially in the cascaded chain. During detection, the chip select signal is first pulled low, and the status register data is read in batches and stored. If a normal chip is present at the corresponding position, the actual status value is returned; otherwise, 0xFF (bus idle state) is returned. Then, the configuration register data is read again. If a normal chip is present, the factory default configuration value will be returned; if no chip is present, 0xFF is also returned. Next, the fault status register data is read in batches. If a normal chip is present, the corresponding fault status code will be returned; if no chip is present, 0xFF is returned. The results of the three reads are combined into a fingerprint triplet and then judged position by position. If all three registers are 0xFF, it is determined that no chip is present. If all three registers are not 0xFF and the configuration register is within the default value range, it is determined that the chip is present normally. If some registers are 0xFF or the configuration value is abnormal, it is determined that the chip is present abnormally. The entire acquisition and judgment process is executed continuously for multiple rounds. After the results of multiple rounds are consistent, the final status is confirmed, and the number of valid DI chips is counted. If an odd number or other abnormal value appears, it is marked as a hardware fault.

[0032] The DO cascade chain multi-round progressive depth measurement and echo verification is designed for cascade shift registers without independent addresses. First, a maximum length of all-zero data is written to the cascade chain and latched. All registers are cleared to eliminate interference from residual power-on data. Then, incrementally increasing feature codes are injected in rounds. After each round of injection, the data is read back and analyzed. The first round injects a single-byte feature code. If the readback is 0xFF, no chip is identified; if it is 0x00, the depth is not less than 1. Subsequent rounds increase the injection length. When a non-zero feature code first appears in the readback data, the cascade depth can be determined based on the current round. If multiple rounds of readback are all zeros, the maximum depth is determined. After the depth is determined, echo verification is performed. A position-encoded feature code of the corresponding length is written to the cascade chain and latched. Then, an all-zero push code is written to push out the encoded data. The readback data is compared with the written data. If they match, all chips in the link are working normally; if they do not match, the corresponding chip is marked as faulty. Regardless of the detection result, a safe recovery operation of all-zero data latching is performed before and after detection to ensure safety in industrial environments.

[0033] Topology feature precise matching is based on a triplet consisting of the number of DI chips, the number of DO chips, and alarm flags. It traverses the topology feature table to perform a completely consistent and precise search. Since the number of valid chips is a discrete value, the overall combination space is small and there is no need for fuzzy matching. The table lookup process is efficient and reliable. If the match is successful, the final product ID is determined by combining the auxiliary detection results. If the detection value is invalid, the hardware is judged to be abnormal, the system enters safe mode and reports an alarm code that can be used for remote diagnosis. Even if the match is successful, the system will still record the health status of the DI chips and the integrity information of the DO links in the diagnostic log. If there are abnormal chips or link breaks, the affected channels will be continuously monitored and alarmed during the operation phase to ensure that abnormal channels will not affect the stable operation of normal channels.

[0034] The table-driven chain-based dynamic configuration and dynamic parameter calculation are combined for execution. Complete configuration parameters are retrieved using a defined product ID as an index. Taking a typical 16-channel DI plus 16-channel DO model without alarms as an example, the system first queries all parameters, including the number of DI bytes, DO bytes, alarm bytes, number of chips, number of parameters, and order number. Then, based on the identification results, the SPI transmission byte count and DMA buffer size are dynamically calculated to reconfigure the MCU peripherals. Simultaneously, the total number of channels is calculated based on the DI byte count, and the corresponding number of DI chip drivers and filtering instances are initialized. The cascade chain driver and output mode parameters are configured based on the DO byte count. Alarm framing in the protocol stack is disabled based on the alarm byte count, but basic hardware fault detection functions are retained. Finally, the uplink and downlink data lengths, parameter area size, and device description information of the protocol stack are set based on the configuration parameters. All software modules operate solely based on configuration parameters, dynamic calculation results, and logical channel mapping relationships, completely decoupled from specific product models. When adding a new product model, only the corresponding record needs to be added to the configuration master table; no modification to the logic code of any functional modules is required, significantly improving the system's scalability and maintainability.

[0035] This embodiment is a basic, conventional implementation with standard fixed parameters and no alarm diagnostic functions. Example 2:

[0036] like Figure 3As shown, the complete initialization process is initiated after the system is powered on. First, multi-register fingerprint signature detection is performed on the DI acquisition chip cascade link. For each possible chip location, the status register, configuration register, and fault status register are read sequentially to generate fingerprint triplet and classify them into no chip, normal operation, and abnormal fault. Multiple rounds of consistency verification are continuously performed during the detection process to ensure stable and reliable chip status determination. Finally, the number of valid DI chips and the health status of each chip are obtained. After the DI chip detection is completed, depth measurement is performed on the DO driver chip cascade link. First, all cascade links are cleared to establish a standard initial state. Then, a multi-round incremental feature code injection method is used to accurately determine the cascade depth by reading back the overflow inflection point of the data. After the depth is confirmed, an echo verification process is performed. A position encoding sequence is written to the link and compared by reading back the push code to complete the integrity verification of the entire link. A safe recovery operation of all-zero data latch is performed before and after the detection to avoid malfunctions in the output channel. Finally, a stable and reliable DO chip cascade depth and link working status are obtained.

[0037] After DI and DO chip detection is completed, auxiliary function detection continues. By reading the level stability of the corresponding pins of the alarm detection circuit, it is determined whether the module has a diagnostic alarm function. At the same time, a test command is sent to the configurable DIO interface and the response signal is detected to determine whether the current hardware supports DI / DO direction programmable function, thereby obtaining the alarm enable flag and the enhanced function flag. The number of DI chips, DO cascade depth, and alarm flag are combined into a topology feature key. An exact match is performed in the topology feature table built into the firmware. If the feature combination is valid and the table lookup is successful, the product series is determined and a unique product ID is output based on the auxiliary detection results. If the number of chips detected is an illegal odd value, or the actual depth is inconsistent with the standard configuration, it is determined that the hardware is abnormal. The system automatically enters a safe operation mode, locates the faulty chip and records the fault code, only opens control permissions for normal channels, and outputs diagnostic alarm information containing the location and type of abnormality.

[0038] Once the product ID is determined, all configuration parameters are read from the product configuration master table using that ID as an index. Based on the identified hardware topology, the number of SPI transmission bytes, DMA buffer length, and data frame length are dynamically calculated. The number of output refresh bytes is calculated based on the DO cascading depth, and the number of input acquisition bytes is calculated based on the number of DI chips. A DMA ring buffer is allocated based on the maximum number of acquisition and refresh bytes, and a transmission counter is configured to adapt to the current hardware structure. After parameter calculation, initialization is completed sequentially along the software module chain. First, the DI acquisition module is initialized, configuring the total number of channels, SPI drive parameters, and channel filtering parameters based on the number of DI bytes and chips. Next, the DO output module is initialized, configuring the output mode, latch timing, and channel attributes based on the number of DO bytes and cascading depth. Then, the fault diagnosis module is initialized, selecting whether to enable alarm framing and upload mechanisms based on the number of alarm bytes, and simultaneously configuring the indicator light driver. Finally, the protocol stack data length, parameter area size, and device description information are configured, ensuring the entire software stack automatically adapts to the current hardware model.

[0039] like Figure 4 As shown, during initialization, a mapping table between logical channels and physical hardware is established synchronously. This table contains logical channel numbers, physical chip numbers, and bit offset information. Based on the identified hardware type, corresponding mapping rules are loaded. For extended topologies, logical channels are sequentially mapped to the corresponding positions of multi-level cascaded chips. For enhanced topologies, dynamic mapping and binding of DI / DO hybrid channels are completed according to configurable rules. During system runtime, upper-layer services only need to call the logical channel number; the underlying driver automatically completes address translation and physical read / write, achieving complete decoupling between the service layer and the hardware layer. All software modules start up solely based on configuration parameters, dynamic calculation results, and mapping relationships, without relying on any fixed model information. After initialization, the system enters a stable operating loop.

[0040] The multi-register fingerprint detection of DI chips is implemented based on batch reading of the SPI bus. The multi-level DI chips adopt a cascaded structure and share the chip select signal. The status register is read in sequence to obtain input sampling information, the configuration register is read to obtain the working mode, and the fault register is read to obtain the self-diagnostic results. The three sets of data are combined into a fingerprint triplet. If all three sets are 0xFF, it is determined that there is no chip. If all three sets are valid and meet the default range, it is determined to be working normally. If some are valid or the values ​​are abnormal, it is determined to be a faulty chip. After multiple rounds of verification, the number of valid chips is counted. If an illegal number is found, a hardware fault is marked and an exception handling process is entered.

[0041] The DO cascade depth detection uses an injection-overflow-echo complete algorithm. First, the link is cleared to establish a clean state. Then, the feature code length is increased round by round. The cascade depth is determined by the round in which a valid feature code first appears in the readback data. After the depth is determined, a position-specific verification code is written and read back for comparison to ensure that the shift function of each chip stage is normal. The detection process maintains a security mechanism. Regardless of success or abnormality, the output is cleared to zero to meet industrial field safety standards.

[0042] Topology feature matching employs a triplet-based precise table lookup method. Since the number of DIs, DO depth, and alarm flags are all finite discrete values, the lookup process is fast and reliable. Successful matching results in model identification; unsuccessful matching initiates fault handling. Even with successful matching, the system continuously records chip health status and link integrity, and during operation, it continuously marks and alarms abnormal channels to ensure system reliability.

[0043] The table-driven dynamic configuration and dynamic parameter calculation work together. Taking a 32-channel pure DI with alarm model as an example, the complete configuration, such as the number of DI bytes, alarm bytes, number of chips, and protocol parameters, is obtained by looking up the table. The SPI and DMA related parameters are dynamically calculated and the peripheral reconfiguration is completed. The filtering and acquisition logic is initialized according to the number of DI channels, the alarm diagnosis and upload mechanism is enabled, and the protocol stack data length and device description information are configured. The whole process does not require code modification, dedicated identification hardware, or multiple firmware sets. It can achieve adaptive support for the entire series of hardware, including pure DI, alarm, and enhanced configurable models. Adding a new model only requires expanding the configuration table, which has strong scalability and maintainability.

[0044] Compared with Embodiment 1, this embodiment adopts a hybrid enhanced architecture instead of a standard fixed structure in terms of hardware topology. Functionally, it adds hardware alarm, fault diagnosis and dynamic mapping mechanisms. In terms of data processing, it can dynamically calculate the number of SPI communication bytes, dynamically allocate DMA buffers and adaptively adjust the data frame length. In terms of operating mode, it has a safety mechanism of automatic fault degradation and automatic exception latching. Overall, it is an enhanced implementation method with alarms, scalability and high reliability.

[0045] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. An industrial I / O module and its dynamic configuration method based on adaptive recognition, characterized in that, Includes the following steps: S1. Multidimensional fingerprint construction: Perform batch reading of multiple registers on the DI acquisition chip to obtain the fingerprint triplet F=(S,C,D) composed of status register, configuration register, and fault status register. After multiple rounds of consistency verification, determine the existence of the chip and the hardware health status, and count the number of valid DI chips N_DI. S2, Cascade Depth Probing: Perform multiple rounds of incrementally increasing feature code injection into the DO cascade link, accurately measure the cascade depth N_DO based on the overflow inflection point of the shift register, and complete the link integrity verification through echo verification; S3. Topology Feature Matching: Combine (N_DI, N_DO, Alarm) into a topology feature key and match it precisely with the preset topology feature table to determine a unique product ID; S4. Dynamic parameter calculation: Dynamically calculate the number of SPI transmission bytes, DMA buffer length, and IO data frame length based on N_DI and N_DO; S5, Table-driven chained configuration: The product configuration master table is queried using the product ID as the index. Combined with dynamically calculated parameters, the integrated initialization and logical channel mapping of DI acquisition, DO output, fault detection, protocol stack and MCU peripherals are completed.

2. The dynamic configuration method based on adaptive identification of industrial I / O modules according to claim 1, characterized in that, The fingerprint triplet determination rule in step S1 is as follows: If F = (0xFF, 0xFF, 0xFF), then there is no chip at that location. If all three registers are not 0xFF and the configuration register is within the default value range, the chip is considered to exist normally. If the register value is 0xFF or the configuration value is abnormal, the chip is determined to be faulty and a hardware fault flag is generated. After multiple rounds of consistent data collection, N_DI was confirmed to have valid values ​​of 0, 2, and 4.

3. The dynamic configuration method based on adaptive identification of industrial I / O modules according to claim 1, characterized in that, Step S2 employs a combined detection algorithm of multi-round progressive depth measurement and echo verification, specifically including: injecting 1 to 4 bytes of feature code step by step; when the readback data first shows a non-zero feature code, the cascade depth is equal to the current round - 1; after the depth is determined, a position code verification code is written, and then the push code is used to push out and compare with the readback data to verify that each chip is functioning normally; all-zero data latching is performed before and after detection.

4. The dynamic configuration method based on adaptive identification of industrial I / O modules according to claim 1, characterized in that, In step S3, the topology feature key includes the number of DI chips, the DO cascade depth, and the alarm function flag Alarm. Precise table lookup matching is used. If N_DI or N_DO is odd, a hardware fault is determined, an abnormal interrupt is triggered, and the fault code is recorded.

5. The dynamic configuration method based on adaptive identification of industrial I / O modules according to claim 1, characterized in that, Step S4 dynamic calculation includes: calculating the number of output refresh bytes B_out = N_DO × K based on the DO depth N_DO, where K is the single-chip bit width coefficient; calculating the number of input acquisition bytes B_in = N_DI × J based on the number of DIs N_DI, where J is the single-chip bit width coefficient; allocating a DMA ring buffer based on the maximum values ​​of B_out and B_in, configuring the DMA transfer count register, and adapting to the current hardware topology.

6. The dynamic configuration method based on adaptive identification of industrial I / O modules according to claim 1, characterized in that, Step S5, the table-driven chain configuration, includes: loading the number of channels, the number of chips, alarm bytes, and protocol stack data length parameters from the product configuration master table; initializing DI filter parameters, DO output mode, and fault diagnosis strategy; and constructing an IO mapping table that maps the logical channels called by the upper layer to specific physical chips and their corresponding bit offsets in their registers through mapping relationships, thereby realizing hardware and software address translation. During runtime, the business logic only accesses the logical channel number.

7. The dynamic configuration method based on adaptive identification of industrial I / O modules according to claim 1, characterized in that, It also includes step S6, an anomaly diagnosis mechanism: if the detection depth is inconsistent with the standard depth in the configuration table, locate the breakpoint chip, restrict the control permissions of the abnormal channel, the system enters safe mode and reports fault alarm information.

8. An industrial I / O module, characterized in that, The method for implementing the dynamic configuration method based on adaptive identification of industrial I / O modules as described in any one of claims 1 to 7 includes: a microcontroller (MCU) connected to a DI / DO function chip via a single SPI bus without any dedicated GPIO pins for hardware model identification; a DI acquisition circuit comprising multiple cascaded DI chips, having a status register, configuration register, and fault status register that can be read in batches; a DO driver circuit comprising multiple cascaded shift registers without independent addresses, forming a closed-loop readback detection link; and a non-volatile memory storing a product configuration master table, a topology feature table, and firmware; wherein the MCU is configured to perform multi-dimensional fingerprint acquisition, cascaded depth detection, topology feature matching, dynamic parameter calculation, and table-driven chain configuration, enabling adaptive operation of the entire series of I / O modules without dedicated identification hardware.

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