LDO compensation circuit, PCB board and linear voltage regulator

Abstract

This invention discloses an LDO compensation circuit, PCB board, and linear regulator, including an error amplification unit, a current limiting protection unit, a clamping protection unit, a buffer unit, a dynamic compensation unit, and a power output unit. The error amplification unit continuously compares the reference voltage with the feedback voltage and adjusts the conduction state of the power output transistor with the help of the dynamic compensation unit and the buffer unit, ultimately achieving stable output voltage. When the load current changes, the dynamic compensation unit automatically adjusts the zero-point position, thereby optimizing loop stability at different operating points. If an output short circuit occurs, the current limiting protection unit will respond quickly and turn off the power transistor to avoid damage. If the drive voltage is too high due to loop abnormalities, the clamping protection unit will limit it to a safe value range. The introduction of multiple protection mechanisms improves the reliability and robustness of the circuit when facing abnormal output conditions, making it more suitable for applications with high performance and reliability requirements.

Description

Technical Field

[0001] This invention relates to the field of linear regulator technology, and in particular to an LDO compensation circuit, a PCB board, and a linear regulator. Background Technology

[0002] As a component of linear regulators, LDO circuits are widely used in the power supply modules of various chips and electronic systems to provide stable and low-noise output voltages. However, traditional LDO circuits have significant drawbacks under high-voltage environments, making them unsuitable for high-performance and high-reliability applications. Traditional LDO circuits mainly consist of an error amplifier, buffer, power MOSFET, feedback resistor, and fixed compensation network. They lack a high-voltage / low-voltage separation structure, allowing high-voltage inputs to directly interfere with low-voltage analog modules, resulting in severe signal crosstalk and poor overall voltage withstand performance. Furthermore, their compensation method is relatively fixed, employing fixed zero-point or pole compensation, which cannot adjust to dynamic load changes. When the load changes, the loop is prone to instability, such as oscillation or slowed response.

[0003] It is evident that existing technologies still need improvement and enhancement. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide an LDO compensation circuit that introduces a dynamic compensation mechanism. When the load current changes, the dynamic compensation unit automatically adjusts the zero point position to optimize loop stability at different operating points.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: An LDO compensation circuit includes an error amplification unit, a current limiting protection unit, a clamping protection unit, a buffer unit, a dynamic compensation unit, and a power output unit. The non-inverting input of the error amplification unit is connected to an external reference voltage. The inverting input of the error amplification unit is connected to the output of the power output unit. The output of the error amplification unit is connected to the input of the dynamic compensation unit. The output of the dynamic compensation unit is connected to the input of the buffer unit. The output of the buffer unit is connected to the input of the power output unit via the clamping protection unit. The input of the current limiting protection unit is connected to the output of the power output unit. The output of the current limiting protection unit is connected to the buffer unit and the power output unit. The input terminal of the power output unit is connected; the error amplification unit is used to differentially amplify the voltage difference between the output sampling voltage of the power output unit and the reference voltage, and send the amplified error voltage signal to the dynamic compensation unit; the dynamic compensation unit is used to dynamically compensate the error voltage signal and provide the buffer unit with a dynamically compensated dynamic zero-point signal; the clamping protection unit is used to detect the drive voltage signal output by the buffer unit, and if the drive voltage signal is abnormal, it sends a safety drive voltage signal to the power output unit; the current limiting protection unit is used to detect whether the output current of the power output unit is abnormal, and if it is abnormal, it shuts down the buffer unit and the power output unit.

[0006] In the LDO compensation circuit, the error amplification unit includes a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, a fourth field-effect transistor (FET) M4, a fifth field-effect transistor (FET) M5, a sixth field-effect transistor (FET) M6, a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, and a tenth field-effect transistor (FET) M10. The drain and gate of the first field-effect transistor (FET) M1 and the gate of the second field-effect transistor (FET) M2 are connected to an external bias node. The sources of the first field-effect transistor (FET) M1 and the second field-effect transistor (FET) M2 are grounded. The drain of the second field-effect transistor (FET) M2 is connected to the sources of the third field-effect transistor (FET) M3 and the fourth field-effect transistor (FET) M4. The gate of the third field-effect transistor (FET) M3 is connected to the output terminal of the power output unit. The gate of the fourth field-effect transistor (FET) M4 is connected to an external reference voltage terminal. The third field-effect transistor (FET) M3... The drain of the fifth field-effect transistor M5 is connected to the source of the fourth field-effect transistor M4, and the drain of the sixth field-effect transistor M6 is connected to the source of the sixth field-effect transistor M6. The gates of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 are connected to an external low-voltage power supply. The drain of the fifth field-effect transistor M5 is connected to the drain and gate of the seventh field-effect transistor M7 and the gate of the eighth field-effect transistor M8. The drain of the sixth field-effect transistor M6 is connected to the drain of the eighth field-effect transistor M8 and the input terminal of the dynamic compensation unit. The source of the seventh field-effect transistor M7 is connected to the drain and gate of the ninth field-effect transistor M9 and the gate of the tenth field-effect transistor M10. The source of the eighth field-effect transistor M8 is connected to the drain of the tenth field-effect transistor M10. The sources of the ninth field-effect transistor M9 and the tenth field-effect transistor M10 are connected to an external power supply.

[0007] In the LDO compensation circuit, the buffer unit includes a 27th field-effect transistor M27 and a fourth resistor R4; the dynamic compensation unit includes a 24th field-effect transistor M24, a 25th field-effect transistor M25, a 26th field-effect transistor M26, a 28th field-effect transistor M28, a 29th field-effect transistor M29, a 30th field-effect transistor M30, and a third resistor R3; the sources of the 24th and 25th field-effect transistors M24 and M25 are connected to an external power supply terminal; the gates of the 24th and 25th field-effect transistors M24 and M25, and their drains are connected to the drain of the 29th field-effect transistor M29; the gate of the 29th field-effect transistor M29 is connected to an external low-voltage power supply terminal; the source of the 29th field-effect transistor M29 is connected to the drain of the 30th field-effect transistor M30; and the 30th field-effect transistor M30... The source of the 0th field-effect transistor M30 is grounded. The gate of the 30th field-effect transistor M30 is connected to the current limiting protection unit and the power output unit. The drain of the 24th field-effect transistor M24 is connected to the source of the 27th field-effect transistor M27, the gate of the 26th field-effect transistor M26, and the input terminal of the power output unit. The gate of the 27th field-effect transistor M27 is connected to one end of the third resistor R3 and the drain of the 6th field-effect transistor M6. The drain of the 27th field-effect transistor M27 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is grounded. The other end of the third resistor R3 is connected to the gate of the 28th field-effect transistor M28. The drain and source of the 28th field-effect transistor M28 are connected to the drain of the 26th field-effect transistor M26. The source of the 26th field-effect transistor M26 is connected to the external power supply terminal.

[0008] In the LDO compensation circuit, the current limiting protection unit includes a current comparator and a trigger. The input terminal of the current comparator is connected to the output terminal of the power output unit, the output terminal of the current comparator is connected to the input terminal of the trigger, and the output terminal of the trigger is connected to the gate of the 27th field-effect transistor M27 and the input terminal of the power output unit.

[0009] In the LDO compensation circuit, the current comparator includes an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, a fourteenth field-effect transistor M14, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, a seventeenth field-effect transistor M17, and an eighteenth field-effect transistor M18; the triggering unit includes a twenty-second field-effect transistor M22, a twenty-third field-effect transistor M23, a first capacitor C1, and a second capacitor C2; the eleventh field-effect transistor M11, the twelfth field-effect transistor M12, the twenty-third field-effect transistor M23, the twenty-second field-effect transistor M24, the twenty-third field-effect transistor M25, the twenty-fourth field-effect transistor M16, the twenty-seventh field-effect transistor M17, the twenty-third field-effect transistor M18, the twenty-second field-effect transistor M23, the twenty-third field-effect transistor M24, the twenty-fourth field-effect transistor M15, the fifteenth field-effect transistor M16, the sixteenth field-effect transistor M17, the twenty-seventh field-effect transistor M18, the twenty-third field-effect transistor M23, the twenty-fourth field-effect transistor M24, the twenty-third field-effect transistor M25, the twenty-fourth field-effect transistor M16, the twenty-seventh field-effect transistor M17, the twenty-seventh field-effect transistor M18, the twenty-third field-effect transistor M17, the twenty-seventh field-effect transistor M18, the twenty-third field-effect transistor M18, the twenty-fourth field-effect transistor M14, the fifteenth field-effect transistor M15, the sixteenth The sources of field-effect transistors M22 and M23 are connected to an external power supply. The gate and drain of the eleventh field-effect transistor M11 and the gate of the twelfth field-effect transistor M12 are connected to the source of the thirteenth field-effect transistor M13. The drain of the twelfth field-effect transistor M12 is connected to the source of the fourteenth field-effect transistor M14. The gate and drain of the thirteenth field-effect transistor M13 and the gate of the fourteenth field-effect transistor M14 are connected to the drain of the fifteenth field-effect transistor M15. The drain of the fourteenth field-effect transistor M14... The drain of the sixteenth field-effect transistor M16, the gate of the twenty-second field-effect transistor M22, the gate of the twenty-third field-effect transistor M23, one end of the first capacitor C1, and one end of the second capacitor C2 are connected. The drain of the twenty-second field-effect transistor M22 is connected to the other end of the first capacitor C1 and the gate of the twenty-seventh field-effect transistor M27. The drain of the twenty-third field-effect transistor M23 is connected to the other end of the second capacitor C2 and the input terminal of the power output unit. The fifteenth field-effect transistor M15 and the... The gate of the sixteenth field-effect transistor M16 is connected to an external low-voltage power supply. The source of the fifteenth field-effect transistor M15 is connected to the drain of the seventeenth field-effect transistor M17. The gate of the seventeenth field-effect transistor M17 is connected to an external bias node. The source of the seventeenth field-effect transistor M17 is grounded. The source of the sixteenth field-effect transistor M16 is connected to the drain of the eighteenth field-effect transistor M18. The gate of the eighteenth field-effect transistor M18 is connected to the gate of the thirtieth field-effect transistor M30. The source of the eighteenth field-effect transistor M18 is grounded.

[0010] In the LDO compensation circuit, the clamping protection unit includes a nineteenth field-effect transistor M19, a twentieth field-effect transistor M20, a twenty-first field-effect transistor M21, a first resistor R1, a second resistor R2, and a Zener diode Z1. The gate of the nineteenth field-effect transistor M19 is connected to an external bias node, the source of the nineteenth field-effect transistor M19 is grounded, the drain of the nineteenth field-effect transistor M19 is connected to the source of the twentieth field-effect transistor M20, and the gate of the twentieth field-effect transistor M20 is connected to an external low-voltage power supply. The drain of the twentieth field-effect transistor M20 is connected to one end of the first resistor R1, the positive terminal of the Zener diode Z1, and the gate of the twentieth field-effect transistor M21. The other end of the first resistor R1 is connected to one end of the second resistor R2. The other end of the second resistor R2, the negative terminal of the Zener diode Z1, and the drain of the twentieth field-effect transistor M21 are connected to an external power supply terminal. The source of the twentieth field-effect transistor M21 is connected to the gate of the twentieth field-effect transistor M27.

[0011] In the LDO compensation circuit, the power output unit includes a 31st field-effect transistor (FET) M31, a 32nd field-effect transistor (FET) M32, a 33rd field-effect transistor (FET) M33, a 34th field-effect transistor (FET) M34, a 35th field-effect transistor (FET) M35, a 36th field-effect transistor (FET) M36, a 37th field-effect transistor (FET) M37, and a sampling section. The sources of the 31st and 32nd FETs are grounded. The gate and drain of the 31st FET M31 and the gate of the 32nd FET M32 are connected to the drain of the 34th FET M34. The drain of the 34th FET M34 is also connected to the gate of the 30th FET M30. The drain of the 32nd FET M32 is connected to the drain of the 33rd FET M33. The gate of the thirteenth field-effect transistor M33 is connected to an external low-voltage power supply. The source of the thirty-third field-effect transistor M33 is connected to the drain and gate of the thirty-fifth field-effect transistor M35 and the gate of the thirty-fourth field-effect transistor M34. The source of the thirty-fourth field-effect transistor M34 is connected to the drain of the thirty-sixth field-effect transistor M36. The source of the thirty-fifth field-effect transistor M35 is connected to the drain of the thirty-seventh field-effect transistor M37 and the sampling section. The sampling node of the sampling section is connected to the gate of the third field-effect transistor M3. The sources of the thirty-sixth field-effect transistor M36 and the thirty-seventh field-effect transistor M37 are connected to an external power supply. The gates of the thirty-sixth field-effect transistor M36 and the thirty-seventh field-effect transistor M37 are connected to the source of the twenty-seventh field-effect transistor M27.

[0012] In the LDO compensation circuit, the sampling section includes a first feedback resistor Rfb1, a second feedback resistor Rfb2, an output capacitor Cout1, and an output resistor Rout1. One end of the first feedback resistor Rfb1 is connected to the drain of the thirty-seventh field-effect transistor M37, and the other end of the first feedback resistor Rfb1 is connected to the gate of the third field-effect transistor M3 and one end of the second feedback resistor Rfb2. The other end of the second feedback resistor Rfb2 is grounded. One end of the output capacitor Cout1 and the output resistor Rout1 are connected to the drain of the thirty-seventh field-effect transistor M37, and the other end of the output capacitor Cout1 and the output resistor Rout1 are grounded.

[0013] This application also provides a PCB board printed with the LDO compensation circuit described above.

[0014] This application also provides a linear regulator, which employs the LDO compensation circuit described above for operation control.

[0015] Beneficial effects: This invention provides an LDO compensation circuit. The error amplification unit continuously compares the reference voltage with the feedback voltage, and, with the help of a dynamic compensation unit and a buffer unit, adjusts the conduction state of the power output transistor to ultimately stabilize the output voltage. When the load current changes, the dynamic compensation unit automatically adjusts the zero-point position, thereby optimizing loop stability at different operating points. In the event of an output short circuit, the current limiting protection unit responds quickly, turning off the power transistor to prevent damage. If the drive voltage is too high due to a loop abnormality, the clamping protection unit limits it to a safe range. Through the coordinated operation of these units, this LDO compensation circuit can operate under higher input voltage conditions and reduce the crosstalk effect of the high-voltage section on the low-voltage analog signal. Its dynamic compensation mechanism enhances the loop's adaptability to different load conditions and improves stability. Simultaneously, the introduction of multiple protection functions improves the circuit's reliability and robustness in the face of abnormal output conditions, making it more suitable for applications with high performance and reliability requirements. Attached Figure Description

[0016] Figure 1 Circuit block diagram of the LDO compensation circuit provided by the present invention Figure 2 The circuit structure diagram of the LDO compensation circuit provided by the present invention is shown.

[0017] Explanation of key component symbols: 1-Error amplification unit, 2-Current limiting protection unit, 3-Clamping protection unit, 4-Buffer unit, 5-Dynamic compensation unit, 6-Power output unit. Detailed Implementation

[0018] This invention provides an LDO compensation circuit, a PCB board, and a linear regulator. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0019] In the description of this invention, it should be understood that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0020] Please see Figures 1 to 2 This invention provides an LDO compensation circuit, including an error amplification unit 1, a dynamic compensation unit 5, a buffer unit 4, a clamping protection unit 3, a current limiting protection unit 2, and a power output unit 6. The error amplification unit 1 receives an external reference voltage and a feedback sampling voltage from the power output unit 6, and amplifies the voltage difference between them to generate an error voltage signal. The input terminal of the dynamic compensation unit 5 is connected to the output terminal of the error amplification unit 1, and receives the error voltage signal, dynamically compensating for the frequency of the power output unit 6 according to its load state to improve the stability of the loop under different load conditions. The input terminal of the buffer unit 4 is connected to the output terminal of the dynamic compensation unit 5 to enhance the driving capability. The output signal of the buffer unit 4 is used to drive the power output unit 6. To ensure a more stable and safer drive of the power output unit 6 by the buffer unit 4, this application also includes a clamping protection unit 3. This clamping protection unit 3 is connected between the output terminal of the buffer unit 4 and the input terminal of the power output unit 6. When the drive voltage signal output by the buffer unit 4 is abnormally high, it clamps the buffer unit 4 within a safe voltage range, thereby preventing damage to the power output unit 6 due to overdrive. Furthermore, to prevent excessive current from being generated at the output terminal due to short circuit or overload, this application also includes a current limiting protection unit 2. The input terminal of this current limiting protection unit 2 is connected to the output terminal of the power output unit 6 to monitor the output current status; its output terminal is connected to the control terminal of the buffer unit 4 and the input terminal of the power output unit 6, respectively. When the output current exceeds a preset safety threshold, the current limiting protection unit 2 can quickly activate, lowering the voltage of the relevant nodes, thereby turning off the buffer unit 4 and the power output unit 6, achieving overcurrent protection. The power output unit 6, as the final power stage of the circuit, receives the drive signal from the buffer unit 4 (via the clamping protection unit 3) at its input terminal, and provides a stable output voltage at its output terminal. A portion of the output voltage is sampled through a feedback network consisting of resistors and sent back to the inverting input of error amplifier unit 1, thus forming a closed-loop voltage negative feedback control system.

[0021] In this embodiment, after the system powers on, the error amplification unit 1 continuously compares the reference voltage with the feedback voltage and adjusts the conduction state of the power output transistor through the dynamic compensation unit 5 and the buffer unit 4, ultimately stabilizing the output voltage. When the load current changes, the dynamic compensation unit 5 automatically adjusts the zero-point position to optimize loop stability at different operating points. If an output short circuit occurs, the current limiting protection unit 2 responds quickly, turning off the power transistor to prevent damage. If the drive voltage is too high due to loop abnormalities, the clamping protection unit 3 limits it to a safe value. Through the cooperation of the above units, this LDO compensation circuit can operate under higher input voltages and reduce the crosstalk effect of the high-voltage section on the low-voltage analog signal. Its dynamic compensation mechanism enhances the loop's adaptability to different load conditions and improves stability. At the same time, the introduction of multiple protection functions also improves the reliability and robustness of the circuit when facing output abnormalities, making it more suitable for application scenarios with high performance and reliability requirements.

[0022] The working principle of this application is as follows: Error amplification unit 1 is responsible for sensing the deviation of the output voltage. Its non-inverting input is connected to an externally provided stable reference voltage, and its inverting input is connected to the output feedback node of power output unit 6, receiving a sampled signal reflecting the magnitude of the output voltage. This unit performs differential comparison and amplification of these two voltage signals to generate an error voltage signal proportional to the magnitude of the error, and outputs it to the subsequent dynamic compensation unit 5. Dynamic compensation unit 5 receives the error voltage signal from error amplification unit 1, which provides frequency compensation for the entire negative feedback loop. Unlike the traditional scheme using fixed zero-pole compensation, the compensation characteristics of this unit can be dynamically adjusted according to the current of the load driven by power output unit 6. Specifically, it contains a voltage-controlled variable impedance element, the control terminal voltage of which is proportional to the current of the power output transistor. When the load current changes, the control voltage changes accordingly, thereby adjusting the resistance value of the variable impedance element, ultimately causing the zero-point frequency generated by the compensation network to move with the load current. This dynamic adjustment ensures the loop maintains ample phase margin across a wide load range, from light to heavy loads, thus improving system stability and reducing oscillations or slow response caused by load step changes. The signal processed by the dynamic compensation unit 5 is sent to the buffer unit 4. The buffer unit 4 primarily enhances drive capability and isolates the preceding and following stages, ensuring sufficient current to drive the large power transistors in the power output unit 6. To make the drive of the power output unit 6 by the buffer unit 4 more stable and safer, this application also includes a clamping protection unit 3. This clamping protection unit 3 is connected between the output of the buffer unit 4 and the input of the power output unit 6. Internally, it typically includes a voltage detection and clamping circuit composed of a resistor divider network and voltage regulators. When the drive voltage signal output by the buffer unit 4 abnormally rises due to transient response or abnormal conditions and exceeds a preset safety threshold, the clamping protection unit 3 will quickly activate, forcibly pulling down the drive voltage applied to the input of the power output unit 6 and limiting it to a safe voltage range. This effectively prevents the power transistor from being damaged by gate overvoltage, improving the circuit's tolerance under abnormal conditions. The current detection input of the current limiting protection unit 2 is connected to the output of the power output unit 6 or a current mirror node to monitor the current flowing through the power transistor in real time. Its output is connected to the control terminal of the buffer unit 4 (such as the output node of the error amplifier) ​​and the input terminal of the power output unit 6, respectively. When the output current exceeds the preset safety threshold, the current limiting protection unit 2 triggers a fast shutdown mechanism, generating a control signal to pull down the input control voltage of the buffer unit 4 and the drive voltage of the power output unit 6, thereby forcing the buffer unit 4 and the power output unit 6 into a shutdown or current limiting state, achieving overcurrent protection for the circuit and load.The input of power output unit 6 receives drive signals from buffer unit 4 (during normal operation) or clamp / current limiting protection unit 2 (in abnormal conditions). Its output provides the final regulated output of the entire LDO circuit and is connected to an external load. The output voltage is sampled by a feedback network composed of high-precision resistors, and the resulting feedback voltage is sent back to the inverting input of error amplifier unit 1, thus forming a complete voltage negative feedback closed-loop control system that stabilizes the output voltage at the target value set by the ratio of the reference voltage and the feedback resistor.

[0023] Specifically, in this embodiment, the error amplification unit 1 includes multiple field-effect transistors (FETs) to implement differential amplification. The sources of the first FET M1 and the second FET M2 are grounded, and their gates are connected to an externally provided bias node IB_LDO. The drain of the first FET M1 is also connected to this bias node, thereby providing a tail current source for the differential input pair. The third FET M3 and the fourth FET M4 constitute a differential input pair. The gate of the fourth FET M4 is connected to an external reference voltage terminal to receive the reference voltage Vref. The gate of the third FET M3 is connected to the feedback sampling node of the power output unit 6 to receive the feedback voltage Vfb. The sources of the third FET M3 and the fourth FET M4 are connected to the drain of the second FET M2. The gates of the fifth FET M5 and the sixth FET M6 are connected to an external low-voltage power supply terminal VDDA, and their sources are connected to the drains of the third FET M3 and the fourth FET M4, respectively, serving as active loads for the differential pair. The seventh field-effect transistor (FET) M7 and the eighth field-effect transistor (FET) M8 form a current mirror load. The drain and gate of the seventh FET M7, and the gate of the eighth FET M8, are connected to the drain of the fifth FET M5. The drain of the eighth FET M8 serves as the output of the error amplification unit 1, connected to the drain of the sixth FET M6 and the input of the dynamic compensation unit 5. The sources of the ninth FET M9 and the tenth FET M10 are connected to the higher external power supply terminal VIN, and their gates are connected. The drain and gate of the ninth FET M9 are connected to the source of the seventh FET M7, and the drain of the tenth FET M10 is connected to the source of the eighth FET M8, thus providing a bias pull-up current for the current mirror. The error amplification unit 1 amplifies the difference between the feedback voltage Vfb and the reference voltage Vref, and outputs the error voltage signal Verr from the drain of the eighth FET M8.

[0024] The dynamic compensation unit 5 is connected between the output of the error amplification unit 1 and the input of the buffer unit 4. This unit includes a 24th field-effect transistor (FET) M24, a 25th field-effect transistor (FET) M25, a 26th field-effect transistor (FET) M26, a 27th field-effect transistor (FET) M27, a 28th field-effect transistor (FET) M28, a 29th field-effect transistor (FET) M29, a 30th field-effect transistor (FET) M30, and a third resistor R3. The sources of the 24th and 25th FETs are connected to an external power supply, and their gates are connected together. The drain of the 25th FET is connected to its gate, and the drain of the 29th FET is connected to its drain. The gate of the 29th FET is connected to an external low-voltage power supply, and its source is connected to the drain of the 30th FET. The source of the 30th FET is grounded, and its gate is connected to a node inside the power output unit 6. The voltage of this node reflects the magnitude of the power output transistor current. The drain of the 24th MOSFET M24 is connected to the source of the 27th MOSFET M27 in buffer unit 4 and the drive input terminal of power output unit 6. The source of the 26th MOSFET M26 is connected to an external power supply terminal, and its gate is also connected to the source of the 27th MOSFET M27. Its drain is connected to the drain and source of the 28th MOSFET M28. The gate of the 28th MOSFET M28 is connected to the output node of error amplifier unit 1 through the third resistor R3. The gate of the 27th MOSFET M27 is directly connected to the output node of error amplifier unit 1, and its drain is grounded through the fourth resistor R4. In this structure, the current flowing through the 27th MOSFET M27 is controlled by the error voltage Verr. The 30th MOSFET M30 acts as a voltage-controlled resistor, and its conduction state is controlled by its gate voltage, which is related to the power transistor current. Therefore, the network consisting of the twenty-eighth field-effect transistor M28, the twenty-sixth field-effect transistor M26, the third resistor R3, and the controlled thirtieth field-effect transistor M30 can generate a zero that moves dynamically with the change of the power transistor current, thereby dynamically compensating the loop and helping to improve the phase margin of the loop under different load conditions.

[0025] The specific working principle is as follows: The main structure of this unit is a phase-shifting network composed of a voltage-controlled resistor and a transconductance amplifier. The 25th MOSFET M25 and the 24th MOSFET M24 form a current mirror. The drain-gate of the 25th MOSFET M25 is shorted, and together with the 29th MOSFET M29, they provide bias for the current mirror. The 29th MOSFET M29 operates in the saturation region, and its gate is connected to a fixed low-voltage power supply, forming a common-source amplifier together with the 30th MOSFET M30. The gate voltage (V_ctrl) of the 30th MOSFET M30 is not fixed, but originates from a current mirror node inside the power output unit 6. This node voltage is proportional to the current flowing through the power output transistor (i.e., the load current I_load). Therefore, the 30th MOSFET M30 can be considered a voltage-controlled resistor (VCR) whose on-resistance is controlled by the load current. When I_load increases, V_ctrl rises, the overdrive voltage of the 30th MOSFET M30 increases, and its on-resistance R_ds30 decreases; conversely, when I_load decreases, R_ds30 increases. The error voltage Verr output by error amplifier unit 1 directly acts on the gate of the 27th MOSFET M27, controlling its drain current I_d27. Simultaneously, Verr is coupled to the gate of the 28th MOSFET M28 through the third resistor R3. In this configuration, the 28th MOSFET M28 mainly operates in the deep linear region or at the edge of the saturation region. Its equivalent channel resistance is modulated by Verr, but its more important role is to form a feedback path with the 26th MOSFET M26. The gate of the 26th MOSFET M26 is connected to the drain of the 24th MOSFET M24 (i.e., node V_drive, which is also the input of the buffer stage), and its drain is connected to the source and drain of the 28th MOSFET M28. The function of the entire dynamic compensation network is to introduce a controlled impedance network between the output node (Verr node) of the error amplifier and the drive node (V_drive node) of the buffer stage. The transfer function of this network contains a zero, the frequency f_z of which is determined by the time constants of the resistors and capacitors in the network. Specifically, the transconductance (g_m28) of the 28th MOSFET M28, the third resistor R3, and the on-resistance (R_ds30) of the 30th MOSFET M30 together form an RC network that generates the zero. Here, R_ds30 is a variable that varies with the load current.

[0026] The dynamic compensation process is as follows: When the load current I_load is small: the V_ctrl voltage from power output unit 6 is low, the conduction of the 30th MOSFET M30 is weak, and R_ds30 is large. This results in a low zero-frequency f_z determined by R3, g_m28, and R_ds30. This lower zero helps to offset a low-frequency pole inherent in the loop (usually related to the power transistor gate), thereby expanding the loop bandwidth and improving the phase margin under light load conditions, preventing an excessively slow response.

[0027] When the load current I_load increases: the V_ctrl voltage rises, the 30th MOSFET M30 conducts more strongly, and R_ds30 decreases. This causes the zero-point frequency f_z to automatically shift to a higher frequency. As the load increases, the dominant pole frequency introduced by the power output stage usually decreases. If a fixed low-frequency zero is maintained, it may lead to insufficient phase margin. In this case, the upward shift of the zero-point frequency f_z can effectively track and compensate for the change of the dominant pole, continuing to offset the phase lag it causes, thereby maintaining loop stability and suppressing oscillations even under heavy load conditions.

[0028] Meanwhile, the twenty-fourth MOSFET M24, acting as a source follower, transmits the current mirror bias current to the V_drive node, providing charging and discharging current for the gate capacitor of the power output stage. Its transconductance also has a certain influence on the main pole of the loop. The introduction of the twenty-sixth MOSFET M26 increases local feedback, which helps to improve the linearity and driving capability of this stage of the circuit.

[0029] The dynamic compensation unit 5 detects the load current and adjusts the equivalent resistance of the 30th MOSFET M30 in real time, thereby enabling the zero-point frequency of the compensation network to dynamically change with the load conditions. This design allows the LDO loop to obtain relatively optimized frequency response characteristics over a wide load range. Compared with the traditional fixed compensation method, it can significantly improve the stability margin of the system across the entire load range without sacrificing transient response speed.

[0030] Buffer unit 4 mainly includes the 27th MOSFET M27 and the 4th resistor R4, as described above. The gate of the 27th MOSFET M27 receives the voltage signal from the error amplification and dynamic compensation node, its source voltage is output as one of the drive signals, and its drain current generates a voltage drop across the 4th resistor R4. This unit mainly serves to isolate and enhance the drive capability.

[0031] Clamping protection unit 3 includes a nineteenth field-effect transistor (FET) M19, a twentieth field-effect transistor (FET) M20, a twenty-first field-effect transistor (FET) M21, a first resistor R1, a second resistor R2, and a Zener diode Z1. The source of the nineteenth FET M19 is grounded, its gate is connected to an external bias voltage, and its drain is connected to the source of the twentieth FET M20. The gate of the twentieth FET M20 is connected to an external low-voltage power supply, and its drain is connected to the external power supply through a series connection of the first resistor R1 and the second resistor R2. The anode of the Zener diode Z1 is connected to the drain of the twentieth FET M20, and its cathode is connected to the external power supply. The gate of the twenty-first FET M21 is connected at the node between the drain of the twentieth FET M20 and the anode of the Zener diode Z1, its source is connected to the gate of the twenty-seventh FET M27 in buffer unit 4, and its drain is connected to the external power supply. When the drive voltage output by buffer unit 4 rises abnormally due to loop anomaly, it may cause the gate voltage of the 27th MOSFET M27 to be abnormally pulled up. At this time, if the voltage exceeds a certain value, causing the drain node voltage of the 20th MOSFET M20 to exceed the sum of its turn-on voltage and the breakdown voltage of the Zener diode Z1, the 21st MOSFET M21 will be turned on, thereby clamping the gate voltage of the 27th MOSFET M27 to a safe level determined by the resistor voltage divider, the Zener diode, and the threshold voltage of the 21st MOSFET M21, preventing the power output unit 6 from being damaged due to excessive drive voltage.

[0032] The current limiting protection unit 2 includes a current comparison section and a trigger section. The current comparison section, composed of eleventh field-effect transistors M11 to eighteenth field-effect transistors M18, compares the output current with a preset threshold. Eleventh field-effect transistor M11 and twelfth field-effect transistor M12 form a current mirror, with their sources connected to an external power supply. The gate and drain of eleventh field-effect transistor M11 are connected to the gate of twelfth field-effect transistor M12, and this node is also connected to the source of thirteenth field-effect transistor M13. The drain of twelfth field-effect transistor M12 is connected to the source of fourteenth field-effect transistor M14. The gates of thirteenth and fourteenth field-effect transistors M13 and M14 are connected and together connected to the drain of fifteenth field-effect transistor M15. The drain of thirteenth field-effect transistor M13 is also connected to this point. The drain of fourteenth field-effect transistor M14 is connected to the drain of sixteenth field-effect transistor M16 and serves as the output node of the current comparison section. The gates of the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 are connected to the external low-voltage power supply. The source of the fifteenth field-effect transistor M15 is grounded through the seventeenth field-effect transistor M17, and the gate of the seventeenth field-effect transistor M17 is connected to the external bias voltage. The source of the sixteenth field-effect transistor M16 is grounded through the eighteenth field-effect transistor M18, and the gate of the eighteenth field-effect transistor M18 is connected to the node in power output unit 6 that reflects the power transistor current. Therefore, the current flowing through the fifteenth field-effect transistor M15 is a reference current Iref set by the bias voltage and the size of the seventeenth field-effect transistor M17, while the current Isense flowing through the sixteenth field-effect transistor M16 is a scaled-down mirror of the power output transistor current. When the output current is normal and Isense is less than Iref, the output node of the current comparator is high. When the output current is too large, causing Isense to exceed Iref, the current capability of the sixteenth field-effect transistor M16 exceeds that of the fourteenth field-effect transistor M14, causing the output node of the current comparator to be pulled low. The trigger section includes a 22nd field-effect transistor (FET) M22, a 23rd field-effect transistor (FET) M23, a first capacitor C1, and a second capacitor C2. The sources of FETs M22 and M23 are connected to an external power supply. When the output node of the current comparator is high, FETs M22 and M23 are turned on, charging the upper plates of capacitors C1 and C2 to a high level. At this time, the drains of FETs M22 and M23 are both in a high-impedance state, which does not affect the normal operation of the circuit. Once the output node of the current comparator is pulled low due to overcurrent, FETs M22 and M23 are quickly turned off. At this time, capacitor C1 discharges through its internal impedance, thereby pulling down the output node voltage of error amplification unit 1 and turning off buffer unit 4; simultaneously, capacitor C2 discharges, pulling down the drive input node voltage of power output unit 6, quickly turning off the power output transistor, and realizing overcurrent shutdown protection.The first capacitor C1 and the second capacitor C2 provide a brief delay.

[0033] The power output unit 6 includes 31 to 37 field-effect transistors M31 through M37 and a sampling section composed of a first feedback resistor Rfb1 and a second feedback resistor Rfb2. The sources of the 36th and 37th field-effect transistors M36 and M37 are connected to an external power supply terminal, and their gates are connected to the source of the 27th field-effect transistor M27 in the buffer unit 4 to receive drive signals. The 37th field-effect transistor M37 serves as the main power output transistor, and its drain outputs a stable voltage Vout. The source of the 35th field-effect transistor M35 is connected to the drain of the 37th field-effect transistor M37, and its gate and drain are shorted. It is connected to the gate of the 34th field-effect transistor M34 and the source of the 33rd field-effect transistor M33, forming part of a common-source common-gate current mirror used to generate a mirror image of the power transistor current. The source of the 34th field-effect transistor M34 is connected to the drain of the 36th field-effect transistor M36, and its drain is connected to the gate and drain of the 31st field-effect transistor M31 and the gate of the 32nd field-effect transistor M32. The sources of the 31st and 32nd field-effect transistors (FETs) are grounded, and together with the 33rd FET, M33, they constitute further processing and biasing of the power transistor's mirrored current. The drain node voltage of the 34th FET, M34, directly reflects the current magnitude of the 37th FET, M37. This node voltage is connected to the gate of the 30th FET, M30, in the dynamic compensation unit 5, and the gate of the 18th FET, M18, in the current limiting protection unit 2, thereby transmitting the load current information to these two units. The sampling section includes a first feedback resistor Rfb1 and a second feedback resistor Rfb2 connected in series between the output Vout and ground. The connection point of the first feedback resistor Rfb1 and the second feedback resistor Rfb2 serves as the sampling node, outputting a feedback voltage Vfb, which is connected to the gate of the third FET, M3, in the error amplification unit 1. The output terminal typically also has an output capacitor Cout1 and a load resistor Rout1 connected in parallel to filter and maintain the transient response.

[0034] The circuit operates as follows: After power-on, the error amplification unit 1 compares the reference voltage Vref with the feedback voltage Vfb and outputs an error voltage Verr. The error voltage Verr controls the dynamic compensation unit 5 and the buffer unit 4, which in turn drive the 36th MOSFET M36 and 37th MOSFET M37 in the power output unit 6 through the clamping protection unit 3, adjusting the output voltage Vout. The output voltage Vout is divided by the first feedback resistor Rfb1 and the second feedback resistor Rfb2 to obtain Vfb. The closed-loop system makes Vfb equal to Vref, thus stabilizing Vout at a preset value. The dynamic compensation unit 5 adjusts the compensation zero point based on the gate voltage of the 30th MOSFET M30, optimizing loop stability. When the load increases, causing the output current to increase, the gate voltage of the 30th MOSFET M30 rises, deepening its conduction and dynamically adjusting the compensation characteristics. If the output current increases sharply due to a short circuit or other reasons, the Isense in the current limiting protection unit 2 exceeds Iref, triggering the shutdown mechanism, rapidly pulling down Verr and the power stage drive voltage to achieve protection. If a loop malfunction causes an abnormal increase in the drive voltage, the 21st field-effect transistor M21 in the clamp protection unit 3 will be turned on to clamp Verr and prevent the power transistor from being overdriven.

[0035] This application also provides a PCB board embodiment. In this embodiment, the LDO compensation circuit described in any of the above embodiments is printed on the circuit trace layer of the PCB board. This circuit achieves electrical connection of various electronic components through copper foil traces, vias, and solder pads on the PCB, forming a complete voltage regulation module.

[0036] This application also provides an embodiment of a linear voltage regulator. This linear voltage regulator operates with the LDO compensation circuit described in any of the above embodiments as its core control and regulation section. The linear voltage regulator typically also includes peripheral auxiliary circuits such as an input filter capacitor, an output filter capacitor, and an enable control circuit. Its input terminal receives an unregulated DC voltage, and its output terminal provides a DC voltage that has been stabilized and adjusted by the LDO compensation circuit.

[0037] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. An LDO compensation circuit, characterized in that, The system includes an error amplification unit, a current limiting protection unit, a clamping protection unit, a buffer unit, a dynamic compensation unit, and a power output unit. The non-inverting input of the error amplification unit is connected to an external reference voltage. The inverting input of the error amplification unit is connected to the output of the power output unit. The output of the error amplification unit is connected to the input of the dynamic compensation unit. The output of the dynamic compensation unit is connected to the input of the buffer unit. The output of the buffer unit is connected to the input of the power output unit via the clamping protection unit. The input of the current limiting protection unit is connected to the output of the power output unit. The output terminal of the current limiting protection unit is connected to the input terminals of the buffer unit and the power output unit; the error amplification unit is used to differentially amplify the voltage difference between the output sampling voltage of the power output unit and the reference voltage, and send the amplified error voltage signal to the dynamic compensation unit; the dynamic compensation unit is used to dynamically compensate the error voltage signal and provide the buffer unit with a dynamically compensated dynamic zero-point signal; the clamping protection unit is used to detect the drive voltage signal output by the buffer unit, and if the drive voltage signal is abnormal, it sends a safety drive voltage signal to the power output unit. The current limiting protection unit is used to detect whether the output current of the power output unit is abnormal. If an abnormality occurs, the buffer unit and the power output unit are turned off.

2. The LDO compensation circuit according to claim 1, characterized in that, The error amplification unit includes a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, a fourth field-effect transistor (FET) M4, a fifth field-effect transistor (FET) M5, a sixth field-effect transistor (FET) M6, a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, and a tenth field-effect transistor (FET) M10. The drain and gate of the first FET M1 and the gate of the second FET M2 are connected to an external bias node. The sources of the first FET M1 and the second FET M2 are grounded. The drain of the second FET M2 is connected to the sources of the third FET M3 and the fourth FET M4. The gate of the third FET M3 is connected to the output terminal of the power output unit. The gate of the fourth FET M4 is connected to an external reference voltage terminal. The drain of the third FET M3 is connected to the source of the fourth FET M4. The source of the fifth field-effect transistor M5 is connected; the drain of the fourth field-effect transistor M4 is connected to the source of the sixth field-effect transistor M6; the gates of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 are connected to an external low-voltage power supply; the drain of the fifth field-effect transistor M5 is connected to the drain and gate of the seventh field-effect transistor M7 and the gate of the eighth field-effect transistor M8; the drain of the sixth field-effect transistor M6 is connected to the drain of the eighth field-effect transistor M8 and the input terminal of the dynamic compensation unit; the source of the seventh field-effect transistor M7 is connected to the drain and gate of the ninth field-effect transistor M9 and the gate of the tenth field-effect transistor M10; the source of the eighth field-effect transistor M8 is connected to the drain of the tenth field-effect transistor M10; and the sources of the ninth field-effect transistor M9 and the tenth field-effect transistor M10 are connected to an external power supply.

3. The LDO compensation circuit according to claim 2, characterized in that, The buffer unit includes a 27th field-effect transistor M27 and a fourth resistor R4; the dynamic compensation unit includes a 24th field-effect transistor M24, a 25th field-effect transistor M25, a 26th field-effect transistor M26, a 28th field-effect transistor M28, a 29th field-effect transistor M29, a 30th field-effect transistor M30, and a third resistor R3; the sources of the 24th and 25th field-effect transistors M24 and M25 are connected to an external power supply terminal; the gates of the 24th and 25th field-effect transistors M24 and M25, and their drains are connected to the drain of the 29th field-effect transistor M29; the gate of the 29th field-effect transistor M29 is connected to an external low-voltage power supply terminal; the source of the 29th field-effect transistor M29 is connected to the drain of the 30th field-effect transistor M30; and the source of the 30th field-effect transistor M30 is grounded. The gate of the thirtieth field-effect transistor M30 is connected to the current limiting protection unit and the power output unit. The drain of the twenty-fourth field-effect transistor M24 is connected to the source of the twenty-seventh field-effect transistor M27, the gate of the twenty-sixth field-effect transistor M26, and the input terminal of the power output unit. The gate of the twenty-seventh field-effect transistor M27 is connected to one end of the third resistor R3 and the drain of the sixth field-effect transistor M6. The drain of the twenty-seventh field-effect transistor M27 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded. The other end of the third resistor R3 is connected to the gate of the twenty-eighth field-effect transistor M28. The drain and source of the twenty-eighth field-effect transistor M28 are connected to the drain of the twenty-sixth field-effect transistor M26. The source of the twenty-sixth field-effect transistor M26 is connected to the external power supply terminal.

4. The LDO compensation circuit according to claim 3, characterized in that, The current limiting protection unit includes a current comparator and a trigger. The input terminal of the current comparator is connected to the output terminal of the power output unit, the output terminal of the current comparator is connected to the input terminal of the trigger, and the output terminal of the trigger is connected to the gate of the 27th field-effect transistor M27 and the input terminal of the power output unit.

5. The LDO compensation circuit according to claim 4, characterized in that, The current comparison section includes an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, a fourteenth field-effect transistor M14, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, a seventeenth field-effect transistor M17, and an eighteenth field-effect transistor M18; the trigger section includes a twenty-second field-effect transistor M22, a twenty-third field-effect transistor M23, a first capacitor C1, and a second capacitor C2; the eleventh field-effect transistor M11, the twelfth field-effect transistor M12, the twenty-second field-effect transistor M22, and the... The source of the 23rd field-effect transistor M23 is connected to an external power supply terminal. The gate and drain of the 11th field-effect transistor M11 and the gate of the 12th field-effect transistor M12 are connected to the source of the 13th field-effect transistor M13. The drain of the 12th field-effect transistor M12 is connected to the source of the 14th field-effect transistor M14. The gate and drain of the 13th field-effect transistor M13 and the gate of the 14th field-effect transistor M14 are connected to the drain of the 15th field-effect transistor M15. The drain of the 14th field-effect transistor M14 is connected to the source of the 15th field-effect transistor M15. The drain of the sixth field-effect transistor M16, the gate of the twenty-second field-effect transistor M22, the gate of the twenty-third field-effect transistor M23, one end of the first capacitor C1, and one end of the second capacitor C2 are connected. The drain of the twenty-second field-effect transistor M22 is connected to the other end of the first capacitor C1 and the gate of the twenty-seventh field-effect transistor M27. The drain of the twenty-third field-effect transistor M23 is connected to the other end of the second capacitor C2 and the input terminal of the power output unit. The fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M27 are connected to the gate of the second field-effect transistor M27. The gate of field-effect transistor M16 is connected to an external low-voltage power supply. The source of the fifteenth field-effect transistor M15 is connected to the drain of the seventeenth field-effect transistor M17. The gate of the seventeenth field-effect transistor M17 is connected to an external bias node. The source of the seventeenth field-effect transistor M17 is grounded. The source of the sixteenth field-effect transistor M16 is connected to the drain of the eighteenth field-effect transistor M18. The gate of the eighteenth field-effect transistor M18 is connected to the gate of the thirtieth field-effect transistor M30. The source of the eighteenth field-effect transistor M18 is grounded.

6. The LDO compensation circuit according to claim 5, characterized in that, The clamping protection unit includes a nineteenth field-effect transistor M19, a twentieth field-effect transistor M20, a twenty-first field-effect transistor M21, a first resistor R1, a second resistor R2, and a Zener diode Z1. The gate of the nineteenth field-effect transistor M19 is connected to an external bias node, the source of the nineteenth field-effect transistor M19 is grounded, the drain of the nineteenth field-effect transistor M19 is connected to the source of the twentieth field-effect transistor M20, the gate of the twentieth field-effect transistor M20 is connected to an external low-voltage power supply, the drain of the twentieth field-effect transistor M20 is connected to one end of the first resistor R1, the anode of the Zener diode Z1, and the gate of the twenty-first field-effect transistor M21, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2, the cathode of the Zener diode Z1, and the drain of the twenty-first field-effect transistor M21 are connected to an external power supply, and the source of the twenty-first field-effect transistor M21 is connected to the gate of the twenty-seventh field-effect transistor M27.

7. The LDO compensation circuit according to claim 6, characterized in that, The power output unit includes a 31st field-effect transistor (FET) M31, a 32nd field-effect transistor (FET) M32, a 33rd field-effect transistor (FET) M33, a 34th field-effect transistor (FET) M34, a 35th field-effect transistor (FET) M35, a 36th field-effect transistor (FET) M36, a 37th field-effect transistor (FET) M37, and a sampling section. The sources of the 31st and 32nd FETs are grounded. The gate and drain of the 31st FET M31 and the gate of the 32nd FET M32 are connected to the drain of the 34th FET M34. The drain of the 34th FET M34 is also connected to the gate of the 30th FET M30. The drain of the 32nd FET M32 is connected to the drain of the 33rd FET M33. The 33rd FET... The gate of M33 is connected to an external low-voltage power supply. The source of the thirty-third field-effect transistor M33 is connected to the drain and gate of the thirty-fifth field-effect transistor M35 and the gate of the thirty-fourth field-effect transistor M34. The source of the thirty-fourth field-effect transistor M34 is connected to the drain of the thirty-sixth field-effect transistor M36. The source of the thirty-fifth field-effect transistor M35 is connected to the drain of the thirty-seventh field-effect transistor M37 and the sampling section. The sampling node of the sampling section is connected to the gate of the third field-effect transistor M3. The sources of the thirty-sixth field-effect transistor M36 and the thirty-seventh field-effect transistor M37 are connected to an external power supply. The gates of the thirty-sixth field-effect transistor M36 and the thirty-seventh field-effect transistor M37 are connected to the source of the twenty-seventh field-effect transistor M27.

8. The LDO compensation circuit according to claim 7, characterized in that, The sampling section includes a first feedback resistor Rfb1, a second feedback resistor Rfb2, an output capacitor Cout1, and an output resistor Rout1. One end of the first feedback resistor Rfb1 is connected to the drain of the thirty-seventh field-effect transistor M37, and the other end of the first feedback resistor Rfb1 is connected to the gate of the third field-effect transistor M3 and one end of the second feedback resistor Rfb2. The other end of the second feedback resistor Rfb2 is grounded. One end of the output capacitor Cout1 and the output resistor Rout1 are connected to the drain of the thirty-seventh field-effect transistor M37, and the other end of the output capacitor Cout1 and the output resistor Rout1 are grounded.

9. A PCB board, characterized in that, The PCB board is printed with an LDO compensation circuit as described in any one of claims 1-8.

10. A linear voltage regulator, characterized in that, The linear regulator employs an LDO compensation circuit as described in any one of claims 1-8.

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