A port-clamp circuit and electronic device

Abstract

The application discloses a port clamping circuit of MCU and electronic equipment, the port clamping circuit of MCU comprises a first diode and a second diode; the cathode of the first diode is electrically connected with a first power supply end, the anode of the second diode is electrically connected with a second power supply end, and the anode of the first diode and the cathode of the second diode are electrically connected with an input port of the MCU; the conduction voltage drop of the first diode and the second diode is Vd, the working voltage range of the MCU is 0V~Vcc, the first voltage signal provided by the first power supply end is V1, and the second voltage signal provided by the second power supply end is V2; wherein, V1=Vcc-Vd, and V2=Vd.The technical scheme provided by the application can improve the clamping reliability of the port clamping circuit and the use safety of the MCU, and prolong the service life of the MCU.

Description

Technical Field

[0001] This invention relates to the field of clamping circuit technology, and more particularly to a port clamping circuit and electronic device. Background Technology

[0002] In the field of power electronics, almost all circuits cannot avoid analog signal acquisition, such as voltage and current acquisition. Typically, analog signals such as voltage or current are transmitted to the ADC port of a microcontroller unit (MCU). The analog-to-digital converter module inside the MCU converts the analog signals such as voltage or current into digital signals.

[0003] MCUs typically have a narrow data acquisition range, generally 0V to 3.3V. Therefore, the MCU's external circuitry is usually configured to set the full-scale range to 0V to 3.3V. The system operates normally when the voltage input to the MCU port is within this range. However, if a short circuit or overvoltage occurs in the external circuitry, the signal input to the MCU port will exceed the MCU's safe operating range, causing it to break down. To prevent damage to the MCU caused by signals exceeding its safe operating range, current technology typically incorporates TVS clamping circuits, diode clamping circuits, or RCD clamping circuits to protect the MCU port.

[0004] TVS clamping works by utilizing the nonlinear characteristics of TVS diodes (UI). When the voltage exceeds the TVS's breakdown voltage, the TVS exhibits low resistance, absorbing additional energy and thus suppressing voltage fluctuations. However, the breakdown voltage of TVS diodes has significant dispersion, making it difficult to select a suitable breakdown voltage value for protection. Furthermore, TVS diodes have large temperature drift, so they are generally only used for ESD protection at PCB ports. Their clamping protection for MCU ports offers relatively low stability. Diode clamping and RCD clamping both utilize the unidirectional conductivity of diodes. The difference is that RCDs have an additional RC circuit to absorb shocks, but diodes have a forward voltage drop, typically around 0.7V for fast recovery diodes and around 0.4V for Schottky diodes. This forward voltage drop means that even with added clamping circuitry, the voltage at the MCU port will still be 0.4V to 0.7V higher than the power supply voltage Vcc in the event of a fault. Since the upper limit voltage that the MCU port can withstand is usually 0.3V higher than Vcc, there is still a risk of damaging the MCU. Furthermore, with technological advancements, the integration and precision of MCUs are continuously improving, leading to lower Vcc voltages and a smaller voltage range that MCU ports can withstand. Traditional clamping circuits are finding it increasingly difficult to adapt to these new demands. Therefore, how to clamp the voltage value of MCU ports within a safe range has become a pressing technical problem that needs to be solved. Summary of the Invention

[0005] This invention provides a port clamping circuit and electronic device, which can improve the clamping reliability of the port clamping circuit and the safety of MCU use, and extend the service life of MCU.

[0006] In a first aspect, the present invention provides a port clamping circuit for an MCU, comprising: a first diode and a second diode; The cathode of the first diode is electrically connected to the first power supply terminal, the anode of the second diode is electrically connected to the second power supply terminal, and both the anode of the first diode and the cathode of the second diode are electrically connected to the input port of the MCU. The forward voltage drop of the first diode and the second diode is Vd. The operating voltage range of the MCU is 0V~Vcc. The first voltage signal provided by the first power supply terminal is V1, and the second voltage signal provided by the second power supply terminal is V2. Where V1 = Vcc - Vd, V2 = Vd.

[0007] Optionally, the port clamping circuit may also include: The first power supply circuit includes a first input terminal, a second input terminal, and a first power supply terminal; the first input terminal is electrically connected to the power supply terminal of the MCU, and the second input terminal is electrically connected to the ground terminal of the MCU.

[0008] Optionally, the first power supply circuit includes: a third diode and a first resistor; The anode of the third diode is electrically connected to the first input terminal, one end of the first resistor is electrically connected to the second input terminal, and the cathode of the third diode and the other end of the first resistor are both electrically connected to the first power supply terminal. The forward voltage drop of the third diode is Vd.

[0009] Optionally, the port clamping circuit may also include: a first voltage follower; The input terminal of the first voltage follower is electrically connected to the cathode of the third diode and the other end of the first resistor, and the output terminal of the first voltage follower is electrically connected to the first power supply terminal.

[0010] Optionally, the port clamping circuit may also include: a first capacitor; One end of the first capacitor is electrically connected to the first power supply terminal, and the other end of the first capacitor is electrically connected to the second input terminal.

[0011] Optionally, the port clamping circuit may also include: The second power supply circuit includes a third input terminal, a fourth input terminal, and a second power supply terminal; the third input terminal is electrically connected to the power supply terminal of the MCU, and the fourth input terminal is electrically connected to the ground terminal of the MCU.

[0012] Optionally, the second power supply circuit includes: a fourth diode and a second resistor; The cathode of the fourth diode is electrically connected to the fourth input terminal, one end of the second resistor is electrically connected to the third input terminal, and the anode of the fourth diode and the other end of the second resistor are both electrically connected to the second power supply terminal. The forward voltage drop of the fourth diode is Vd.

[0013] Optionally, the port clamping circuit may also include: a second voltage follower; The input terminal of the second voltage follower is electrically connected to the anode of the fourth diode and the other end of the second resistor, and the output terminal of the second voltage follower is electrically connected to the second power supply terminal.

[0014] Optionally, the port clamping circuit may also include: a second capacitor; One end of the second capacitor is electrically connected to the second power supply terminal, and the other end of the second capacitor is electrically connected to the fourth input terminal.

[0015] In a second aspect, the present invention provides an electronic device, comprising: an MCU and at least one port clamping circuit as described in the first aspect; The MCU includes at least one analog signal acquisition port, and the port clamping circuit is electrically connected to each analog signal acquisition port in a one-to-one correspondence. The technical solution provided by this invention involves setting a port clamping circuit at the port of the MCU. The port clamping circuit includes a first diode and a second diode. The cathode of the first diode is electrically connected to a first power supply terminal, and the anode of the second diode is electrically connected to a second power supply terminal. Both the anode of the first diode and the cathode of the second diode are electrically connected to the input port of the MCU. The forward voltage drop of both the first diode and the second diode is Vd. The operating voltage range of the MCU is 0V~Vcc. The first voltage signal V1 provided by the first power supply terminal is set to Vcc-Vd, and the second voltage signal V2 provided by the second power supply terminal is set to Vd. This ensures that the voltage signal transmitted between the first diode and the second diode can be clamped between 0V and Vcc, meeting the safe voltage range of the MCU, improving the clamping reliability of the port clamping circuit and the safety of the MCU, and extending the service life of the MCU. Attached Figure Description

[0016] Figure 1 A circuit diagram of a port clamping circuit for an MCU provided in an embodiment of the present invention; Figure 2 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention; Figure 3A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention; Figure 4 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention; Figure 5 A circuit diagram of a port clamping circuit for an MCU provided in an embodiment of the present invention; Figure 6 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention; Figure 7 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention; Figure 8 A voltage line graph of an MCU port provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0018] Figure 1 A circuit diagram of a port clamping circuit for an MCU provided in an embodiment of the present invention is shown below. Figure 1 As shown, the port clamping circuit 100 of the MCU includes a first diode D1 and a second diode D2. The cathode of the first diode D1 is electrically connected to the first power supply terminal Vc1, and the anode of the second diode D2 is electrically connected to the second power supply terminal Vc2. Both the anode of the first diode D1 and the cathode of the second diode D2 are electrically connected to the input port of the MCU. The forward voltage drop of both the first diode D1 and the second diode D2 is Vd. The operating voltage range of the MCU is 0V~Vcc. The first voltage signal provided by the first power supply terminal Vc1 is V1, and the second voltage signal provided by the second power supply terminal Vc2 is V2.

[0019] Where V1 = Vcc - Vd, V2 = Vd.

[0020] The first diode D1 and the second diode D2 can be silicon diodes or germanium diodes, etc. When the first diode D1 and the second diode D2 are silicon diodes, the forward voltage drop Vd of the first diode D1 and the second diode D2 is 0.7V. When the first diode D1 and the second diode D2 are germanium diodes, the forward voltage drop Vd of the first diode D1 and the second diode D2 is 0.3V. The specific type of the first diode D1 and the second diode D2 can be set according to actual needs, and no specific limitation is made here.

[0021] Specifically, the operating voltage range of the MCU is 0V~Vcc, meaning that the safe voltage range that the MCU port can withstand is 0V~Vcc. If the voltage value transmitted to the MCU port exceeds 0V~Vcc, it will cause problems such as MCU breakdown and damage. Therefore, a port clamping circuit 100 needs to be set at the MCU port. This is to ensure that the input signal vin, which is originally transmitted directly from the external input terminal VIN to the MCU port Port, is clamped by the port clamping circuit 100, so that the voltage value finally transmitted to the MCU port Port is within the MCU's operating range. This improves the MCU's safety and extends its service life.

[0022] The clamping principle of the port clamping circuit 100 for the input signal vin is as follows: When the input signal vin provided by the external input terminal VIN is <0V, the voltage difference between the second power supply terminal Vc2 and the cathode of the second diode D2 is V2 – vin = Vd – vin > Vd. That is, the voltage difference between the anode and cathode of the second diode D2 is greater than the forward voltage drop Vd of the second diode D2. At this time, the second diode D2 is turned on, and the second voltage signal V2 of the second power supply terminal Vc2 is transmitted to the cathode of the second diode D2 through the second diode D2, causing the voltage of the cathode of the second diode D2 to rise. When the voltage of the cathode of the second diode D2 rises to 0V, V2 – vin = Vd – 0 = Vd, the circuit reaches balance, and the voltage signal of the MCU's port Port is precisely clamped at 0V.

[0023] When the input signal vin provided by the external input terminal VIN is greater than Vcc, the voltage difference between the anode of the first diode D1 and the first power supply terminal Vc1 is vin – V1 = vin – (Vcc – Vd) > Vd. That is, the voltage difference between the anode and cathode of the first diode D1 is greater than the forward voltage drop Vd of the first diode D1. At this time, the first diode D1 is turned on, and the input signal vin is transmitted to the cathode of the first diode D1 through the first diode D1, which reduces the voltage at the anode of the first diode D1. When the voltage at the anode of the first diode D1 drops to Vcc, vin – V1 = Vcc – (Vcc – Vd) = Vd, the circuit reaches balance, and the voltage signal at the MCU port Port is precisely clamped at Vcc.

[0024] When the input signal vin provided by the external input terminal VIN satisfies 0V≤vin≤Vcc, neither the first diode D1 nor the second diode D2 conducts, and the circuit operates normally.

[0025] In summary, by setting the first power signal V1 provided by the first power supply terminal Vc1 in the port clamping circuit 100 to Vcc-Vd and the second power signal V2 provided by the second power supply terminal Vc2 to Vd, and by setting the first diode D1 and the second diode D2 connected in series between the first power supply terminal Vc1 and the second power supply terminal Vc2, the voltage range of the port Port input to the MCU is precisely clamped between 0V and Vcc, which meets the voltage range within which the MCU can operate safely, protects the MCU, and improves the clamping reliability of the port clamping circuit and the safety of the MCU.

[0026] The technical solution provided by this invention provides a port clamping circuit at the port of the MCU. The port clamping circuit includes a first diode and a second diode. The cathode of the first diode is electrically connected to a first power supply terminal, and the anode of the second diode is electrically connected to a second power supply terminal. Both the anode of the first diode and the cathode of the second diode are electrically connected to the input port of the MCU. The forward voltage drop of both the first diode and the second diode is Vd. The operating voltage range of the MCU is 0V~Vcc. The first voltage signal V1 provided by the first power supply terminal is set to Vcc-Vd, and the second voltage signal V2 provided by the second power supply terminal is set to Vd. This ensures that the voltage signal transmitted between the first diode and the second diode can be clamped between 0V and Vcc, meeting the safe voltage range of the MCU, improving the clamping reliability of the port clamping circuit and the safety of the MCU, and extending the service life of the MCU.

[0027] Optional, Figure 2 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention is shown below. Figure 2 As shown, the port clamping circuit 100 also includes a first power supply circuit 10, which includes a first input terminal, a second input terminal, and a first power supply terminal Vc1; the first input terminal is electrically connected to the power supply terminal VCC of the MCU, and the second input terminal is electrically connected to the ground terminal GND of the MCU.

[0028] The power supply voltage provided by the MCU's power supply terminal VCC is Vcc.

[0029] Specifically, by setting the first input terminal of the first power supply circuit 10 to be electrically connected to the power supply terminal VCC of the MCU, and the second input terminal to be electrically connected to the ground terminal GND of the MCU, the first power supply circuit 10 can perform voltage division and other processing on the voltage signal Vcc provided by the power supply terminal VCC to form the first power signal V1 required by the first power supply terminal Vc1. There is no need to set up an additional power supply terminal and ground terminal for the first power supply circuit 10, reducing wiring.

[0030] It should be noted that, based on the fact that the first power supply circuit 10 is electrically connected to the power supply terminal VCC and the ground terminal GND of the MCU, and the first power supply circuit 10 can provide the first power signal V1, the circuit structure of the first power supply circuit 10 can be set according to actual needs. The circuit structure of the first power supply circuit 10 is only described as an example below. The structure of the first power supply circuit 10 is not limited to this, and no specific limitation is made here.

[0031] Optional, continue to refer to Figure 2 The first power supply circuit 10 includes a third diode D3 and a first resistor R1; the anode of the third diode D3 is electrically connected to the first input terminal, one end of the first resistor R1 is electrically connected to the second input terminal, and the cathode of the third diode D3 and the other end of the first resistor R1 are both electrically connected to the first power supply terminal Vc1.

[0032] The forward voltage drop of the third diode D3 is Vd. The resistance value of the first resistor R1 can be set according to actual needs, and is not specifically limited here.

[0033] Specifically, by setting a third diode D3 and a first resistor R1, the anode of the third diode D3 is electrically connected to the power supply terminal VCC, and the cathode of the third diode D3 is electrically connected to the ground terminal GND through the first resistor R1. The first resistor R1 provides bias current to the third diode D3, causing the third diode D3 to conduct. The third diode D3 is forward-biased. Since the third diode D3 has a forward voltage drop Vd, the power signal Vcc from the power supply terminal VCC is transmitted to the ground terminal GND through the third diode D3 and the first resistor R1, forming an electrical path. In this electrical path, the voltage signal at the cathode of the third diode D3 is Vcc-Vd. Thus, by setting the first power supply circuit 10 to include a third diode D3 and a first resistor R1, and ensuring that the forward voltage drop of the third diode D3 is the same as that of the first diode D1 and the second diode D2, the voltage signal output to the first power supply terminal Vc1 is Vcc-Vd, improving the accuracy of the first power signal Vcc-Vd provided by the first power supply terminal Vc1, thereby improving the clamping reliability of the port clamping circuit.

[0034] Optional, Figure 3 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention is shown below. Figure 3 As shown, the port clamping circuit 100 also includes a first voltage follower U1; the input terminal of the first voltage follower U1 is electrically connected to the cathode of the third diode D3 and the other end of the first resistor R1, and the output terminal of the first voltage follower U1 is electrically connected to the first power supply terminal Vc1.

[0035] Specifically, the voltage follower has a voltage amplification factor of 1, and its output voltage completely follows the input voltage, with the output voltage being equal in magnitude and phase to the input voltage. By placing a first voltage follower U1 between the cathode of the third diode D3 and the first power supply terminal Vc1, the first voltage follower U1 features high input impedance, low output impedance, and in-phase input and output. This isolates high-resistance signal sources from low-resistance loads, preventing interference between the preceding and following stages, thus providing signal isolation and improving the anti-interference and voltage regulation capabilities of the first power supply circuit 10.

[0036] Optional, Figure 4 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention is shown below. Figure 4 As shown, the port clamping circuit 100 also includes a first capacitor C1; one end of the first capacitor C1 is electrically connected to the first power supply terminal Vc1, and the other end of the first capacitor C1 is electrically connected to the second input terminal.

[0037] The capacitance value of the first capacitor C1 can be set according to actual needs, and no specific limitation is made here.

[0038] Specifically, by setting a first capacitor C1 between the first power supply terminal Vc1 and the ground terminal GND, the first capacitor C1 can filter out noise, making the first power signal V1 transmitted to the first power supply terminal Vc1 smoother and improving the voltage stability of the first power signal V1.

[0039] Optional, Figure 5 A circuit diagram of a port clamping circuit for an MCU provided in an embodiment of the present invention is shown below. Figure 5 As shown, the port clamping circuit 100 also includes a second power supply circuit 20, which includes a third input terminal, a fourth input terminal, and a second power supply terminal Vc2; the third input terminal is electrically connected to the power supply terminal VCC of the MCU, and the fourth input terminal is electrically connected to the ground terminal GND of the MCU.

[0040] The power supply voltage provided by the MCU's power supply terminal VCC is Vcc.

[0041] Specifically, by setting the third input terminal of the second power supply circuit 20 to be electrically connected to the power supply terminal VCC of the MCU, and the fourth input terminal to be electrically connected to the ground terminal GND of the MCU, the second power supply circuit 20 can perform voltage division and other processing on the voltage signal Vcc provided by the power supply terminal VCC to form the second power signal V2 required by the second power supply terminal Vc2. There is no need to set up an additional power supply terminal and ground terminal for the second power supply circuit 20, reducing wiring.

[0042] It should be noted that, based on the fact that the second power supply circuit 20 is electrically connected to the power supply terminal VCC and the ground terminal GND of the MCU, and the second power supply circuit 20 can provide the second power signal V2, the circuit structure of the second power supply circuit 20 can be set according to actual needs. The circuit structure of the second power supply circuit 20 is only described as an example below. The structure of the second power supply circuit 20 is not limited to this, and no specific limitation is made here.

[0043] Optional, continue to refer to Figure 5 The second power supply circuit 20 includes a fourth diode D4 and a second resistor R2; the cathode of the fourth diode D4 is electrically connected to the fourth input terminal, one end of the second resistor R2 is electrically connected to the third input terminal, and the anode of the fourth diode D4 and the other end of the second resistor R2 are both electrically connected to the second power supply terminal Vc2.

[0044] The forward voltage drop of the fourth diode D4 is Vd. The value of the second resistor R2 can be set according to actual needs and is not specifically limited here.

[0045] Specifically, by setting a fourth diode D4 and a second resistor R2, the cathode of the fourth diode D4 is electrically connected to the ground terminal GND, and the anode of the fourth diode D4 is electrically connected to the power supply terminal VCC through the second resistor R2. The second resistor R2 is a current-limiting resistor used to limit the forward operating current of the fourth diode D4 to prevent overcurrent damage. The fourth diode D4 is forward-biased. Since the fourth diode D4 has a forward voltage drop Vd, the 0V signal from the ground terminal GND is transmitted to the anode of the fourth diode D4 after passing through the fourth diode D4, and the voltage signal at the anode of the fourth diode D4 is Vd. Thus, by setting the second power supply circuit 20 to include the fourth diode D4 and the second resistor R2, and the forward voltage drop of the fourth diode D4 is the same as that of the first diode D1 and the second diode D2, the voltage signal output to the second power supply terminal Vc2 is Vd, which improves the accuracy of the second power supply signal Vd provided by the second power supply terminal Vc2, thereby improving the clamping reliability of the port clamping circuit.

[0046] Optional, Figure 6 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention is shown below. Figure 6As shown, the port clamping circuit 100 also includes a second voltage follower U2; the input terminal of the second voltage follower U2 is electrically connected to the anode of the fourth diode D4 and the other end of the second resistor R2, and the output terminal of the second voltage follower U2 is electrically connected to the second power supply terminal Vc2.

[0047] Specifically, the voltage follower has a voltage amplification factor of 1, and its output voltage completely follows the input voltage, with the output voltage being equal in magnitude and phase to the input voltage. A second voltage follower U2 is placed between the anode of the fourth diode D4 and the second power supply terminal Vc2. This second voltage follower U2 features high input impedance, low output impedance, and in-phase input and output. It effectively isolates high-resistance signal sources from low-resistance loads, preventing interference between the preceding and following stages and thus providing signal isolation. This improves the anti-interference capability and voltage regulation capability of the second power supply circuit 20.

[0048] Optional, Figure 7 A circuit diagram of another MCU port clamping circuit provided in an embodiment of the present invention is shown below. Figure 7 As shown, the port clamping circuit 100 also includes a second capacitor C2; one end of the second capacitor C2 is electrically connected to the second power supply terminal Vc2, and the other end of the second capacitor C2 is electrically connected to the fourth input terminal.

[0049] The capacitance value of the second capacitor C2 can be set according to actual needs, and no specific limitation is made here.

[0050] Specifically, by setting a second capacitor C2 between the second power supply terminal Vc2 and the ground terminal GND, the second capacitor C2 can filter out noise, making the second power signal V2 transmitted to the second power supply terminal Vc2 smoother and improving the voltage stability of the second power signal V2.

[0051] Figure 8 A voltage line graph of an MCU port is provided as an embodiment of the present invention, such as... Figure 8 As shown in the figure, the horizontal axis represents the input signal vin originally provided by the external input terminal VIN, and the vertical axis represents the voltage value. The broken line in the figure represents the voltage Vport input to the MCU port. As can be seen from the figure, when the input signal vin is less than 0V, the voltage Vport transmitted to the MCU port is 0; when the input signal vin satisfies 0V≤vin≤Vcc, the voltage Vport transmitted to the MCU port is the same as vin; when the input signal vin>Vcc, the voltage Vport transmitted to the MCU port is Vcc. Thus, using the port clamping circuit 100 provided by this invention, the voltage signal input to the MCU port can be stably clamped between 0V and Vcc, improving the operational safety of the MCU.

[0052] Based on the same inventive concept, the present invention also provides an electronic device. Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention, such as... Figure 9 As shown, the electronic device 200 includes an MCU and at least one port clamping circuit 100 provided in any embodiment of the present invention; the MCU includes at least one analog signal acquisition port P, and the port clamping circuit 100 is electrically connected to the analog signal acquisition port P in a one-to-one correspondence.

[0053] The analog signal acquisition terminal P is used to acquire analog signals. In an optional embodiment, the number of analog signal acquisition terminals P is n, namely the first analog signal acquisition terminal P1, the second analog signal acquisition terminal P2, ..., the nth analog signal acquisition terminal Pn. n is a positive integer, and the specific value can be set as needed, without being specifically limited here.

[0054] Specifically, the number of port clamping circuits 100 is the same as the number of analog signal acquisition ports P, so that the port clamping circuits 100 can clamp the input signal vin of each analog signal acquisition port P, thereby improving the working safety of the MCU and extending the service life of the MCU.

[0055] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A port clamping circuit for an MCU, characterized in that, include: First diode and second diode; The cathode of the first diode is electrically connected to the first power supply terminal, the anode of the second diode is electrically connected to the second power supply terminal, and both the anode of the first diode and the cathode of the second diode are electrically connected to the input port of the MCU. The forward voltage drop of the first diode and the second diode is Vd. The operating voltage range of the MCU is 0V~Vcc. The first voltage signal provided by the first power supply terminal is V1, and the second voltage signal provided by the second power supply terminal is V2. Where V1 = Vcc - Vd, V2 = Vd.

2. The port clamping circuit according to claim 1, characterized in that, Also includes: The first power supply circuit includes a first input terminal, a second input terminal, and a first power supply terminal; the first input terminal is electrically connected to the power supply terminal of the MCU, and the second input terminal is electrically connected to the ground terminal of the MCU.

3. The port clamping circuit according to claim 2, characterized in that, The first power supply circuit includes: a third diode and a first resistor; The anode of the third diode is electrically connected to the first input terminal, one end of the first resistor is electrically connected to the second input terminal, and the cathode of the third diode and the other end of the first resistor are both electrically connected to the first power supply terminal. The forward voltage drop of the third diode is Vd.

4. The port clamping circuit according to claim 3, characterized in that, It also includes: a first voltage follower; The input terminal of the first voltage follower is electrically connected to the cathode of the third diode and the other end of the first resistor, and the output terminal of the first voltage follower is electrically connected to the first power supply terminal.

5. The port clamping circuit according to claim 4, characterized in that, Also includes: First capacitor; One end of the first capacitor is electrically connected to the first power supply terminal, and the other end of the first capacitor is electrically connected to the second input terminal.

6. The port clamping circuit according to claim 1, characterized in that, Also includes: The second power supply circuit includes a third input terminal, a fourth input terminal, and the second power supply terminal. The third input terminal is electrically connected to the power supply terminal of the MCU, and the fourth input terminal is electrically connected to the ground terminal of the MCU.

7. The port clamping circuit according to claim 6, characterized in that, The second power supply circuit includes: a fourth diode and a second resistor; The cathode of the fourth diode is electrically connected to the fourth input terminal, one end of the second resistor is electrically connected to the third input terminal, and the anode of the fourth diode and the other end of the second resistor are both electrically connected to the second power supply terminal. The forward voltage drop of the fourth diode is Vd.

8. The port clamping circuit according to claim 7, characterized in that, Also includes: Second voltage follower; The input terminal of the second voltage follower is electrically connected to the anode of the fourth diode and the other end of the second resistor, and the output terminal of the second voltage follower is electrically connected to the second power supply terminal.

9. The port clamping circuit according to claim 8, characterized in that, Also includes: Second capacitor; One end of the second capacitor is electrically connected to the second power supply terminal, and the other end of the second capacitor is electrically connected to the fourth input terminal.

10. An electronic device, characterized in that, Includes: an MCU and at least one port clamping circuit as described in any one of claims 1 to 9; The MCU includes at least one analog signal acquisition port, and the port clamping circuit is electrically connected to each analog signal acquisition port in a one-to-one correspondence.

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