A low dropout linear regulator with feedforward gate modulation function

Abstract

The application relates to the technical field of low-dropout linear voltage stabilizers, and particularly discloses a low-dropout linear voltage stabilizer with a feedforward gate modulation function, which is characterized in that a PMOS driving tube is connected in series between the output end of an error amplifier and the gate of a main power tube, and a power supply ripple signal extracted by a feedforward ripple extraction circuit is injected into the gate of the driving tube, so that the transconductance of the driving tube can modulate the charge amount of the gate of the power tube in real time, the dynamic source-gate voltage of the power tube is clamped near zero, the physical path of the power supply ripple converted into an output ripple through the transconductance effect of the power tube is fundamentally cut off, the loss of feedback loop gain caused by the degradation of the intrinsic impedance of a transistor under an advanced process is effectively compensated, and deep suppression of narrow-band frequency band power supply ripples is realized; meanwhile, the introduction of the driving tube eliminates the risk of ringing in the transient response of the load, and the phase margin of the loop is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of voltage regulation technology, and in particular to a low-dropout linear regulator with feedforward gate modulation function. Background Technology

[0002] In deep-sea exploration, underwater wireless sensor networks, and high-precision acoustic detection systems, high-performance sensors place extremely stringent requirements on the ripple noise level of the power supply. Especially in the critical acoustic frequency band of 1kHz to 10kHz, minute ripple fluctuations at the power supply end can easily couple to the sensitive analog front end, leading to a significant degradation in the system's signal-to-noise ratio (SNR) and severely limiting the long-range accuracy and data robustness of underwater detection systems.

[0003] To improve the power supply rejection ratio (PSRR) of low-dropout linear regulators (LDOs), feedforward ripple cancellation (FFRC) technology is widely used. In existing technologies, the injection location of the feedforward ripple signal mainly falls into three categories: the first is to directly inject the extracted power supply ripple into the gate of the main power transistor, achieving cancellation through superposition of inverted ripple; the second is to inject the ripple signal into the substrate of the main power transistor, utilizing the substrate modulation effect to suppress the output ripple; the third is to use an adder or summing circuit to superimpose the feedforward ripple component onto the output of the error amplifier, and then drive the gate of the power transistor. All of the above technical solutions can improve PSRR to a certain extent in specific application scenarios.

[0004] However, as semiconductor processes evolve towards 40nm and more advanced nodes, the aforementioned existing technologies have exposed a series of common physical limitations. First, the intrinsic impedance of the drain-source transistors degrades drastically under advanced processes, resulting in a severe deficiency of the intrinsic gain of the main power transistor at low operating frequencies. All three types of feedforward schemes only focus on the injection path of the ripple signal, without structurally modifying the signal path between the error amplifier output and the power transistor gate. Therefore, they cannot compensate for the feedback loop gain lost due to intrinsic gain degradation, fundamentally limiting ripple suppression capabilities in the 1kHz narrowband band. Second, in existing schemes, the output of the error amplifier is directly connected to the gate of the power transistor. The large parasitic capacitance of the power transistor interacts with the output impedance of the third-stage error amplifier, easily forming high-Q complex pole pairs in the mid-frequency band. This leads to insufficient system damping, gain spikes, and phase margin degradation, making it prone to ringing or even oscillation during load transient responses. Furthermore, the above solutions all lack a targeted compensation mechanism for intrinsic gain degradation under 40nm process technology, making it difficult to achieve a balance between deep ripple suppression and loop stability in narrowband frequency bands. Summary of the Invention

[0005] This invention provides a low-dropout linear regulator with feedforward gate modulation function. The technical problem it solves is: how to overcome the low-frequency gain deficiency caused by the intrinsic gain degradation of the main power transistor under advanced process conditions such as 40nm, while eliminating complex pole pairs in the mid-frequency band to enhance loop stability, and achieving depth power supply noise suppression for the core frequency band of underwater detection at around 1kHz.

[0006] To address the above technical problems, this invention provides a low-dropout linear regulator with feedforward gate modulation function, comprising an input voltage, a feedforward ripple extraction circuit, an eighth PMOS transistor, a ninth PMOS transistor, a feedback voltage divider network, an error amplifier, and a reference voltage. The input voltage is connected to the power input terminal of the feedforward ripple extraction circuit, the source of the eighth PMOS transistor, and the source of the ninth PMOS transistor. The gate of the eighth PMOS transistor is connected to the output terminal of the feedforward ripple extraction circuit. The drain of the eighth PMOS transistor is connected to the gate of the ninth PMOS transistor and the output terminal of the error amplifier. The drain of the ninth PMOS transistor is connected to the input terminal of the feedback voltage divider network. The voltage divider node of the feedback voltage divider network is connected to the inverting input terminal of the error amplifier. The non-inverting input terminal of the error amplifier and the reference voltage input terminal of the feedforward ripple extraction circuit are connected to the reference voltage.

[0007] Preferably, the feedforward ripple extraction circuit includes a filter capacitor, a filter resistor, an operational amplifier, a first resistor, a second resistor, and a 23rd NMOS transistor. One end of the filter capacitor is connected to the input voltage, and the other end is connected to one end of the filter resistor and the non-inverting input of the operational amplifier. The other end of the filter resistor is connected to the reference voltage. One end of the first resistor is connected to the input voltage, and the other end is connected to the drain of the 23rd NMOS transistor and the gate of the 8th PMOS transistor. The gate of the 23rd NMOS transistor is connected to the output of the operational amplifier. The source of the 23rd NMOS transistor is connected to the inverting input of the operational amplifier and one end of the second resistor. The other end of the second resistor is grounded.

[0008] Preferably, the resistance values ​​of the first resistor and the second resistor are equal.

[0009] Preferably, the operational amplifier is a folded cascode operational amplifier.

[0010] Preferably, the feedback voltage divider network includes a third resistor and a fourth resistor. One end of the third resistor is connected to the drain of the ninth PMOS transistor, and the other end of the third resistor is connected to one end of the fourth resistor to form the voltage divider node. The other end of the fourth resistor is grounded.

[0011] Preferably, the error amplifier is a three-stage amplifier, the first stage amplifier is a folded cascode amplifier, the second stage amplifier is a single-ended output amplifier circuit, and the third stage amplifier is an NMOS input cascode structure.

[0012] Preferably, the error amplifier is provided with a first bias circuit for generating an analog bias voltage applied to the three-stage amplifier.

[0013] Preferably, the error amplifier includes an inverter as a switch enable to provide a digital enable signal for the first bias circuit and the three-stage amplifier.

[0014] Preferably, the feedforward ripple extraction circuit includes a second bias circuit for generating an analog bias voltage applied to the operational amplifier.

[0015] Preferably, the inverter in the error amplifier simultaneously provides a digital enable signal for both the operational amplifier and the second bias circuit.

[0016] This invention provides a low-dropout linear regulator with feedforward gate modulation. By connecting a PMOS driver transistor in series between the output of the error amplifier and the gate of the main power transistor, and injecting the power ripple signal extracted by the feedforward ripple extraction circuit into the gate of the driver transistor, the transconductance of the driver transistor can modulate the charge on the gate of the power transistor in real time. This clamps the dynamic source-gate voltage of the power transistor to near zero, fundamentally cutting off the physical path of power ripple being converted into output ripple through the transconductance effect of the power transistor. This effectively compensates for the feedback loop gain loss caused by the degradation of the intrinsic impedance of the transistor under advanced processes, achieving deep suppression of power ripple in narrowband frequencies. At the same time, the introduction of this driver transistor changes the damping relationship between the output impedance of the third-stage error amplifier and the parasitic capacitance of the power transistor, increasing the dynamic damping coefficient of the system. This decouples the original high-gain peak mid-frequency complex pole pair into real poles and pushes the non-dominant poles to higher frequency bands, thereby eliminating the ringing risk in the load transient response and significantly improving the phase margin of the loop. Therefore, this invention achieves the unity of narrowband ripple depth suppression and loop stability enhancement through a single driving transistor, overcoming the technical challenge of balancing these two aspects in traditional LDO design. Attached Figure Description

[0017] Figure 1 This is an overall circuit diagram of a low-dropout linear regulator with feedforward gate modulation function provided in an embodiment of the present invention;

[0018] Figure 2 This is an exemplary circuit diagram of an error amplifier provided in an embodiment of the present invention;

[0019] Figure 3This is an exemplary circuit diagram of the feedforward ripple extraction circuit provided in an embodiment of the present invention;

[0020] Figure 4 This is a waveform comparison of the power supply rejection ratio (PSRR) before and after the improvement of the low dropout linear regulator provided in this embodiment of the invention. Detailed Implementation

[0021] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments are given for illustrative purposes only and should not be construed as limiting the present invention. The accompanying drawings are for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0022] This invention provides a low-dropout linear regulator with feedforward gate modulation function, the circuit of which is as follows: Figure 1 As shown, including input voltage Feedforward ripple extraction circuit, eighth PMOS transistor (As a driver transistor), the ninth PMOS transistor (as a power transistor), feedback voltage divider network, error amplifier, and reference voltage Input voltage Connect the power input terminal of the feedforward ripple extraction circuit and the eighth PMOS transistor. The source of the ninth PMOS transistor The source of the eighth PMOS transistor The gate of the eighth PMOS transistor is connected to the output of the feedforward ripple extraction circuit. The drain of the ninth PMOS transistor is connected. The gate and output of the error amplifier, the ninth PMOS transistor The drain is connected to the input of the feedback voltage divider network, and the voltage divider node of the feedback voltage divider network outputs the feedback voltage. Connect the inverting input of the error amplifier, and connect the non-inverting input of the error amplifier and the reference voltage input of the feedforward ripple extraction circuit to the reference voltage. .

[0023] The feedforward ripple extraction circuit includes a filter capacitor. Filter resistor Operational amplifier, first resistor Second resistor 23 NMOS transistor Filter capacitor One end is connected to the input voltage The other end is connected to a filter resistor. One end is connected to the non-inverting input of the operational amplifier, and the filter resistor is... The other end is connected to the reference voltage. First resistor One end is connected to the input voltage The other end is connected to the twenty-third NMOS transistor. The drain and the eighth PMOS transistor The gate of the twenty-third NMOS transistor The gate of the 23rd NMOS transistor is connected to the output of the operational amplifier. The source is connected to the inverting input of the operational amplifier and the second resistor. One end, the second resistor The other end is grounded. Among them, the filter capacitor... Filter resistor public terminal This is the drive control node, used to transmit the extracted input voltage ripple signal to the subsequent amplification circuit. Operational amplifier, 23rd NMOS transistor. Second resistor public terminal As the output voltage node of the extraction network, it is used to inject the feedforward ripple signal into the driver transistor with a specific gain and phase relationship. The gate of the power transistor enables control of the power transistor. Dynamic modulation of the gate.

[0024] As an example, a feedback voltage divider network includes a third resistor. and the fourth resistor The third resistor One end is connected to the power transistor The drain (output terminal) ), third resistor The other end is connected to the fourth resistor One end is connected to form a voltage divider node, the fourth resistor The other end is grounded. This feedback voltage divider network senses the output in real time through the voltage divider node. Voltage fluctuations are converted into feedback voltage. Feedback voltage The voltage is fed back to the inverting input of the error amplifier, while the other input of the error amplifier is connected to the reference voltage output from the bandgap reference source. Therefore, the feedback voltage With reference voltage The difference between the two values ​​is amplified by an error amplifier and then transmitted through a drive transistor. Drive power transistor The gate forms a negative feedback closed loop, thereby stabilizing the output voltage. This feedback voltage divider network has a simple structure and high accuracy, and works well with subsequent error amplifiers and power transistors. This ensures the stability of the LDO's output voltage under different load conditions.

[0025] Figure 1 The working principle of the low dropout linear regulator shown is as follows:

[0026] When the input voltage When low-frequency ripple exists (e.g., interference in the 1kHz to 10kHz underwater detection frequency band), the feedforward ripple extraction circuit uses a filter capacitor... With filter resistor The constructed high-pass filter network extracts the input voltage. The AC ripple component in the circuit is processed by an operational amplifier and the 23rd NMOS transistor. and the first resistor Second resistor After processing, in the third node An AC voltage signal in phase with the input ripple is generated at this third node. Directly connected to the drive transistor The drain of the transistor is used to inject the feedforward ripple signal into the driver transistor. The control terminal. Simultaneously, the output terminal of the error amplifier is connected to the drive transistor. drain and power transistor The gate. In Under the transconductance effect, the feedforward ripple signal received by its gate is converted in real time into a signal for the power transistor. Dynamic modulation of gate charge enables the power transistor The gate potential of the power transistor changes synchronously with the input ripple, thereby causing the power transistor to... Dynamic source-gate voltage Constrained near zero, i.e. , , Power transistors The source and gate voltages. Therefore, the power supply ripple passes through the power transistor. The physical path through which the transconductance effect is converted into output ripple is completely cut off, achieving deep suppression of power supply ripple in the narrowband frequency band.

[0027] In addition, drive tube The introduction also changed the output stage of the error amplifier and the power transistor. Impedance characteristics between gates. Without the introduction of a driver transistor. At that time, the output impedance of the error amplifier and the power transistor The interaction of the gate parasitic capacitance easily forms high-Q complex pole pairs, leading to insufficient system damping. Introducing a driver transistor... Subsequently, the system's dynamic damping coefficient increases, high-Q complex pole pairs decouple into real poles, and non-dominant poles split towards higher frequencies, effectively eliminating the risk of ringing in the load transient response and significantly improving the loop's phase margin.

[0028] This invention provides a low-dropout linear regulator with feedforward gate modulation function, which is achieved by connecting the output of the feedforward ripple extraction circuit to the driving transistor. The gate, and the drive transistor Connected in series with the output of the error amplifier and the power transistor A novel topology of "feedforward extraction—isolation modulation—power output" is formed between the gates. Based on this structure, the output voltage node of the feedforward ripple extraction circuit... A feedforward voltage in phase with the input ripple is generated and directly injected into the driver transistor. The gate of the transistor. Simultaneously, the DC bias and low-frequency adjustment signal output from the error amplifier are applied to the drive transistor. The drain of the driving transistor The drain further drives the power transistor The gate of the driving transistor. Under the influence of transconductance, the feedforward ripple signal injected into the gate is converted into a signal for the power transistor in real time. The reverse modulation of the gate charge makes the power transistor The source-gate dynamic voltage is 0, thus physically cutting off the power supply ripple through the power transistor. The transconductance effect, flowing to the output, achieves deep suppression of power supply ripple in the core frequency band of underwater detection, effectively improving the power supply rejection ratio (PSRR) of the LDO in this band. Simultaneously, the drive transistor... The introduction of this changed the output impedance of the error amplifier and the power transistor. The damping characteristics between the gate parasitic capacitances affect the system's dynamic damping coefficient. The increase in Q-value decouples the original high-Q complex pole pairs into real poles, and the non-dominant poles split towards higher frequencies, eliminating gain spikes in the mid-frequency band and the ringing risk in the load transient response, significantly enhancing the loop phase margin. Therefore, this application, through the driving transistor... In synergy with the feedforward ripple extraction circuit, it overcomes the contradiction between narrowband ripple suppression depth and loop stability in traditional LDO design without the need for complex methods such as adders or substrate implantation. At the same time, it compensates for the gain loss caused by the degradation of the intrinsic gain of transistors under the 40 nm advanced process, providing a power supply solution with both high power supply rejection ratio and high stability for underwater high-precision sensors.

[0029] Figure 2 This is an exemplary circuit diagram of an error amplifier. Figure 2As shown, the error amplifier employs a three-stage amplifier. The first stage amplifier is a folded cascode amplifier, including a first PMOS transistor. Second PMOS transistor Third PMOS transistor Fourth PMOS transistor Fifth PMOS transistor The sixth PMOS transistor Nineteenth PMOS transistor 20th PMOS transistor The sixth NMOS transistor 7th NMOS transistor Eighth NMOS transistor Ninth NMOS transistor Composition. Reference voltage Connect the second PMOS transistor The gate of the first PMOS transistor Gate access feedback voltage First PMOS transistor Second PMOS transistor By forming an input differential pair, it can provide a wide input common-mode range and effectively suppress low-frequency flicker noise.

[0030] The second-stage amplifier uses a seventh PMOS transistor. 10th NMOS transistor Together, they form a single-ended output amplifier circuit that acts as a load current mirror, further amplifying the voltage of the preceding signal and providing high DC gain for the loop along with the first stage.

[0031] The third-stage amplifier uses a common-source, common-gate NMOS input structure, consisting of an eleventh NMOS transistor. 12th NMOS transistor 13th NMOS transistor Fourteenth NMOS transistor 10th PMOS transistor Eleventh PMOS transistor This structure provides a high secondary voltage divider impedance while forming a noise feedforward path inside the error amplifier.

[0032] The error amplifier also includes a first capacitor. Fifth resistor Second capacitor As a Miller compensation, it is connected between the second and third stage amplifiers to adjust loop stability, phase margin, and gain-bandwidth product, etc.

[0033] In addition, the error amplifier also includes a first bias circuit, which consists of a first NMOS transistor. Second NMOS transistor Third NMOS transistor Fourth NMOS transistor 24th NMOS transistor 27th NMOS transistor and bias signal It is configured to provide bias voltages NBC and NB, and also serve as a main current mirror to the sixth NMOS transistor. 7th NMOS transistor Eighth NMOS transistor Ninth NMOS transistor 10th NMOS transistor Eleventh NMOS transistor 13th NMOS transistor Fourteenth NMOS transistor Provides bias. NB and NBC are analog bias voltages with different values ​​generated by the first bias circuit. They are used to provide a stable gate bias, ensuring that the gate always operates in the saturation region to achieve high gain. The values ​​of NB and NBC are set by the first bias circuit and do not change with the enable state (they are constant during normal operation); they are analog bias voltages.

[0034] The error amplifier also incorporates a 25th NMOS transistor. and the eighteenth PMOS transistor The inverter, composed of these components, acts as a switch enable, controlling the nineteenth PMOS transistor by generating EN and ENB signals. 20th PMOS transistor 24th NMOS transistor 27th NMOS transistor EN and ENB are a pair of complementary digital enable signals (0V or 3.3V) used to control the switching state of the corresponding MOSFETs.

[0035] The working principle of the error amplifier is: to use a feedback voltage divider network to sense the output terminal in real time. Voltage fluctuations are converted into feedback voltage. , and reference voltage In differential pair tubes and The difference between the two values ​​is compared at a certain point, and after being amplified three times, it is output from the single-ended output port of the third stage to drive subsequent circuits. To improve the power supply rejection ratio (PSR) of the 1kHz underwater sensor in a specific operating frequency band and to enhance the stability of multi-stage high-order loops, this invention connects the output of the third-stage error amplifier to the main power transistor... A drive transistor is connected in series between the control gate and the control gate. and drive tube The output voltage of the gate connected to the feedforward ripple elimination network ( (Node). This drive tube Operating in the saturation region under static conditions, it is equivalent to an active impedance element in AC small-signal analysis. Its connection alters the impedance distribution and small-signal current path at the third-stage output node. (Driver transistor) The intrinsic impedance of the power transistor, together with its parasitic capacitance, forms an AC impedance divider network, reducing the transmission coefficient of power supply ripple from the source to the gate and enhancing the power supply ripple following capability. Therefore, the power transistor... The gate alternating voltage and input ripple always satisfy the in-phase and equal-amplitude conditions at the frequency point, and the power transistor The alternating transconducting current approaches zero, thus improving the power supply rejection ratio (PSRR) of the LDO near the specified frequency. Furthermore, this drive transistor... The introduction of this technology also altered the closed-loop pole distribution of the entire three-stage high-order system, achieving enhanced damping and pole splitting: due to the increased damping factor, the original high-Q complex pole pairs were decoupled into real poles, eliminating potential transient oscillations in the loop under audio current steps at the frequency point; the series-connected drive transistors This reduces the direct perception of the large parasitic capacitance of the power transistor by the preamplifier, enables the splitting of non-dominant poles into the high-frequency band, and increases the distance between secondary dominant poles and dominant poles.

[0036] Figure 3 This is an exemplary circuit diagram of a feedforward ripple elimination circuit. For example... Figure 3 As shown, the feedforward ripple extraction circuit mainly consists of filter capacitors. Filter resistor The twelfth PMOS transistor Thirteenth PMOS transistor Fourteenth PMOS transistor The fifteenth PMOS transistor Sixteenth PMOS transistor The seventeenth PMOS transistor The nineteenth NMOS transistor 22nd PMOS transistor 20th NMOS transistor 21st NMOS transistor 22nd NMOS transistor The constructed folded cascode operational amplifier, with the twenty-third NMOS transistor. First resistor Second resistor Composition, and involves reference voltage Input voltage and nodes , , .node Connect the non-inverting input of the folded cascode operational amplifier (i.e.) The gate of the operational amplifier (the inverting input terminal of the operational amplifier) (gate) connection node The output terminal of the operational amplifier ( Drain and (the common terminal of the drain) connection The gate; source connection node and at the same time Grounding, Leakage connect And the drain node serves as the output terminal. Directly connected to the drive transistor The gate.

[0037] In addition, the feedforward ripple elimination circuit also includes a second bias circuit, which is powered by the fifteenth NMOS transistor. Sixteenth NMOS transistor The seventeenth NMOS transistor The eighteenth NMOS transistor 26th NMOS transistor 28th NMOS transistor and bias signal Its configuration provides a different bias voltage than NB and NBC. and And as the main current mirror for the nineteenth NMOS transistor 20th NMOS transistor 21st NMOS transistor 22nd NMOS transistor Provides bias. and It is an analog bias voltage with different values ​​generated by the second bias circuit, used to provide a stable gate bias so that it always operates in the saturation region to obtain high gain. and The value is set by the second bias circuit and does not change with the enable state (it is constant during normal operation), belonging to the analog bias voltage.

[0038] Meanwhile, the error amplifier is equipped with the 25th NMOS transistor. and the eighteenth PMOS transistor The inverter, composed of these components, acts as a switch enable and also controls the 21st PMOS transistor via the EN and ENB signals. 22nd PMOS transistor 26th NMOS transistor 28th NMOS transistor .

[0039] The working principle of the feedforward ripple elimination circuit is: when the input voltage... When low-frequency ripples are present (e.g., interference in the 1 kHz to 10 kHz underwater detection frequency band), and The constructed high-pass filter extracts and The ripple-in-phase AC components at the nodes Voltage formed on ( (This is a small AC signal with input ripple). This signal is amplified by a folded cascode operational amplifier and then used to drive... Due to the deep negative feedback of the operational amplifier, the node AC potential follower ,Right now Therefore, in the resistor Alternating current is generated on The current flows through and resistance At the node The total AC small-signal voltage formed on When the resistance ratio is strictly guaranteed to meet the requirements... ,at this time, , i.e., node The communication is virtual, successfully shielding the pre-amplifier ripple noise, preventing it from being transmitted to the power transistor. .

[0040] This feedforward ripple extraction circuit boasts a simple structure, employing only a few passive components and a folded cascode operational amplifier to accurately extract power supply ripple and convert it into a gate modulation signal synchronized with the input ripple, eliminating the need for complex adders or substrate injection circuits. In advanced 40 nm processes, this circuit effectively compensates for loop gain loss due to intrinsic gain degradation in the main power transistors, achieving deep ripple suppression, particularly in the 1kHz narrowband band. It also helps reduce static power consumption and chip area, and is easy to integrate.

[0041] The core innovation of the low-dropout linear regulator with feedforward gate modulation provided in this embodiment lies in directly connecting the AC ripple voltage output from the feedforward ripple extraction circuit to the newly introduced PMOS isolation transistor. The gate, rather than acting directly on the power transistor as in traditional technologies. Due to the isolation tube gate potential Real-time and high-precision tracking of AC power supply ripple (i.e. This results in a follower phenomenon in the small-signal model, where the main power transistor moves with the input voltage source. The gate of the main power transistor is subjected to strong synchronous modulation injected through the feedforward path. Ultimately, this causes the dynamic source-gate voltage of the main power transistor to ( The small-signal components are strictly clamped near zero. Through this feedforward synchronous clamping control, even if the intrinsic gain and output resistance of the transistor are severely degraded in the 40nm process, the physical path of the AC ripple drain current generated by the main power transistor due to the transconductance effect has been completely cut off, fundamentally achieving a leap in power supply rejection ratio.

[0042] Figure 4 The LDO (improved) of this invention is different from the one without the feedforward ripple extraction circuit and the third PMOS transistor of this application. Power supply rejection ratio waveform of LDO (before improvement) (input voltage) Reference voltage Output voltage Load current (Frequency point is 1kHz). From Figure 4 As can be seen, at a frequency of 1kHz, this invention achieves -94.98dB, an improvement of over 20dB compared to existing technologies. This verifies the effectiveness of the feedforward ripple extraction circuit for the driving transistor. The correctness of the high-precision in-phase drive strategy for the gate, and the driving transistor The effectiveness of introducing post-damping correction and pole splitting mechanism.

[0043] In summary, this invention, through the error amplifier and power transistor... PMOS drive transistors connected in series The ripple signal extracted by the feedforward ripple extraction circuit is then injected into the driver transistor. The gate of the power transistor is modulated using transconductance modulation. The dynamic source-gate voltage is clamped to zero, thereby cutting off the ripple conduction path and significantly improving the PSRR in the 1kHz~10kHz frequency band (measured at -94.98dB@1kHz); at the same time, the driving transistor The introduction of this method optimizes the loop damping characteristics, decoupling complex poles into real poles and enhancing system stability. This scheme solves the technical challenge of balancing narrowband suppression and loop stability under advanced processes with a simple topology, making it suitable for demanding scenarios such as powering high-precision underwater sensors.

[0044] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A low-dropout linear regulator with feedforward gate modulation function, characterized in that: The system includes an input voltage, a feedforward ripple extraction circuit, an eighth PMOS transistor, a ninth PMOS transistor, a feedback voltage divider network, an error amplifier, and a reference voltage. The input voltage is connected to the power input terminal of the feedforward ripple extraction circuit, the source of the eighth PMOS transistor, and the source of the ninth PMOS transistor. The gate of the eighth PMOS transistor is connected to the output terminal of the feedforward ripple extraction circuit. The drain of the eighth PMOS transistor is connected to the gate of the ninth PMOS transistor and the output terminal of the error amplifier. The drain of the ninth PMOS transistor is connected to the input terminal of the feedback voltage divider network. The voltage divider node of the feedback voltage divider network is connected to the inverting input terminal of the error amplifier. The non-inverting input terminal of the error amplifier and the reference voltage input terminal of the feedforward ripple extraction circuit are connected to the reference voltage.

2. A low-dropout linear regulator with feedforward gate modulation function according to claim 1, characterized in that: The feedforward ripple extraction circuit includes a filter capacitor, a filter resistor, an operational amplifier, a first resistor, a second resistor, and a 23rd NMOS transistor. One end of the filter capacitor is connected to the input voltage, and the other end is connected to one end of the filter resistor and the non-inverting input of the operational amplifier. The other end of the filter resistor is connected to the reference voltage. One end of the first resistor is connected to the input voltage, and the other end is connected to the drain of the 23rd NMOS transistor and the gate of the 8th PMOS transistor. The gate of the 23rd NMOS transistor is connected to the output of the operational amplifier. The source of the 23rd NMOS transistor is connected to the inverting input of the operational amplifier and one end of the second resistor. The other end of the second resistor is grounded.

3. A low-dropout linear regulator with feedforward gate modulation function according to claim 2, characterized in that: The resistance values ​​of the first resistor and the second resistor are equal.

4. A low-dropout linear regulator with feedforward gate modulation function according to claim 2, characterized in that: The operational amplifier is a folded common-source cascode operational amplifier.

5. A low-dropout linear regulator with feedforward gate modulation function according to claim 1, characterized in that: The feedback voltage divider network includes a third resistor and a fourth resistor. One end of the third resistor is connected to the drain of the ninth PMOS transistor, and the other end of the third resistor is connected to one end of the fourth resistor to form the voltage divider node. The other end of the fourth resistor is grounded.

6. A low-dropout linear regulator with feedforward gate modulation function according to claim 2, characterized in that: The error amplifier is a three-stage amplifier. The first stage amplifier is a folded cascode amplifier, the second stage amplifier is a single-ended output amplifier circuit, and the third stage amplifier is an NMOS input cascode structure.

7. A low-dropout linear regulator with feedforward gate modulation function according to claim 6, characterized in that: The error amplifier is provided with a first bias circuit for generating an analog bias voltage that is applied to the three-stage amplifier.

8. A low-dropout linear regulator with feedforward gate modulation function according to claim 7, characterized in that: The error amplifier is equipped with an inverter as a switch enable, providing a digital enable signal for the first bias circuit and the third-stage amplifier.

9. A low-dropout linear regulator with feedforward gate modulation function according to claim 8, characterized in that: The feedforward ripple extraction circuit is provided with a second bias circuit for generating an analog bias voltage applied to the operational amplifier.

10. A low-dropout linear regulator with feedforward gate modulation function according to claim 9, characterized in that: The inverter in the error amplifier simultaneously provides a digital enable signal for the operational amplifier and the second bias circuit.

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