Floating power based push-pull source follower

Abstract

The application discloses a push-pull type source follower based on a floating power supply, comprising a differential structure follower unit and an energy storage capacitor unit, wherein the follower unit is a push-pull type source follower structure biased by a capacitor, the voltage margin problem of a traditional source follower under low power supply voltage is solved, and high current efficiency is realized through current multiplexing; the energy storage capacitor unit effectively fixes the output common-mode voltage by taking the energy storage capacitor as a floating power supply, and the problem that the traditional source follower is sensitive to process, voltage and temperature is solved. In addition, the application also proposes a static and dynamic biasing mode suitable for the circuit, and the practicability is improved.

Description

Technical Field

[0001] This invention belongs to the field of amplifier technology, specifically relating to a push-pull source follower based on a floating power supply. Background Technology

[0002] A common-drain amplifier, also known as a source follower, is an important analog circuit unit in integrated circuits. Its typical structure consists of a single MOSFET, with the signal input at the gate and output at the source. This circuit features high input impedance, low output impedance, near-unity voltage gain, and excellent level shifting capability. Therefore, it is widely used in analog and mixed-signal systems, such as as a buffer stage to isolate preceding and following circuits, as an output stage to drive heavy loads, or to provide high-precision level shifting in voltage reference circuits.

[0003] However, traditional source followers have several inherent technical limitations that restrict their performance in advanced process nodes and high-performance applications. These limitations are mainly reflected in the following aspects: First, there is the issue of voltage margin loss. To ensure that the transistor operates in the saturation region, the input voltage and output voltage of the source follower must meet specific bias conditions. This results in the upper limit of its output voltage swing being at least one transistor threshold voltage lower than the power supply voltage. In low power supply voltage design environments, this voltage margin loss severely restricts the signal processing range and dynamic performance, leading to a decrease in the signal-to-noise ratio.

[0004] Second, there is the sensitivity to process variations and temperature drift. Parameters such as the threshold voltage and carrier mobility of transistors can drift with changes in manufacturing process angles and ambient temperature. These drifts can directly alter the bias point of the source follower, leading to unstable circuit performance.

[0005] To address these issues, the literature [M. Al-Shyoukh, H. Lee and R. Perez, "A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation," in IEEE J. Solid-State Circuits, vol. 42, no. 8, pp.1732-1742, Aug. 2007] proposed a super source follower that reduces output impedance while fixing the output common-mode voltage range through an additional common-source amplifier. However, this approach introduces additional area and power consumption. In addition, the literature [T.Xie, T.-H. Wang, Z. Liu and S. Li, "An 84-dB-SNDR low-OSR fourth-order noise-shaping SAR with an FIA-assisted EF-CRFF structure and noise-mitigated push-pull buffer-in-loop technique," in IEEE J. Solid-State Circuits, vol.57, no. 12, pp. 3804-3815, Dec. 2022] proposes a push-pull source follower, which fixes the output common-mode voltage at the common-mode voltage while solving the voltage margin problem. However, it still causes output common-mode offset in the case of mismatch.

[0006] Therefore, there is an urgent need in this field for an improved source follower circuit structure or method that can effectively overcome the shortcomings of traditional source followers while maintaining advantages such as high input impedance and low output impedance. Summary of the Invention

[0007] In view of the above, the present invention provides a push-pull source follower based on a floating power supply, which uses a floating power supply to fix the output common-mode voltage and solves the voltage margin problem of traditional source followers under low power supply voltage through the structure of the push-pull source follower.

[0008] A push-pull source follower based on a floating power supply includes a differential follower unit and an energy storage capacitor unit. The follower unit adopts a capacitor-biased push-pull source follower structure and achieves high current efficiency signal following through current multiplexing. The energy storage capacitor unit uses an energy storage capacitor as a floating power supply, which supplies power to the follower unit after reset and effectively fixes the output common-mode voltage.

[0009] Furthermore, the follower unit adopts a push-pull structure composed of NMOS and PMOS transistors. The input signal is coupled to the gate of the MOS transistor through a capacitor, so that the NMOS and PMOS transistors are simultaneously turned on and current multiplexed during the amplification stage, achieving signal following with high current efficiency. During the reset stage, the input capacitor and the common-mode voltage at the output terminal are preset to ensure that the output common-mode voltage is stable during the amplification stage. It is insensitive to changes in process, power supply voltage and temperature, thereby obtaining a stable and low-distortion follower output.

[0010] Furthermore, the energy storage capacitor unit includes an energy storage capacitor C. RES And four switches S1, S2, S3, and S4, one end of which is connected to the power supply voltage V. DD The other end of S1 is connected to C RES One end of S2 is connected to one end of S3, one end of S2 is grounded, and the other end of S2 is connected to C. RES The other end of S3 is connected to one end of S4. The other end of S3 serves as the floating power rail of the energy storage capacitor unit, and the other end of S4 serves as the floating ground rail of the energy storage capacitor unit. The on / off states of switches S1 and S2 are controlled by clock signal φ1, and the on / off states of switches S3 and S4 are controlled by clock signal φ2. This energy storage capacitor unit structure replaces the traditional power rail power supply and enables the dynamic operation of the follower.

[0011] Furthermore, the follower unit includes two NMOS transistors M1 and M2, two PMOS transistors M3 and M4, four capacitors C1, C2, C3, and C4, and eight switches S5, S6, S7, S8, S9, and S1. 10 S 11 S 12 The drains of M1 and M2 are connected to the floating power rail of the energy storage capacitor unit. The drains of M3 and M4 are connected to the floating ground rail of the energy storage capacitor unit. The sources of M1 and M3, as well as one end of S5, are connected as the inverting output of the push-pull source follower. The sources of M2 and M4, as well as one end of S6, are connected as the non-inverting output of the push-pull source follower. The gate of M1 is connected to one end of C1 and one end of S9. The gate of M2 is connected to one end of C3 and S9. 10 One end of M3 is connected to the gate of C2 and the S. 11 One end is connected, the gate of M4 is connected to one end of C4 and S 12 One end of S5 is connected to the other end of S6, and the other end of S5 is connected to the common-mode voltage V. CMThe other end of C1 is connected to the other end of C2 and one end of S7 as the inverting input of the push-pull source follower. The other end of C3 is connected to the other end of C4 and one end of S8 as the non-inverting input of the push-pull source follower. The other ends of S7 and S8 are connected to the common-mode voltage V. CM The other end of S9 is connected to S 10 The other end is connected to the bias voltage V BN S 11 The other end and S 12 The other end is connected to the bias voltage V BP Eight switches S5~S 12 The switching on and off of the circuit is controlled by the clock signal φ1. This follower unit structure can improve transconductance and increase current efficiency.

[0012] Furthermore, the clock signal φ1 is used to close the switch during the system reset phase, and the clock signal φ2 is used to close the switch during the amplification phase. φ1 and φ2 are complementary in phase and have a certain dead time.

[0013] Furthermore, the bias voltage V BN and V BP Generated by a static bias circuit, which includes an amplifier OTA and two NMOS transistors M. n1 and M n2 A PMOS transistor M p1 And a current source, one end of which is connected to the power supply voltage V. DD The other end of the current source is connected to M n1 The drain and gate are connected to generate a bias voltage V. BN M n1 The source and M p1 The source terminal of the OTA is connected to the non-inverting input terminal, and the inverting input terminal of the OTA is connected to the common-mode voltage V. CM OTA output terminal and M n2 The gate is connected to M. n2 The source is grounded, M n2 The drain and M p1 The drain and gate are connected to generate a bias voltage V. BP This static bias circuit provides a stable operating current for the push-pull source follower.

[0014] Furthermore, the bias voltage V BN and V BP Generated by a dynamic bias circuit, which includes an energy storage capacitor C. RES2 Two NMOS transistors M5 and M6, two PMOS transistors M7 and M8, and four switches S 13 S 14 S15 S 16 S 13 One end is connected to the power supply voltage V DD S 13 The other end and C RES2 one end and S 15 One end is connected, S 14 One end is grounded, S 14 The other end and C RES2 The other end and S 16 One end is connected, S 15 The other end is connected to the drain of M5, the gate of M5, the drain of M6, and the gate of M6 to generate a bias voltage V. BN S 16 The other end is connected to the drain of M7, the gate of M7, the drain of M8, and the gate of M8 to generate a bias voltage V. BP The source of M5 is connected to the source of M7, and the source of M6 is connected to the source of M8. The four switches S... 13 ~S 16 The switching on and off is controlled by the clock signal φ1. This dynamic bias circuit enables the operating current of the push-pull source follower to change with the frequency, thereby achieving real-time tracking of power consumption and operating frequency.

[0015] Furthermore, the dynamic bias circuit provides a dynamic bias voltage to the follower unit according to the different periods of the clock signal φ1. The use of dynamic bias enables the push-pull source follower to provide a gate-source bias that varies with frequency, making it more suitable for operating conditions with frequency variations.

[0016] Compared with existing technologies, this invention employs a push-pull source follower controlled by a floating power supply. Through a capacitor-biased push-pull source follower structure, it solves the voltage margin problem of traditional source followers at low supply voltages and achieves higher current efficiency (twice that of traditional source followers) through current multiplexing. Simultaneously, by using an energy storage capacitor as a floating power supply, this invention effectively fixes the output common-mode voltage, solving the sensitivity of traditional source followers to process technology, voltage, and temperature. Furthermore, this invention proposes static and dynamic biasing methods suitable for this circuit, improving its practicality. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the push-pull source follower based on a floating power supply according to the present invention.

[0018] Figure 2 This is a schematic diagram of the two-phase non-overlapping clock signals in the push-pull source follower structure of the present invention.

[0019] Figure 3This is a schematic diagram of the static bias circuit structure applicable to the push-pull source follower structure of the present invention.

[0020] Figure 4 This is a schematic diagram of the dynamic bias circuit structure applicable to the push-pull source follower structure of the present invention.

[0021] Figure 5 This is a schematic diagram of the circuit structure of a traditional NMOS source follower.

[0022] Figure 6 This diagram illustrates a comparison of the output performance of the push-pull source follower structure of this invention with that of a traditional structure under certain DC input conditions.

[0023] Figure 7 The figure shows the simulation results of the average current consumption of the push-pull source follower of the present invention as a function of operating frequency under dynamic bias.

[0024] Figure 8 The figure shows the simulation results of the gain of the push-pull source follower of the present invention as a function of the operating frequency under dynamic bias. Detailed Implementation

[0025] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] This embodiment provides a push-pull source follower based on a floating power supply, including a differential follower unit and an energy storage capacitor unit. The follower unit adopts a capacitor-biased push-pull source follower structure, and the energy storage capacitor unit supplies power to the source follower unit after reset.

[0027] like Figure 1 As shown, in this embodiment, the energy storage capacitor unit includes a capacitor C. RES And four switches S1, S2, S3, and S4, one end of which is connected to the power supply voltage V. DD The other end of S1 is connected to C RES One end of S2 is connected to one end of S3, one end of S2 is grounded, and the other end of S2 is connected to C. RES The other end of S3 is connected to one end of S4. The other end of S3 is the floating power rail of the energy storage capacitor unit, and the other end of S4 is the floating ground rail of the energy storage capacitor unit. The switching on and off of switches S1 and S2 is controlled by clock signal φ1, and the switching on and off of switches S3 and S4 is controlled by clock signal φ2. The conventional power rail charges the energy storage capacitor unit in the φ1 stage, and the capacitor unit then replaces the conventional power rail to supply power to the push-pull source follower in the φ2 stage.

[0028] like Figure 1As shown, in this embodiment, the follower unit includes two NMOS transistors M1 and M2, two PMOS transistors M3 and M4, four capacitors C1, C2, C3, and C4, and eight switches S5, S6, S7, S8, S9, and S1. 10 S 11 S 12 The drains of M1 and M2 are connected to the floating power rail of the energy storage capacitor unit. The drains of M3 and M4 are connected to the floating ground rail of the energy storage capacitor unit. The sources of M1 and M3, as well as one end of S5, are connected as the inverting output of the push-pull source follower. The sources of M2 and M4, as well as one end of S6, are connected as the non-inverting output of the push-pull source follower. The gate of M1 is connected to one end of C1 and one end of S9. The gate of M2 is connected to one end of C3 and S9. 10 One end of M3 is connected to the gate of C2 and the S. 11 One end is connected, the gate of M4 is connected to one end of C4 and S 12 One end of S5 is connected to the other end of S6, and the other end of S5 is connected to the common-mode voltage V. CM The other end of C1 is connected to the other end of C2 and one end of S7 as the inverting input of the push-pull source follower. The other end of C3 is connected to the other end of C4 and one end of S8 as the non-inverting input of the push-pull source follower. The other ends of S7 and S8 are connected to the common-mode voltage V. CM The other end of S9 is connected to S 10 The other end is connected to the NMOS transistor bias voltage V. BN S 11 The other end and S 12 The other end is connected to the PMOS transistor bias voltage V. BP Switches S5~S 12 The switching on and off of the circuit is controlled by the clock signal φ1. In the φ1 stage, the circuit samples the bias voltage to control the gate-source voltage of M1~M4, and then enters the follower mode in the subsequent φ2 stage. The bias current of M1~M4 is determined by the sampled gate-source voltage. Based on the characteristic that the output current of the energy storage capacitor is equal to the input current, the common-mode output of the circuit can remain stable.

[0029] like Figure 2 As shown, clock signal φ1 is used to close the switch during the system reset phase, and clock signal φ2 is used to close the switch during the amplification phase. φ1 and φ2 are complementary in phase and have a certain dead time. During the reset phase, φ1, S1, and S2 are closed, and C... RES The upper and lower plates are respectively connected to V DD And GND, to charge it, while S5, S6, S7, S8, S9, S 10 S 11 and S 12Closed, the output of the push-pull source follower is connected to V CM To perform a reset, the gates of the four MOSFETs are connected to capacitors and then to V. CM Apply bias; during the amplification stage, φ2, S5, S6, S7, S8, S9, S 10 S 11 and S 12 When S3 and S4 are closed, power is supplied to the push-pull source follower.

[0030] also, Figure 3 A static bias circuit for a push-pull source follower based on a floating power supply, applicable to this example, is presented, including an amplifier OTA and two NMOS transistors M. n1 M n2 A PMOS transistor M p1 And a current source, one end of which is connected to the power supply voltage V. DD The other end of the current source is connected to M n1 The drain and gate of the NMOS transistor generate the bias voltage V. BN M n1 The source of the transistor and M p1 The source of the transistor is connected to the non-inverting input of the OTA, M p1 The drain of the tube and M p1 The gate of the transistor and M n2 The drains of the transistors are connected, generating the PMOS transistor bias voltage V. BP M n2 The gate of the transistor is connected to the output terminal of the OTA, M n2 The source of the transistor is grounded, and the inverting input of the OTA is connected to the common-mode voltage V. CM M n1 With M p1 The source of the amplifier is located at V. CM This is to provide the bias voltage required by the input MOSFET of the follower unit.

[0031] Figure 4 A dynamic biasing circuit for a push-pull source follower based on a floating power supply, applicable to this example, is also provided, including an additional energy storage capacitor C. RES2 Two additional NMOS transistors M5 and M6, two additional PMOS transistors M7 and M8, and four additional switches S. 13 S 14 S 15 S 16 S 13 One end is connected to the power supply voltage V DD S 13 The other end and C RES2 one end and S 15 One end is connected, S 14One end is grounded, S 14 The other end and C RES2 The other end and S 16 One end is connected, S 15 The other end is connected to the drain of M5, the gate of M5, the drain of M6, and the gate of M6, generating the bias voltage V of the NMOS transistor. BN S 16 The other end is connected to the drain of M7, the gate of M7, the drain of M8, and the gate of M8, generating the bias voltage V of the PMOS transistor. BP The source of M5 is connected to the source of M7, and the source of M6 is connected to the source of M8. Switch S 13 ~S 16 The switching on and off of the circuit is controlled by the clock signal φ1, which provides a dynamic bias voltage to the push-pull source follower according to the different periods of the clock signal φ1. During the φ1 phase, the dynamic bias circuit consists of the energy storage capacitor C. RES2 Power is supplied, and the MOSFET connected by two diodes continuously discharges, with a bias voltage V. BN With V BP Over time, continuously moving towards V CM As the transistor approaches the clock signal φ1, the gate-source voltage of the MOSFET continuously decreases. Therefore, this dynamic bias circuit provides a bias voltage directly related to the clock signal φ1 period.

[0032] At the end of phase φ1, taking the left-side circuit as an example, Figure 1 The voltage across C1 is V. BN -V CM The voltage across C2 is V. BP -V CM At this point, the source and drain currents of M1 and M2 are equal, and the circuit is in a balanced state. After entering the φ2 stage, the voltage on the left side of the capacitor switches to V. IN The gate voltage of M1 becomes V IN +V BN -V CM The gate voltage of M2 becomes V IN +V BP -V CM If V IN Greater than V CM If the source-drain current of M1 is greater than the source-drain current of M2, the excess current in M1 flows to the output V. ON Power is supplied to the output capacitor, making V ON Rise. When V ON Rise to equal V IN At that time, the gate-source voltages of M1 and M2 are restored to V respectively. BN With V BP Once the source and drain currents are balanced again, the follow-up phase ends.

[0033] Compared to Figure 5 Compared to the conventional source follower demonstrated, the source follower in this embodiment offers the following advantages: (1) No static power consumption, enabling event-driven operation.

[0034] (2) A push-pull structure is adopted, which doubles the equivalent transconductance of the circuit. When operating in follower mode, the transconductance of the push-pull source follower in this embodiment is... G m and output impedance R out As shown below, the magnification factor is approximately 1.

[0035]

[0036]

[0037] (3) There is no fixed DC level offset between input and output.

[0038] (4) Lower input equivalent thermal noise and higher current utilization. The input equivalent thermal noise of a traditional source follower is:

[0039] in: k Boltzmann's constant, γ The noise figure of the MOSFET; the NMOS transistor M that provides current. n3 It only contributes noise, not transconductance. The equivalent thermal noise of the input in this embodiment is as follows, and the input noise is significantly reduced under the same current.

[0040]

[0041] (5) Lower flicker noise and DC offset. Traditional source followers typically operate in a pure continuous-time state. Without chopping, flicker noise has a significant impact, and M n3 and M n4 The flicker noise will be directly superimposed. In the push-pull source follower of this embodiment, during the φ1 stage, the circuit samples the bias voltage and stores the low-frequency flicker noise and the DC offset voltage of the transistor in the corresponding capacitors. In the subsequent following stage, the stored offset and low-frequency noise are effectively eliminated through charge conservation and differential cancellation mechanisms.

[0042] (6) Higher power supply noise rejection ratio. In the traditional source follower structure, high-frequency ripple and noise on the power rail can easily be directly coupled to the output through the drain-source path of the transistor; however, in the push-pull source follower of this embodiment, the floating power supply is disconnected from the external power supply during the following stage, and the power supply noise cannot be directly coupled to the output, which fundamentally improves the power supply noise rejection ratio of the system.

[0043] Figure 6 The output performance of the push-pull source follower in this embodiment is compared with that of the conventional structure under the conditions of a common-mode level of 600mV and a DC differential input of 200mV. Experimental results show that the present invention achieves dynamic tracking function without consuming static power consumption and effectively eliminates the fixed DC offset present in the conventional structure.

[0044] Figure 7 The simulation results show the average power consumption of the push-pull source follower in this embodiment as a function of the operating frequency when using dynamic bias. It can be seen that by combining the structure of this invention with dynamic bias, a wide operating frequency range can be achieved, and the power consumption changes linearly with the frequency, thereby realizing dynamic operation. Figure 8 The simulation results of the input-output gain of the push-pull source follower in this embodiment as a function of operating frequency are shown under the same bias conditions. As can be seen from the figure, the structure of the present invention can maintain the stability of the gain over a wide operating frequency range.

[0045] Therefore, this invention, based on a floating power supply, solves the voltage margin problem of traditional source followers at low power supply voltages through a capacitor-biased push-pull source follower structure, and achieves high current efficiency through current multiplexing. Simultaneously, by using an energy storage capacitor as a floating power supply, this invention effectively fixes the output common-mode voltage, solving the problem of traditional source followers being sensitive to process, voltage, and temperature variations.

[0046] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A push-pull source follower based on a floating power supply, characterized in that: It includes a differential follower unit and an energy storage capacitor unit. The follower unit adopts a capacitor-biased push-pull source follower structure and achieves high current efficiency signal following through current multiplexing. The energy storage capacitor unit uses an energy storage capacitor as a floating power source, which supplies power to the follower unit after reset and effectively fixes the output common-mode voltage.

2. The push-pull source follower based on a floating power supply according to claim 1, characterized in that: The follower unit adopts a push-pull structure composed of NMOS and PMOS transistors. The input signal is coupled to the gate of the MOS transistor through a capacitor, so that the NMOS and PMOS transistors are simultaneously turned on and current multiplexed during the amplification stage, achieving signal following with high current efficiency. During the reset stage, the input capacitor and the common-mode voltage at the output terminal are preset to ensure that the output common-mode voltage is stable during the amplification stage.

3. The push-pull source follower based on a floating power supply according to claim 1, characterized in that: The energy storage capacitor unit includes a energy storage capacitor C. RES And four switches S1, S2, S3, and S4, one end of which is connected to the power supply voltage V. DD The other end of S1 is connected to C RES One end of S2 is connected to one end of S3, one end of S2 is grounded, and the other end of S2 is connected to C. RES The other end of S1 is connected to one end of S4. The other end of S3 serves as the floating power rail of the energy storage capacitor unit, and the other end of S4 serves as the floating ground rail of the energy storage capacitor unit. The on / off state of switches S1 and S2 is controlled by clock signal φ1, and the on / off state of switches S3 and S4 is controlled by clock signal φ2.

4. The push-pull source follower based on a floating power supply according to claim 1, characterized in that: The follower unit includes two NMOS transistors M1 and M2, two PMOS transistors M3 and M4, four capacitors C1, C2, C3, and C4, and eight switches S5, S6, S7, S8, S9, and S1. 10 S 11 S 12 The drains of M1 and M2 are connected to the floating power rail of the energy storage capacitor unit. The drains of M3 and M4 are connected to the floating ground rail of the energy storage capacitor unit. The sources of M1 and M3, as well as one end of S5, are connected as the inverting output of the push-pull source follower. The sources of M2 and M4, as well as one end of S6, are connected as the non-inverting output of the push-pull source follower. The gate of M1 is connected to one end of C1 and one end of S9. The gate of M2 is connected to one end of C3 and S9. 10 One end of M3 is connected to the gate of C2 and the S. 11 One end is connected, the gate of M4 is connected to one end of C4 and S 12 One end of S5 is connected to the other end of S6, and the other end of S5 is connected to the common-mode voltage V. CM The other end of C1 is connected to the other end of C2 and one end of S7 as the inverting input of the push-pull source follower. The other end of C3 is connected to the other end of C4 and one end of S8 as the non-inverting input of the push-pull source follower. The other ends of S7 and S8 are connected to the common-mode voltage V. CM The other end of S9 is connected to S 10 The other end is connected to the bias voltage V BN S 11 The other end and S 12 The other end is connected to the bias voltage V BP Eight switches S5~S 12 The on / off state is controlled by the clock signal φ1.

5. The push-pull source follower based on a floating power supply according to claim 3, characterized in that: The clock signal φ1 is used to close the switch during the system reset phase, and the clock signal φ2 is used to close the switch during the amplification phase. φ1 and φ2 are complementary in phase and have a certain dead time.

6. The push-pull source follower based on a floating power supply according to claim 4, characterized in that: The bias voltage V BN and V BP Generated by a static bias circuit, which includes an amplifier OTA and two NMOS transistors M. n1 and M n2 A PMOS transistor M p1 And a current source, one end of which is connected to the power supply voltage V. DD The other end of the current source is connected to M n1 The drain and gate are connected to generate a bias voltage V. BN M n1 The source and M p1 The source terminal of the OTA is connected to the non-inverting input terminal, and the inverting input terminal of the OTA is connected to the common-mode voltage V. CM OTA output terminal and M n2 The gate is connected to M. n2 The source is grounded, M n2 The drain and M p1 The drain and gate are connected to generate a bias voltage V. BP .

7. The push-pull source follower based on a floating power supply according to claim 4, characterized in that: The bias voltage V BN and V BP Generated by a dynamic bias circuit, which includes an energy storage capacitor C. RES2 Two NMOS transistors M5 and M6, two PMOS transistors M7 and M8, and four switches S 13 S 14 S 15 S 16 S 13 One end is connected to the power supply voltage V DD S 13 The other end and C RES2 one end and S 15 One end is connected, S 14 One end is grounded, S 14 The other end and C RES2 The other end and S 16 One end is connected, S 15 The other end is connected to the drain of M5, the gate of M5, the drain of M6, and the gate of M6 to generate a bias voltage V. BN S 16 The other end is connected to the drain of M7, the gate of M7, the drain of M8, and the gate of M8 to generate a bias voltage V. BP The source of M5 is connected to the source of M7, and the source of M6 is connected to the source of M8. The four switches S... 13 ~S 16 The on / off state is controlled by the clock signal φ1.

8. The push-pull source follower based on a floating power supply according to claim 7, characterized in that: The dynamic bias circuit provides dynamic bias voltage to the follower unit according to the different periods of the clock signal φ1.

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