A time synchronization method and apparatus

Abstract

The application provides a time synchronization method and device, relates to the technical field of communication, and is used for realizing time synchronization of a plurality of dies in a core particle system. The method is applied to a communication device, the communication device comprises a first die and a second die interconnected through a core particle interface, and the first die and the second die are further interconnected through a first synchronization interface. The method comprises the following steps: the first die sends a first synchronization signal through the first synchronization interface; the second die receives the first synchronization signal through the first synchronization interface; a first sending timestamp is acquired, the first sending timestamp indicates a timestamp of sending the first synchronization signal; a first receiving timestamp is acquired, the first receiving timestamp indicates a timestamp of receiving the first synchronization signal; wherein the first sending timestamp and the first receiving timestamp are used for determining a time deviation between the first die and the second die, and the time deviation is used for time synchronization of the first die and the second die.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a time synchronization method and apparatus. Background Technology

[0002] As the pace of advanced process iterations slows and Moore's Law gradually diminishes, the development cost and complexity of advanced processes are increasing daily. Affected by factors such as chip heat dissipation, transmission bandwidth, and manufacturing yield, chip development has encountered bottlenecks such as the "power consumption wall, memory wall, and area wall," limiting the performance improvement of individual chips.

[0003] Chiplet technology can package different dies together using die-to-die interconnect technology to form a complete chiplet system without changing the manufacturing process. The different dies in this chiplet system can be flexibly designed and selected as needed, thus greatly improving the system's performance. During operation, multiple dies in this chiplet system need to work collaboratively at the same time reference to ensure data consistency and coordination, and improve system reliability and efficiency. Therefore, a method for achieving time synchronization of multiple dies in a chiplet system is urgently needed. Summary of the Invention

[0004] This application provides a time synchronization method and apparatus for achieving time synchronization of multiple dies in a die system.

[0005] Firstly, a time synchronization method is provided, applied in a communication device. The communication device includes a first die and a second die interconnected via a die interface, and the first die and the second die are also interconnected via a first synchronization interface. Exemplarily, the communication device is a die system or a communication device containing a die system, with the first die and the second die packaged together and having the same clock frequency. The method includes: the first die transmitting a first synchronization signal through the first synchronization interface; the second die receiving the first synchronization signal through the first synchronization interface; obtaining a first transmission timestamp, the first transmission timestamp indicating the timestamp of transmitting the first synchronization signal; obtaining a first reception timestamp, the first reception timestamp indicating the timestamp of receiving the first synchronization signal; wherein the first transmission timestamp and the first reception timestamp are used to determine the time deviation between the first die and the second die, and this time deviation is used for time synchronization between the first die and the second die, for example, correcting the time of the first die or the second die based on the time deviation to complete time synchronization. Optionally, the first synchronization interface includes: a general purpose input / output (GPIO) interface, or a serializer / deserializer (SerDers) interface.

[0006] In the above technical solution, the first die and the second die transmit a first synchronization signal through a first synchronization interface, and obtain the first transmission timestamp and the first reception timestamp of the first synchronization signal. Based on the first transmission timestamp and the first reception timestamp, the time deviation between the first die and the second die is determined, and the time synchronization between the first die and the second die in the communication device is achieved based on the time deviation.

[0007] In one possible implementation of the first aspect, the first and second dies are baseband dies, meaning two or more baseband dies are packaged together using die-packing technology to form a larger-scale, high-specification baseband chip. In the aforementioned possible implementation, when the communication device includes two packaged baseband dies, the two baseband dies can achieve high-precision time synchronization by transmitting synchronization signals through a synchronization interface, ensuring that different baseband dies can work collaboratively and achieve precise alignment of data transmission and reception.

[0008] In one possible implementation of the first aspect, the time deviation is determined based on the difference between the first receive timestamp and the first send timestamp, and the transmission delay between the first die and the second die. Optionally, the transmission delay may be preset and stored in the communication device. For example, the time deviation is equal to the difference minus the transmission delay. In the above possible implementations, the time deviation between the first die and the second die can be quickly determined based on the difference between the first send timestamp and the first receive timestamp, and the transmission delay between the first die and the second die.

[0009] In one possible implementation of the first aspect, the first synchronization signal is transmitted periodically, and the time deviation is determined based on the differences between multiple first receive timestamps and multiple first send timestamps, as well as the transmission delay; wherein the multiple first send timestamps and the multiple first receive timestamps correspond to first synchronization signals for multiple synchronization periods. In the above possible implementation, by periodically transmitting the first synchronization signal and determining the time deviation based on the first send timestamps and first receive timestamps corresponding to the first synchronization signals for multiple synchronization periods, as well as the transmission delay, the accuracy of the time deviation can be improved.

[0010] In one possible implementation of the first aspect, the first die and the second die are also interconnected via a second synchronization interface. Optionally, the second synchronization interface includes a general purpose input / output (GPIO) interface or a serializer / deserializer (SerDers) interface. The method further includes: the second die transmitting a second synchronization signal via the second synchronization interface; the first die receiving the second synchronization signal via the second synchronization interface; obtaining a second transmission timestamp, which indicates the time of transmitting the second synchronization signal; obtaining a second reception timestamp, which indicates the time of receiving the second synchronization signal; wherein the second transmission timestamp and the second reception timestamp are used to determine the time deviation. In the above possible implementation, the first die and the second die can transmit the first synchronization signal via the first synchronization interface and the second synchronization signal via the second synchronization interface, and obtain the first transmission timestamp and the first reception timestamp of the first synchronization signal, as well as the second transmission timestamp and the second reception timestamp of the second synchronization signal. Based on the first transmission timestamp, the first reception timestamp, the second transmission timestamp, and the second reception timestamp, the time deviation between the first die and the second die is determined, and high-precision time synchronization is achieved between the dies based on this time deviation.

[0011] In one possible implementation of the first aspect, the time deviation is determined based on the difference between the first receiving timestamp and the first sending timestamp, and the difference between the second receiving timestamp and the second sending timestamp. Optionally, the time deviation is determined based on a first difference between the first receiving timestamp and the first sending timestamp, and a second difference between the second receiving timestamp and the second sending timestamp. For example, the time deviation is equal to half of a third difference, which is equal to the first difference minus the second difference. In the above possible implementations, determining the time deviation based on the difference between the first receiving timestamp and the first sending timestamp, and the difference between the second receiving timestamp and the second sending timestamp, can improve the accuracy of the time deviation.

[0012] In one possible implementation of the first aspect, the first synchronization signal and the second synchronization signal are transmitted periodically, and the time deviation is determined based on the differences between multiple first receiving timestamps and multiple first sending timestamps, and the differences between multiple second receiving timestamps and multiple second sending timestamps; wherein the multiple first sending timestamps and the multiple first receiving timestamps correspond to multiple synchronization periods of the first synchronization signal, and the multiple second sending timestamps and the multiple second receiving timestamps correspond to multiple periods of the second synchronization signal. In the above possible implementation, by periodically transmitting the first synchronization signal and the second synchronization signal, and determining the time deviation based on the first sending timestamps and first receiving timestamps corresponding to the first synchronization signals in multiple synchronization periods, and the second sending timestamps and second receiving timestamps corresponding to the second synchronization signals in multiple synchronization periods, the accuracy of the time deviation can be improved.

[0013] In a second aspect, a communication device is provided, comprising a first die and a second die interconnected via a die interface, the first die and the second die also interconnected via a first synchronization interface; the first die is configured to transmit a first synchronization signal via the first synchronization interface; the second die is configured to receive the first synchronization signal via the first synchronization interface; the first die is further configured to acquire a first transmission timestamp, the first transmission timestamp indicating the timestamp of transmitting the first synchronization signal; the second die is further configured to acquire a first reception timestamp, the first reception timestamp indicating the timestamp of receiving the first synchronization signal; wherein the first transmission timestamp and the first reception timestamp are used to determine the time deviation between the first die and the second die, the time deviation being used for time synchronization between the first die and the second die.

[0014] In one possible implementation of the second aspect, the first die and the second die are baseband dies.

[0015] In one possible implementation of the second aspect, the time offset is determined based on the difference between the first receive timestamp and the first send timestamp, and the transmission delay between the first die and the second die.

[0016] In one possible implementation of the second aspect, the first synchronization signal is transmitted periodically, and the time deviation is determined based on the difference between a plurality of first receive timestamps and a plurality of first send timestamps, as well as the transmission delay; wherein the plurality of first send timestamps and the plurality of first receive timestamps correspond to the first synchronization signal of a plurality of synchronization periods.

[0017] In one possible implementation of the second aspect, the first die and the second die are also interconnected via a second synchronization interface; the second die is further used to transmit a second synchronization signal via the second synchronization interface; the first die is further used to receive the second synchronization signal via the second synchronization interface; the second die is further used to acquire a second transmission timestamp, which indicates the timestamp of transmitting the second synchronization signal; the first die is further used to acquire a second reception timestamp, which indicates the timestamp of receiving the second synchronization signal; wherein the second transmission timestamp and the second reception timestamp are used to determine the time deviation.

[0018] In one possible implementation of the second aspect, the time offset is determined based on the difference between the first receiving timestamp and the first sending timestamp, and the difference between the second receiving timestamp and the second sending timestamp.

[0019] In one possible implementation of the second aspect, the first synchronization signal and the second synchronization signal are transmitted periodically, and the time deviation is determined based on the differences between a plurality of first receiving timestamps and a plurality of first sending timestamps, and the differences between a plurality of second receiving timestamps and a plurality of second sending timestamps; wherein the plurality of first sending timestamps and the plurality of first receiving timestamps correspond to a plurality of first synchronization signals for a plurality of synchronization periods, and the plurality of second sending timestamps and the plurality of second receiving timestamps correspond to a plurality of second synchronization signals for a plurality of periods.

[0020] In one possible implementation of the second aspect, the first or second synchronization interface includes: a general purpose input / output (GPIO) interface, or a serializer / deserializer (SerDers) interface.

[0021] In another aspect of this application, a computer-readable storage medium is provided, which stores a computer program or instructions that, when executed on a device, cause the device to perform a time synchronization method as provided in the first aspect or any possible implementation thereof.

[0022] In another aspect of this application, a computer program product is provided, comprising: a computer program (also referred to as code or instructions) that, when run by a device, causes the device to perform a time synchronization method as provided in the first aspect or any possible implementation thereof.

[0023] Understandably, the beneficial effects achieved by any of the communication devices, computer-readable storage media, and computer program products provided above can be referred to in accordance with the beneficial effects of the time synchronization methods provided above, and will not be repeated here. Attached Figure Description

[0024] Figure 1 This application provides a schematic diagram of the structure of a wireless communication system according to an embodiment of the present application.

[0025] Figure 2 This is a schematic diagram of the structure of a wireless communication device provided in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of another communication device provided in an embodiment of this application;

[0028] Figure 5 A flowchart illustrating a time synchronization method provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram illustrating the transmission of a first synchronization signal between dies, provided as an embodiment of this application;

[0030] Figure 7 A timing diagram for transmitting a first synchronization signal provided in an embodiment of this application;

[0031] Figure 8 A flowchart illustrating another time synchronization method provided in an embodiment of this application;

[0032] Figure 9 A schematic diagram illustrating the transmission of a first synchronization signal and a second synchronization signal between dies, provided as an embodiment of this application;

[0033] Figure 10 A timing diagram for transmitting a first synchronization signal and a second synchronization signal is provided for an embodiment of this application;

[0034] Figure 11 This is a schematic diagram of the structure of a first bare die provided in an embodiment of this application;

[0035] Figure 12 This is a schematic diagram of another first bare die provided in an embodiment of this application;

[0036] Figure 13 This is a schematic diagram of the structure of a second bare die provided in an embodiment of this application;

[0037] Figure 14 This is a schematic diagram of another second bare die provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0039] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0040] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0041] Before introducing the embodiments of this application, the relevant background of this application will be explained first.

[0042] As the pace of advanced process technology iteration slows and Moore's Law gradually diminishes, the development cost and complexity of advanced processes are increasing daily. Influenced by factors such as chip heat dissipation, transmission bandwidth, and manufacturing yield, chip development has encountered bottlenecks such as the "power wall," "memory wall," and "area wall," limiting the performance improvement of individual chips. Chiplet technology, however, can package different dies together using die-to-die interconnect technology to form a complete chiplet system without changing the manufacturing process. The different dies within this chiplet system can be flexibly designed and selected as needed, thereby significantly improving the performance of the chip system. This chiplet system can also be called a chip system, and the dies within it can be called chips, dies, or small chips.

[0043] The advantages of chip-level technology mainly include the following three points. First, it enables agile chip design through chip-level intellectual property (IP) reuse or prefabrication and combination. Since chips can be designed and assembled independently, manufacturers can choose different types, specifications, or suppliers of chips to combine according to specific needs, improving the flexibility and customizability of chip design. This not only meets the "fragmented" requirements of application scenarios but also significantly shortens the time-to-market. Second, smaller chip sizes lead to higher yields and reduced manufacturing costs. By breaking down large chips into several smaller chips, chip-level technology greatly reduces the probability of failure occurring on a single chip. The resulting integrated chip-level system can achieve breakthroughs in manufacturing area and yield, significantly reducing manufacturing costs. Third, different chips can utilize different process technologies, overcoming the limitations of single-process technologies. Under the chip-level system architecture, chips responsible for different functions no longer need to iterate to a unified process technology. Instead, different chips with optimal node implementations can be mixed and integrated, not only reducing the cost of a single engineering process but also significantly shortening the product launch cycle.

[0044] In the packaged architecture of a die-processor system, time synchronization becomes crucial as multiple dies collaborate to perform complex computational and communication tasks. Different dies may operate in independent clock domains; without precise time synchronization, timing errors, inconsistencies in latency, and even system crashes can occur during data transmission. High-precision time synchronization ensures that multiple dies can work collaboratively on the same time base, avoiding information loss and performance degradation due to clock skew, thereby ensuring system data consistency and coordination, and optimizing overall performance. Furthermore, time synchronization is essential for handling parallel processing tasks across multiple dies, achieving seamless data exchange, and guaranteeing low-latency communication across dies, improving system reliability and efficiency.

[0045] Therefore, in designs focused on cost control, finding a low-cost solution to achieve time synchronization between different dies within the same chip system is particularly important. Achieving time synchronization between different dies within a chip system is especially crucial for cost-effective products used in wireless communication, edge computing, and the Internet of Things (IoT), as it ensures performance while controlling overall costs, enabling efficient chip systems to be competitive across a wide range of markets.

[0046] For example, in wireless transceivers, the overall system performance is limited by the processing power of the baseband chip. As the number of antennas increases, the processing complexity of the baseband chip grows exponentially. Chip-on-chip technology addresses this by co-packing and cascading two low-specification baseband chips to form a larger-scale, high-specification baseband chip. The core of this technology lies in distributing the resource burden of the same node across individual dies, allowing each die to perform computations in parallel to complete signal processing, thereby achieving efficient resource utilization and a larger system scale. For instance, an 8-stream 320MHz bandwidth baseband chip in a Wi-Fi receiver can be co-packaged from two 4-stream 320MHz baseband dies. The two dies exchange high-bandwidth data through a chip-on-chip interface, significantly improving the chip's ability to process large-bandwidth data. However, for the baseband chip, the modules within the two dies need to work in strict parallel coordination to ensure precise alignment of multi-stream data transmission and reception over the air interface. Therefore, high-precision time synchronization must be achieved between the two dies.

[0047] Based on this, this application provides a time synchronization method for achieving time synchronization between a first die and a second die in a die-processing system. The first die and the second die are interconnected through a die-processing interface and a synchronization interface. The first die and the second die can transmit a synchronization signal through the synchronization interface and obtain the transmission timestamp and reception timestamp of the synchronization signal. Based on the transmission timestamp and reception timestamp, the time deviation between the dies is determined to achieve time synchronization.

[0048] The technical solutions provided in this application can be applied to various wireless communication systems. For example, these wireless communication systems may include, but are not limited to: Wi-Fi communication systems, Long Time Evolution (LTE) systems, Frequency Division Duplex (FDD) systems, Time Division Duplex (TDD) systems, Code Division Multiple Access (CDMA) systems, Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) communication systems, Public Land Mobile Network (PLMN) systems, hybrid networking communication systems, or future communication systems. The technical solutions in this application can include various application scenarios, such as enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (uRLLC), and massive machine-type communication (mMTC).

[0049] The wireless communication systems and application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application. As those skilled in the art will know, with the evolution of communication systems and the emergence of new application scenarios, the technical solutions provided in this application are also applicable to similar technical problems.

[0050] It should be understood that in this wireless communication system, devices can be divided into devices that provide wireless network services and devices that use wireless network services. The devices providing wireless network services can also be called network equipment or network units; for example, such network equipment includes wireless access devices. The devices using wireless network services can be called terminal devices or simply terminals. Terminal devices can establish connections with network equipment and provide wireless communication services to users based on the services offered by the network equipment. The following example illustrates the structure of this wireless communication system, which includes wireless access devices and terminal devices.

[0051] Figure 1 This is a schematic diagram of a wireless communication system provided in an embodiment of this application. The wireless communication system may include one or more wireless access devices 10 and one or more terminal devices 20. The terminal devices 20 can communicate wirelessly with the wireless access devices 10, and different wireless access devices 10 and different terminal devices 20 can also communicate with each other. In this wireless communication system, the wireless access device 10 can provide communication coverage for a specific geographical area through integrated or external antenna devices. Terminal devices 20 located within the communication coverage area of ​​the wireless access device 10 can access the wireless access device 10 and communicate with it. Figure 1 Example (a) illustrates the wireless communication system, which includes a wireless access device 10 and three terminal devices 20.

[0052] Optionally, the wireless access device 10 may include a base station, which may also be referred to as a wireless access point or a transmission reception point (TRP). In one possible example, the base station may be a generation Node B (gNB) in a new radio (NR) system, an evolutionary Node B (eNB) in a long-term evolution (LTE) system, etc. Depending on the physical form or transmission power of the base station, it may be classified as a macro base station or a micro base station; a micro base station may also be referred to as a small base station or a small cell.

[0053] Optionally, the terminal device 20 may include, but is not limited to: mobile phones, tablets, laptops, desktop computers, handheld computers, ultra-mobile personal computers (umPCs), mobile internet devices (MIDs), netbooks, cameras, camcorders, wearable devices (such as smartwatches and smart bracelets), in-vehicle devices (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying devices (such as smart robots, hot air balloons, drones, airplanes), etc.

[0054] In one possible embodiment, such as Figure 1 As shown in (b), the wireless communication system is a Wi-Fi communication system, the wireless access device 10 is an access point (AP), and the terminal device 20 is a station (STA). For example, the Wi-Fi communication system includes an AP and three STAs connected to the AP, which can communicate with the AP.

[0055] In this embodiment, both the wireless access device 10 and the terminal device 20 can be referred to as wireless communication devices. The following description uses a mobile phone as an example to illustrate the structure of the wireless communication device.

[0056] Figure 2 This is a schematic diagram of the structure of a wireless communication device provided in an embodiment of this application. The wireless communication device may include components such as a radio frequency (RF) circuit 110, a memory 120, an input unit 130, a display unit 140, a sensor 150, an audio circuit 160, a processor 170, and a power supply 180.

[0057] The RF circuit 110 can be used to transmit and receive information, or to receive or send signals during a call. Specifically, it receives downlink information from the base station and processes it in the processor 170; additionally, it transmits uplink data to the base station. Typically, the RF circuit 110 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, the RF circuit 110 can also communicate wirelessly with networks and other devices.

[0058] The memory 120 can be used to store data, software programs, and modules; it includes a program storage area and a data storage area. The program storage area can store the operating system and applications required for at least one function, such as sound playback and image playback functions. The data storage area can store data created based on the use of the wireless communication device, such as audio data, image data, and a phone book. Furthermore, the wireless communication device may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. In this embodiment, the memory may include multiple memories, including a first memory and a second memory.

[0059] Input unit 130 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the wireless communication device. Input unit 130 may include touch screen 131 and other input devices 132. Touch screen 131 can collect touch operations on or near the user and drive corresponding connection devices according to a pre-set program. For example, touch operations may include operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch screen. Optionally, other input devices 132 may include, but are not limited to, one or more of physical keyboards, function keys, mice, joysticks, etc., such as volume control buttons, power switch buttons, etc.

[0060] Display unit 140 can be used to display information input by the user or information provided to the user, as well as various menus of the wireless communication device. In one example, display unit 140 may include display screen 141, which may be configured as a liquid crystal display (LCD), organic light-emitting diode (OLED), or similar form. Further, touchscreen 131 may cover display screen 141. When touchscreen 131 detects a touch operation on or near it, it transmits the information to processor 170 to determine the type of touch event. Subsequently, processor 170 provides corresponding visual output on display screen 141 based on the type of touch event. Although in the figures, touchscreen 131 and display screen 141 are shown as two separate components to implement the input and output functions of the wireless communication device, in some embodiments, touchscreen 131 and display screen 141 can be integrated to implement the input and output functions of the wireless communication device.

[0061] Sensor 150 may include one or more sensors for providing status assessments of various aspects of the wireless communication device. Sensor 150 may include a light sensor, which can be used in imaging applications, i.e., as a component of a camera or video camera. Furthermore, sensor 150 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor. Sensor 150 can detect acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes of the wireless communication device, etc.

[0062] Audio circuitry 160, a speaker, and a microphone provide an audio interface between the user and the wireless communication device. Audio circuitry 160 converts received audio data into electrical signals, transmits them to the speaker, and the speaker converts them into sound signals for output. On the other hand, the microphone converts collected sound signals into electrical signals, which are received by audio circuitry 160, converted into audio data, and then output to RF circuitry 110 for transmission to, for example, another mobile phone, or to memory 120 for further processing.

[0063] The processor 170 is the control center of the wireless communication device. It connects various parts of the device via various interfaces and lines, and performs overall control by running or executing software programs and / or modules stored in the memory 120, and by calling data stored in the memory 120, thereby executing various functions and processing data. Optionally, the processor 170 includes one or more processing units, which may include, but are not limited to: a central processing unit (CPU), a baseband processor, a network processing unit (NPU), a graphics processing unit (GPU), an image signal processor (ISP), a tensor processing unit (TPU), a data processing unit (DPU), a digital signal processor (DSP), a microcontroller, or a microprocessor. Furthermore, processor 170 may also include other hardware circuitry or accelerators, such as application-specific integrated circuits (ASICs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Optionally, processor 170 may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a digital signal processor, and a microprocessor.

[0064] The wireless communication device may also include a power supply 180 (e.g., a battery) to power various components. The power supply 180 can be logically connected to the processor 170 via a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. Optionally, the power management system can simultaneously support fast charging and non-fast charging technologies. In practical applications, the power management system can charge the battery in the power supply 180 using either fast charging or non-fast charging technologies.

[0065] Optionally, the wireless communication device may also include a Wi-Fi module, a Bluetooth module, etc., which will not be described in detail in the embodiments of this application. Those skilled in the art will understand that... Figure 2The structure of the wireless communication device shown does not constitute a limitation on the wireless communication device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0066] Furthermore, the wireless communication device also includes a communication unit, which may integrate one or more components of the wireless communication device, or integrate one or more bare dies corresponding to the components.

[0067] For example, Figure 3 This is a schematic diagram of a communication device provided in an embodiment of this application. The communication device can be applied to network devices or terminal devices. The communication device includes a first die and a second die packaged together, interconnected via a chip interface and at least one synchronization interface. Furthermore, the communication device may also include multiple channels coupled to the first die and multiple channels coupled to the second die, which can be used to couple with multiple antennas.

[0068] Optionally, each of the first and second dies may include, but is not limited to, at least one processing unit and a timer. At least one processing unit in each die can transmit data through the die interface; the timer in each die can transmit a synchronization signal through the at least one synchronization interface to achieve time synchronization between the first and second dies. The clock signals of the first and second dies can be from the same source, meaning the clock frequency of the first die is the same as the clock frequency of the second die, thus ensuring that the counting step size of the timer in the first die is the same as the counting step size of the timer in the second die.

[0069] Optionally, the synchronization interface may include a general purpose input / output (GPIO) interface, a serializer / deserializer (SerDers) interface, or other interconnect interfaces, etc., and this application embodiment does not impose specific limitations on this. The GPIO interface may include a general purpose output (GPO) interface and a general purpose input (GPI) interface. This synchronization interface can also be called a dedicated interface, that is, an interface specifically used for transmitting synchronization signals to achieve time synchronization. In this application embodiment, at least one synchronization interface between the first die and the second die can be used to achieve time synchronization between the first die and the second die, that is, to achieve cross-die time synchronization.

[0070] Optionally, the first and second dies can be two dies with the same function, or two dies with different functions. For example, both the first and second dies can be baseband dies; or, one of the first and second dies can be a baseband die and the other a non-baseband die. As an example, such as... Figure 4 As shown, both the first and second dies are baseband dies, and they can exchange data via a chip interface after at least one processing node. For example, the baseband die may include multiple time-domain channels in the receiving direction, and multiple processing nodes such as channel estimation, equalization, demodulation, and decoding connected sequentially to these time-domain channels. Each time-domain channel may include an analog front end (AFE), a digital front end (DFE), and a Fast Fourier Transform (FFT). The first and second dies can exchange data after the FFT, equalization, and / or demodulation processing nodes.

[0071] Figure 5 This is a flowchart illustrating a time synchronization method provided in an embodiment of this application. The method can be applied to a communication device, which includes a first die and a second die interconnected via a die interface. The first die and the second die are also interconnected via a first synchronization interface. The method includes the following steps.

[0072] S201: The first die transmits a first synchronization signal through the first synchronization interface, and the first transmission timestamp indicates the timestamp of transmitting the first synchronization signal. Optionally, the first transmission timestamp can be obtained by the first die; for example, the first die can obtain the timestamp of the transmission time of the first synchronization signal to obtain the first transmission timestamp.

[0073] S202: The second die receives the first synchronization signal through the first synchronization interface, and the first reception timestamp indicates the timestamp of receiving the first synchronization signal. Optionally, the first reception timestamp can be obtained by the second die; for example, the second die can obtain the first transmission timestamp by obtaining the timestamp of the reception time of the second synchronization signal.

[0074] In this embodiment of the application, the first transmission timestamp and the first reception timestamp are used to determine the time deviation between the first die and the second die, and the time deviation is used for time synchronization between the first die and the second die.

[0075] Optionally, each of the first and second dies can integrate a timing module for time synchronization, which can be called a timer. The timer in the first die and the timer in the second die can obtain their respective local timestamps by sending and receiving synchronization signals, and calculate the time deviation based on the time of flight (ToF) principle, thereby completing time synchronization based on the time deviation.

[0076] In one possible embodiment, the first die includes a first timer, and the second die includes a second timer. After the communication device is powered on, the upper-layer software can send a reset signal to the first and second dies. Upon receiving the reset signal, the first and second dies can clear their respective timers, and the cleared timers will start counting again. Then, the first timer of the first die can send a first synchronization signal to the second die through a first synchronization interface and obtain the timestamp of the first timer at the time of transmission, i.e., obtain the first transmission timestamp. The second timer of the second die can receive the first synchronization signal through a second synchronization interface and obtain the timestamp of the second timer at the time of reception, i.e., obtain the first reception timestamp. Then, based on the first transmission timestamp and the first reception timestamp, the time deviation between the first and second dies is determined, and the first or second timer is corrected according to the time deviation to complete time synchronization.

[0077] Optionally, the time deviation is determined based on the difference between the first receiving timestamp and the first sending timestamp, and the transmission delay between the first die and the second die. The transmission delay can be pre-set and stored in the communication device, and its specific value can be obtained by those skilled in the art through actual measurement, estimation, or derivation. For example, the time deviation is equal to the difference minus the transmission delay.

[0078] As a possible example, such as Figure 6 As shown in (a), the first die includes Timer 1, the second die includes Timer 2, and the first synchronization interface is a GPIO interface, i.e., the first die side has a GPIO interface and the second die side has a GPIO interface. Then: the first die sends the first synchronization signal through the GPIO interface, and the first transmission timestamp of the transmission time of the first synchronization signal is t. a The second die receives the first synchronization signal through the GPI interface, and the first timestamp of the reception time of the first synchronization signal is t. b Optionally, if the time deviation is expressed as Δ clock , then Δ clock =t b -t a -T.

[0079] As another possible example, Figure 6 As shown in (b), the first die includes Timer 1, the second die includes Timer 2, and the first synchronization interface is a SerDers interface. Then: the first die sends a first synchronization signal through this SerDers interface, and the first transmission timestamp of the first synchronization signal transmission time is t. a The second die receives the first synchronization signal through the SerDers interface, and the first timestamp of the reception time of the first synchronization signal is t. b Optionally, if the time deviation is expressed as Δ clock , then Δ clock =t b -t a -T.

[0080] For example, the above Figure 6 In (a) or (b) of the diagram, the timing diagram for the first die transmitting the first synchronization signal and the second die receiving the first synchronization signal can be as follows: Figure 7 As shown in (a) in the figure.

[0081] Optionally, the first synchronization signal can be transmitted periodically. Each synchronization period can correspond to a first transmission timestamp and a first reception timestamp, and multiple synchronization periods can correspond to multiple first transmission timestamps and multiple first reception timestamps. The time deviation can be determined based on the difference between the multiple first reception timestamps and the multiple first transmission timestamps, as well as the transmission delay.

[0082] In this system, there is a difference between the first receive timestamp and the first send timestamp corresponding to each synchronization period. Multiple synchronization periods correspond to multiple differences, and this time deviation can be determined based on the statistical value of these multiple differences and the transmission delay. Optionally, the statistical value of these multiple differences may include, but is not limited to, the average value, the median value, etc.

[0083] As a possible example, such as Figure 7 As shown in (b), the periodic transmission of a first synchronization signal from the first die to the second die may include: during a first synchronization period, the first die transmits the first synchronization signal to the second die through the GPO interface, and the first transmission timestamp of the transmission time of the first synchronization signal is t. a1 The first timestamp of the first synchronization signal reception time is t. b1 During the second synchronization cycle, the first die sends a first synchronization signal to the second die through the GPO interface. The first transmission timestamp of the first synchronization signal transmission time is t. a2 The first timestamp of the first synchronization signal reception time is t. b2Similarly, during the nth synchronization cycle, the first die sends a first synchronization signal to the second die through the GPO interface, and the first transmission timestamp of the first synchronization signal is t. an The first timestamp of the first synchronization signal reception time is t. bn , where n is a positive integer. Optionally, if the time deviation is expressed as Δ... clock , then Δ clock It satisfies the following formula (1-1)-(1-2).

[0084]

[0085] Δ clock =t b -t a -T (1-2)

[0086] Furthermore, the first and second dies are interconnected via a second synchronization interface, such as... Figure 8 As shown, the method also includes S203-S204. S203-S204 and S201-S202 can be executed in any order; for example, S201-S202 can be executed first, followed by S203-S204, or S203-S204 can be executed first, followed by S201-S202, or S201-S202 and S203-S204 can be executed simultaneously. Figure 8 The example below illustrates this by taking S203-S204 as an example of S201-S202.

[0087] S203: The second die transmits a second synchronization signal through the second synchronization interface, and the second transmission timestamp indicates the timestamp of transmitting the second synchronization signal. Optionally, the second transmission timestamp can be obtained by the second die; for example, the second die can obtain the timestamp of the transmission time of the second synchronization signal to obtain the second transmission timestamp.

[0088] S204: The first die receives the second synchronization signal through the second synchronization interface, and the second reception timestamp indicates the timestamp of receiving the second synchronization signal. Optionally, the second reception timestamp can be obtained by the first die; for example, the second reception timestamp can be obtained by the first die acquiring the timestamp of the moment the second synchronization signal is received.

[0089] In this embodiment, the first transmission timestamp, the first reception timestamp, the second transmission timestamp, and the second reception timestamp are used to determine the time deviation between the first die and the second die, which is used for time synchronization between the first die and the second die. Optionally, the time deviation is determined based on a first difference between the first reception timestamp and the first transmission timestamp, and a second difference between the second reception timestamp and the second transmission timestamp. For example, the time deviation is equal to half of a third difference, and the third difference is equal to the first difference minus the second difference.

[0090] In one possible embodiment, the first die includes a first timer, and the second die includes a second timer. After the communication device is powered on, the upper-layer software can send a reset signal to the first and second dies. Upon receiving the reset signal, the first and second dies can clear their respective timers, and the cleared timers will start counting again. Subsequently, the first die can send a first synchronization signal to the second die through a first synchronization interface. The first die obtains the timestamp of the first timer at the time of transmission (i.e., obtains the first transmission timestamp), and the second die obtains the timestamp of the second timer at the time of reception (i.e., obtains the first reception timestamp). The second die can send a second synchronization signal to the first die through a second synchronization interface. The second die obtains the timestamp of the second timer at the time of transmission (i.e., obtains the second transmission timestamp), and the first die obtains the timestamp of the second timer at the time of reception (i.e., obtains the second reception timestamp). Based on the first transmission timestamp, the first reception timestamp, the second transmission timestamp, and the second reception timestamp, the time deviation between the first and second dies is determined, and the first or second timer is corrected according to the time deviation to complete time synchronization.

[0091] As a possible example, such as Figure 9 As shown in (a), the first die includes Timer 1, and the second die includes Timer 2. Both the first and second synchronization interfaces are GPIO interfaces, meaning that both the first and second dies include GPIO and GPIO interfaces. Therefore, the first die sends the first synchronization signal through the GPIO interface, and the first transmission timestamp of the transmission time of the first synchronization signal is t. a The second die receives the first synchronization signal via the GPI interface. The first timestamp of the reception time of the first synchronization signal is t. b The second die sends a second synchronization signal via the GPO interface. The second transmission timestamp of the second synchronization signal is t. c The first die receives the second synchronization signal via the GPI interface. The second timestamp of the received second synchronization signal is t. d Optionally, if the time deviation is expressed as Δ clock , then Δ clock =[tb -t a -(t d -t c )] / 2.

[0092] Optionally, the aforementioned second synchronization signal can also be transmitted through the first synchronization interface, that is, the first die and the second die transmit the first synchronization signal and the second synchronization signal through the same synchronization interface.

[0093] As another possible example, Figure 9 As shown in (b), the first die includes Timer 1, the second die includes Timer 2, and the first synchronization interface is a SerDers interface. Then: the first die sends a first synchronization signal through this SerDers interface, and the first transmission timestamp of the first synchronization signal transmission time is t. a The second die receives the first synchronization signal through the SerDers interface, and the first timestamp of the reception time of the first synchronization signal is t. b The second die sends a second synchronization signal through the SerDers interface, and the second transmission timestamp of the second synchronization signal is t. c The first die receives the second synchronization signal through the SerDers interface, and the second timestamp of the time of receiving the second synchronization signal is t. d Optionally, if the time deviation is expressed as Δ clock , then Δ clock =[t b -t a -(t d -t c )] / 2.

[0094] Optionally, the first synchronization signal and the second synchronization signal can be transmitted serially or in parallel. Specifically, when the first synchronization signal and the second synchronization signal are transmitted through different synchronization interfaces, they can be transmitted in parallel or serially; when they are transmitted through the same synchronization interface, they can be transmitted serially. For example, the above... Figure 9 In (a) or (b) of the diagram, the timing diagram for the first die transmitting the first synchronization signal and receiving the second synchronization signal, and the timing diagram for the second die receiving the first synchronization signal and transmitting the second synchronization signal, can be as follows: Figure 10 As shown in (a) or (b) in the text. Figure 10 In (a) of the diagram, the first synchronization signal and the second synchronization signal are transmitted in parallel. Figure 10 In (b) of the above, the first synchronization signal and the second synchronization signal are transmitted serially.

[0095] Optionally, the first synchronization signal and the second synchronization signal can be transmitted periodically. Each synchronization period's first synchronization signal can correspond to a first transmission timestamp and a first reception timestamp, and each synchronization period's second synchronization signal can correspond to a second transmission timestamp and a second reception timestamp. Multiple synchronization periods can correspond to multiple first transmission timestamps and multiple first reception timestamps, as well as multiple second transmission timestamps and multiple second reception timestamps. The time deviation can be determined based on the differences between the multiple first reception timestamps and the multiple first transmission timestamps, and the differences between the multiple second reception timestamps and the multiple second transmission timestamps.

[0096] In this system, a first difference exists between the first receive timestamp and the first send timestamp corresponding to each synchronization period, and a second difference exists between the second receive timestamp and the second send timestamp corresponding to each synchronization period. Multiple synchronization periods correspond to multiple first differences and multiple second differences. The time deviation can be determined based on the statistical values ​​of these multiple first differences and multiple second differences. Optionally, a third difference can be obtained based on a first difference and a second difference, thus multiple first differences and multiple third differences can correspond to multiple third differences. The time deviation can be the statistical value of these multiple third differences. For example, the statistical value may include, but is not limited to, the average value, the median value, etc.

[0097] As a possible example, such as Figure 10 As shown in (c) or (d) in the diagram, a first synchronization signal and a second synchronization signal are periodically transmitted between the first die and the second die. Figure 10 In (c), the first synchronization signal and the second synchronization signal are transmitted in parallel. Figure 10 In (d) of the diagram, the first synchronization signal and the second synchronization signal are transmitted serially. Specifically, in n synchronization cycles, the first transmission timestamp of the first synchronization signal is t. a1 t a2 t a3 …, the first timestamp of the first synchronization signal reception time is t b1 t b2 t b3 …, where n is a positive integer; in n synchronization cycles, the second transmission timestamp of the second synchronization signal transmission time is t respectively. c1 t c2 t c3 …, the second timestamp of the second synchronization signal reception time is t d1 t d2 t d3 …Optionally, if the time deviation is expressed as Δ clock , then Δ clockIt satisfies the following formula (2-1)-(2-3).

[0098]

[0099] Δ clock =[t b -t a -(t d -T c )] / 2 (2-3)

[0100] Optionally, the steps of determining the time deviation between the first and second dies, and correcting the first or second timer based on the time deviation, can be performed by the first or second die, or by other modules besides the first and second dies. For example, the first and second dies can send their respective timestamps to the central processing unit (CPU) for execution.

[0101] In one possible embodiment, the time deviation Δ between the first die and the second die is determined. clock Then, the time deviation Δ can be subtracted from the timestamp of the second timer in the second die. clock Alternatively, add the time deviation Δ to the timestamp of the first timer in the first die. clock This achieves alignment of the timestamps of the first timer and the second timer, thus enabling time synchronization between the first and second dies.

[0102] In this embodiment, the first die and the second die can transmit a first synchronization signal through a first synchronization interface and a second synchronization signal through a second synchronization interface. The first transmission timestamp and the first reception timestamp of the first synchronization signal, as well as the second transmission timestamp and the second reception timestamp of the second synchronization signal, are obtained. Based on the first transmission timestamp, the first reception timestamp, the second transmission timestamp, and the second reception timestamp, the time deviation between the first die and the second die is determined. Based on this time deviation, high-precision time synchronization is achieved between the dies, thereby ensuring the collaborative work between the dies and achieving precise alignment of data transmission and reception between different dies.

[0103] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first die and the second die. It is understood that, in order to achieve the above functions, the first die and the second die include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0104] This application embodiment can divide the first die and the second die into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of each functional module according to each function as an example.

[0105] When using integrated units, Figure 11 A schematic diagram of the structure of a first die involved in the above embodiments is shown. The first die includes: a transmitting unit 301, a receiving unit 302, and a processing unit 303. In one possible embodiment, the transmitting unit 301 is used to support the first die in performing S201 in the above method embodiments; the receiving unit 302 is used to support the first die in performing S204 in the above method embodiments; the processing unit 303 is used to support the first die in performing one or more steps in the above method embodiments, such as obtaining a first transmitting timestamp, obtaining a second receiving timestamp, and / or determining the time deviation between the first die and the second die.

[0106] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here in the embodiments of this application.

[0107] Based on hardware implementation, the processing unit 303 in this embodiment can be the processor of the first die, the sending unit 301 can be the transmitter of the first die, and the receiving unit 302 can be the receiver of the first die. The transmitter can usually be integrated with the receiver as a transceiver. The specific transceiver can also be called a communication interface or interface circuit.

[0108] like Figure 12The diagram shown illustrates another structural design of the first die according to the embodiments described above in this application. The first die includes a processor 312, a memory 311, and a communication interface 313. Both the processor 312 and the memory 311 are connected to the communication interface 313. Optionally, the communication interface includes a die interface and a synchronization interface. In one possible embodiment, the processor 312 supports the first die in performing one or more steps in the above method embodiments, such as obtaining a first transmission timestamp, obtaining a second reception timestamp, or determining the time deviation between the first die and the second die. The communication interface 313 supports the first die in communication, for example, communication between the first die and the second die.

[0109] In this embodiment, processor 312 can be a processor, which may include a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0110] When using integrated units, Figure 13 A schematic diagram of the structure of a second die involved in the above embodiments is shown. The second die includes: a receiving unit 401, a transmitting unit 402, and a processing unit 403. In one possible embodiment, the receiving unit 401 is used to support the second die in executing S202 in the above method embodiments; the transmitting unit 402 is used to support the second die in executing S203 in the above method embodiments; the processing unit 403 is used to support the second die in executing one or more steps in the above method embodiments, such as obtaining a first receiving timestamp, obtaining a second transmitting timestamp, and / or determining the time deviation between the first die and the second die.

[0111] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here in the embodiments of this application.

[0112] Based on hardware implementation, the processing unit 403 in this embodiment can be a processor of the second die, the receiving unit 401 can be a receiver of the second die, and the sending unit 402 can be a transmitter of the second die. The transmitter can usually be integrated with the receiver as a transceiver. The specific transceiver can also be called a communication interface or interface circuit.

[0113] like Figure 14The diagram shown illustrates another structural design of the second die according to the embodiments described above. The second die includes a processor 412, a memory 411, and a communication interface 413. Both the processor 412 and the memory 411 are connected to the communication interface 413. Optionally, the communication interface includes a die interface and a synchronization interface. In one possible embodiment, the processor 412 supports the second die in performing one or more steps in the above method embodiments, such as obtaining a first receiving timestamp, obtaining a second sending timestamp, or determining the time deviation between the first and second dies. The communication interface 413 supports the second die in communication, for example, communication between the first and second dies.

[0114] In this embodiment, processor 412 can be a processor, which may include a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0115] In another embodiment of this application, a communication device is provided, comprising a first die and a second die connected via a die interface and at least one synchronization interface; wherein the first die can be as described above. Figure 11 or Figure 12 The provided die is used to perform the steps of the first die in the method embodiment described above; the second die can be the one described above. Figure 13 or Figure 14 The provided die is used to perform the steps of the second die in the method embodiments described above. Optionally, the communication device can be a chip system or a wireless communication device.

[0116] It is understood that all relevant content of each step involved in the above method embodiments can be referenced in the embodiments of the communication device, and the embodiments of this application will not be repeated here.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0118] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium may include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0120] In another embodiment of this application, a readable storage medium is also provided, which stores a computer program or instructions that, when a device runs the computer program or instructions, cause the device to perform the steps of the first die in the above method embodiment.

[0121] In another embodiment of this application, a readable storage medium is also provided, which stores a computer program or instructions that, when a device runs the computer program or instructions, cause the device to perform the steps of the second die in the above method embodiment.

[0122] In another embodiment of this application, a computer program product is also provided, which includes a computer program that, when executed by a device, causes the device to perform the steps of the first die in the above method embodiment.

[0123] In another embodiment of this application, a computer program product is also provided, which includes a computer program that, when executed by a device, causes the device to perform the steps of the second die in the above method embodiment.

[0124] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A time synchronization method, characterized in that, Applied in a communication device, the communication device including a first die and a second die interconnected via a die interface, the first die and the second die also interconnected via a first synchronization interface, the method comprising: The first die sends a first synchronization signal through the first synchronization interface; The second die receives the first synchronization signal through the first synchronization interface; Obtain the first transmission timestamp, which indicates the timestamp at which the first synchronization signal was transmitted; Obtain the first received timestamp, which indicates the timestamp at which the first synchronization signal was received; The first sending timestamp and the first receiving timestamp are used to determine the time deviation between the first die and the second die, and the time deviation is used for time synchronization between the first die and the second die.

2. The method according to claim 1, characterized in that, The first die and the second die are baseband dies.

3. The method according to claim 1, characterized in that, The time deviation is determined based on the difference between the first received timestamp and the first sent timestamp, and the transmission delay between the first die and the second die.

4. The method according to any one of claims 1-3, characterized in that, The first synchronization signal is sent periodically, and the time deviation is determined based on the difference between multiple first receiving timestamps and multiple first sending timestamps, as well as the transmission delay; wherein the multiple first sending timestamps and the multiple first receiving timestamps correspond to the first synchronization signal of multiple synchronization periods.

5. The method according to claim 1, characterized in that, The first die and the second die are also interconnected via a second synchronization interface, and the method further includes: The second die sends a second synchronization signal through the second synchronization interface; The first die receives the second synchronization signal through the second synchronization interface; Obtain the second transmission timestamp, which indicates the timestamp at which the second synchronization signal was transmitted; Obtain a second received timestamp, which indicates the timestamp at which the second synchronization signal was received; The second sending timestamp and the second receiving timestamp are used to determine the time deviation.

6. The method according to claim 5, characterized in that, The time deviation is determined based on the difference between the first receiving timestamp and the first sending timestamp, and the difference between the second receiving timestamp and the second sending timestamp.

7. The method according to claim 5 or 6, characterized in that, The first synchronization signal and the second synchronization signal are transmitted periodically, and the time deviation is determined based on the differences between multiple first receiving timestamps and multiple first sending timestamps, and the differences between multiple second receiving timestamps and multiple second sending timestamps; wherein, the multiple first sending timestamps and the multiple first receiving timestamps correspond to the first synchronization signal of multiple synchronization periods, and the multiple second sending timestamps and the multiple second receiving timestamps correspond to the second synchronization signal of multiple periods.

8. The method according to any one of claims 1-7, characterized in that, The first or second synchronization interface includes: a general purpose input / output (GPIO) interface, or a serializer / deserializer (SerDers) interface.

9. A communication device, characterized in that, The communication device includes a first die and a second die interconnected via a die interface, and the first die and the second die are also interconnected via a first synchronization interface; The first die is used to send a first synchronization signal through the first synchronization interface; The second die is used to receive the first synchronization signal through the first synchronization interface; The first die is also used to obtain a first transmission timestamp, which indicates the timestamp when the first synchronization signal was transmitted; The second die is also used to obtain a first receiving timestamp, the first receiving timestamp indicating the timestamp of receiving the first synchronization signal; The first sending timestamp and the first receiving timestamp are used to determine the time deviation between the first die and the second die, and the time deviation is used for time synchronization between the first die and the second die.

10. The apparatus according to claim 9, characterized in that, The first die and the second die are baseband dies.

11. The apparatus according to claim 10, characterized in that, The time deviation is determined based on the difference between the first received timestamp and the first sent timestamp, and the transmission delay between the first die and the second die.

12. The apparatus according to any one of claims 9-11, characterized in that, The first synchronization signal is sent periodically, and the time deviation is determined based on the difference between multiple first receiving timestamps and multiple first sending timestamps, as well as the transmission delay; wherein the multiple first sending timestamps and the multiple first receiving timestamps correspond to the first synchronization signal of multiple synchronization periods.

13. The apparatus according to claim 9, characterized in that, The first die and the second die are also interconnected via a second synchronization interface; The second die is also used to send a second synchronization signal through the second synchronization interface; The first die is also used to receive the second synchronization signal through the second synchronization interface; The second die is also used to obtain a second transmission timestamp, which indicates the timestamp when the second synchronization signal was transmitted; The first die is also used to obtain a second receiving timestamp, the second receiving timestamp indicating the timestamp of receiving the second synchronization signal; The second sending timestamp and the second receiving timestamp are used to determine the time deviation.

14. The apparatus according to claim 13, characterized in that, The time deviation is determined based on the difference between the first receiving timestamp and the first sending timestamp, and the difference between the second receiving timestamp and the second sending timestamp.

15. The apparatus according to claim 13 or 14, characterized in that, The first synchronization signal and the second synchronization signal are transmitted periodically, and the time deviation is determined based on the differences between multiple first receiving timestamps and multiple first sending timestamps, and the differences between multiple second receiving timestamps and multiple second sending timestamps; wherein, the multiple first sending timestamps and the multiple first receiving timestamps correspond to the first synchronization signal of multiple synchronization periods, and the multiple second sending timestamps and the multiple second receiving timestamps correspond to the second synchronization signal of multiple periods.

16. The apparatus according to any one of claims 9-15, characterized in that, The first or second synchronization interface includes: a general purpose input / output (GPIO) interface, or a serializer / deserializer (SerDers) interface.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on the device, cause the device to perform the method as described in any one of claims 1-8.

18. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a device, causes the device to perform the method as described in any one of claims 1-8.

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