A multi-device visual fault recording method and system

Abstract

The application discloses a kind of multi-device visual fault recording methods and systems related to energy storage converter control technical field, to solve data storage redundancy, transmission anti-interference ability is weak, multi-device time synchronization precision is poor and visual interaction single etc. problem.The application is based on the DSP of energy storage converter and realizes output closed-loop control core task, simultaneously by built-in ADC module, bus voltage is sampled in real time, dynamically adjusts PWM pulse signal to control IGBT device on-off, realizes output voltage closed-loop regulation and control;After MCU receives the fault interrupt signal of DSP, start fault recording process, collect voltage by ADC and first store in SRAM then store in external FLASH;Voltage data and fault recording data are transmitted to total display station by differential shielded twisted pair and Ethernet link respectively by each energy storage converter.The application improves the accuracy of fault recording and the efficiency of multi-device cooperation, provides technical support for power system stable operation.

Description

Technical Field

[0001] This invention relates to a method and system for visualizing fault recording of multiple devices, belonging to the field of energy storage converter control technology. Background Technology

[0002] In power electronic systems, energy storage converters are core devices, and their voltage output stability directly affects the operational safety of the entire system. Fault recording and voltage oscilloscopes are key methods for monitoring the operating status of energy storage converters and troubleshooting faults. Current technologies often employ a single-chip architecture for fault recording, which suffers from slow response speed, low data storage reliability, and difficulty in synchronous monitoring of multiple devices. While a single digital signal processor architecture offers strong computing power, its data storage and peripheral expansion capabilities are limited. A single microprocessor architecture struggles to meet the real-time requirements of voltage closed-loop control. Furthermore, traditional fault recording response times are typically in the microsecond range. Simultaneously, multi-device monitoring is prone to signal transmission interference, insufficient interfaces, and waveform asynchrony, affecting the accuracy of fault analysis. Therefore, a technical solution is needed that balances real-time control, rapid response, reliable storage, and synchronous oscilloscope monitoring across multiple devices.

[0003] Fault recording and voltage oscilloscopes are key technologies for monitoring the operating status of energy storage converters, locating the root cause of faults, and optimizing system operation and maintenance. With the rapid development of power electronics technology, the power level of energy storage converters is constantly increasing, and their performance requirements are also constantly rising.

[0004] The core requirement of fault recording is to accurately capture voltage waveform data before and after a fault occurs, providing original evidence for fault analysis; while voltage oscilloscopes need to achieve real-time visualization of voltage signals from multiple devices, allowing maintenance personnel to intuitively grasp the overall operating status of the system. However, existing technical solutions have many insurmountable shortcomings in practical applications.

[0005] The single digital signal processor architecture lacks peripheral expansion and storage capabilities, while the single microprocessor architecture lacks computing speed and real-time control capabilities, both of which cannot meet the needs of multitasking. Traditional solutions have difficulty capturing instantaneous faults in real time due to task scheduling and other reasons. Simplifying the acquisition process can lead to insufficient sampling density, which affects fault location. A single static random-access memory (SRAM) stores volatile data when power is lost, while single flash memory (FLASH) has slow read / write speeds, limited lifespan, and a lack of proper storage partitioning leads to data timing disorder. Analog-to-Digital Converters (ADCs) with insufficient channels require additional adapter modules, and long-distance single-ended signal transmission is susceptible to interference. The low-speed communication interface leads to inefficient retrieval of historical data, lacks the function of multi-device waveform synchronization and comparison, and displays without timing alignment processing, which affects operation and maintenance judgment.

[0006] Existing fault recording and voltage oscilloscope technologies have significant shortcomings in chip architecture, response speed, storage reliability, multi-device synchronization, and visualization, and cannot meet the high-precision, high-reliability, and high-efficiency monitoring requirements of modern power electronic systems. An integrated solution that takes into account real-time control, rapid response, reliable storage, and multi-device synchronous oscilloscope is needed to solve these problems. Summary of the Invention

[0007] The purpose of this invention is to propose a multi-device visualized fault recording method and system, which aims to solve the core pain points of existing technologies in complex power scenarios, such as low signal processing efficiency, redundant data storage, weak transmission anti-interference capability, insufficient time synchronization accuracy of multiple devices, and limited visualization interaction.

[0008] To achieve the above objectives, the present invention is implemented using the following technical solution: In a first aspect, the present invention proposes a multi-device visualized fault recording method, which is implemented by coordinating fault recording data from multiple energy storage converters, including: The digital signal processor based on the energy storage converter obtains voltage data by sampling the bus voltage of the energy storage converter in real time through the built-in ADC module, and performs fault detection on the voltage data. When no fault occurs, the voltage is adjusted based on the closed-loop voltage control algorithm; when a fault occurs, an interrupt signal is generated immediately. The interrupt signal of each energy storage converter is transmitted to the corresponding microprocessor, and the fault recording process is started. The voltage data of the current energy storage converter is cached in the first memory in real time, and the fault recording data in the first memory is transferred to the second memory for permanent storage. The system interacts with several energy storage converters through the main display console to obtain and display fault recording data and status information of each energy storage converter. The main display console interacts with several energy storage converters via Ethernet, including: Transmit the voltage data of each energy storage converter to the main display panel; The fault recording data in the microprocessors of each energy storage converter is transmitted to the main display panel. The main display panel shows the voltage data and fault waveform data received from each energy storage converter.

[0009] Furthermore, the fault detection includes: When the digital signal processor acquires the voltage data, it uses a built-in algorithm to judge the acquired voltage data. When an abnormal voltage is detected, an interrupt signal is sent through the board-level general-purpose input / output pin (GPIO) interface between the processor and the microprocessor.

[0010] Furthermore, the closed-loop voltage control algorithm adjusts the voltage by: The bus voltage of the energy storage converter is sampled in real time using a digital signal processor to obtain the bus voltage sample value. The sampled bus voltage value is compared with a preset bus voltage reference value to calculate the deviation. The obtained deviation is adjusted by a PI controller and output as a reference command. According to the reference command, the parameters of the pulse width modulation (PWM) signal are adjusted. The PWM signal drives the insulated gate bipolar transistor (IGBT) in the inverter bridge to adjust its on / off state, thereby adjusting the voltage output of the energy storage converter.

[0011] Furthermore, the fault recording process includes: The microprocessor collects voltage data from multiple channels via an ADC module. These multiple channels include the bus voltage, which is the same as the bus voltage collected by the digital signal processor. The collected voltage data is sequentially cached in a first memory (SRAM). The SRAM includes a pre-fault acquisition area and a post-fault acquisition area. The sampling time interval is 50μs. Each time an interrupt occurs, the voltage values ​​of multiple ADC channels are read. Each channel accumulates 2000 voltage values, achieving a fault recording function of 100ms. Under normal operating conditions, the system acquires data cyclically at a period of 50μs, and updates the acquisition area before the fault in real time using a cyclic coverage method. This ensures that the voltage waveform of the area is always preserved for the most recent 2 seconds (i.e., 40,000 sampling points per channel), so that complete pre-recorded waveform data can be retrieved when a fault is triggered. When the system detects a fault, a GPIO interrupt signal from the DSP triggers the microprocessor to immediately switch to the post-fault acquisition area for data storage, preventing historical data from being overwritten, and simultaneously recording the timestamp of the fault occurrence. The post-fault acquisition area also records continuously at 50μs intervals until 2 seconds (40,000 points per channel) of data are stored. At this point, the microprocessor initiates a write operation to the second memory (FLASH) via an internal variable flag, writing the complete data sequence (a total of 80,000 points per channel, corresponding to a total duration of 4 seconds) from the pre-fault and post-fault acquisition areas in the SRAM, along with the fault timestamp at the starting position, into the FLASH for permanent storage. After completing the FLASH write, the flag is updated, and the cyclic refresh of the pre-fault acquisition area in the SRAM is restarted, restoring the system to its normal acquisition state. The sampling timing strictly maintains an equal interval of 50μs / point, and each channel stores a total of 80,000 valid sampling points, achieving full-time fault recording with a total duration of 4s (2s pre-fault recording + 2s fault recording after the fault). It can completely capture the dynamic change trend of voltage signals before and after the fault occurs, meeting the high-precision data requirements for fault tracing and characteristic analysis of power electronic systems.

[0012] Furthermore, the step of transmitting the voltage data of each energy storage converter to the main display panel includes: The first instrumentation amplifier is used to convert the single-ended voltage signal collected at the energy storage converter terminal into a differential signal; The differential signal is transmitted to the main display panel via a twisted-pair shielded cable; The differential signal received by the main display console is restored to a single-ended signal using a second instrumentation amplifier. The voltage data is obtained by sampling the restored single-ended signal using an ADC sampling module.

[0013] Furthermore, the step of transmitting the fault recording data from the microprocessors of each energy storage converter to the main display panel includes: The system obtains instructions from the main display panel to each energy storage converter. These instructions include two types of execution instructions: the first type is a file list display instruction, which requests the display of the names of all fault waveform files and their corresponding generation times; the second type is a specified waveform data display instruction, which requests the transmission of fault waveform files from a specified time. The microprocessor based on the energy storage converter parses the instructions and sends the corresponding data to the main display panel according to the type of the parsed instructions.

[0014] Secondly, the present invention proposes a multi-device visual fault recording system, including a main display console and several energy storage converters; The energy storage converter includes a main control voltage output module and a fault recording module. The voltage output module uses a digital signal processor as the core control chip and has a built-in ADC module and algorithm module to detect faults in the bus voltage of the energy storage converter. When a fault occurs, it sends an interrupt signal to notify the microprocessor to start the fault recording process. The fault recording module uses a microprocessor as the core processing unit to store voltage data in layers. The main display panel is equipped with a data receiving module, a waveform processing module, and a graphical display module. The data receiving module receives voltage sampling data from each energy storage converter. The waveform processing module processes the received voltage sampling data from each energy storage converter to generate voltage waveform data that meets the requirements for graphical display. The graphical display module visualizes the voltage waveform data corresponding to each energy storage converter in the form of an independent channel waveform diagram, realizing synchronous graphical display of voltage waveforms from multiple energy storage converters.

[0015] Furthermore, the data receiving module includes an ADC sampling module and an IO expansion chip; the IO expansion chip is used to expand the number of interfaces of the main display station to access multiple voltage output channels of multiple energy storage converters; the ADC sampling module is used to acquire multiple voltage signals from multiple energy storage converters accessed by the IO expansion chip.

[0016] Furthermore, the digital signal processors and microprocessors of the main display console and each energy storage converter are all equipped with BeiDou time synchronization modules for time synchronization.

[0017] Furthermore, it also includes a first memory and a second memory that are communicatively connected to the microprocessor. The first memory is used to cyclically cache real-time voltage data, and the second memory is used to permanently store fault waveform data after a fault is triggered.

[0018] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: This invention fully leverages the computing power advantage of digital signal processors in complex algorithm operations, and relies on microprocessors to construct a collaborative working mode of "high-speed computing + precise control" to improve response speed and resource utilization efficiency. Through a graphical and intuitive interactive interface, it facilitates data analysis for operation and maintenance personnel, comprehensively improves the accuracy of fault recording, the efficiency of multi-device collaboration, and the convenience of data application, and provides strong technical support for the safe and stable operation of the power system.

[0019] The hierarchical storage and partition management strategy proposed in this invention not only ensures the continuity of data storage (without breaks) but also achieves the permanent preservation of faulty data. The partition design supports the rapid retrieval and tracing of faulty data.

[0020] This invention uses an analog multiplexer to achieve multi-channel access, differential transmission technology to reduce long-distance transmission interference (signal distortion ≤0.5%), BeiDou time synchronization to ensure time synchronization accuracy ≤1μs, and supports waveform synchronous comparison and analysis of multiple devices.

[0021] This invention comprehensively covers core aspects such as fault recording, data storage, multi-device synchronization, and visualization. The technical solution features high precision, high reliability, and high efficiency, which can meet the stringent requirements of modern power electronic systems for monitoring technology and has broad application prospects and promotional value. Attached Figure Description

[0022] Figure 1 This is a framework diagram of a multi-device visual fault recording method proposed in an embodiment of the present invention; Figure 2 This is a flowchart of a multi-device visual fault recording method proposed in an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use.

[0024] Example 1:

[0025] This embodiment proposes a multi-device visual fault recording system, including a main display console and several energy storage converters, such as... Figure 1 As shown; The energy storage converter uses a TI TMS320F28377D 32-bit floating-point DSP as its core voltage control unit. The power conversion system (PCS) includes a main control voltage output module and a fault recording module. The voltage output module uses a digital signal processor (DSP) as the core control chip. This chip has a main frequency of 200MHz and integrates a hardware floating-point unit (FPU) and a control law accelerator (CLA). It can support single-cycle proportional-integral (PI) calculations to meet the high real-time requirements of voltage closed-loop control. When its ADC module is configured in single-ended mode, it has 24 channels of 12-bit high-speed analog acquisition channels, and the system-level sampling throughput is ≤14MSPS, which can adapt to the requirements of synchronous acquisition of multi-dimensional electrical quantities.

[0026] The fault recording module uses an STM32F103VET6 microcontroller unit (MCU) as its core processing unit. It expands upon this with an 8MB high-speed static random access memory (SRAM, model APS6404L) and a 2GB NOR flash memory (NOR FLASH, model GD55X02GE) via an SPI serial peripheral interface. The SRAM is used for real-time data caching at the moment of fault triggering, while the NOR FLASH provides non-volatile permanent storage of the recorded data. The MCU's interconnect pin with the DSP is configured for rising-edge triggered external interrupt mode. When the DSP detects a fault event, it can send a fault trigger command to the MCU through this interrupt channel. Simultaneously, the module initializes and configures the MCU's built-in ADC module, acquiring data from 24 voltage channels with sampling accuracy calibrated to ±0.5% of full scale, and preset the sampling timing to 50 microseconds per point (50μs / point).

[0027] The GPIO pins connecting the MCU and DSP are configured to use rising-edge triggered external interrupt mode, serving as the DSP's fault interrupt synchronization signal input channel. When an interrupt trigger signal sent by the DSP is detected, a fault trigger command can be sent to the MCU through this interrupt channel. Simultaneously, the initialization configuration of the MCU's built-in ADC module is completed, data acquisition is performed on 24 voltage channels, the sampling accuracy is calibrated to ±0.5% of full scale (FS), and the sampling timing is preset to 50 microseconds per point (50μs / point). The acquired parameters include: three-phase AC output voltage, grid-side three-phase voltage, DC bus voltage, bridge arm midpoint voltage, and fault detection redundant voltage, among other core electrical parameters.

[0028] The main display console interacts with the MCUs of each PCS device via an Ethernet interface.

[0029] At the hardware level, the main control unit uses a Xilinx Artix-7 series FPGA chip, externally connected to an LTC2380-24 24-channel high-speed ADC chip and a TI CD4051BM96 analog multiplexer. The FPGA establishes a highly reliable communication link with the ADC module through a hardware SPI interface protocol IP core. Each ADC acquisition channel is equipped with a CD4051BM96 analog multiplexer, and channel switching and time-division acquisition of multiple PCS devices are achieved by changing the pin addresses. The main display console is equipped with a data receiving module, a waveform processing module, and a graphical display module, constructing a complete PCS device voltage waveform monitoring system.

[0030] At the software level, a simplified TCP / IP protocol stack is embedded inside the FPGA. The functional logic of the link layer, network layer, and transport layer is modularized using a hardware description language. Multiple communication channels share the core logic resources of the protocol stack. Resource access conflicts are avoided through time-division multiplexing or parallel processing mechanisms. At the same time, each channel is configured with an independent data packet buffer (BRAM) to achieve time-series isolation and high-concurrency processing for data transmission and reception of each channel.

[0031] The main display console is equipped with a data receiving module, a waveform processing module, and a graphical display module, constructing a full-process PCS equipment voltage waveform monitoring system. The data receiving module is responsible for accurately acquiring multi-channel voltage sampling data output from the ADC module, providing a high-fidelity raw data source for subsequent signal processing and ensuring the stability and integrity of data transmission. The waveform processing module performs refined processing based on the raw sampling data, achieving multi-channel data timing alignment through a timestamp synchronization algorithm, with alignment accuracy strictly controlled to ≤1μs. For breakpoints occurring during sampling, a cubic spline interpolation algorithm is used for data completion, with an interpolation error ≤0.3%, ensuring the continuity and accuracy of waveform data. Finally, the processed data is standardized and formatted into a CSV file, compatible with mainstream data analysis tools, facilitating data archiving and secondary analysis. The graphical display module adopts a professional visualization design, presenting the PCS equipment voltage waveform in the form of independent channel waveform diagrams. It supports custom channel color differentiation, adaptive amplitude scaling, and bidirectional dragging of the time axis, improving the flexibility of waveform observation. It has multi-channel parallel display capabilities, supporting up to 24 channels of waveform simultaneous display. The interface allows for quick switching to rotate the voltage waveform monitoring of multiple PCS devices, meeting the needs of clustered equipment operation and maintenance. It supports the overlay display of fault trigger time marker lines and voltage threshold lines (upper / lower limits), intuitively presenting the fault occurrence sequence and voltage anomaly range, helping maintenance personnel to quickly locate the fault propagation path and assess the fault impact boundary; it provides a fault waveform file import function, supports historical fault waveform backtracking and offline analysis, and provides data support for fault cause investigation.

[0032] In the signal transmission link design, each PCS device uses an INA128 instrumentation amplifier (CMRR≥100dB, gain adjustable from 1-1000 times) to convert the single-ended voltage signal (0-5V) into a differential signal (±5V), and transmits it over long distances through a twisted-pair shielded cable with a characteristic impedance of 120Ω. The differential transmission and shielding structure effectively suppress common-mode interference. The main display console also uses an INA128 instrumentation amplifier to restore the differential signal to a single-ended signal, which is then connected to an RC low-pass filter circuit (cutoff frequency set to 10kHz) to filter out high-frequency noise and noise introduced during transmission, keeping the signal distortion within 0.5%. After processing by this circuit, the signal sampling accuracy can reach ±0.1% FS, and finally, it is sent to the ADC module for digital acquisition, realizing a complete link from transmission, anti-interference transmission to accurate reconstruction.

[0033] Each PCS device has a built-in Beidou time synchronization module (model BD-808), and the DSP and MCU synchronize the clock with the Beidou time synchronization module in real time. The main display station is also equipped with a Beidou time synchronization module of the same specification. This module is based on the second pulse signal combined with the serial communication mechanism to complete the accurate clock calibration between multiple devices, ensuring that the timestamp deviation of the voltage sampling data of multiple PCS devices is ≤1μs, which meets the application requirements of synchronous comparison and analysis of sampling data.

[0034] During the initialization phase of the DSP, MCU, and FPGA, after the first BeiDou clock synchronization is completed, the DSP sends a sampling trigger instruction to the MCU via GPIO interrupt 2 seconds in advance. The MCU forwards the instruction to the FPGA via the network. Each core control unit uses the PPS second pulse signal as the interrupt trigger source and starts the ADC sampling process synchronously on the rising edge of the second PPS interrupt after receiving the instruction, so as to achieve strict consistency of the timing of the three-channel voltage sampling of the DSP, MCU, and FPGA.

[0035] Example 2:

[0036] Based on Example 1, this embodiment proposes a multi-device visual fault recording method.

[0037] 1. Complete system hardware initialization configuration: After the system powers on, the F28377D DSP completes main frequency initialization, configuring the CPU core frequency to 200MHz. Subsequently, it performs peripheral layer initialization, focusing on differentiated configuration of the Enhanced Pulse Width Modulation (ePWM) module: the ePWM1 module is configured independently, its time base clock (TBCLK) is divided by 2 to 100MHz, an up-counting mode is adopted, and the period register TBPRD is set to 4, generating an ePWM1 trigger signal with a frequency of 20MHz. This signal serves as the sampling timing reference for the ADC module, achieving a precise sampling period of 50μs / point, providing a synchronous timing basis for system control. The trigger interrupt configuration of the ADC module is completed synchronously. By modifying the TRIGSEC0CTL register's TRIGSEC0 bit to 5, the trigger source of ADC SOC0 is specified as ePWM1 (completely independent of the IGBT-driven ePWM channel), establishing a hardware synchronization link for ePWM-triggered ADC sampling.

[0038] Initialize the general peripherals, configure the two GPIO pins to push-pull output mode, complete the baud rate (115200bps) parameter configuration of the UART peripheral, initialize the BeiDou positioning module and its matching GPIO pins, and configure the GPIO to rise-edge triggered interrupt mode to achieve accurate capture of the BeiDou PPS second pulse synchronization signal. Complete the low-level parameter configuration of the I2C bus interface, enable the RTC time synchronization and calibration mechanism, and in the interrupt service routine of the BeiDou PPS second pulse, read the high-precision time information output by the BeiDou module through the UART, write it into the RTC register to complete the initial time calibration, and design periodic calibration logic to read the current RTC time every 30 seconds and compare it with the BeiDou time synchronization time. If the deviation exceeds the preset threshold, the RTC time recalibration operation is performed.

[0039] The DSP executes the coordinated control process for ADC sampling. After all peripherals are initialized, the DSP sends a sampling preparation synchronization signal to the MCU 2 seconds in advance via GPIO interrupt. At the same time, it transmits the currently calibrated RTC timestamp to the MCU via serial port. 2 seconds later, the DSP starts the periodic sampling operation of the ADC.

[0040] After the MCU powers on, it completes system clock initialization, configuring the STM32F103VET6 main frequency to 72MHz; it then sequentially completes peripheral low-level driver initialization, initializes the SPI bus driver, and completes hardware initialization and functional verification of the SRAM, FLASH, and W5500 network modules; it initializes the serial port link for communication with the DSP and two GPIO interfaces to achieve cross-chip data interaction and signal synchronization; it initializes the serial communication link for the Beidou module, and simultaneously configures the GPIO pin corresponding to the Beidou PPS second pulse to rising edge triggered interrupt mode, using the same timing logic as the DSP to complete system time calibration.

[0041] At the analog signal acquisition level, the interrupt trigger source of the on-chip ADC module is configured as software-triggered by modifying the EXTSEL bit of the ADC_CR2 register. For timing sampling requirements, a general-purpose timer, Timer2, is initialized and connected to the APB1 bus. After frequency multiplication, its clock frequency is 72MHz. The time base register prescaler (PSC) is configured to 71, dividing the counting clock to 1MHz. Combined with the automatic reload value (ARR) of 49, a 50μs period timing interrupt is achieved. The ADC data reading operation is performed in the Timer2 interrupt service function. Since the STM32F103VET6 only has 16 external ADC channels, an external ADS7830 ADC chip (12-bit resolution, 8 single-ended inputs) with an I2C interface is needed to expand the acquisition channels. Combined with the on-chip 16 channels, this ultimately achieves the acquisition of 24 channels of ADC voltage data.

[0042] In terms of acquisition control logic, after the MCU receives the GPIO interrupt signal from the DSP, it sends the ADC acquisition start command to the main display FPGA through the W5500 module; at the same time, it reads the Beidou time synchronization information received by the serial port and compares it with the local RTC time. If the time deviation reaches 2 seconds, the ADC voltage acquisition process is started.

[0043] After the main display panel is powered on, the FPGA loads the embedded hardware logic program, initializes the SPI communication interface, analog multiplexer control logic and TCP / IP protocol stack module; configures the PHY interface driver logic, enables 10 / 100 / 1000Mbps adaptive rate and MDI / MDIX automatic crossover function; and calibrates the local clock through the Beidou time synchronization module.

[0044] 2. Fault recording procedure implementation: The DSP acquires the PCS bus voltage in real time via its built-in ADC module, calculates the deviation from the preset reference voltage, and outputs a PWM modulation command through a PI regulation algorithm to dynamically adjust the on / off duty cycle of the IGBT power devices, controlling the bus voltage fluctuation rate within ±2% of the rated value. Simultaneously, the DSP runs a voltage anomaly detection algorithm to monitor for voltage surges, dips, short-term short circuits, and other faults in real time, with a fault detection delay controlled to ≤100ns. Once a fault is detected, a GPIO interrupt is immediately sent to the MCU.

[0045] The MCU divides the SRAM storage space into two main areas: a "pre-fault storage area" and a "post-fault recording area," to achieve continuous storage of ADC data before and after a fault.

[0046] When no fault GPIO interrupt signal is received, the MCU acquires 24-channel ADC voltage data in real time in the timer interrupt service routine and cyclically writes the sampled values ​​of each channel into the pre-fault storage area, continuously writing 40,000 sample points per channel. At the same time, a waveform recording file management structure is defined, which includes the following core fields: SRAM write address pointer before fault (sram_index_before), SRAM write address pointer after fault (sram_index_after), fault status flag (fault_flag), fault data write completion flag (fault_finish_write_flag), RTC timestamp of fault occurrence (fault_rtc_time), fault file sequence number (fault_file_num), FLASH write start address of fault waveform recording file (flash_fault_start_addr), and FLASH write start address of fault waveform recording timestamp (flash_fault_rtc_start_addr).

[0047] The data refresh logic follows strict status judgment rules. The refresh operation of the ADC sampling data in the pre-fault storage area is only performed when fault_flag is 0 (no fault) and fault_finish_write_flag is 1 (fault data writing is completed). When the data of each channel in the pre-fault storage area reaches 40,000 sampling points, the ADC voltage data is overwritten and refreshed starting from the storage start address to realize the cyclic pre-storage of the pre-fault data.

[0048] When the MCU receives a fault GPIO interrupt signal from the DSP, it immediately sets fault_flag to 1, synchronously records the current RTC timestamp (fault_rtc_time), and calculates the FLASH write address according to the formula flash_fault_rtc_start_addr + fault_file_num×20 (20 bytes of storage space are allocated for each timestamp), and writes the fault timestamp to the designated FLASH area; at the same time, the data write area is switched to the post-fault recording area, and the writing process of 24-channel ADC voltage data to the post-fault recording area is started.

[0049] After each channel of the post-fault recording area completes the writing of 40,000 sampling points, the fault_flag is cleared and the FLASH data writing process is triggered: First, the data in the pre-fault storage area is read from the address pointed to by sram_index_before, and written to the corresponding FLASH area according to the formula flash_fault_start_addr + fault_file_num×7680000 (7680000 bytes is the length of a single recording file). First, (3840000 - sram_index_before) bytes of data are written, and then the remaining data is read from the starting address of the pre-fault storage area to complete the writing, completing the FLASH solidification of the data in the 2 seconds before the fault; then, all the data in the post-fault recording area is continuously written to the same FLASH address, completing the FLASH storage of a total of 3840000 bytes of post-fault voltage data, and at the same time, fault_finish_write_flag is set to 1.

[0050] 3. Implementation of multi-device synchronous monitoring and data transmission: The core control unit of the main display console uses an FPGA chip. This FPGA has a built-in MAC protocol simulation logic module and eight external PHY chips. The PHY chips are connected to shielded twisted-pair cables via RJ45 interfaces to establish an Ethernet communication link, enabling bidirectional data interaction with the built-in MCUs of each PCS device. Data transmission between the FPGA and the PHY chips is completed through the MII / RMII interface. The MAC protocol simulation module is compatible with the IEEE 802.3 standard and supports an adaptive communication rate of 10 / 100Mbps, meeting the concurrent data interaction requirements of multiple PCS devices.

[0051] The main display FPGA is equipped with a 24-channel ADC acquisition module (resolution ≥ 12 bits, sampling rate ≥ 100kSPS). Each acquisition channel pin of the ADC module is connected to the output of an analog multiplexer (model CD4051BM96). Each analog multiplexer is configured with 8 inputs, which are connected to the voltage acquisition ports of different PCS devices through shielded twisted-pair cables. The address control pins (A0 / A1 / A2) and enable pins (EN) of all analog multiplexers are connected to the I / O ports of the ADC module on the FPGA. The FPGA outputs control signals to select the channels of the multiplexer.

[0052] The main display console is equipped with a touch screen, which communicates with the FPGA via a serial bus to issue operation commands, display fault waveform lists and voltage data waveforms, etc. The touch screen has a built-in human-machine interface, which is divided into three major functional modules: "PCS device selection area", "fault waveform operation area" and "voltage waveform display area", supporting visual interaction for operators.

[0053] The main display panel touch screen sends a command to view the fault waveform file list. This command is encapsulated into an Ethernet data frame by the FPGA (the frame header carries the target PCS device address) and transmitted to the MCU of the corresponding PCS device through the PHY chip and Ethernet link. After receiving the command, the MCU reads the locally stored fault waveform file list (including file number, timestamp, device identifier, etc.), encapsulates it into a data frame according to the preset protocol format, and sends it back to the FPGA. After parsing, the FPGA pushes the list data to the touch screen for display.

[0054] When the operator switches the target PCS device on the touch screen, the touch screen transmits the device switching command to the FPGA. After the FPGA parses the command, it outputs the corresponding address control signal (A0 / A1 / A2 level combination) to all analog multiplexers according to the preset "PCS device-multiplexer address mapping table", adjusts the input gate state of the multiplexers, and realizes the switching of the mapping relationship between the input of the analog multiplexer and the voltage acquisition port of the PCS device.

[0055] After the PCS device switching is completed, the FPGA controls the external ADC module to synchronously sample the 24 channels. The sampled data is then digitally filtered and scaled within the FPGA and transmitted to the touch screen in real time. The touch screen has a built-in waveform rendering engine that visualizes the 24 voltage data in the form of time-domain waveforms. It supports waveform zooming, time axis dragging, and other operations, making it easy for operators to view the voltage change trends of each channel.

[0056] After the operator selects a record with a specified timestamp in the fault waveform list of the target PCS device on the touch screen, the FPGA sends a fault waveform data transmission command to the MCU of the corresponding PCS device. After receiving the command, the MCU reads the fault waveform file corresponding to the timestamp (containing 24 channels of voltage data, including 40,000 sampling points in the pre-fault storage area and 40,000 sampling points in the post-fault waveform area) from the local FLASH, and transmits it back in fragments according to the Ethernet frame format. After the FPGA receives all the fragmented data and completes the splicing, it transmits the data to the touch screen. The display screen splits the data by channel and renders it as voltage waveforms before and after the fault, realizing the visualization of the fault waveform data.

[0057] Meanwhile, the interface overlays the fault trigger time marker line and the upper and lower voltage threshold lines, intuitively presenting the fault occurrence sequence and voltage anomaly range; it supports the import function of fault waveform files, allowing users to trace back historical fault waveforms and perform offline analysis, which helps in fault tracing and cause investigation.

[0058] Example 3:

[0059] This embodiment, based on Embodiment 2, provides a specific example. Taking the centralized monitoring scenario of six PCS energy storage converters in a 10kV power distribution system as an example, it deploys a fault recording system based on a collaborative architecture of TI TMS320F28377D DSP + STM32F103VET6 MCU, coupled with a Xilinx Artix-7 FPGA central display platform, to achieve 24-channel synchronous voltage acquisition, real-time fault recording, and visualization of the oscilloscope from multiple PCS devices. The entire process can be viewed. Figure 2 The specific implementation process is as follows: S11: After the system is powered on, the DSP collects the PCS bus voltage in real time and adjusts the IGBT duty cycle through the PI algorithm to control the bus voltage fluctuation rate within ±2%. S12: The MCU collects 24 voltage data channels at a frequency of 50μs interrupted by Timer2, and writes them cyclically to the SRAM "pre-fault storage area" (40,000 sampling points per channel, corresponding to a duration of 2 seconds). Data overwrite refresh is only performed when fault_flag=0 and fault_finish_write_flag=1.

[0060] S13: The main display panel selects the PCS1 device by default. The FPGA controls the multiplexer to select the corresponding input terminal. The ADC module collects 24 channels of voltage data, and after digital filtering, renders the time domain waveform in real time on the touch screen. The waveform refresh rate is 10 frames / second, and it supports operations such as time axis dragging and amplitude magnification.

[0061] S21: When a PCS3 device malfunctions, the DSP's voltage anomaly detection algorithm determines the fault and immediately sends a GPIO interrupt signal to the MCU. The MCU sets fault_flag to 1, records the fault RTC timestamp (e.g., 2025-06-10 14:25:30.123456), and writes the timestamp to FLASH according to the formula flash_fault_rtc_start_addr + fault_file_num × 20 (fault_file_num is initially 0).

[0062] S22: The MCU switches the data writing area to the "post-fault recording area" and continuously collects 24 channels of voltage data to 40,000 sampling points per channel (2 seconds). After completion, the fault_flag is cleared and the FLASH writing process is triggered.

[0063] S23: Starting from sram_index_before (assumed to be 1920000 bytes), first write 3840000 - 1920000 = 1920000 bytes, then write 1920000 bytes from the starting address of the pre-stored area, thus completing the data solidification 2 seconds before the fault.

[0064] S24: Continue writing 3,840,000 bytes to the above address. The total length of a single waveform file is 7,680,000 bytes, and the storage address is flash_fault_start_addr + fault_file_num × 7,680,000. After writing, fault_finish_write_flag is set to 1, and fault_file_num is incremented to 1.

[0065] S31: The operator switches to the PCS3 device on the main display screen and issues a command to view the fault waveform file list. The MCU sends back the fault list. After selecting the fault record, the FPGA issues a data transmission command, and the MCU sends back the 7,680,000-byte waveform file in segments (1024 bytes each). The FPGA then splices the segments and transmits them to the touch screen.

[0066] S32: The display shows the voltage waveforms before and after the fault, overlaying the fault time marker line (14:25:30.123456) and the voltage lower limit threshold line (85% of the rated value), clearly presenting the start time, duration and recovery process of the voltage drop. It supports exporting waveform data to CSV format for offline fault analysis.

[0067] S33: When it is necessary to view the real-time voltage of the PCS5 device, the operator clicks on the PCS5 device in the PCS device selection area of ​​the touch screen. After the FPGA parses the instructions, it configures the address control signals of A0, A1, and A2. The multiplexer switches to the corresponding input terminal of the PCS5, and the display screen refreshes to show the 24-channel voltage waveform of the PCS5 device.

[0068] S34: If it is necessary to retrieve the historical fault waveform files of 6 PCS devices in batches, the main display console broadcasts the command through the FPGA, and each MCU sends back the file list in sequence. The operator can view the fault waveform of each device one by one, realizing centralized monitoring of multiple devices and fault comparison analysis.

[0069] In this example, the MCU uses a flag mechanism to achieve data interaction between SRAM and FLASH, avoiding storage conflicts. Under normal operating conditions, it cyclically overwrites the "pre-fault storage area," while fault data is permanently stored in FLASH, supporting multi-file archiving and retrieval. At the hardware level, it employs twisted-pair shielded cable transmission, impedance matching circuits, and RC filtering circuits. At the software level, it uses timing synchronization, data verification, and interpolation completion algorithms to ensure stable system operation in complex power environments. The visual interface supports real-time monitoring of fault waveforms, historical data backtracking, and collaborative viewing of multiple devices, allowing maintenance personnel to quickly locate fault propagation paths, assess fault impact boundaries, and improve fault troubleshooting efficiency.

[0070] Those skilled in the art will recognize that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0071] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and equipment can be referred to the corresponding process in the foregoing method implementation, and will not be repeated here.

[0072] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0073] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the objectives of the embodiments of the present invention, depending on actual needs.

[0074] In addition, the functional modules in the embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0075] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the sending / receiving methods of various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0076] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

[0077] It should be understood that the sequence number of each step in the invention and its embodiments does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A multi-device visual fault recording method, characterized in that, include: The digital signal processor based on the energy storage converter obtains voltage data by sampling the bus voltage of the energy storage converter in real time through the built-in ADC module, and performs fault detection on the voltage data. When no fault occurs, the voltage is adjusted based on the closed-loop voltage control algorithm; when a fault occurs, an interrupt signal is generated immediately. The interrupt signal of each energy storage converter is transmitted to the corresponding microprocessor, and the fault recording process is started. The voltage data of the current energy storage converter is cached in the first memory in real time, and the fault recording data in the first memory is transferred to the second memory for permanent storage. The system interacts with several energy storage converters through the main display console to obtain and display fault recording data and status information of each energy storage converter. The main display console interacts with several energy storage converters via Ethernet, including: Transmit the voltage data of each energy storage converter to the main display panel; The fault recording data in the microprocessors of each energy storage converter is transmitted to the main display panel. The main display panel shows the voltage data and fault waveform data received from each energy storage converter.

2. The multi-device visual fault recording method according to claim 1, characterized in that, The fault detection includes: When the digital signal processor acquires the voltage data, it uses a built-in algorithm to judge the acquired voltage data. When an abnormal voltage is detected, an interrupt signal is sent through the board-level GPIO interface between the processor and the microprocessor.

3. The multi-device visual fault recording method according to claim 1, characterized in that, The closed-loop voltage control algorithm adjusts the voltage as follows: The bus voltage of the energy storage converter is sampled in real time using a digital signal processor to obtain the bus voltage sample value. The bus voltage sample value is compared with a preset bus voltage reference value to calculate the deviation. The obtained deviation is adjusted by a PI controller and a reference command is output. The PWM pulse signal parameters are adjusted according to the reference command to drive the inverter bridge IGBT to adjust the on / off state, thereby adjusting the voltage output of the energy storage converter.

4. The multi-device visual fault recording method according to claim 1, characterized in that, The fault recording process includes: The microprocessor acquires voltage data from multiple channels via an ADC module. These multiple channels include the bus voltage, which is the same as the bus voltage acquired by the digital signal processor. The acquired voltage data is then cached sequentially in a first memory. The first memory includes a pre-fault acquisition area and a post-fault acquisition area. When the microprocessor receives an interrupt signal, it switches the first storage to the post-fault acquisition area for data storage; When the preset storage trigger condition is met, the data storage operation is triggered by the internal variable flag bit of the microprocessor, and the data cached in the fault acquisition area in the first memory is stored in the second memory for permanent storage. After writing to the second memory is completed, the variable flag is updated, and data refresh of the area before the failure of the first memory is initiated.

5. The multi-device visual fault recording method according to claim 1, characterized in that, The step of transmitting voltage data from each energy storage converter to the main display panel includes: The first instrumentation amplifier is used to convert the single-ended voltage signal collected at the energy storage converter terminal into a differential signal; The differential signal is transmitted to the main display panel via a twisted-pair shielded cable; The differential signal received by the main display console is restored to a single-ended signal using a second instrumentation amplifier. The voltage data is obtained by sampling the restored single-ended signal using an ADC sampling module.

6. The multi-device visual fault recording method according to claim 1, characterized in that, The step of transmitting the fault recording data from the microprocessors of each energy storage converter to the main display panel includes: The system obtains instructions from the main display panel to each energy storage converter. These instructions include two types of execution instructions: the first type is a file list display instruction, which requests the display of the names of all fault waveform files and their corresponding generation times; the second type is a specified waveform data display instruction, which requests the transmission of fault waveform files from a specified time. The microprocessor based on the energy storage converter parses the instructions and sends the corresponding data to the main display panel according to the type of the parsed instructions.

7. A multi-device visual fault recording system, characterized in that, Includes a main display panel and several energy storage converters; The energy storage converter includes a main control voltage output module and a fault recording module. The voltage output module uses a digital signal processor as the core control chip and has a built-in ADC module and algorithm module to detect faults in the bus voltage of the energy storage converter. When a fault occurs, it sends an interrupt signal to notify the microprocessor to start the fault recording process. The fault recording module uses a microprocessor as the core processing unit to store voltage data in layers. The main display panel is equipped with a data receiving module, a waveform processing module, and a graphical display module. The data receiving module receives voltage sampling data from each energy storage converter. The waveform processing module processes the received voltage sampling data from each energy storage converter to generate voltage waveform data that meets the requirements for graphical display. The graphical display module visualizes the voltage waveform data corresponding to each energy storage converter in the form of an independent channel waveform diagram, realizing synchronous graphical display of voltage waveforms from multiple energy storage converters.

8. The multi-device visual fault recording system according to claim 7, characterized in that, The data receiving module includes an ADC sampling module and an IO expansion chip; the IO expansion chip is used to expand the number of interfaces of the main display station to connect to multiple voltage output channels of multiple energy storage converters; the ADC sampling module is used to collect multiple voltage signals from multiple energy storage converters connected to the IO expansion chip.

9. The multi-device visual fault recording system according to claim 7, characterized in that, The digital signal processors and microprocessors of the main display panel and each energy storage converter are all equipped with Beidou time synchronization modules for time synchronization.

10. The multi-device visual fault recording system according to claim 7, characterized in that, It also includes a first memory and a second memory that are communicatively connected to the microprocessor. The first memory is used to cyclically cache real-time voltage data, and the second memory is used to permanently store fault waveform data after a fault is triggered.

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