Flash memory storage stability optimization method and device, storage control chip and medium

Abstract

The application provides a flash memory storage stability optimization method and device, a storage control chip and a medium. The method comprises the following steps: obtaining the block erasing state of each Plane in the flash memory, and calculating and obtaining the proportion of normal erasing blocks of each Plane; calculating the normal erasing threshold proportion of the flash memory according to the proportion of normal erasing blocks corresponding to each Plane; performing a first filtering operation based on the normal erasing threshold proportion, wherein the first filtering operation is to eliminate the Plane whose proportion of normal erasing blocks is lower than the normal erasing threshold proportion, and obtain a first set, wherein the first set contains at least one Plane; performing full-disk read-write verification on the Plane contained in the first set; if the full-disk read-write verification is passed, the Plane contained in the first set is used as an available Plane; and if the full-disk read-write verification is not passed, the flash memory is determined to be unqualified. The application can effectively improve the data storage stability of the flash memory.

Description

Technical Field

[0001] This invention relates to the field of flash memory technology, and in particular to a method, apparatus, storage control chip, and medium for optimizing flash memory storage stability. Background Technology

[0002] NAND Flash (hereinafter referred to as flash memory) is a mainstream non-volatile storage medium. With its large capacity and high read and write speed, it has been widely used in various storage products such as USB flash drives, SD cards, and solid-state drives.

[0003] Storage stability is crucial for ensuring the reliability of flash memory data. Existing technologies primarily improve flash memory stability through fine-tuning strategies, such as word-line page kicking, ECC bit-based page kicking configurations, fixed page removal of unstable pages, and bad block replacement. However, these methods have significant limitations: when the effective page ratio of a flash block exceeds 90% and the number of page error bits is low, conventional fine-tuning alone is insufficient to further improve flash memory stability. Therefore, there is an urgent need to introduce new optimization schemes to comprehensively improve flash memory stability, enabling it to successfully pass the H2Test test (a test specifically for testing flash memory storage stability) and meet the factory requirements for storage products. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a flash memory storage stability optimization method, apparatus, storage control chip and medium that can improve the data storage stability of flash memory.

[0005] The first aspect of this application provides a method for optimizing the stability of flash memory storage, including:

[0006] Obtain the block erase status of each Plane in the flash memory, and calculate and obtain the percentage of normally erased blocks for each Plane;

[0007] The normal erase threshold percentage of the flash memory is calculated based on the percentage of normal erase blocks corresponding to each Plane.

[0008] A first filtering operation is performed based on the normal erasure threshold ratio. The first filtering operation is to remove the Plane whose normal erasure block ratio is lower than the normal erasure threshold ratio to obtain a first set, wherein the first set contains at least one Plane.

[0009] A full disk read / write check is performed on the Planes included in the first set. If the full disk read / write check passes, the Planes included in the first set are considered usable Planes; if the full disk read / write check fails, the flash memory is determined to be unqualified flash memory.

[0010] Furthermore, in one preferred embodiment, if the full disk read / write verification fails, the method further includes:

[0011] Read the specification parameters of each Plane in the first set, including Plane capacity and block capacity;

[0012] Using the sum of the maximum Plane capacity and the block capacity as the base denominator, and the sum of the Plane capacity and the block capacity corresponding to each Plane in the first set as the base numerator, the capacity percentage of the Planes included in the first set is calculated respectively.

[0013] A second filtering operation is performed based on the capacity ratio. The second filtering operation is to remove the Plane corresponding to the capacity ratio being lower than a preset capacity threshold to obtain a second set, wherein the second set contains at least one Plane.

[0014] The full disk read / write check is performed again on the Plane included in the second set. If the full disk read / write check passes, the Plane included in the second set is considered a usable Plane; if the full disk read / write check fails, the flash memory is determined to be unqualified flash memory.

[0015] Further, in one preferred embodiment, the step of obtaining the block erase status of each plane in the flash memory and calculating and obtaining the percentage of normally erased blocks for each plane includes:

[0016] The protocol type for reading flash memory;

[0017] Based on the protocol type, a preset read command is sent to the flash memory to obtain the block erase status of each plane in the flash memory. The block erase status is represented by the value of the status register.

[0018] The value of the status register is converted. If the high 4 bits of the status register value are any one of C, D, E, and F, and the low 4 bits of the status register value are even, then the current block is determined to be a normal erase block.

[0019] The number of normal erase blocks in each Plane is counted, and the percentage of normal erase blocks in each Plane is calculated by combining the total number of blocks in each Plane.

[0020] Further, in one preferred embodiment, after converting the value of the status register, if the high 4 bits of the status register value are any one of C, D, E, and F, and the low 4 bits of the status register value are even, and the current block is determined to be a normal erase block, the method further includes:

[0021] The Plane identifier to which the normal erase block belongs is recorded synchronously, so that the Plane to which the normal erase block belongs corresponds to the erase state.

[0022] A second aspect of this application provides a flash memory storage stability optimization device, comprising:

[0023] The acquisition module is used to acquire the block erase status of each Plane in the flash memory, and calculate and obtain the percentage of normally erased blocks for each Plane;

[0024] The calculation module is used to calculate the normal erase threshold ratio of the flash memory based on the normal erase block ratio corresponding to each Plane.

[0025] A first filtering module is used to perform a first filtering operation based on the normal erasure threshold ratio. The first filtering operation is to remove the Plane whose normal erasure block ratio is lower than the normal erasure threshold ratio to obtain a first set, wherein the first set contains at least one Plane.

[0026] The first verification module is used to perform a full disk read / write verification on the Planes included in the first set. If the full disk read / write verification passes, the Planes included in the first set are considered as usable Planes; if the full disk read / write verification fails, the flash memory is determined to be unqualified flash memory.

[0027] Furthermore, in one preferred embodiment, it further includes:

[0028] The specification reading module is used to read the specification parameters of each Plane in the first set, including Plane capacity and block capacity.

[0029] The benchmark module is used to calculate the capacity percentage of the Plane included in the first set, with the sum of the Plane capacity and the block capacity at the maximum value as the benchmark denominator and the sum of the Plane capacity and the block capacity corresponding to each Plane in the first set as the benchmark numerator.

[0030] The second filtering module is used to perform a second filtering operation based on the capacity ratio. The second filtering operation is to remove the Plane corresponding to the capacity ratio being lower than the preset capacity threshold ratio to obtain a second set, wherein the second set contains at least one Plane.

[0031] The second verification module is used to perform the full disk read / write verification on the Plane included in the second set again. If the full disk read / write verification passes, the Plane included in the second set is considered a usable Plane; if the full disk read / write verification fails, the flash memory is determined to be a defective flash memory.

[0032] Further, in one preferred embodiment, the acquisition module includes:

[0033] The read unit specifies the protocol type used to read flash memory.

[0034] The acquisition unit is used to send a preset read instruction to the flash memory based on the protocol type, and to obtain the block erase status of each plane in the flash memory. The block erase status is represented by the value of the status register.

[0035] The conversion unit is used to convert the value of the status register. If the high 4 bits of the status register value are any one of C, D, E, and F, and the low 4 bits of the status register value are even, then the current block is determined to be a normal erase block.

[0036] The calculation unit is used to count the number of normal erase blocks in each Plane, and calculate the proportion of normal erase blocks in each Plane by combining the total number of blocks in each Plane.

[0037] Furthermore, in one preferred embodiment, the acquisition module further includes:

[0038] The synchronization unit is used to synchronously record the Plane identifier to which the normal erase block belongs, so that the Plane to which the normal erase block belongs corresponds to the erase state.

[0039] A third aspect of this application provides a storage control chip, including the flash memory storage stability optimization device described above:

[0040] A fourth aspect of this application provides a computer-readable storage medium storing executable code that, when executed by a processor of an electronic device, causes the processor to perform the flash memory storage stability optimization method as described above.

[0041] The technical solution of this application includes: obtaining the block erase status of each Plane in the flash memory, calculating and obtaining the normal erase block ratio of each Plane; calculating the normal erase threshold ratio of the flash memory based on the normal erase block ratio of each Plane; performing a first filtering operation based on the normal erase threshold ratio, wherein the first filtering operation is to remove Planes whose normal erase block ratio is lower than the normal erase threshold ratio to obtain a first set, wherein the first set contains at least one Plane; performing a full disk read / write verification on the Planes contained in the first set, wherein if the full disk read / write verification passes, the Planes contained in the first set are considered as usable Planes; if the full disk read / write verification fails, the flash memory is determined to be unqualified flash memory.

[0042] This technical solution calculates the threshold percentage based on the proportion of normal erase blocks in the Plane and performs screening and removal, quickly eliminating Planes with poor erasure stability. It also combines full disk read / write verification for secondary verification, accurately identifying flash memory stability defects and effectively improving the data storage stability of flash memory. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic flowchart illustrating a flash memory storage stability optimization method according to an embodiment of this application;

[0045] Figure 2 This is a flowchart illustrating a flash memory storage stability optimization method according to another embodiment of this application;

[0046] Figure 3 The diagram shown is a schematic diagram of a flash memory storage stability optimization device according to an embodiment of this application;

[0047] Figure 4 The diagram shown is a schematic representation of a flash memory storage stability optimization device according to another embodiment of this application.

[0048] Figure 5 The diagram shown is a schematic diagram of the structure of a storage control chip in one embodiment of this application. Detailed Implementation

[0049] To facilitate understanding of the present invention, a more complete description of the invention is provided below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0050] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] Storage stability is crucial for ensuring the reliability of flash memory data. Many related technologies improve flash memory stability through fine-tuning strategies, such as word-line page kicking, ECC bit-based page kicking configurations, fixed removal of unstable pages, and bad block replacement. However, these methods have significant limitations: when the effective page ratio of a flash block exceeds 90% and the number of page error bits is low, conventional fine-tuning alone is insufficient to further improve flash memory stability. Therefore, there is an urgent need to introduce new optimization schemes to comprehensively improve flash memory stability, enabling it to successfully pass H2Test (a test specifically for flash memory storage stability) and meet the factory requirements for storage products.

[0053] Therefore, in order to solve the above-mentioned technical problems, this application discloses a flash memory storage stability optimization method and corresponding embodiments, which can improve the data storage stability of flash memory.

[0054] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0055] like Figure 1 The diagram shown is a flowchart of a flash memory storage stability optimization method according to an embodiment of this application.

[0056] Please see Figure 1 A method for optimizing the stability of flash memory storage includes the following steps:

[0057] Step S110: Obtain the block erase status of each Plane in the flash memory, and calculate and obtain the percentage of normally erased blocks for each Plane.

[0058] Flash memory is hierarchically structured as LUN (Die)-Plane and Block-Page. The LUN is the basic unit for receiving and executing flash memory commands, the Block is the smallest erase unit, and the Page is the smallest read / write unit. Since flash memory contains several Planes, and each Plane has slight physical differences, primarily in the quantity and quality of blocks and pages within different Planes, the technical solution of this application essentially involves eliminating Planes with poor stability, thereby optimizing flash memory stability.

[0059] In this embodiment, the block erase status of each Plane in the flash memory is obtained, and the percentage of normally erased blocks in each Plane is calculated and obtained as follows: The protocol type of the flash memory is read; based on the protocol type, a preset read command is sent to the flash memory to obtain the block erase status of each Plane in the flash memory. The block erase status is represented by the value of the status register; the value of the status register is converted. If the high 4 bits of the status register value are any one of C, D, E, or F, and the low 4 bits of the status register value are even, then the current block is determined to be a normally erased block; the number of normally erased blocks in each Plane is counted, and combined with the total number of blocks in each Plane, the percentage of normally erased blocks in each Plane is calculated.

[0060] It should be noted that flash memory can be categorized into Toggle type or ONFI type based on its protocol. While the operation commands differ depending on the protocol, flash memory has become largely homogenized in terms of most operation commands over the past few decades. For example, in this embodiment, when it is necessary to obtain the erase status of blocks in each plane, regardless of whether it is Toggle type or ONFI type, the operation command "Read Status 70h" is used. Under this operation command, the flash memory internally returns the value of an 8-bit status register to indicate the erase status of the current block, as shown in Table 1.

[0061]

[0062] Table 1

[0063] In this configuration, D0~D3 belong to the lower 4 bits of the status register, and D4~D7 belong to the higher 4 bits. In this embodiment, when the 8-bit value of the status register is read, it is converted to hexadecimal and then judged. If the higher 4 bits of the status register value are any one of C, D, E, or F, and the lower 4 bits are even, then the current block is determined to be a normal erase block; otherwise, the current block is determined to be an abnormal erase block. Performing the above operation on each Plane's blocks yields the distribution data of normal erase blocks for each Plane. Then, the proportion of normal erase blocks for each Plane is calculated using Formula 1):

[0064] Percentage NRB =Number NRB / Number TB 1)

[0065] Among them, "Percentage" NRB "Number" represents the percentage of blocks that were normally erased; NRB "Number" represents the number of blocks that were normally erased; TB "Represents the total number of blocks in the Plane".

[0066] Step S120: Calculate the normal erase threshold ratio of the flash memory based on the normal erase block ratio corresponding to each Plane.

[0067] By combining the normal erase block percentage data of each plane, the quantitative indicators of all planes in the flash memory are integrated, and the normal erase threshold percentage of the entire flash memory is calculated by averaging. This is used as a unified quantitative evaluation standard for subsequent plane filtering.

[0068] In this embodiment, after determining the percentage of normal erase blocks for each Plane, the Percentage of all Planes is collected. NRB The value will be the total percentage. NRB After summing, calculate the arithmetic mean and set this mean as the percentage of normal erase threshold for the entire flash memory.

[0069] Let's illustrate this with a specific example: Taking the B58R flash memory as an example, this flash memory contains six independent planes. After calculation, the percentage of normally erased blocks in each plane is as follows:

[0070]

[0071] Table 2

[0072] The average of the above six sets of percentage data is calculated as follows: (95%+80%+50%+20%+10%+5%) / 6≈43.33%. Therefore, 43.33% is determined as the current normal erase threshold percentage of flash memory.

[0073] It should be noted that, unlike the local evaluation method that independently judges a single plane, this embodiment uses six sets of proportion data to output global quantitative statistical results. Combined with the differences in the actual multi-plane physical architecture of flash memory, a global averaging calculation logic is used to generate a unified threshold. Calculating the threshold based on multi-dimensional measured data can fit the overall performance distribution of flash memory, avoid the problem of one-sided judgment by a single indicator, and provide an objective and suitable judgment basis for the next step of differentiated filtering of unstable planes, realizing standardized hierarchical screening of flash memory stability under multi-plane architecture.

[0074] Step S130: Perform a first filtering operation based on the proportion of normal erase thresholds. The first filtering operation is to remove the Planes whose proportion of normal erase blocks is lower than the proportion of normal erase thresholds to obtain a first set, wherein the first set contains at least one Plane.

[0075] Thus, by performing this filtering step, we can remove the three planes P3 to P5 and obtain the first set, which contains the three planes P0 to P2.

[0076] Using the percentage of normal erase blocks as an objective screening boundary, filtering is implemented for multi-plane architectures within the flash memory. Considering the physical characteristics of flash memory, each plane exhibits erase differences due to manufacturing processes, structure, and usage. A lower percentage of normally erased blocks indicates a higher probability of abnormal block erasures within that plane. This means that long-term read / write operations using blocks from the current plane are more prone to stability issues such as bit errors and data drift. This step uses the percentage of normal erase blocks as the dividing line to accurately identify and remove weak planes with an insufficient percentage of normally erased blocks, retaining high-quality planes with erase performance at or above the overall average level. These retained qualified planes form the first set, and it is strictly guaranteed that at least one usable plane is retained in the first set to avoid a situation where all planes are removed, leaving no usable storage area in the flash memory.

[0077] It should be noted that, building upon the results of previous plane status statistics and threshold calculations, this approach abandons the traditional single method of uniform fine-tuning and optimization. Instead, it specifically filters out inherently unstable storage areas at the physical level, reducing potential flash memory storage anomalies at the source. Compared to conventional global optimization methods, this layered filtering approach is adaptable to the differentiated hardware characteristics of multiple planes. Its filtering logic is simple, efficient, and has low execution costs. It can quickly narrow down the range of unstable areas, providing stable and reliable detection targets for subsequent full-disk read / write verification, thereby improving the storage reliability of flash memory.

[0078] Step S140: Perform a full disk read / write check on the Planes contained in the first set. If the full disk read / write check passes, the Planes contained in the first set are considered usable Planes; if the full disk read / write check fails, the flash memory is determined to be unqualified flash memory.

[0079] It should be noted that after obtaining the first set, the qualified planes remaining in the first set are used as the test objects to carry out full-coverage full-disk read and write verification tests. The erase block ratio can only reflect the quality of the erase ratio of different planes in flash memory, and cannot directly reflect the operational stability of actual data read and write storage. Therefore, it is necessary to simulate the actual working scenario of flash memory mass production and fully verify the data writing, reading and data storage retention capabilities of the remaining planes through full-disk read and write tests.

[0080] In this embodiment, if the full disk read / write verification passes smoothly, it verifies that the filtered and retained plane storage performance is stable and can be directly identified as a usable data storage area of ​​the flash memory; if the full disk read / write verification fails, it indicates that even if the degraded plane is removed, the remaining storage area of ​​the flash memory still has hidden storage stability defects and cannot meet the requirements for long-term reliable storage and factory testing, thus directly determining that the flash memory is a defective flash memory.

[0081] Figure 2 A flowchart illustrating a flash memory storage stability optimization method according to another embodiment of this application is shown.

[0082] Please see Figure 2 A method for optimizing the stability of flash memory storage includes the following steps:

[0083] Step S210: Obtain the block erase status of each Plane in the flash memory, and calculate and obtain the percentage of normally erased blocks for each Plane.

[0084] It should be noted that the description of this step is in step S110, and will not be repeated here.

[0085] Further, in this embodiment, obtaining the block erase status of each Plane in the flash memory and calculating the proportion of normally erased blocks for each Plane can be performed as follows: read the protocol type of the flash memory; based on the protocol type, send a preset read command to the flash memory to obtain the block erase status of each Plane in the flash memory, the block erase status is represented by the value of the status register; convert the value of the status register, if the high 4 bits of the status register value is any one of C, D, E, F, and the low 4 bits of the status register value is even, then the current block is determined to be a normally erased block; synchronously record the Plane identifier to which the normally erased block belongs, so that the Plane to which the normally erased block belongs corresponds to the erase status; count the number of normally erased blocks in each Plane, and combine it with the total number of blocks in each Plane to calculate the proportion of normally erased blocks for each Plane.

[0086] It should be noted that, unlike step S110, this embodiment adds "synchronously recording the Plane identifier to which the normally erased block belongs." The purpose is to synchronously bind the Plane identifier of the block with the erase status data, achieving accurate matching of storage block ownership information and status information, and avoiding data statistical confusion between different Planes. This ensures the accuracy and reliability of the calculation results for the number and percentage of normally erased blocks in each Plane, providing a basis for subsequent Percentage calculations. NRB Calculations and plane filtering provide accurate data support, thereby improving the reliability of flash memory stability. For example, if a flash memory contains two planes, P0 and P1, only reading the erase status will only show two normal erase blocks, without distinguishing their ownership. After synchronously recording the plane identifier, it can be accurately distinguished that P0 contains one normal block and P1 contains one normal block. Accurately calculating their respective proportions avoids statistical errors.

[0087] Step S220: Calculate the normal erase threshold ratio of the flash memory based on the normal erase block ratio corresponding to each Plane.

[0088] It should be noted that the description of this step is in step S120, and will not be repeated here.

[0089] Step S230: Perform a first filtering operation based on the proportion of normal erase thresholds. The first filtering operation is to remove the Planes whose proportion of normal erase blocks is lower than the proportion of normal erase thresholds to obtain a first set, wherein the first set contains at least one Plane.

[0090] It should be noted that the description of this step is in step S130, and will not be repeated here.

[0091] Step S240: Perform a full disk read / write check on the Planes contained in the first set. If the full disk read / write check passes, the Planes contained in the first set are considered as usable Planes; if the full disk read / write check fails, proceed to step S250.

[0092] It should be noted that the description of this step is the same as that in step S140, and will not be repeated here. The difference is that in this embodiment, after performing a full-disk read and write verification on the Planes in the first set, the flash memory is not immediately determined to be unqualified. Instead, a secondary filtering process is initiated, which sets stricter filtering conditions to filter out Planes with stronger storage stability.

[0093] Step S250: Read the specification parameters of each Plane in the first set. The specification parameters include Plane capacity and block capacity.

[0094] It should be noted that in this embodiment, a specified operation command is sent to the flash memory to read the specification parameters of each plane. The specification parameters include plane capacity, block capacity, etc., resulting in the data shown in Table 3:

[0095]

[0096] Table 3

[0097] Step S260: Using the sum of the maximum Plane capacity and the block capacity as the base denominator, and the sum of the Plane capacity and the block capacity corresponding to each Plane in the first set as the base numerator, calculate the capacity percentage of the Planes contained in the first set.

[0098] In this embodiment, the maximum Plane capacity is used as one of the baseline denominators, mainly for the following reasons:

[0099] 1. Controlling capacity loss

[0100] Ensure that the proportion of retained planes in the total effective capacity of the flash memory is not too low, and avoid excessive loss of effective capacity due to filtering.

[0101] 2. Implicit stability optimization

[0102] The formula for calculating the capacity of a single Plane is:

[0103] Plane Capacity=Block Number×Page Number×Page Size 2)

[0104] Here, "Block Number" represents the number of blocks; "Page Number" represents the number of pages; and "Page Size" represents the page size.

[0105] A larger capacity plane indicates that its overall performance in terms of effective block count, effective page count, and actual page size is better, which can be indirectly considered as a plane with better overall stability than other planes.

[0106] In this embodiment, the maximum block capacity is used as one of the base denominators, mainly for the following reasons:

[0107] 3. Supplement the single-block stability dimension that was missed during Plane filtering.

[0108] The smallest unit for erasing flash memory is the block, and the smallest unit for programming it is the page. The formula for calculating block capacity is:

[0109] Block Capacity=Page Number×Page Size 3)

[0110] Using the block with the largest capacity as the denominator ensures that the retained blocks after filtering have the best overall index of effective page count and page size in the entire flash memory, further strengthening the filtering of the stability of the underlying cells.

[0111] Thus, based on the specifications in Table 3, Table 4 can be calculated.

[0112]

[0113] Table 4

[0114] Step S270: Perform a second filtering operation based on the capacity ratio. The second filtering operation is to remove the Planes whose capacity ratio is lower than the preset capacity threshold ratio to obtain a second set, wherein the second set contains at least one Plane.

[0115] It should be noted that, based on the calculated capacity percentage, more stringent screening conditions are added on top of the first filtering operation. Planes with a low capacity percentage generally exhibit weaker storage stability and are more prone to hidden storage failures such as bit errors and read / write anomalies under long-term high-pressure read / write scenarios. This step further filters out unstable planes by selectively eliminating weaker planes that do not meet capacity standards, completing a second filtering process on top of the first set, and progressively raising the overall stability threshold of the flash memory.

[0116] In addition, in this embodiment, since the sum of the maximum Plane capacity and the block capacity is used as the base denominator, the Plane retained by the secondary filtering can account for a certain percentage of the flash memory capacity, so as not to cause excessive loss of flash memory capacity. In other words, it avoids blindly sacrificing the entire flash memory capacity in order to pass the H2Test test.

[0117] Step S280: Perform a full disk read / write check on the Planes contained in the second set again. If the full disk read / write check passes, the Planes contained in the second set are considered usable Planes; if the full disk read / write check fails, the flash memory is determined to be unqualified flash memory.

[0118] It should be noted that this embodiment, in conjunction with the results of the two preceding filtering processes, replicates a full-disk read / write verification for the Planes in the second set, forming a multi-level verification system of filtering, specification screening, and secondary read / write verification. By measuring read / write performance, the actual data storage reliability of the remaining Planes after double filtering is verified, overcoming the limitations of single-parameter filtering. The combined logic of double filtering and secondary verification can accurately select high-quality Planes with excellent erase performance, large capacity ratio, and stable read / write operation, effectively solving the problem of the difficulty in deeply optimizing flash memory with high effective page ratio and low error bits. If the verification still fails after double filtering, it indicates that the flash memory has inherent hardware defects and is accurately judged as a non-conforming product, strictly meeting the high-standard testing requirements for flash memory leaving the factory.

[0119] Corresponding to the aforementioned method embodiments, this application discloses a flash memory storage stability optimization device and corresponding embodiments.

[0120] like Figure 3 The diagram shown is a schematic diagram of a flash memory storage stability optimization device in one embodiment of this application.

[0121] Please see Figure 3 A flash memory storage stability optimization device 300 includes: an acquisition module 310, a calculation module 320, a first filtering module 330, and a first verification module 340. Wherein:

[0122] The acquisition module 310 is used to acquire the block erase status of each plane in the flash memory, and calculate and obtain the percentage of normally erased blocks for each plane.

[0123] The calculation module 320 is used to calculate the normal erase threshold ratio of the flash memory based on the normal erase block ratio corresponding to each Plane.

[0124] The first filtering module 330 is used to perform a first filtering operation based on the proportion of normal erasure thresholds. The first filtering operation is to remove the Planes whose proportion of normal erasure blocks is lower than the proportion of normal erasure thresholds to obtain a first set, wherein the first set contains at least one Plane.

[0125] The first verification module 340 is used to perform a full disk read / write verification on the Planes contained in the first set. If the full disk read / write verification passes, the Planes contained in the first set are considered as usable Planes; if the full disk read / write verification fails, the flash memory is determined to be unqualified flash memory.

[0126] Please see Figure 3 Furthermore, as a preferred embodiment, the acquisition module 310 includes: a reading unit 311, an acquisition unit 312, a conversion unit 313, and a calculation unit 314. Wherein:

[0127] The read unit 311 is used to read the protocol type of the flash memory.

[0128] The acquisition unit 312 is used to send a preset read instruction to the flash memory based on the protocol type to obtain the block erase status of each plane in the flash memory. The block erase status is represented by the value of the status register.

[0129] The conversion unit 313 is used to convert the value of the status register. If the high 4 bits of the status register value are any one of C, D, E, and F, and the low 4 bits of the status register value are even, then the current block is determined to be a normal erase block.

[0130] The calculation unit 314 is used to count the number of normally erased blocks in each Plane, and combined with the total number of blocks in each Plane, calculates the percentage of normally erased blocks in each Plane.

[0131] It should be noted that the flash memory storage stability optimization method implemented by the flash memory storage stability optimization device disclosed in this embodiment is the same as that described in the above embodiments, and therefore will not be described in detail here. Optionally, each module and the other operations or functions described above are respectively for implementing the methods in the foregoing embodiments.

[0132] like Figure 4 The diagram shown is a structural schematic of a flash memory storage stability optimization device in another embodiment of this application.

[0133] Please see Figure 4A flash memory storage stability optimization device 300 includes: an acquisition module 310, a calculation module 320, a first filtering module 330, a first verification module 340, a specification reading module 350, a reference module 360, a second filtering module 370, and a second verification module 380. For the functions of the acquisition module 310, calculation module 320, first filtering module 330, and first verification module 340, please refer to [link to relevant documentation]. Figure 3 This will not be elaborated upon here.

[0134] The specification reading module 350 is used to read the specification parameters of each Plane in the first set, including Plane capacity and block capacity.

[0135] The baseline module 360 ​​is used to calculate the capacity percentage of the Planes contained in the first set by using the sum of the maximum Plane capacity and the block capacity as the baseline denominator and the sum of the Plane capacity and the block capacity of each Plane in the first set as the baseline numerator.

[0136] The second filtering module 370 is used to perform a second filtering operation based on the capacity percentage. The second filtering operation is to remove the Planes whose capacity percentage is lower than the preset capacity threshold percentage to obtain a second set, wherein the second set contains at least one Plane.

[0137] The second verification module 380 is used to perform a full disk read / write verification on the Planes contained in the second set. If the full disk read / write verification passes, the Planes contained in the second set are considered as usable Planes; if the full disk read / write verification fails, the flash memory is determined to be unqualified flash memory.

[0138] Please see Figure 4 Furthermore, the acquisition module 310 includes: a reading unit 311, an acquisition unit 312, a conversion unit 313, a synchronization unit 315, and a calculation unit 314. Please refer to [link to documentation] for the reading unit 311, the acquisition unit 312, the conversion unit 313, and the calculation unit 314. Figure 3 The functional description is omitted here.

[0139] The synchronization unit 315 is used to synchronously record the Plane identifier to which the normal erase block belongs, so that the Plane to which the normal erase block belongs corresponds to the erase state.

[0140] Please refer to 5, a storage control chip 500, which includes the flash memory storage stability optimization device 300 described above.

[0141] The storage control chip 500 of this application calculates the threshold ratio based on the proportion of normal erase blocks in the Plane and completes the screening and elimination, quickly screening out Planes with poor erasure stability, and performs secondary verification in combination with full disk read and write verification, accurately identifying flash memory stability defects, which can effectively improve the data storage stability of flash memory.

[0142] It should be noted that the storage controller chip 500 is a logic chip. The storage controller chip 500 consists of analog circuits, digital circuits, and a firmware layer. Other functions that perform complex digital logic functions, such as protocol processing, error correction, address mapping, and storage management algorithms, fall under the category of logic chips.

[0143] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.

[0144] Alternatively, this application may be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium) storing executable code (or computer program or computer instruction code) thereon, which, when executed by a processor of an electronic device (or server, etc.), causes the processor to perform part or all of the steps of the methods described above according to this application.

[0145] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for optimizing the stability of flash memory storage, characterized in that, include: Obtain the block erase status of each Plane in the flash memory, and calculate and obtain the percentage of normally erased blocks for each Plane; The normal erase threshold percentage of the flash memory is calculated based on the percentage of normal erase blocks corresponding to each Plane. A first filtering operation is performed based on the normal erasure threshold ratio. The first filtering operation is to remove the Plane whose normal erasure block ratio is lower than the normal erasure threshold ratio to obtain a first set, wherein the first set contains at least one Plane. A full disk read / write check is performed on the Planes included in the first set. If the full disk read / write check passes, the Planes included in the first set are considered usable Planes; if the full disk read / write check fails, the flash memory is determined to be unqualified flash memory.

2. The flash memory storage stability optimization method according to claim 1, characterized in that, If the full disk read / write verification fails, the following steps are also included: Read the specification parameters of each Plane in the first set, including Plane capacity and block capacity; Using the sum of the maximum Plane capacity and the block capacity as the base denominator, and the sum of the Plane capacity and the block capacity corresponding to each Plane in the first set as the base numerator, the capacity percentage of the Planes included in the first set is calculated respectively. A second filtering operation is performed based on the capacity ratio. The second filtering operation is to remove the Plane corresponding to the capacity ratio being lower than a preset capacity threshold to obtain a second set, wherein the second set contains at least one Plane. The full disk read / write check is performed again on the Plane included in the second set. If the full disk read / write check passes, the Plane included in the second set is considered a usable Plane; if the full disk read / write check fails, the flash memory is determined to be unqualified flash memory.

3. The flash memory storage stability optimization method according to claim 2, characterized in that, The process of obtaining the block erase status of each plane in the flash memory and calculating and obtaining the percentage of normally erased blocks for each plane includes: The protocol type for reading flash memory; Based on the protocol type, a preset read command is sent to the flash memory to obtain the block erase status of each plane in the flash memory. The block erase status is represented by the value of the status register. The value of the status register is converted. If the high 4 bits of the status register value are any one of C, D, E, and F, and the low 4 bits of the status register value are even, then the current block is determined to be a normal erase block. The number of normal erase blocks in each Plane is counted, and the percentage of normal erase blocks in each Plane is calculated by combining the total number of blocks in each Plane.

4. The flash memory storage stability optimization method according to claim 3, characterized in that, The step of converting the value of the status register, where the high 4 bits of the status register value are any one of C, D, E, and F, and the low 4 bits of the status register value are even, after determining that the current block is a normal erase block, further includes: The Plane identifier to which the normal erase block belongs is recorded synchronously, so that the Plane to which the normal erase block belongs corresponds to the erase state.

5. A flash memory storage stability optimization device, characterized in that, include: The acquisition module is used to acquire the block erase status of each Plane in the flash memory, and calculate and obtain the percentage of normally erased blocks for each Plane; The calculation module is used to calculate the normal erase threshold ratio of the flash memory based on the normal erase block ratio corresponding to each Plane. A first filtering module is used to perform a first filtering operation based on the normal erasure threshold ratio. The first filtering operation is to remove the Plane whose normal erasure block ratio is lower than the normal erasure threshold ratio to obtain a first set, wherein the first set contains at least one Plane. The first verification module is used to perform a full disk read / write verification on the Planes included in the first set. If the full disk read / write verification passes, the Planes included in the first set are considered as usable Planes; if the full disk read / write verification fails, the flash memory is determined to be unqualified flash memory.

6. The flash memory storage stability optimization device according to claim 5, characterized in that, Also includes: The specification reading module is used to read the specification parameters of each Plane in the first set, including Plane capacity and block capacity. The benchmark module is used to calculate the capacity percentage of the Plane included in the first set, with the sum of the Plane capacity and the block capacity at the maximum value as the benchmark denominator and the sum of the Plane capacity and the block capacity corresponding to each Plane in the first set as the benchmark numerator. The second filtering module is used to perform a second filtering operation based on the capacity ratio. The second filtering operation is to remove the Plane corresponding to the capacity ratio being lower than the preset capacity threshold ratio to obtain a second set, wherein the second set contains at least one Plane. The second verification module is used to perform the full disk read / write verification on the Plane included in the second set again. If the full disk read / write verification passes, the Plane included in the second set is considered a usable Plane; if the full disk read / write verification fails, the flash memory is determined to be a defective flash memory.

7. The flash memory storage stability optimization device according to claim 5, characterized in that, The acquisition module includes: The read unit specifies the protocol type used to read flash memory. The acquisition unit is used to send a preset read instruction to the flash memory based on the protocol type, and to obtain the block erase status of each plane in the flash memory. The block erase status is represented by the value of the status register. The conversion unit is used to convert the value of the status register. If the high 4 bits of the status register value are any one of C, D, E, and F, and the low 4 bits of the status register value are even, then the current block is determined to be a normal erase block. The calculation unit is used to count the number of normal erase blocks in each Plane, and calculate the proportion of normal erase blocks in each Plane by combining the total number of blocks in each Plane.

8. The flash memory storage stability optimization device according to claim 7, characterized in that, The acquisition module further includes: The synchronization unit is used to synchronously record the Plane identifier to which the normal erase block belongs, so that the Plane to which the normal erase block belongs corresponds to the erase state.

9. A storage control chip, comprising the flash memory storage stability optimization device as described in any one of claims 5 to 8.

10. A computer-readable storage medium, characterized in that, The device stores executable code that, when executed by a processor of an electronic device, causes the processor to perform the flash memory storage stability optimization method as described in any one of claims 1 to 4.

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