Memory control method and storage device

Abstract

The application provides a memory control method and a storage device. The method comprises: when a power-off warning signal is detected, an energy storage parameter of a memory is acquired to determine an operation time window; background activities of the storage device are frozen, a minimum consistent set maintained in advance and user data marked as high priority are extracted to form an emergency write queue; items in the emergency write queue are sorted based on a multi-factor weighted scoring model, the sorted items are organized into strip groups, and the strip groups are divided into multiple data strips, a redundancy strategy is dynamically selected according to the operation time window; based on the redundancy strategy, the data strips are sequentially written into a sacrifice area according to multiple planes and blocks; after the writing is completed, a read voltage parameter table is called to perform data verification. Through the cooperative design of energy budget adaptation, intelligent queue scheduling, high fault-tolerant writing and low-energy-consumption verification, reliable saving of the minimum consistent set is ensured at the moment of power-off, and fast recovery is realized after power-on.

Description

Technical Field

[0001] This application relates to the field of memory control, and more particularly to a memory control method and a memory device. Background Technology

[0002] In the NAND flash memory module (NAND Flash) storage system, logical-to-physical (L2P) address mapping is one of the core mechanisms. It not only implements the basic address mapping function, but also solves problems such as the inability of NAND Flash to be overwritten, inconsistent erase / write units, and bad block management. However, L2P tables typically require a large amount of memory resources.

[0003] Under normal power supply, NAND Flash concurrently performs host writes, garbage collection (GC), and L2P mapping updates. When a power outage occurs and the remaining energy is insufficient to complete the writing of critical metadata to disk, problems such as loss of critical metadata may easily occur after power-on.

[0004] Therefore, how to reliably preserve critical metadata and achieve rapid recovery during a power outage with highly uncertain energy levels is an urgent problem to be solved. Summary of the Invention

[0005] In view of this, this application provides a memory control method and a storage device to solve or partially solve the above problems.

[0006] In a first aspect, this application provides a memory control method applied to a storage device including a memory controller and a memory module. The method includes: in response to detecting a power failure warning signal, acquiring energy storage parameters of the memory controller and determining an operating time window based on the energy storage parameters, wherein the energy storage parameters include an effective energy storage capacitor, a minimum operating voltage, and a current voltage; freezing background activities of the storage device; extracting a pre-maintained minimum consistency set and user data marked as high priority to form an emergency write queue; wherein the minimum consistency set stores a logical-to-physical address mapping update log in a continuous interval recording manner, and the total volume of the minimum consistency set and the estimated flush time are within the normal operating range. The system is dynamically constrained to not exceed a preset emergency time threshold, which is determined based on the minimum energy of the energy storage capacitor. Items in the emergency write queue are sorted using a multi-factor weighted scoring model, organized into stripe groups, and further divided into multiple data stripes. A redundancy strategy is dynamically selected based on the operation time window. Based on the redundancy strategy, the data stripes are written to the sacrificial region in a sequence spanning multiple planes and blocks. Each stripe is updated with a progress marker immediately after writing, stored in a fixed location within the sacrificial region, used to identify partially written stripe groups during power-on recovery. After writing is complete, a pre-learned and optimized read voltage parameter table is called for data verification.

[0007] A second aspect of this application provides a storage device, comprising: a connection interface for electrically connecting to a host system; a memory module including multiple planes, each plane including multiple blocks, each block including multiple physical pages; and a memory controller including error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module; wherein the memory controller is configured to perform the memory control method as described in the first aspect.

[0008] This application provides a memory control method and a storage device. The method includes: upon detecting a power failure warning signal, acquiring the energy storage parameters of the memory to determine an operation time window; freezing the background activities of the storage device, extracting a pre-maintained minimum consistency set and user data marked as high priority, and forming an emergency write queue; sorting the items in the emergency write queue based on a multi-factor weighted scoring model, organizing the sorted items into stripe groups, and dividing them into multiple data stripes, dynamically selecting a redundancy strategy according to the operation time window; based on the redundancy strategy, writing the data stripes into the sacrificial region in a sequence spanning multiple planes and blocks; after writing is completed, calling a pre-learned optimized read voltage parameter table for data verification. Through the collaborative design of adaptive energy budget, intelligent queue scheduling, high fault-tolerant writing, and low-energy verification, reliable preservation of the minimum consistency set is ensured at the moment of power failure, and rapid recovery is achieved after power-on. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0010] Figure 1 A schematic diagram of an exemplary memory storage system according to an embodiment of this application is shown.

[0011] Figure 2 A schematic diagram of an exemplary memory controller according to an embodiment of this application is shown.

[0012] Figure 3 A schematic diagram of an exemplary memory management module according to an embodiment of this application is shown.

[0013] Figure 4 A flowchart illustrating an exemplary memory management method according to an embodiment of this application is shown. Detailed Implementation

[0014] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0016] Figure 1 A schematic diagram of an exemplary memory storage system 100 according to an embodiment of this application is shown.

[0017] like Figure 1As shown, the memory storage system 100 includes a host system 102 (also referred to as a host) and a storage device 104. The host system 102 can be any type of computer system, such as a laptop computer, desktop computer, smartphone, tablet computer, industrial computer, etc. The storage device 104 is used to store data from the host system 102. The storage device 104 may include a solid-state drive (SSD), universal flash storage (UFS), embedded multimedia card (eMMC), secure digital card (SD), USB flash drive, or other types of non-volatile storage devices. The host system 102 can be electrically connected to the storage device 104 via a Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCI Express), Universal Serial Bus (USB), or other types of connection interfaces. Therefore, host system 102 can store data to storage device 104 and / or read data from storage device 104.

[0018] Storage device 104 may include a connection interface 1041, a memory module 1042, and a memory controller 1043. The connection interface 1041 is used to connect storage device 104 to host system 102. Storage device 104 can communicate with host system 102 via connection interface 1041.

[0019] Memory module 1042 is used to store data. Memory module 1042 may include a non-volatile memory module. Memory module 1042 includes an array of memory cells. The memory cells in memory module 1042 store data in the form of voltage. In some embodiments, memory module 1042 may be a NAND flash memory module (NAND Flash).

[0020] Memory controller 1043 is connected to connection interface 1041 and memory module 1042. Memory controller 1043 can be used to control storage device 104; for example, memory controller 1043 can control connection interface 1041 and memory module 1042 for data access and data management. For example, memory controller 1043 may include a central processing unit (CPU), graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices.

[0021] In some embodiments, the memory controller 1043 is also referred to as a flash memory controller or flash memory module. The memory module 1042 may receive a sequence of instructions from the memory controller 1043 and read data stored in the memory cells according to the sequence of instructions.

[0022] Figure 2 A schematic diagram of an exemplary memory controller 1043 according to an embodiment of this application is shown.

[0023] Please refer to Figure 1 and Figure 2 The memory controller 1043 includes a host system interface 12, a memory interface 16, and a memory control circuit 14. The host system interface 12 is used to connect to the host system 102 via a connection interface 1041 for communication with the host system 102. The memory interface 16 is used to connect to the memory module 1042 for access to the memory module 1042.

[0024] Memory control circuitry 14 is connected to host system interface 12 and memory interface 16. Memory control circuitry 14 can be used to control or manage the overall or partial operation of memory controller 1043. For example, memory control circuitry 14 can communicate with host system 102 via host system interface 12 and access memory module 1042 via memory interface 16. For example, memory control circuitry 14 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 14 is equivalent to the description of memory controller 1043.

[0025] In some embodiments, the memory controller 1043 may further include a buffer memory 20. The buffer memory 20 is connected to the memory control circuitry 14 and is used to cache data. For example, the buffer memory 20 may be used to cache instructions from the host system 102, data from the host system 102, and / or data from the memory module 1042. In particular, a logical-to-physical mapping table is typically resident or cached in the buffer memory 20 to support high-speed access and updates.

[0026] In some embodiments, the memory controller 1043 may further include an error checking and correction circuit 22. The error checking and correction circuit 22 is connected to the memory control circuit 14 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 22 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In some embodiments, the memory controller 1043 may also include other types of circuit modules (e.g., power management circuits), which are not limited herein.

[0027] In some embodiments, the memory controller 1043 may further include a power management circuit 18. The power management circuit 18 is connected to the memory control circuit 14 and is used to control the power supply to the storage device 104.

[0028] Figure 3 A schematic diagram of an exemplary memory management module according to an embodiment of this application is shown.

[0029] Please refer to Figures 1 to 3 The memory module 1042 includes multiple physical units 301(0)-301(B). Each physical unit includes multiple storage cells for non-volatile data storage.

[0030] In some embodiments, an entity unit may include an entity programming unit. In some embodiments, an entity programming unit is also referred to as an entity programming unit. In some embodiments, an entity programming unit may be considered as an entity page.

[0031] In some embodiments, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application does not impose any limitations. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited to this.

[0032] In some embodiments, a physical programming unit is the smallest unit of synchronously written data in the memory module 1042. For example, when performing a programming operation (also known as a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0033] In some embodiments, an entity erasure unit may comprise multiple entity programmatic units. In some embodiments, an entity erasure unit may be considered as an entity block.

[0034] In some embodiments, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0035] In some embodiments, the memory control circuit 14 can logically associate physical units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Physical units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 102. For example, any physical unit in the data area 31 can store valid data and / or invalid data. Furthermore, physical units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0036] In some embodiments, if a unit does not store valid data, it may be associated with the free zone 32. Furthermore, units in the free zone 32 may be erased to clear the data within them. In some embodiments, units in the free zone 32 are also referred to as idle units. In some embodiments, the free zone 32 is also referred to as the free pool.

[0037] In some embodiments, when data needs to be stored, the memory control circuit 14 may select one or more physical units from the idle area 32 and instruct the memory module 1042 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0038] In some embodiments, the memory control circuit 14 may configure multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0039] In some embodiments, if a physical unit is currently mapped by any logical unit, the memory control circuit 14 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 14 can determine that this physical unit does not currently store any valid data.

[0040] In some embodiments, the memory control circuit 14 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-physical mapping table, or L2P table). In some embodiments, the memory control circuit 14 may instruct the memory module 1042 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0041] As mentioned above, Nand Flash concurrently performs host writes, garbage collection (GC), and L2P mapping updates under normal power supply. When a brown-out occurs and the remaining energy is insufficient to complete the writing of critical metadata to disk, problems such as loss of critical metadata may easily occur after power-on.

[0042] For example, if the L2P update has not yet been written back to the Nand Flash during a power outage, the L2P mapping cannot be used directly after power-on. In this case, the mapping page needs to be scanned and the L2P mapping needs to be rebuilt, which makes the data recovery timed. If the data is not written to the Nand Flash during a power outage or is written to the Nand Flash but the L2P mapping is not updated, it will lead to user data loss or rollback exceeding limits. Using methods such as normal SLC (Single-Level Cell) write caching, data migration / log compression, or host state-triggered recycling cannot guarantee recovery even in the case of a one-time minimum disk setup with extremely low energy and partial write success.

[0043] To at least address the aforementioned issues, this application provides a memory control method and a storage device. The method includes: upon detecting a power failure warning signal, acquiring the memory's energy storage parameters to determine an operation time window; freezing the background activities of the storage device, extracting a pre-maintained minimum consistency set and user data marked as high priority, and forming an emergency write queue; sorting the items in the emergency write queue based on a multi-factor weighted scoring model, organizing the sorted items into stripe groups, and dividing them into multiple data stripes, dynamically selecting a redundancy strategy according to the operation time window; based on the redundancy strategy, writing the data stripes to the sacrificial region in a sequence spanning multiple planes and blocks; and after writing is complete, calling a pre-learned optimized read voltage parameter table for data verification. Through the collaborative design of adaptive energy budget, intelligent queue scheduling, high fault-tolerant writing, and low-energy verification, reliable preservation of the minimum consistency set is ensured at the moment of power failure, and rapid recovery is achieved after power-on.

[0044] Figure 4 A flowchart illustrating an exemplary memory control method 400 according to an embodiment of this application is shown. This method 400 is used to achieve emergency write-to-write and rapid consistency recovery of critical data in a memory controller 1043 with limited remaining energy. Figure 4 As shown, method 400 may include the following steps.

[0045] In step 402, an adaptive emergency operation window is dynamically decided based on the energy budget. The memory controller can monitor the supply voltage and its rate of decline in real time. When a power failure warning signal is detected, the energy storage parameters of the memory controller are obtained, and the operation time window T is determined based on the energy storage parameters. ∗ This provides strict time budget constraints for all subsequent emergency operations. The energy storage parameters include the effective energy storage capacity, minimum operating voltage, and current voltage.

[0046] In some embodiments, the remaining energy E is calculated using the following formula, based on the current voltage V sampled by the analog-to-digital converter (ADC) and the slope:

[0047]

[0048] Where C is the effective energy storage capacitor of the memory controller 1043. This is the minimum operating voltage for the memory controller 1043.

[0049] Combined with the average power consumption of historical emergency writes The average power consumption is initialized to a preset conservative value and dynamically updated based on the actual power consumption after each emergency write operation. The minimum available time is then obtained based on the remaining energy and the dynamically updated average power consumption. Finally, a safety factor is introduced. Determine the emergency operation time window Average power consumption based on historical emergency writes Recording dynamic updates allows for adjustments to the emergency operation time window T. ∗ The estimates are becoming increasingly accurate.

[0050] This application embodiment dynamically calculates the safety factor by sampling voltage and drop slope in real time, combined with hardware capacitor parameters and historical power consumption data, and accurately estimates the emergency operation time window that changes over time. This method transforms abstract energy reserves into concrete, executable time budgets, subjecting all subsequent operations to this hard constraint and fundamentally avoiding write failures caused by energy misjudgment.

[0051] In related technologies, after a power failure warning is triggered, a redundancy strategy is dynamically selected based on the current T*. However, there is a brief delay (milliseconds) between the voltage drop and the completion of T* estimation. If the voltage drop slope is very steep, T* may be extremely short, while the encoding and writing of the XOR(4+1) scheme still require some time, and may not be able to complete in time.

[0052] In one embodiment, to cope with extreme power-down scenarios where the voltage drop slope is extremely steep, during normal operation, the memory controller 1043 not only monitors the absolute value of the voltage but also continuously calculates the second derivative (i.e., acceleration) of the voltage drop slope. When the acceleration of the drop slope is detected to exceed a threshold (e.g., the voltage drops rapidly), even if a power-down warning has not yet been triggered, the memory controller 1043 pre-switches to a low-redundancy mode. In other words, while determining the operating time window T*, it further includes continuously monitoring the second derivative of the voltage drop slope and pre-switching the redundancy strategy.

[0053] Specifically, during normal operation, the memory controller 1043 calculates the first derivative (i.e., the falling slope, dv / dt) and the second derivative (i.e., the acceleration of the slope, d²v / dt²) of the voltage V with respect to time t in real time. Three slope intervals are defined: a stable region (dv / dt < k1), a slow descent region (k1 ≤ dv / dt < k2), and a rapid descent region (dv / dt ≥ k2), where k1 and k2 are preset thresholds.

[0054] When it is detected that the voltage enters the slow descent region and the second derivative is positive (i.e., the voltage is accelerating downwards), the memory controller 1043 switches the maintenance strategy of the minimum consistency set (MCS) from standard compression to ultra-low redundancy pre-compression. That is, multiple MCS buckets are merged into a smaller set in advance (for example, only the root node and the most recent N interval records are retained), ensuring that even if T* is very short, the most core mappings can be saved.

[0055] When it is detected that the voltage enters the rapid descent region, the memory controller 1043 actively triggers an emergency write process. Without waiting for the power-off warning signal, it directly starts to actively write the most critical entries (such as the current active bucket) in the current active bucket to the sacrifice area, while continuing to monitor the voltage. If the voltage subsequently recovers above the slow descent region, the emergency write is aborted and marked for cleaning; if the voltage continues to drop, a head start has been achieved to complete partial saving.

[0056] The above embodiments utilize voltage trend prediction to change passive response to active anticipation, which can争取额外的数毫秒写入时间,提高存活率。此方案与能量预算自适应的方案形成时间域上的互补。

[0057] In one embodiment, in order to further reduce the delay caused by MCS compression at the moment when the power-off warning is triggered, the memory controller 1043 actively performs MCS pre-compression based on the prediction of the host IO mode.

[0058] Specifically, during normal operation, the memory controller 1043 continuously monitors the access mode characteristics of the host: consecutive sequential writes, random small writes, intensive file system metadata updates, etc. Using a lightweight online predictor (such as based on linear regression or state machine), when it is predicted that the host will initiate a large number of metadata updates (such as file system defragmentation, database log flushing) within a short period of time in the future (for example, within the next 1 second), the memory controller 1043 actively performs MCS compression in advance: merging all the currently unflushed buckets to generate a more compact MCS snapshot, and writing this snapshot in advance to a reserved area in the sacrifice area (referred to as the pre-compression staging area).

[0059] It should be noted that there is an unclear expression in the original text of . I have translated it as best as possible according to the context, but it may need to be adjusted according to the specific meaning.When an actual power outage warning occurs, the memory controller 1043 no longer needs to perform compression operations; it can directly extract the most recent pre-compressed snapshot for incremental supplementation. Furthermore, the memory controller 1043 assigns a prediction confidence score to the pre-compressed snapshot. If the actual host behavior deviates from the prediction by more than a threshold (e.g., predicted as intensive updates but actually idle), the pre-compressed snapshot is discarded, and the predictor weights are adjusted. These predictor parameters are calibrated online based on feedback from the actual compression time after each power outage. This shifts the compression operation from the power outage trigger to the idle period, leveraging machine learning to predict host behavior, further reducing the time overhead of emergency handling.

[0060] In one embodiment, to further optimize the energy budget allocation strategy under different power outage scenarios, the memory controller 1043 continuously learns and records the pattern characteristics of historical power outage events during normal operation, including: the time interval between power outages, the average slope of voltage drop, the ratio of successfully saved MCS size to actual time consumption, and the types of items that ultimately failed to be saved. Based on the learned statistical distribution, the memory controller 1043 divides a preset energy reservation pool into multiple virtual budget slots with different priority levels.

[0061] Specifically, when the current power-down mode is detected to match a historical high-success-rate mode (e.g., voltage drop slope is in the same range and host write load is similar), the memory controller 1043 dynamically adjusts the safety factor γ and the MCS compression trigger threshold, allowing more energy budget to be reserved for high-consistency critical projects (such as root node updates). Conversely, if the current mode is detected to match multiple historical low-success-rate modes (e.g., extremely steep instantaneous voltage collapse), the memory controller 1043 proactively switches the redundancy strategy to XOR(2+1) by default and initiates asynchronous migration in advance, freeing up sacrificial region space to accommodate more critical data. This learning model uses incremental updates; after each complete power-down → power-on recovery process, the memory controller 1043 uses the actual result as a training sample to update the parameter weights of the mode matching. By using historical data to drive current decisions, the energy allocation strategy possesses memory and adaptive evolution capabilities, unlike traditional solutions that rely on fixed or only real-time parameters.

[0062] In step 404, an emergency queue can be constructed and dynamically sorted. When a power failure warning signal is detected, the system immediately freezes background activities of the storage device (such as garbage collection), extracts the pre-maintained minimal consistency set (MCS) and user data marked as high priority, and forms an emergency write queue.

[0063] In some embodiments, during normal operation of the storage device, the memory controller 1043 continuously maintains a compressed, differential logical-to-physical address (L2P) mapping update log, i.e., MCS. This mechanism defines a minimum consistency set data structure, which stores the logical-to-physical address mapping update log in a continuous interval recording manner. The total volume of the minimum consistency set and the estimated flush time are dynamically constrained during normal operation to not exceed a preset emergency time threshold, which is determined based on the minimum energy of the energy storage capacitor. This forward-looking constraint design ensures that, upon power failure, the MCS can be directly used for emergency flushing without temporary reorganization, guaranteeing deterministic operation within a very short time window.

[0064] To meet the dual requirements of speed and reliability for emergency writes, the MCS can be maintained using an efficient compression and encapsulation format, designed to record mapping changes with minimal data volume and ensure rapid writes. In some embodiments, the MCS can consist of a series of basic storage units called entries. Each entry records the latest mapping relationship of a contiguous logical address, including key information such as the starting logical address, contiguous length, corresponding physical address hints, and timestamps.

[0065] For example, the entry {LBA:1000,Len:8,Phy:0xA300,TS:t1} indicates that the latest data in logical addresses 1000-1007 is located in physical block 0xA300. This continuous range recording method reduces the amount of data that needs to be stored.

[0066] In some embodiments, multiple entries are packaged into a fixed-size bucket as a management unit. Each bucket has a management header, which includes a bucket ID, the number of entries, a logical address range, pointers to the preceding and following buckets (forming a doubly linked list), and the operation time window T when the bucket was created. ∗ Estimated values ​​and checksums. The size of each bucket is designed so that its write / flush time is much shorter than the typical operation time window T. ∗ .

[0067] During storage device operation, in some embodiments, new mapping updates are appended to the currently active bucket. When the active bucket is about to fill or reaches a time threshold, it is evaluated whether the total time to write all unflushed buckets to the storage module is greater than an urgent time threshold. If it is greater than the urgent time threshold, a compaction operation is triggered, merging old entries in all unflushed buckets so that the total flush time of the compacted minimum consistency set meets the constraint of the urgent time threshold.

[0068] In related technologies, the trigger condition for MCS compression is that the active bucket is about to fill up or reaches a time threshold, and the compression target is that the total write time does not exceed the emergency time threshold. However, the emergency time threshold is a fixed value determined based on the minimum energy of the energy storage capacitor. As the capacitor ages, its actual effective capacitance will decrease; at the same time, the host's write mode (sequential / random) will also affect the growth rate of MCS. A fixed threshold will lead to two problems: after the capacitor ages, the fixed threshold may be too high, and the MCS may not be able to complete the write operation when power is lost; or when the capacitor is healthy, the threshold may be too conservative, and frequent compression will affect performance.

[0069] In one embodiment, to adapt to the aging of the energy storage capacitor and the dynamic changes in the host write mode, an adaptive emergency time threshold adjustment mechanism is proposed. That is, the emergency time threshold for triggering compression is not a fixed value, but rather adopts an adaptive adjustment mechanism.

[0070] Specifically, the memory controller 1043 performs a capacitor health self-test after each power-on of the storage device: when the storage device is idle, it performs a test write operation with a known time consumption (e.g., writing a fixed-size data block to a dedicated test area / an idle physical block), measures the voltage drop during the process, and, combined with the known write power consumption, deduces the current effective energy storage capacitor value C_effective, and compares it with the factory nominal value C_nominal to obtain the capacitor aging factor α = C_effective / C_nominal.

[0071] Then, the emergency time threshold is dynamically updated: T_threshold_new = T_threshold_base × α. Where T_threshold_base is the reference value calibrated at the factory based on the nominal capacitance.

[0072] Furthermore, the memory controller 1043 can continuously learn the host's write patterns: statistically analyze the growth rate (bytes / second) of MCS entries per unit time and record historical peak values. When the active bucket is about to be full or reaches a time threshold, the memory controller 1043 not only evaluates the total flush time of all currently unflushed buckets, but also predicts the expected growth of the MCS within a future emergency time threshold cycle. If the predicted total flush time after growth is greater than the dynamically updated emergency time threshold, compression is triggered in advance to avoid the MCS being unable to be saved due to insufficient compression at the last moment before power failure.

[0073] The above embodiments enable the MCS compression strategy to adapt to hardware aging and dynamic workload, avoiding both overly optimistic over-optimism leading to power failure after capacitor aging and excessive compression sacrificing performance under healthy capacitors.

[0074] In step 406, the items in the emergency write queue are sorted based on the multi-factor weighted scoring model, the sorted items are organized into strip groups and divided into multiple data strips, and a redundancy strategy is dynamically selected according to the operation time window.

[0075] Multifactor weighted scoring model As shown below:

[0076]

[0077] in, Indicates the consistency criticality. Indicates the risk level of the medium. Indicates the priority of host commands. The weights represent the factors. This multi-factor weighted scoring model can quantify the score of each item to be saved (such as an MCS entry or user data) in the queue to determine the order of urgent writes.

[0078] In some embodiments, the multi-factor weighted scoring model considers the following indicators:

[0079] Consistency criticality This indicates the degree of impact of a project on the consistency of the global L2P mapping table. The consistency criticality values ​​for different projects are shown below:

[0080] Mapping table root node update: (Most crucial)

[0081] Range updates spanning multiple logical blocks:

[0082] Single logical page update:

[0083] Internal log:

[0084] Media Risk (Memory Module 1042) Level The current health status of the target flash memory physical cell (such as erase / write cycles, bit error rate) is used to comprehensively assess the health of the target physical block.

[0085] Media risk level The calculation formula is as follows:

[0086]

[0087] Where P / E represents the number of erase / write cycles, and RBER represents the original bit error rate. This represents the measured and cached programming time when the history was written to this physical block, and Norm indicates normalization to [0,1].

[0088] Host command priority The write urgency flag issued by the host is used to directly convey the priority of host commands (e.g., urgent = 1.0, normal = 0.2, background = 0.0). Items with higher scores are processed first to ensure that the most critical data is written before energy is exhausted.

[0089] A root node update Write to a medium wear block The host is marked as a normal command. Assuming the weight is Then its emergency queue score is: .

[0090] In related technologies, although the total time window T* is estimated, the actual time taken for each item (MCS entry, user data) in the emergency queue during writing is affected by factors such as the die state of the memory module 1042 (e.g., whether it is busy with other operations), wear level, and redundancy strategy calculation overhead, resulting in fluctuations. If writing is simply done sequentially, uneven time taken for early items may lead to insufficient energy and failure of later items.

[0091] In one embodiment, to further improve the write success rate within a limited operation time window T*, a scheme is proposed that includes time slice pre-allocation and dynamic re-evaluation for each item in the emergency write queue.

[0092] Specifically, after building the emergency queue and before starting the write operation, the memory controller 1043 pre-calculates an estimated execution time slice for each item. This time slice includes: data read time, redundancy coding calculation time, cross-die or plane programming / write time, and verification read time.

[0093] In detail, the memory control circuit 14 reads the item data from the buffer memory 20, calculates the parity striping time according to the selected redundancy strategy (XOR or RS), writes the data stripes across multiple flash memory chips and the memory module 1042 that programs the planar sequence, and the low-energy check read time after writing.

[0094] Before writing to each item, the memory controller 1043 checks whether the current remaining time T*_remaining is greater than 1.2 times the estimated time slice of that item (safety margin). If not, the item is skipped (or only its metadata pointer is saved), and a smaller / more critical item is written instead.

[0095] After each item is written, the memory controller 1043 measures its actual time and updates the remaining operation time window in real time: T_remaining = T_remaining − actual_time. Simultaneously, based on the deviation between the actual time and the estimated time, an exponentially weighted moving average (EWMA) is used to dynamically adjust the estimation coefficients for subsequent items. When the remaining time budget (T_remaining) is less than the preset minimum atomic operation time (e.g., one page programming time), the memory controller 1043 actively stops writing new items and immediately enters the verification and finalization phase to avoid unrecoverable writes to the last item due to energy depletion.

[0096] The above embodiments refine the energy budget from a global, one-time allocation to item-by-item reservation and dynamic feedback, improving the write success rate under extreme time windows and avoiding cascading failures caused by fluctuations in the time consumption of individual projects. This scheme works in conjunction with progress markers to further record the completion status of each project, forming a complete atomicity guarantee chain.

[0097] In one embodiment, to prevent L2P table inconsistencies caused by partial commits of the mapping update log due to energy depletion, the memory controller 1043 further performs dependency resolution and atomic grouping after constructing the emergency write queue.

[0098] Specifically, the memory controller 1043 scans each MCS entry in the queue and identifies a chain of entries with logical dependencies (e.g., a range update entry is split into two consecutive sub-range update entries, and the invalidation of the old entry depends on the activation of the new entry).

[0099] The memory controller 1043 forcibly assigns these interdependent entries to the same stripe group and ensures that the stripe group uses atomic commit semantics during writes: the status field in the metadata of the stripe group is only set to committed after the write progress flags of all data stripes and parity stripes within the stripe group have been updated to complete and verified. If a power failure occurs during the write process of the stripe group, and the controller detects that the status field is uncommitted upon power-up, it directly discards all data in the stripe group and rolls back to the last saved MCS snapshot. Furthermore, the controller generates a globally unique commit sequence number for each stripe group, which is linked to the version number of the L2P table. This ensures that the latest valid mapping can be identified during recovery, avoiding logical addresses being mapped to overwritten physical addresses due to partial commits. This solves the atomicity problem between multi-entry mapping updates, a crucial point easily overlooked in traditional power-loss protection schemes, and improves the logical consistency of the L2P table after power-up.

[0100] In step 408, based on the redundancy strategy, data stripes are written to the sacrificial region in sequence across multiple planes and blocks; wherein, after each stripe is written, a progress marker is updated immediately, and the progress marker is stored in a fixed position within the sacrificial region to identify the partially written stripe group during power-on recovery.

[0101] A highly fault-tolerant emergency write channel supporting partial write success is provided. To ensure that critical data can still be recovered even if the write operation is unexpectedly interrupted in the extremely short time before energy depletion, this application innovatively combines sacrificing the SLC region, striped writing, and adaptive redundancy coding (XOR / RS) to construct an emergency write channel. Its core lies in the fact that the system can adjust the remaining operation time window T based on the remaining time window. ∗ Dynamically selecting redundancy strategies (e.g., XOR for tight deadlines, RS for ample time) and combining this with sequential writes across dies / planets ensures that even if only some stripes are successfully written, data can still be fully recovered using the k-of-n rule, significantly improving data survival rate under extreme conditions. The k-of-n rule is a criterion that states the system is considered usable / successful if at least k of the n components are functioning correctly.

[0102] The sorted data will be written to a dedicated SLC sacrifice area for emergencies. To ensure data recoverability in extreme situations, striped writing is employed, supplemented by adaptive redundancy coding.

[0103] In some embodiments, data is segmented into multiple data stripes. A single emergency write constitutes a stripe group containing n data stripes and r parity stripes. Metadata describing this stripe group is crucial, recording information such as the encoding scheme (XOR / RS), the number of stripes, the data logical range, and the die / plane location of each stripe. The encoding scheme indicates whether a simple XOR check is used or a more complex Reed-Solomon (RS) erasure code is employed. The number of stripes specifies the exact number of data stripes and parity stripes. The data logical range describes the logical address range protected by this stripe group. The physical layout records which flash memory die and plane each stripe is located on; this is critical information for enabling parallel writes across cells and avoiding single points of failure. A backup scheme is an optional backup encoding scheme identifier used to attempt recovery if the primary scheme fails.

[0104] In some embodiments, the system may use an estimated operation time window T ∗ Dynamically select redundancy strategies. When time is tight (operation time window is less than the first threshold), use computationally simple XOR coding (e.g., 4 data stripes + 1 parity stripe); when time is ample (operation time window is greater than or equal to the second threshold), use RS erasure coding with stronger fault tolerance.

[0105] For example, in response to the operation time window Then, the XOR (4+1) scheme is adopted, that is, 4 data stripes are matched with 1 odd stripe, and a maximum of 1 stripe loss is tolerated. This responds to the operation time window. If the condition is met, the RS (6+3) scheme can be used, which consists of 6 data stripes with 3 odd and even stripes, tolerating a maximum of 3 stripe losses. This provides stronger fault tolerance and can handle more extreme media failures. If the operating time window T* is greater than or equal to the first threshold and less than the second threshold, the XOR (2+1) scheme can be used.

[0106] In some embodiments, stripes are written to the sacrificial region in a strict order across multiple planes and blocks to maximize write bandwidth and reliability. For metadata protection, in some embodiments, metadata describing the stripe group is written in duplicate to the beginning and end positions of the stripe group to prevent the entire group from becoming unrecognizable due to partial media failure.

[0107] In related technologies, items in the emergency write queue are processed sequentially, with the next stripe group only proceeding after each stripe group has been written. When T* is relatively ample (e.g., ≥3ms) and the storage device has multi-die parallel capabilities, sequential writing fails to fully utilize the bandwidth of the memory module 1042, potentially resulting in energy waste (because the programming current of the memory module 1042 still consumes standby power even when idle).

[0108] In one embodiment, in order to fully utilize the parallel write capability of the memory module 1042 to increase the total amount of data written within the emergency time window T*, the memory controller 1043 further executes a dynamic parallelism adjustment and hybrid redundancy strategy.

[0109] Specifically, the memory controller 1043 calculates the maximum parallelism P_max=min(number of available dies, floor(T* / T_program)) based on the length of the currently estimated operation time window T* and the number of available free dies in the storage device (excluding worn or bad blocks), where T_program is the single-page programming time (e.g., 200 microseconds).

[0110] If P_max ≥ 2, the memory controller 1043 packages multiple items at the top of the urgent write queue (e.g., two MCS buckets or one MCS bucket plus one high-priority user data) into a single parallel write task. This parallel write task can interleave data stripes from different items onto different dies for simultaneous writing. For example, stripe 0 of item A is written to Die 0, stripe 0 of item B is written to Die 1, stripe 0 of item C is written to Die 2, and so on.

[0111] Simultaneously, different redundancy strategies are used in combination based on the criticality of each project. Specifically, for projects with a consistency criticality I_c ≥ 0.7 (such as mapping table root node updates / MCS root nodes), a high redundancy scheme of RS(6+3) is adopted. For projects with I_c < 0.7, an XOR(4+1) or XOR(2+1) scheme is used. However, all stripes are physically interleaved during writing. The memory controller 1043 maintains a global stripe group mapping table, recording which project each stripe belongs to and what type of redundancy is used.

[0112] The memory controller 1043 maintains a global stripe group mapping table, recording the project to which each stripe belongs and its redundancy policy. When energy is about to run out, the memory controller 1043 prioritizes submitting partially completed parallel tasks. For example, a parallel task marks a project as recoverable as long as the number of surviving stripes meets the minimum requirement of its redundancy policy (e.g., XOR(4+1) requires at least 4 surviving stripes), without waiting for all stripes to complete.

[0113] The above embodiments fully utilize the parallel writing capability of multiple dies, enabling the writing of more data within the same time window T*, or providing higher redundancy for critical data. The hybrid redundancy strategy further optimizes the energy input-output ratio. Striped writing is extended from a single stripe group to a parallel scheduling level across projects.

[0114] In related technologies, during power-on recovery, the sacrificed region is scanned first, all stripe groups are reconstructed, the MCS is replayed, and finally, asynchronous migration is performed. This process involves a full scan and a full reconstruction, which may have two efficiency issues: First, if the sacrificed region is large, scanning all physical pages takes a long time, affecting the system's rapid availability; second, for partially written stripe groups (progress markers indicate that only part of the stripes have been completed), existing solutions require a complete reconstruction of all stripes (including unwritten stripes), resulting in unnecessary computation.

[0115] In one embodiment, in order to further improve the reconstruction efficiency of partial write stripe groups during power-on recovery, a priority-based hierarchical recovery and incremental reconstruction scheme is proposed.

[0116] Specifically, the memory controller 1043 pre-maintains a metadata index block in the sacrificial region. This index block stores the logical address range, redundancy policy, list of live stripes (generated based on progress markers), and highest consistency criticality of the MCS entries contained in each stripe group in a B+ tree or skip table structure.

[0117] Upon power-up, the memory controller 1043 first reads the index block (which is of fixed size and can be loaded within microseconds) instead of scanning the entire sacrificed region. Then, the memory controller 1043 reconstructs the stripe groups in priority order: priority is determined by the highest consistency criticality recorded in the index block, with the stripe group containing the root node update (I_c=1.0) having the highest priority, followed by the interval mapping update (I_c=0.7), single-page mapping update (I_c=0.3), and user data (I_c=0). The stripe group containing the root node and critical mappings is reconstructed first, enabling the L2P table to quickly return to a serviceable state (even if some user data has not yet been recovered).

[0118] For stripe groups where the progress markers indicate partial writes, the memory controller 1043 employs a breakpoint-resume reconstruction method. Specifically, based on the mathematical properties of redundancy coding, only the missing stripes are reconstructed. For example, for the XOR(4+1) scheme, if three data stripes and one odd / even stripe are known, and the fourth data stripe needs to be recovered, only one XOR operation needs to be performed, without needing to fully decode all stripes.

[0119] During the reconstruction process, once all MCS entries with a consistency criticality I_c ≥ 0.7 have been reconstructed and replayed (i.e., all MCS entries have been restored), the L2P mapping table reaches a safe point, and the memory controller 1043 immediately releases the blocking of host read and write requests, allowing the front end to access; at the same time, the background continues to reconstruct the remaining entries with I_c < 0.7 and user data.

[0120] In one embodiment, each stripe group corresponds to a progress marker bitmap. This bitmap records not only whether each data stripe has been written successfully, but also the verification status of each stripe (whether it has passed low-energy checksum verification). The bitmap is stored atomically in two independent physical pages (which serve as backups of each other) within the sacrificial region. When a power failure causes partial writing to a stripe group, upon power-up, the memory controller 1043 first reads the bitmap to identify the set of stripes that have been successfully written and verified.

[0121] The above embodiments optimize the power-on recovery time from full recovery to incremental and priority recovery, shortening the system unavailability window (from seconds to milliseconds). Breakpoint-resume reconstruction reduces redundant computation and lowers energy consumption during the recovery process (especially important for battery-powered devices).

[0122] In one embodiment, to address the issue of insufficient capacity or waste that may result from a fixed size of the sacrificial region, the memory controller 1043 dynamically adjusts the number of physical blocks in the sacrificial region based on the historical distribution of the current operating time window T* and the aging degree of the energy storage capacitor.

[0123] Specifically, the memory controller 1043 maintains an energy-to-capacity mapping function that maps the currently estimated T* to the minimum number of physical blocks required for the sacrifice region N_required=ceil(T* / T_block_program), where T_block_program is the estimated time to erase and program a complete physical block (including all pages).

[0124] During normal operation, the memory controller 1043 dynamically allocates additional physical blocks from the idle area to the sacrificial area, or releases physical blocks that have not been used for a long time in the sacrificial area back to the idle area. When it detects that T* is continuously below a certain low threshold (e.g., T* is less than 1ms in three consecutive power outage events), the memory controller 1043 actively shrinks the sacrificial area and uses the released physical blocks to accelerate garbage collection or wear leveling to improve normal performance. At the same time, the memory controller 1043 maintains an emergency write count for each physical block in the sacrificial area. When a block is frequently used for emergency writes (e.g., the count exceeds the threshold), it is marked as a high-wear block and rotated in advance to avoid write failures in the sacrificial area at critical moments due to concentrated wear. In this way, the size of the sacrificial area is dynamically correlated with the real-time energy budget, historical power outage patterns, and wear status, avoiding both insufficient capacity and resource waste.

[0125] In step 410, after the writing is completed, the pre-learned and optimized read voltage parameter table is called to verify the data.

[0126] A low-energy, rapid verification method for emergency scenarios. Addressing the energy constraints of the verification process after a power outage, this application's embodiments design a specialized low-energy verification read process. By calling a read voltage parameter table pre-learned for emergency scenarios, the energy-intensive full threshold scan is replaced. Upon read failure, the process directly jumps to a high-intensity ECC (Error Correction Code) mode, completing data verification with minimal rereads and energy consumption, thus saving critical energy.

[0127] To save energy and time, in some embodiments, a pre-learned and optimized Read Voltage Parameter Table (RVPT) can be invoked for rapid data reading and verification. If the data cannot be correctly read from the RVPT, the system jumps directly to a stronger Error Correction (ECC) level for rereading, avoiding time-consuming full threshold scanning. The RVPT is dynamically acquired and updated by the storage device during normal operation through background scanning or failure recovery operations during host read / write processes, and only coarse-grained segmented values ​​of the offset voltage are stored.

[0128] Maintain a set of read voltage parameter tables optimized for emergency scenarios. During verification, these pre-stored thresholds are directly applied for reading, instead of performing a full voltage scan that consumes significant power. If data cannot be read correctly using the regular thresholds, a more robust ECC error correction engine is immediately activated for rereading, completing the verification with the fewest possible attempts.

[0129] An intelligent emergency data scheduling and tiered recovery system. This application proposes a multi-factor weighted scoring model that intelligently schedules the emergency write queue order based on three dimensions: data consistency criticality, media unit health, and host command priority, ensuring that the most critical and secure data is saved first. Simultaneously, a complete tiered recovery process is established, encompassing power-on scanning, k-of-n rule reconstruction, MCS replay, and asynchronous migration, achieving seamless integration from data recoverability to rapid system availability and storage media optimization.

[0130] After the storage device is powered on again, a hardware reset and power stability check are first performed. Then, the data block urgently written is located in the SLC sacrificial region, and the complete mapping update log and user data of the data block are reconstructed using redundancy coding rules. Mapping recovery is then performed, replaying the reconstructed MCS, and quickly rebuilding a globally consistent L2P mapping table, bringing the storage system to an immediately usable state. Next is background migration. While the system is normally serving host requests, the recovered data is asynchronously migrated from the SLC sacrificial region back to its target storage medium (such as TLC / QLC), and finally, the sacrificial region space is cleaned up. This process is asynchronous and does not affect the performance of front-end host access. The sacrificial region is divided into multiple physical blocks, using a cyclical usage strategy. When data in a block is successfully migrated back, the block is marked for erasure, and an erasure operation is performed when the storage device is idle. If the number of available blocks in the sacrificial region falls below a threshold, active migration and erasure are triggered.

[0131] The memory controller 1043, as the main actuator, is responsible for voltage / slope sampling, capacitance model calculation, and operating time window T. ∗ Dynamic estimation; maintaining the MCS (Multi-Segment Classification) for addition, deletion, modification, and querying, implementing interval compression and rolling updates to ensure it meets the operation time window T. ∗ Constraints; responsible for queue construction, scoring sorting, and write trigger control; responsible for SLC sacrifice area allocation, striping organization, cross-die / plane sequential writing, and parity generation; integrating read voltage threshold table and hierarchical reread strategy to achieve fast, low-power post-write verification; performing striping scan, k-of-n rule reconstruction, L2P mapping recovery, and asynchronous data migration after power-on; the core adaptive brain. Based on flash memory health, temperature, historical performance data, etc., it dynamically adjusts parameters such as safety factor, scoring weight, redundancy strategy threshold, and read voltage table.

[0132] In some embodiments, a state machine and timing control can also be configured. S0 is the normal state, indicating that the storage device is operating normally, and the background maintains the MCS and learns parameters (such as reading the voltmeter). S1 is the warning state, indicating that a voltage drop triggers a warning. Immediately estimate the operating time window. The system freezes all non-emergency background operations, preparing for emergency processing. S2 is the emergency write state, where adaptive redundant striping writes are performed according to the score, along with low-energy verification. S3 is the active standby state, indicating that after the emergency write is completed, operations are actively stopped and the system waits for the voltage to drop to the reset threshold before hardware reset. S4 is the power-on recovery state, indicating that sacrificial region scanning, data reconstruction, and L2P mapping recovery are performed to bring the system to a consistency safety point. S5 is the migration state, indicating that the system is providing normal service, with data migration and sacrificial region cleanup performed asynchronously in the background.

[0133] This application embodiment systematically solves the core problem of how to reliably preserve critical states and achieve rapid recovery in the event of a power outage with highly uncertain energy levels through a full-chain collaborative design that includes energy budget sensing, data minimization organization, high fault tolerance in the write channel, low energy consumption in the verification process, and intelligent recovery process.

[0134] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory control method, characterized in that, Applied to a storage device including a memory controller and a memory module, the method includes: In response to the detection of a power failure warning signal, the energy storage parameters of the memory controller are acquired, and an operating time window is determined based on the energy storage parameters, which include the effective energy storage capacitor, the minimum operating voltage, and the current voltage. Freeze background activities of the storage device, extract the pre-maintained minimum consistency set and user data marked as high priority, and form an emergency write queue; The minimum consistency set stores the mapping update log from logic to physical address in a continuous interval recording manner, and the total volume and estimated flush time of the minimum consistency set are dynamically constrained to not exceed a preset emergency time threshold during normal operation. The emergency time threshold is determined based on the minimum energy of the energy storage capacitor. The items in the emergency write queue are sorted based on a multi-factor weighted scoring model, the sorted items are organized into stripe groups, and then divided into multiple data stripes. A redundancy strategy is dynamically selected based on the operation time window. Based on the redundancy strategy, the data stripes are written to the sacrificial region in a sequence spanning multiple planes and blocks; wherein, after each stripe is written, a progress marker is updated immediately, and the progress marker is stored in a fixed position within the sacrificial region for identifying partially written stripe groups during power-on recovery; After the writing is complete, the pre-learned and optimized voltage parameter table is called to verify the data.

2. The method according to claim 1, characterized in that, The step of obtaining the energy storage parameters of the memory controller and determining the operation time window based on the energy storage parameters includes: Calculate the remaining energy based on the energy storage parameters; The average power consumption of historical emergency writes is obtained, and the average power consumption is initialized to a preset conservative value, and then dynamically updated based on the actual power consumption after each emergency write is completed. Based on the remaining energy and the dynamically updated average power consumption, calculate the minimum available time; The operation time window is determined based on the minimum available time and the safety factor.

3. The method according to claim 1, characterized in that, The basic storage unit of the minimum consistency set includes a series of entries, each of which records the latest mapping relationship of a continuous logical address. The key information of the latest mapping relationship includes at least the starting logical address, the continuous length, the corresponding physical address hint, and the timestamp. Multiple entries are packaged into buckets of fixed size as management units. Each bucket has a management header. The information in the management header includes bucket ID, number of entries, logical address range, pointers to the previous and next buckets, estimated operation time window value when the bucket was generated, and checksum. The write / fetch time for each bucket is much shorter than the operation time window.

4. The method according to claim 1, characterized in that, The multi-factor weighted scoring model consists of the following indicators: Consistency criticality is used to represent the degree of impact of a project on the consistency of the global mapping table; Media risk level is used to comprehensively assess the health of the target physical block; Host command priority, used to directly transmit the priority of host commands.

5. The method according to claim 1, characterized in that, The redundancy strategy includes XOR encoding and RS erasure coding. The dynamic selection of the redundancy strategy based on the operation time window includes: In response to the operation time window being less than the first threshold, the XOR (4+1) scheme is adopted; In response to the operation time window being greater than or equal to the second threshold, the RS (6+3) scheme is adopted; In response to the operation time window being greater than or equal to the first threshold and less than the second threshold, the XOR (2+1) scheme is adopted.

6. The method according to claim 1, characterized in that, The step of writing the data stripes into the sacrificial region in a sequence spanning multiple planes and blocks includes: The metadata describing the stripe group is written in duplicate to the start and end positions of the stripe group, which consists of multiple data stripes written at once.

7. The method according to claim 1, characterized in that, After the writing is completed, the pre-learned and optimized voltage parameter table is called for data verification, including: During verification, data is read based on the voltage parameter reading table; If the data cannot be read correctly from the voltage parameter table, immediately initiate the rereading operation process; The voltage parameter table is dynamically collected and updated by the storage device during normal operation through background scanning or failure recovery operations during host read / write processes, and only coarse-grained segmented values ​​of the offset voltage are saved.

8. The method according to claim 1, characterized in that, The method further includes: After the storage device is powered on again, a hardware reset and power stability test are performed first, and then the data block to be urgently written is located in the sacrificial area. The complete mapping update log and user data of the data block are reconstructed using redundant coding rules; Replay the reconstructed minimum consistency set and rebuild the globally consistent logical-to-physical address mapping table; While the host is making normal service requests, the recovered user data is asynchronously migrated from the sacrificed area back to the target storage medium, and the space in the sacrificed area is cleaned up. The sacrifice area is divided into multiple physical blocks and uses a cyclical strategy. When the data in a block is successfully migrated back, the block is marked as to be erased and an erasure operation is performed when the storage device is idle. If the number of available blocks in the sacrifice area is lower than a threshold, active migration and erasure are triggered.

9. The method according to claim 1, characterized in that, The method further includes: The system includes a state machine and timing control, wherein the state machine includes a normal state, an early warning state, an emergency write state, an active standby state, a power-on recovery state, and a transition state. The normal state is used to indicate that the storage device is operating normally, and the background maintains a minimum consistency set and learning parameters; The warning state is used to indicate that a voltage drop triggers a warning. Under the warning state, the operation time window is immediately estimated, all non-emergency background operations are frozen, and preparations are made to enter emergency handling. In the emergency write state, adaptive redundant striping write is performed according to the score sorting, and low-energy verification is performed; The active standby state is used to indicate that after an emergency write is completed, the operation is actively stopped and the voltage is allowed to drop to the reset threshold before hardware reset. The power-on recovery state is used to indicate the execution of sacrificial region scanning, data reconstruction, and mapping recovery. The migration state is used to indicate normal system service, with data migration and sacrificial area cleanup performed asynchronously in the background.

10. The method according to claim 3, characterized in that, The method further includes: When the storage device is running, new mapping updates are appended to the currently active bucket; In response to the current active bucket being full or reaching a time threshold, assess whether the total time for writing all unwritten buckets to the memory module is greater than the emergency time threshold. If the time exceeds the emergency time threshold, a compression operation is triggered to merge all old entries in the unflushed buckets, so that the total flush time of the compressed minimum consistency set meets the constraint of the emergency time threshold.

11. The method according to claim 4, characterized in that, The media risk level is obtained by normalizing and weighting the number of erase / write cycles, the original bit error rate, and the measured and cached programming time during historical writes to the physical block.

12. A storage device, characterized in that, include: A connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple physical pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 11.

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