A method and device for ensuring that data of an idle QLC solid state disk is not lost
By using an independent power module and an automated refresh mechanism in the processor system, the problem of data retention degradation in QLC solid-state drives under normal temperature offline idle conditions is solved, achieving reliable data maintenance and low-power refresh, and avoiding data loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- DONGGUAN RAMAXEL MEMORY TECH LTD
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-21
Smart Images
Figure CN122431609A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to a method and apparatus for ensuring that data on an idle QLC solid-state drive is not lost. Background Technology
[0002] With the development of storage technology, solid-state drives (SSDs) have evolved from single-cell (SLC) to multi-cell (MLC), three-cell (TLC), and finally to the current four-cell (QLC). Each generation of technology integrates more bits within a single storage cell, thereby significantly increasing storage density and reducing unit cost.
[0003] However, this high-density storage also brings new physical challenges. QLC solid-state drives (SSDs) differentiate the charge states within storage cells more precisely, making charge leakage more pronounced. When the drive is idle at room temperature and without power, the lack of an external electric field causes the charge in the storage cells to gradually dissipate over time, leading to a shift in the voltage threshold of the stored data. This can eventually exceed the error correction capabilities of the error correction code, resulting in permanent data loss. Compared to previous mainstream SSDs, QLC SSDs exhibit significantly reduced data retention in offline idle states, a problem particularly prominent in high-density storage applications.
[0004] Existing technologies do not yet provide an effective maintenance mechanism for QLC solid-state drives in long-term offline idle scenarios. Summary of the Invention
[0005] This invention provides a method and apparatus for ensuring that data is not lost when an idle QLC solid-state drive is in use. The technical problem it aims to solve is: how to provide a reliable and automated data maintenance solution to address the problem of data retention degradation of QLC solid-state drives in a normal temperature, off-power, and idle state.
[0006] In a first aspect, embodiments of the present invention provide a method for ensuring that data on idle QLC solid-state drives is not lost, wherein the data refresh device includes: a power module for providing independent power-on and power-off control for multiple slots; a processor system including a central processing unit, a memory module, a storage module, and a timing module; and an interface module connecting the central processing unit and the multiple slots for data transmission; the method includes: The central processing unit detects whether a QLC solid-state drive is connected to each slot via the interface module. For each QLC solid-state drive in place, the identification information of the QLC solid-state drive is read, and the read identification information and the current time obtained from the timing module are associated and stored in the storage module as the most recent refresh time. The power module is controlled to power off all slots and the processor system is put into a low-power mode. In the low-power mode, only the timing function of the timing module, the slot's presence status detection function, and the interrupt response function are retained. The timing module wakes up the processor system periodically, causing the processor system to exit the low-power mode and enter the normal mode. In the normal mode, the most recent refresh time corresponding to each QLC solid-state drive is read from the storage module, and the current time is obtained from the timing module to calculate the time difference between the current time and the most recent refresh time; Determine whether the time difference exceeds a preset refresh time threshold. If it does, perform a refresh operation on the corresponding QLC solid-state drive: control the power module to power on the slot where the corresponding QLC solid-state drive is located, read all the data stored in the corresponding QLC solid-state drive through the interface module via the central processing unit and temporarily store it in the memory module, and then write all the data temporarily stored in the memory module back to the corresponding QLC solid-state drive unchanged through the interface module via the central processing unit. After the refresh operation is completed, control the power module to power off the slot where the corresponding QLC solid-state drive is located, and update the most recent refresh time of the corresponding QLC solid-state drive stored in the storage module to the current time obtained from the timing module. After all the QLC solid-state drives that need to be refreshed have completed the refresh operation, proceed to the step of putting the processor system into low-power mode.
[0007] Optionally, the step of detecting whether a QLC solid-state drive is connected to each slot via the interface module through the central processing unit, and for each QLC solid-state drive in place, reading the identification information of the QLC solid-state drive, and storing the read identification information and the current time obtained from the timing module as the most recent refresh time in the storage module includes: During system power-on initialization, the central processing unit detects whether a QLC solid-state drive is connected to each slot. For slots where a QLC solid-state drive (SSD) is detected to be connected, the manufacturer information, model information, and serial number information of the QLC SSD are read through the interface module as the identification information, and the identification information and the current time obtained from the timing module are used as the most recent refresh time, and stored in the storage module with the slot number as the index. For slots where no QLC solid-state drive connection is detected, the storage content of the corresponding slot number in the storage module is cleared to zero.
[0008] Optionally, the refresh time threshold can be between one month and three months.
[0009] Optionally, the method further includes: When the interface module detects a change in the presence status of any slot, it generates an interrupt signal to wake up the processor system and enter the normal mode. Determine whether the interrupt signal is triggered by an insertion event or an removal event of the QLC solid-state drive; If the interrupt signal is triggered by the removal event of the QLC solid-state drive, then the identification information of the corresponding slot number and the most recent refresh time in the storage module will be cleared to zero. If the interrupt signal is triggered by the insertion event of a QLC solid-state drive, the identification information of the newly inserted QLC solid-state drive is read through the interface module, and the identification information and the current time obtained from the timing module are stored as the most recent refresh time in the corresponding slot number position in the storage module. Then, a refresh operation is performed on the newly inserted QLC solid-state drive, and after the refresh is completed, the most recent refresh time in the storage module is updated to the current time obtained from the timing module; the processor system is then controlled to re-enter the low-power mode.
[0010] Optionally, performing a refresh operation on the newly inserted QLC solid-state drive includes: The system controls the power module to power on the slot where the newly inserted QLC solid-state drive is located. The central processing unit reads all the data stored in the newly inserted QLC solid-state drive through the interface module and temporarily stores it in the memory module. The central processing unit then writes all the data temporarily stored in the memory module back to the newly inserted QLC solid-state drive intact through the interface module. Finally, the system controls the power module to power off the slot where the newly inserted QLC solid-state drive is located.
[0011] Optionally, the wake-up cycle of the processor system is less than the preset refresh time threshold, which is achieved by the timing module periodically waking it up.
[0012] Optionally, all data includes data corresponding to all user logical addresses in the QLC solid-state drive.
[0013] Optionally, the power module can provide independent power supply control for each slot, and the power-on or power-off operation of any slot will not affect the power supply status of other slots.
[0014] In a second aspect, embodiments of the present invention provide a data refresh device for performing the method described in the first aspect for ensuring that data on idle QLC solid-state drives is not lost, including: The power module is used to provide independent power-on and power-off control for multiple slots; The processor system includes a central processing unit, a memory module, a storage module, and a timing module, wherein the central processing unit is connected to the memory module, the storage module, and the timing module respectively; An interface module connects the central processing unit to the multiple slots for data transmission.
[0015] Optionally, the interface module includes multiple PCIe interfaces, each of which is connected to the central processing unit and corresponds one-to-one with multiple slots. The power supply module is connected to the central processing unit, memory module, storage module, and timing module, respectively. This invention provides a method and apparatus for ensuring data retention in idle QLC solid-state drives (SSDs). By using independent power supply modules to power each slot, a timed wake-up mechanism for the processor system, and a time difference comparison mechanism, this invention achieves automated refresh and maintenance of QLC SSDs in idle states. Specifically, in low-power mode, this method retains only timing and presence detection functions. The timing module periodically wakes the system and performs full read / write operations only on drives idle for more than a preset threshold. After refresh, the system returns to a low-power state. Therefore, without manual intervention, it proactively compensates for the degradation in data retention caused by charge leakage in QLC SSDs under off-power conditions at room temperature, effectively reducing the risk of data read errors. Simultaneously, selective refresh and low-power design significantly reduce energy consumption and device wear, providing a reliable and automated data maintenance solution. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of a data refresh device provided in an embodiment of the present invention.
[0018] Figure 2 This is a flowchart illustrating a method for ensuring that data on idle QLC solid-state drives is not lost, as provided in an embodiment of the present invention. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0021] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0022] It should also be further understood that the term “and / or” as used in this specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0023] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."
[0024] Please see Figure 1 This invention provides a data refresh device for executing a method proposed in this invention to ensure that data on idle QLC solid-state drives is not lost, comprising: Power module 10 is used to provide independent power-on and power-off control for multiple slots; The processor system 20 includes a central processing unit 21, a memory module 22, a storage module 23, and a timing module 24, wherein the central processing unit 21 is connected to the memory module 22, the storage module 23, and the timing module 24 respectively. An interface module connects the central processing unit 21 to the multiple slots for data transmission.
[0025] In practice, the power module 10 provides independent power-on and power-off control for multiple slots. The power module 10 obtains input power from an external AC or DC power source and generates multiple DC power supplies of different voltage levels through an internal voltage conversion circuit. The power module 10 also includes multiple controllable power switches, each corresponding to one slot. The central processing unit 21 can independently control the on / off state of each power switch via control signals, thereby achieving independent power supply management for each slot.
[0026] Furthermore, the processor system 20 includes a central processing unit (CPU) 21, a memory module 22, a storage module 23, and a timing module 24. The CPU 21 is connected to the memory module 22, storage module 23, and timing module 24. Specifically, the CPU 21 is connected to the memory module 22 via a memory bus, used to read instructions and data from and write data to the memory module 22. The CPU 21 is connected to the storage module 23 via a storage bus. The storage module 23 is a non-volatile memory, such as NOR flash or NAND flash, used to store firmware programs, slot recording information, and configuration parameters. The CPU 21 is connected to the timing module 24 via a peripheral bus. The timing module 24 is a real-time clock circuit with a built-in crystal oscillator and counter, capable of continuing operation powered by a backup battery in power-off or standby states, maintaining continuous time accumulation.
[0027] Furthermore, the interface module connects the central processing unit 21 to multiple slots for data transmission. The interface module contains multiple data links, each with one end connected to the PCIe controller of the central processing unit 21 and the other end connected to a slot. The interface module conforms to the PCIe protocol specification and supports high-speed serial data transmission. The central processing unit 21 uses the interface module to send commands, receive status updates, and read / write data to the QLC solid-state drives in the slots.
[0028] In some preferred embodiments, the interface module includes multiple PCIe interfaces, each connected to the central processing unit 21 and corresponding to a specific slot; the power supply module 10 is connected to the central processing unit 21, the memory module 22, the storage module 23, and the timing module 24, respectively. In practice, multiple PCIe interfaces are connected to the central processing unit 21, and each corresponds to a different slot. The number of PCIe interfaces is equal to the number of slots; for example, eight PCIe interfaces correspond to eight slots.
[0029] Furthermore, the power supply module 10 is connected to the central processing unit 21, memory module 22, storage module 23, and timing module 24, respectively. The power supply module 10 generates multiple independent supply voltages, including the core voltage of the central processing unit 21, the input / output interface voltage of the central processing unit 21, the operating voltage of the memory module 22, the operating voltage of the storage module 23, the operating voltage of the timing module 24, and multiple slot-independently controlled interfaces and slot power supplies. Furthermore, the central processing unit 21 communicates with the power supply module 10 via a power management bus, sending voltage regulation commands and power switch control commands. Furthermore, the power supply module 10 internally contains multiple low-dropout linear regulators or DC-DC converters to generate the aforementioned voltages. Furthermore, each power supply line providing power to a slot is equipped with an independent load switch, and the central processing unit 21 controls the on / off state of each load switch via general-purpose input / output pins or dedicated power control pins.
[0030] Please see Figure 2 This invention provides a method for ensuring that data on idle QLC solid-state drives is not lost, the method comprising the following steps: S1, the central processing unit detects whether a QLC solid-state drive is connected to each slot via the interface module. For each QLC solid-state drive in place, the identification information of the QLC solid-state drive is read, and the read identification information and the current time obtained from the timing module are associated and stored in the storage module as the most recent refresh time.
[0031] In practice, the central processing unit (CPU) first detects whether a QLC solid-state drive (SSD) is connected to each slot via an interface module. Specifically, the CPU sends a device detection command to each slot through the interface module, and determines the presence of a QLC SSD based on whether a valid device response is received. For each QLC SSD detected as present, the CPU reads its identification information via the interface module. This identification information can include the drive's manufacturer name, model name, serial number, or other information that uniquely identifies the drive.
[0032] Furthermore, the central processing unit (CPU) obtains the current time value from the timing module as the current time. The CPU uses the read identification information and the obtained current time as the most recent refresh time, and stores the two in the storage module. The storage module is a non-volatile memory, such as a flash memory chip, so that the information is not lost after power failure.
[0033] In some preferred embodiments, step S1 specifically includes: during system power-on initialization, the central processing unit detects whether a QLC solid-state drive is connected to each slot; for slots where a QLC solid-state drive is detected, the interface module reads the manufacturer information, model information, and serial number information of the QLC solid-state drive as the identification information, and uses the identification information and the current time obtained from the timing module as the most recent refresh time, storing them in the storage module with the slot number as the index; for slots where no QLC solid-state drive is detected, the storage content of the corresponding slot number in the storage module is cleared.
[0034] In practice, system power-on initialization refers to the process by which the processor system performs self-tests, hardware initialization, and establishes the basic environment after the data refresh device is powered on. During this initialization process, the central processing unit executes a slot scanning program to detect whether a QLC solid-state drive is connected to each slot.
[0035] Specifically, the central processing unit (CPU) sends device identification commands sequentially to each slot via the interface module. The interface module communicates with the devices in the slots according to the PCIe protocol specification. If a QLC SSD is present in a slot, it will respond to the identification command, returning device type and status information. The CPU determines whether a QLC SSD is present in the slot based on whether a valid response is received. If no response is received or the response is invalid, the slot is determined to be empty.
[0036] Furthermore, for slots where a QLC solid-state drive (SSD) is detected as connected, the CPU reads the manufacturer information, model information, and serial number information of the QLC SSD through the interface module. The manufacturer information can be obtained by reading the drive's manufacturer identification register, the model information can be obtained by reading the drive's product name string, and the serial number information can be obtained by reading the drive's unique serial number string. The CPU uses these three pieces of information together as the identification information for the QLC SSD.
[0037] Furthermore, the CPU obtains the current timing value from the timing module as the current time and uses this current time as the most recent refresh time of the QLC SSD. The CPU uses the slot number as an index to associate this identification information with the most recent refresh time and stores it in the storage module. The slot number is a fixed number for each slot, such as J1, J2, up to Jn, which serves as the lookup key in the storage module.
[0038] Furthermore, for slots where no QLC SSD connection is detected, the CPU clears the storage content of the corresponding slot number in the storage module. The clearing operation involves writing all binary 1s or all 0s to the identification information field associated with the corresponding slot number and the most recent refresh time field, indicating that the slot is currently empty. This clearing operation ensures that the records in the storage module remain synchronized with the actual physical slot occupancy status, preventing outdated and invalid information from being read during subsequent queries.
[0039] S2, control the power module to power off all slots and put the processor system into a low-power mode. In the low-power mode, only the timing function of the timing module, the slot's on-state detection function, and the interrupt response function are retained.
[0040] In practice, the central processing unit (CPU) controls the power supply module to power off all slots. The CPU also controls the processor system to enter a low-power mode. In low-power mode, the processor system retains only the timing function of the timing module, the slot presence detection function, and the interrupt response function; other functional modules are shut down or enter a sleep state to reduce power consumption.
[0041] Furthermore, the timing module continues to run, maintaining the accumulation of time. The slot presence detection function continuously monitors each slot for the insertion or removal of a QLC solid-state drive via the interface module. The interrupt response function enables the processor system to respond to external interrupt signals.
[0042] S3, the processor system is woken up periodically by the timing module, so that the processor system exits the low power mode and enters the normal mode.
[0043] In practice, the timing module generates a wake-up signal when the timer value reaches the wake-up time according to a preset timing period. Furthermore, in response to this wake-up signal, the processor system exits low-power mode and enters normal mode. In normal mode, all functional modules of the processor system operate normally.
[0044] S4. In the normal mode, the most recent refresh time corresponding to each QLC solid-state drive is read from the storage module, and the current time is obtained from the timing module. The time difference between the current time and the most recent refresh time is calculated.
[0045] In practice, after entering normal mode, the CPU reads the most recent refresh time for each QLC SSD from the storage module. Furthermore, the CPU obtains the current time value from the timing module as the current time. The CPU calculates the time difference between the current time and the most recent refresh time. This time difference represents the length of time elapsed from the completion of the last refresh operation to the current moment.
[0046] S5, determine whether the time difference exceeds a preset refresh time threshold. If it does, perform a refresh operation on the corresponding QLC solid-state drive: control the power module to power on the slot where the corresponding QLC solid-state drive is located, read all the data stored in the corresponding QLC solid-state drive through the interface module via the central processing unit and temporarily store it in the memory module, and then write all the data temporarily stored in the memory module back to the corresponding QLC solid-state drive unchanged through the interface module via the central processing unit. After the refresh operation is completed, control the power module to power off the slot where the corresponding QLC solid-state drive is located, and update the most recent refresh time of the corresponding QLC solid-state drive stored in the storage module to the current time obtained from the timing module.
[0047] In practice, the central processing unit (CPU) determines whether the time difference exceeds a preset refresh time threshold. The refresh time threshold is a pre-configured time length value used to determine when a data refresh operation needs to be performed on the QLC SSD. If the time difference does not exceed the refresh time threshold, no operation is performed on the QLC SSD. Conversely, if the time difference exceeds the refresh time threshold, the CPU performs a refresh operation on the QLC SSD.
[0048] Further, the specific process of the refresh operation is as follows: The CPU controls the power module to power on the slot where the QLC SSD is located. After power-on, the QLC SSD enters the operable state. The CPU reads all the data stored in the QLC SSD via the interface module. All data includes data within the logical address range accessible to all users of the drive. The read data is temporarily stored in the memory module. The memory module can be a dynamic random access memory, providing sufficient capacity to hold all the data of a QLC SSD. Further, the CPU writes all the data temporarily stored in the memory module back to the same logical address location of the same QLC SSD via the interface module. This write operation is equivalent to reprogramming the storage cells, resetting the charge state of each storage cell. Further, after the refresh operation is completed, the CPU controls the power module to power off the slot where the QLC SSD is located. Further, the CPU updates the most recent refresh time of the QLC SSD stored in the storage module to the current time obtained from the timing module to record the completion time of this refresh operation.
[0049] In some preferred embodiments, the refresh time threshold ranges from one month to three months.
[0050] In practice, the refresh time threshold is limited to a range of one to three months. The refresh time threshold is a configurable time parameter used to determine the benchmark used by the central processing unit (CPU) to decide whether a refresh operation needs to be performed. This refresh time threshold represents the maximum allowed time interval between the completion of the most recent refresh operation and the current moment.
[0051] In practice, the refresh time threshold can be preset by the equipment manufacturer during production or adjusted by the user through a configuration interface. The unit of the refresh time threshold can be days or months. A dedicated configurable parameter storage area can be set up in the processor system's storage module to store the value of this refresh time threshold. Furthermore, when the central processing unit executes the time difference judgment logic, it reads the threshold value from this storage area and compares the calculated time difference with the threshold.
[0052] Furthermore, the value range is limited to one to three months, meaning that the minimum value of this threshold is no less than one month and the maximum value is no more than three months. For example, the threshold can be set to one month, that is, a refresh operation is performed on the hard drive every month; it can also be set to two months or three months.
[0053] Furthermore, the choice of this value range is based on the physical characteristics of QLC solid-state drives, where charge leakage leads to data degradation. Idle time exceeding three months may increase the risk of data irrecoverability, while refresh cycles shorter than one month may cause unnecessary power consumption and write wear.
[0054] In some preferred embodiments, the wake-up cycle of the processor system is less than the preset refresh time threshold when the timing module wakes it up periodically.
[0055] In practice, the wake-up period of the processor system, which is periodically woken up by the timing module, is set to be less than a preset refresh time threshold. The wake-up period refers to the time interval between the timer module generating a wake-up signal. The timing module internally maintains a counter or timer, and when the count value reaches the count value corresponding to the preset wake-up period, the timing module outputs a wake-up interrupt signal.
[0056] Furthermore, the preset refresh time threshold is a time length value, such as one month. The wake-up period is the time interval between two consecutive wake-ups of the timing module, such as one day or one week. A wake-up period shorter than the refresh time threshold means that within the time length covered by the refresh time threshold, the timing module will wake up the processor system multiple times.
[0057] For example, if the refresh time threshold is set to two months and the wake-up cycle is set to one day, then the timing module will wake up the processor system approximately sixty times within a two-month time span. After each wake-up, the processor system performs steps such as reading the most recent refresh time from the storage module, calculating the time difference, determining whether the threshold has been exceeded, and performing a refresh operation. If the most recent refresh time of a certain hard drive is more than two months away from the current time, a refresh operation will be performed during that wake-up period.
[0058] Furthermore, the specific wake-up cycle value can be configured by the device manufacturer based on the balance requirements of power consumption and response speed. A shorter wake-up cycle allows for more frequent calculation of the time difference, enabling more timely detection of hard drives that have reached the refresh threshold, but it increases the device's power consumption. Conversely, a longer wake-up cycle can reduce power consumption, but may result in the hard drive being refreshed only after exceeding the refresh threshold for an extended period.
[0059] In some preferred embodiments, the total data includes data corresponding to all user logical addresses in the QLC solid-state drive.
[0060] In practice, all data read during the refresh operation is limited to data corresponding to all user logical addresses in the QLC SSD. A user logical address refers to the range of logical block addresses that are visible and accessible to the operating system or file system. The storage space of a QLC SSD is organized in units of logical block addresses, typically starting from logical block address 0 and ending at the maximum logical block address corresponding to the disk's nominal capacity.
[0061] Furthermore, during a full disk read operation, the central processing unit (CPU) sends a read command to the QLC solid-state drive (SSD) via the interface module. The starting logical block address of the read command is 0, and the number of blocks read is the total number of logical blocks on the hard drive. After responding to the read command, the hard drive sequentially returns the data stored in each logical block within the range of logical block address 0 to the maximum logical block address. This data includes all information stored on the storage medium, such as file system metadata, user file contents, partition table information, and boot records.
[0062] Furthermore, in the full write-back operation, the central processing unit (CPU) writes all the data temporarily stored in the memory module back to the corresponding logical block addresses of the hard disk in the same logical block address order as when it was read. The write-back operation covers the entire user-addressable storage space of the hard disk, without omitting any logical block address.
[0063] Furthermore, this embodiment emphasizes that the refresh operation covers the entire user data area, rather than just a portion of the area or only the valid data area of the file system. Any data stored in the user logical address space of the QLC solid-state drive, regardless of whether it is a valid file, is included in the refresh operation.
[0064] In some preferred embodiments, the power module can provide independent power supply control for each slot, and the power-on or power-off operation of any slot does not affect the power supply status of other slots.
[0065] In practice, the power module is designed to provide independent power control for each slot, ensuring that powering on or off any slot does not affect the power supply to other slots. The power module contains multiple independent power switches or power management units, with each power switch corresponding to one slot. The input of each power switch is connected to the power module's main power bus, and its output is connected to the power pin of the corresponding slot.
[0066] Furthermore, the central processing unit (CPU) is connected to the control terminal of each power switch via control signal lines. The CPU can send independent on or off commands to any power switch. When the CPU needs to power on a QLC SSD in a specific slot, it only sends an on command to the power switch corresponding to that slot, turning on the power switch and supplying power to that slot. The power switches for other slots remain unchanged and are unaffected by the power-on operation. Similarly, when the CPU needs to power off a slot, it only sends an off command to the power switch corresponding to that slot, cutting off the power supply to that slot. The power supply to other slots remains unaffected.
[0067] Furthermore, this independent control capability allows the device to simultaneously power on some slots out of multiple slots to perform refresh operations, while keeping other slots powered off. Even during a refresh operation, the central processing unit can respond to interrupt events in other slots and independently control the power-on or power-off of the corresponding slots without interrupting the ongoing refresh operation.
[0068] S6, after all the QLC solid-state drives that need to be refreshed have completed the refresh operation, proceed to the step of putting the processor system into low-power mode.
[0069] In practice, the central processing unit (CPU) performs the aforementioned time difference determination and refresh operations on each of the QLC solid-state drives (SSDs) recorded in the storage module. After all QLC SSDs requiring refresh have completed the refresh operation, the process transitions to putting the processor system into a low-power mode, thus forming a cyclically executed data refresh and maintenance process. This cycle is executed periodically to ensure that each QLC SSD receives a complete full-disk data rewrite whenever the time since the last refresh exceeds a preset threshold, thereby maintaining the reliability of data storage.
[0070] This invention, through the establishment of a data refresh device comprising a power module, a processor system, and an interface module, and the execution of the aforementioned periodic detection and refresh method, achieves automated maintenance of data on idle QLC solid-state drives (SSDs). The central processing unit (CPU) first records the identification information and initial refresh time of each in-situ drive, then controls the device to enter a low-power mode to reduce long-term energy consumption. A timing module periodically wakes up the processor system, enabling the device to proactively check the last refresh time of each drive at intervals shorter than the data retention degradation time interval. When the idle time of a drive exceeds a preset threshold, the device automatically performs a full-disk read-and-write refresh operation, resetting the charge state by reprogramming the storage units, effectively combating data degradation caused by charge leakage. Furthermore, this method ensures that data in offline QLC SSDs remains intact and readable even after long-term idleness without manual intervention, solving the problem of data loss due to charge leakage. Furthermore, through the combination of low-power mode and periodic wake-up, the device achieves low energy consumption while providing reliable maintenance.
[0071] In some preferred embodiments, the method further includes: when the interface module detects a change in the presence status of any slot, generating an interrupt signal to wake up the processor system and enter the normal mode; determining whether the interrupt signal is triggered by an insertion event or a removal event of the QLC solid-state drive; if the interrupt signal is triggered by a removal event of the QLC solid-state drive, then clearing all the identification information of the corresponding slot number and the most recent refresh time in the storage module; if the interrupt signal is triggered by an insertion event of the QLC solid-state drive, then reading the identification information of the newly inserted QLC solid-state drive through the interface module, storing the identification information and the current time obtained from the timing module as the most recent refresh time in the corresponding slot number position in the storage module, then performing a refresh operation on the newly inserted QLC solid-state drive, and updating the corresponding most recent refresh time in the storage module to the current time obtained from the timing module after the refresh is completed; and controlling the processor system to re-enter the low-power mode.
[0072] In practice, when the interface module detects a change in the presence status of any slot, it generates an interrupt signal. Changes in presence status include two scenarios: a QLC solid-state drive (SSD) is inserted into a previously empty slot, or a hard drive is removed from a slot that previously had one. The interface module identifies these changes through changes in the physical signal level of the slot or through the hot-plug detection mechanism of the protocol layer. This interrupt signal is sent to the processor system, waking it up and putting it into normal mode. Regardless of whether the processor system is currently in low-power mode or normal mode, the interrupt signal will enable it to enter normal mode to handle the event.
[0073] Furthermore, after the processor system is woken up, the central processing unit (CPU) reads the interrupt status register recorded in the interface module to determine whether the interrupt signal was triggered by an insertion event or a removal event of the QLC solid-state drive. Specifically, each slot in the interface module corresponds to a status flag bit, and the CPU determines the event type by reading the value of this flag bit.
[0074] Furthermore, if the determination result is a removal event, meaning that the QLC solid-state drive that was originally in a slot has been removed, the central processing unit will clear the identification information of the corresponding slot number and the most recent refresh time in the storage module. The clearing operation ensures that the record of the slot is cleared, avoiding the mistaken assumption that there is still a hard drive in the slot during subsequent periodic checks, thus preventing the execution of an invalid refresh operation.
[0075] Furthermore, if the determination result is an insertion event, meaning a QLC SSD has been inserted into an empty slot, the CPU reads the identification information of the newly inserted QLC SSD through the interface module. The reading process is the same as during initialization, including manufacturer information, model information, and serial number information. The CPU obtains the current time value from the timing module as the current time and uses this current time as the most recent refresh time. The CPU stores the read identification information and the most recent refresh time in the storage module at the corresponding slot number index. Subsequently, the CPU performs a refresh operation on the newly inserted QLC SSD. After the refresh operation is completed, the CPU updates the corresponding most recent refresh time in the storage module to the current time obtained from the timing module. Finally, the CPU controls the processor system to re-enter low-power mode, waiting for the next timed wake-up or interrupt event.
[0076] This embodiment achieves real-time response to QLC solid-state drive (SSD) hot-plug events through an interrupt mechanism. When a user inserts a new QLC SSD into the device at any time, the device automatically reads the drive's identification information and immediately performs a refresh operation, ensuring the newly inserted drive receives a complete charge reset from the moment of insertion, and its data retention period is calculated from the insertion time. Furthermore, when a user removes a drive, the device automatically clears the corresponding record in the storage module, preventing subsequent erroneous operations due to residual invalid information in the storage module. This interrupt handling mechanism allows the device to dynamically adapt to changes in slot status without manual configuration or restart by the user, ensuring that the records in the storage module are always precisely consistent with the actual physical connection state. Furthermore, the immediate refresh operation for newly inserted drives ensures that the data on the drive is also protected by the periodic maintenance mechanism during subsequent idle periods, avoiding the potential data loss risk that might arise from an unknown refresh time for newly inserted drives.
[0077] It's important to note that the reason for immediately refreshing a newly inserted hard drive, rather than waiting for a scheduled wake-up cycle, is that the device cannot know the length of time the hard drive was idle before insertion. The hard drive's last refresh time (i.e., the time when the charge state of its internal storage cells was last reset) is unknown and may have approached or exceeded the critical point for data retention. To avoid data loss during the waiting period (which could last several weeks) due to waiting for the next scheduled wake-up cycle, the device adopts a conservative strategy, performing a refresh immediately after insertion to ensure that the hard drive's data retention cycle is reset from the moment of insertion, thus allowing it to be seamlessly integrated into the device's subsequent periodic maintenance system.
[0078] In some preferred embodiments, performing a refresh operation on the newly inserted QLC solid-state drive includes: controlling the power module to power on the slot where the newly inserted QLC solid-state drive is located; reading all the data stored in the newly inserted QLC solid-state drive through the interface module via the central processing unit and temporarily storing it in the memory module; writing all the data temporarily stored in the memory module back to the newly inserted QLC solid-state drive unchanged through the interface module via the central processing unit; and then controlling the power module to power off the slot where the newly inserted QLC solid-state drive is located.
[0079] In practice, after the refresh operation begins, the central processing unit (CPU) first controls the power module to power on the slot where the newly inserted QLC solid-state drive (SSD) is located. The power module receives the slot selection signal and power-on command sent by the CPU, connects the power supply line of the slot, and enables the QLC SSD in the slot to obtain operating voltage and complete initialization.
[0080] Furthermore, after power-on, the CPU sends a read command to the QLC SSD via the interface module. The command carries an address range covering the entire disk's logical block address interval. In response to the read command, the QLC SSD transfers all user data from its storage medium page by page or block by block to the CPU via the interface module. The CPU receives this data and temporarily stores it in the memory module. The memory module provides sufficient storage capacity to hold all the user data from the QLC SSD. For large-capacity QLC SSDs, the memory module may require several gigabytes or even tens of gigabytes of cache space.
[0081] Furthermore, after all data has been read and completely stored in the memory module, the CPU writes all the data temporarily stored in the memory module back to the newly inserted QLC solid-state drive (SSD) intact via the interface module. Specifically, the CPU sends a write command to the QLC SSD, with the address range in the write command being exactly the same as the address range in the read command. The CPU then sends the data temporarily stored in the memory module to the hard drive page by page or block by block, according to the hard drive's write granularity. After receiving the data, the QLC SSD programs the data into its flash memory cells. This programming process re-establishes the charge of the floating-gate transistors in each memory cell, restoring the voltage thresholds representing different bit combinations in the memory cell to their initial programming state.
[0082] Furthermore, after the write operation is complete, the central processing unit controls the power module to power down the slot containing the newly inserted QLC solid-state drive. This power-down operation cuts off the power supply to the slot, and the drive enters a power-off state. At this point, the refresh operation is complete.
[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0084] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, this invention is also intended to include these modifications and variations as long as they fall within the scope of the claims and their equivalents.
[0085] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for ensuring that data on idle QLC solid-state drives is not lost, characterized in that, The data refresh device includes: a power module for providing independent power-on and power-off control for multiple slots; a processor system including a central processing unit, a memory module, a storage module, and a timing module; and an interface module connecting the central processing unit and the multiple slots for data transmission; the method includes: The central processing unit detects whether a QLC solid-state drive is connected to each slot via the interface module. For each QLC solid-state drive in place, the identification information of the QLC solid-state drive is read, and the read identification information and the current time obtained from the timing module are associated and stored in the storage module as the most recent refresh time. The power module is controlled to power off all slots and the processor system is put into a low-power mode. In the low-power mode, only the timing function of the timing module, the slot's presence status detection function, and the interrupt response function are retained. The timing module wakes up the processor system periodically, causing the processor system to exit the low-power mode and enter the normal mode. In the normal mode, the most recent refresh time corresponding to each QLC solid-state drive is read from the storage module, and the current time is obtained from the timing module to calculate the time difference between the current time and the most recent refresh time; Determine whether the time difference exceeds a preset refresh time threshold. If it does, perform a refresh operation on the corresponding QLC solid-state drive: control the power module to power on the slot where the corresponding QLC solid-state drive is located, read all the data stored in the corresponding QLC solid-state drive through the interface module via the central processing unit and temporarily store it in the memory module, and then write all the data temporarily stored in the memory module back to the corresponding QLC solid-state drive unchanged through the interface module via the central processing unit. After the refresh operation is completed, control the power module to power off the slot where the corresponding QLC solid-state drive is located, and update the most recent refresh time of the corresponding QLC solid-state drive stored in the storage module to the current time obtained from the timing module. After all the QLC solid-state drives that need to be refreshed have completed the refresh operation, proceed to the step of putting the processor system into low-power mode.
2. The method for ensuring no data loss when idle QLC solid-state drives are used, as described in claim 1, is characterized in that... The process involves the central processing unit detecting whether a QLC solid-state drive (SSD) is connected to each slot via the interface module. For each QLC SSD present, the identification information of the QLC SSD is read, and the read identification information, along with the current time obtained from the timing module, is stored in the storage module as the most recent refresh time. This includes: During system power-on initialization, the central processing unit detects whether a QLC solid-state drive is connected to each slot. For slots where a QLC solid-state drive (SSD) is detected to be connected, the manufacturer information, model information, and serial number information of the QLC SSD are read through the interface module as the identification information, and the identification information and the current time obtained from the timing module are used as the most recent refresh time, and stored in the storage module with the slot number as the index. For slots where no QLC solid-state drive connection is detected, the storage content of the corresponding slot number in the storage module is cleared to zero.
3. The method for ensuring no data loss when idle QLC solid-state drives are used, as described in claim 1, is characterized in that... The refresh time threshold ranges from one month to three months.
4. The method for ensuring no data loss when idle QLC solid-state drives are used, as described in claim 1, is characterized in that... The method further includes: When the interface module detects a change in the presence status of any slot, it generates an interrupt signal to wake up the processor system and enter the normal mode. Determine whether the interrupt signal is triggered by an insertion event or an removal event of the QLC solid-state drive; If the interrupt signal is triggered by the removal event of the QLC solid-state drive, then the identification information of the corresponding slot number and the most recent refresh time in the storage module will be cleared to zero. If the interrupt signal is triggered by the insertion event of a QLC solid-state drive, the identification information of the newly inserted QLC solid-state drive is read through the interface module, and the identification information and the current time obtained from the timing module are stored as the most recent refresh time in the corresponding slot number position in the storage module. Then, a refresh operation is performed on the newly inserted QLC solid-state drive, and after the refresh is completed, the most recent refresh time in the storage module is updated to the current time obtained from the timing module; the processor system is then controlled to re-enter the low-power mode.
5. The method for ensuring no data loss when idle QLC solid-state drives are used, as described in claim 4, is characterized in that... The step of performing a refresh operation on the newly inserted QLC solid-state drive includes: The system controls the power module to power on the slot where the newly inserted QLC solid-state drive is located. The central processing unit reads all the data stored in the newly inserted QLC solid-state drive through the interface module and temporarily stores it in the memory module. The central processing unit then writes all the data temporarily stored in the memory module back to the newly inserted QLC solid-state drive intact through the interface module. Finally, the system controls the power module to power off the slot where the newly inserted QLC solid-state drive is located.
6. The method for ensuring no data loss during idle QLC solid-state drives according to claim 1, characterized in that, The wake-up cycle of the processor system, which is timed by the timing module, is less than the preset refresh time threshold.
7. The method for ensuring no data loss when idle QLC solid-state drives are used, as described in claim 1, is characterized in that... The data includes all user logical addresses in the QLC solid-state drive.
8. The method for ensuring no data loss when idle QLC solid-state drives are used, as described in claim 1, is characterized in that... The power module can provide independent power supply control for each slot, and the power-on or power-off operation of any slot will not affect the power supply status of other slots.
9. A data refresh device, characterized in that, A method for performing the method for ensuring that idle QLC solid-state drives do not lose data as described in any one of claims 1-8, comprising: The power module is used to provide independent power-on and power-off control for multiple slots; The processor system includes a central processing unit, a memory module, a storage module, and a timing module, wherein the central processing unit is connected to the memory module, the storage module, and the timing module respectively; An interface module connects the central processing unit to the multiple slots for data transmission.
10. The data refresh device according to claim 9, characterized in that, The interface module includes multiple PCIe interfaces, each of which is connected to the central processing unit and corresponds to a different slot. The power module is connected to the central processing unit, memory module, storage module and timing module respectively.