RAID check source data parallel caching method based on multi-channel MM2S ring buffer queue

Abstract

The application relates to a RAID check source data parallel cache method based on a multi-channel MM2S ring cache queue, belonging to the field of data storage, and the method comprises the following steps: a RAID controller distributes multi-channel MM2S_BUF cache spaces according to received write data commands or recovery data requests, generates a read source data instruction and an operation request of a check engine; source data is written into specified cache addresses in MM2S ring cache queues of each channel through a memory mapping interface; after the check engine judges that the source data of each channel is ready, the source data in the MM2S ring cache queues of each channel is read out simultaneously and in parallel through a data flow interface to perform check value operation or inverse operation; the check data or the recovery data is written into a hard disk; and the corresponding multi-channel MM2S_BUF cache spaces are released. The method can ensure that each ring cache queue is distributed and used in the order from small to large according to the address, and realizes the ordered and efficient cyclic use of the cache spaces.

Description

Technical Field

[0001] This invention belongs to the field of data storage, and in particular relates to a parallel caching method for RAID verification source data based on a multi-channel MM2S ring cache queue. Background Technology

[0002] Redundant Arrays of Independent Disks (RAID) is a group of hard drives composed of multiple independent hard drives. It improves access performance through concurrent hard drive operations and enhances data security by utilizing redundant data. In RAID systems with redundant data, such as RAID5 and RAID6, the working principle of RAID includes: when writing user data, constructing parity data as redundant data according to certain rules to provide data security protection; when some data is lost, recovering the lost data from the remaining data through inverse operations to rebuild the RAID system.

[0003] When calculating parity data or recovering lost data, the RAID controller needs to obtain the source data for parity calculation or inverse calculation from the host and / or hard drives, and cache it in multiple cache channels. Once the data for all channels is ready, the parity engine in the RAID controller reads the source data from all channels and performs parity calculation or inverse calculation to obtain the parity data or recovery data.

[0004] like Figure 1 As shown, RAID controllers typically cache data using an external high-speed cache (such as DDR4). The RAID controller serially writes the source data obtained from the host and / or hard drive into the DDR for caching. Once the source data for all channels is ready, the parity engine in the RAID controller then sequentially reads the source data for each channel from the DDR and performs parity calculations or the reverse operation. While the above scheme can meet the functional requirements of data caching, it has the following shortcomings: First, the RAID controller writes and reads data from multiple channels serially, requiring twice the total data operation time (serial data write time and serial data read time). This results in significant data access latency, impacting the efficiency of parity calculations or inverse calculations.

[0005] Secondly, the RAID controller requires additional circuitry to continuously monitor and record the write and read operations of each cache space to ensure that the parity engine reads the correct source data from the DDR, making the control logic more complex.

[0006] With the development of technology, various upper-layer application systems have placed increasingly higher demands on the read and write performance of RAID systems. The traditional method of caching source data through external DDR can no longer meet the bandwidth requirements for calculating RAID parity or recovering lost data. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of the invention is to provide a parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue, which ensures that each ring buffer queue is allocated and used in ascending order of address, so as to realize the orderly and efficient cyclic use of the buffer space.

[0008] This invention proposes a parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue, comprising: S1, the RAID controller allocates multi-channel MM2S_BUF cache space according to the received write data command or recovery data request, and generates read source data command and verification engine operation request; The multi-channel MM2S_BUF cache space includes multiple MM2S circular cache queues of the same depth, used for parallel caching of the verification source data of multiple channels; the data writing interface of the MM2S circular cache queue of each channel adopts a memory-mapped interface; the data reading interface of the MM2S circular cache queue of each channel adopts a data stream interface. S2, according to the read source data instruction, write the source data to the specified cache address of the MM2S circular cache queue of each channel through the memory mapping interface; S3, the verification engine receives and parses the operation request. When it is determined that the source data of each channel in the operation request is ready, the source data in the MM2S ring buffer queue of each channel is read out in parallel through the data flow interface to perform verification value operation or inverse operation, and the completed verification data or recovery data is written into the corresponding buffer address. S4, the RAID controller sends a write data command to the verification hard drive to write the verification data to the verification hard drive; or sends a write data command to the newly added hard drive to write the recovery data to the newly added hard drive to rebuild the RAID system; S5, after the verification data or recovery data is written, release the corresponding multi-channel MM2S_BUF cache space.

[0009] Furthermore, the memory-mapped interface of each channel is interconnected with the hard disk data write bus and the host data write bus via bus interconnect, and the data stream interface of each channel is interconnected with the verification engine.

[0010] Furthermore, the MM2S ring buffer queue includes: a dual-port RAM, a memory-mapped slave interface, a data stream master interface, and a ring buffer queue monitoring circuit, wherein, The dual-port RAM includes a RAM write port and a RAM read port to independently complete write and read operations; The memory mapping slave interface is connected to the memory mapping interface, and the read and write operations of the memory mapping interface are converted into read and write operations of the RAM write port to execute the write operation of host or hard disk source data; The main data stream interface is connected to the data stream interface, and reads the stored source data from the RAM read port in ascending order of address, and outputs it through the data stream interface so that the verification engine can read the source data. The ring buffer queue monitoring circuit controls the read / write pointers, status flags, and buffer bitmap of the ring buffer queue to read out the out-of-order source data in ascending order of address.

[0011] Furthermore, the ring buffer queue monitoring circuit includes a memory-mapped write pointer MM_WR_PTR, a head pointer QH_PTR, and a tail pointer QT_PTR. Wherein, the memory-mapped write pointer MM_WR_PTR is the ring cache queue slot number pointed to by the memory-mapped interface write data address; The initial value of the queue head pointer QH_PTR is 0. When the main interface of the data stream finishes reading the specified amount of data, the queue head pointer QH_PTR is incremented by 1. The tail pointer QT_PTR is initially set to 0. When the memory mapping interface completes writing a specified amount of data to a cache slot outside the cache queue, the value of the tail pointer QT_PTR is updated to MM_WR_PTR+1.

[0012] Furthermore, the storage addresses of the dual-port RAM are connected end to end to construct a circular buffer area. The circular buffer area has N cache slots, and the cache slot numbers are from 0 to N-1. Each cache slot caches source data. The storage space from the head pointer QH_PTR to the tail pointer QT_PTR in the direction of increasing slot number constitutes the MM2S circular cache queue.

[0013] Furthermore, the ring buffer queue monitoring circuit includes a ring buffer queue empty flag and a ring buffer queue full flag. Specifically, when the tail pointer QT_PTR is equal to the head pointer QH_PTR, the ring buffer queue empty flag is set high; otherwise, the ring buffer queue empty flag is set low.

[0014] When the tail pointer QT_PTR+1 equals the head pointer QH_PTR, the full flag of the circular buffer queue is set high; otherwise, the full flag of the circular buffer queue is set low.

[0015] Furthermore, the ring-shaped cache queue monitoring circuit includes a cache bitmap, which has N bits. Each bit represents whether the data in the corresponding cache slot is valid. If the data in the cache slot is valid, the corresponding bit is set to 1; if the data in the cache slot is invalid, the corresponding bit is set to 0.

[0016] Furthermore, the main data stream interface of the circular buffer queue reads data from the buffer slots sequentially in ascending order of slot number, and the main data stream interface continuously judges the empty flag signal of the queue and the bit status of the buffer bit map pointed to by the queue head pointer QH_PTR. When the buffer queue is not empty and the bit in the buffer bitmap pointed to by the queue head pointer QH_PTR is 1, it indicates that the data is ready and data transfer is allowed.

[0017] Furthermore, when the RAID controller receives a write data command or a data recovery request, it generates a cache space allocation request of length n based on the length of the operation data and the RAID stripe size. If the cache space allocation table DBUF_Table determines that the current cache queue free slot count value DBUF_Free_Count > n, it allocates n consecutive cache slots starting from the cache slot x pointed to by the tail pointer DBUF_TPTR to the request.

[0018] Furthermore, after the RAID controller writes the verification data or recovery data processed by the verification engine to the hard disk, it immediately requests the release of the corresponding multi-channel MM2S ring cache space, and the cache space allocation table DBUF_Table clears the bit corresponding to the cache space to zero; the cache space of the multiple MM2S ring cache queues is released and reclaimed in ascending order of address.

[0019] The beneficial effects of this invention are as follows: 1. The data write interface of the MM2S ring cache queue of the present invention adopts a memory-mapped slave interface, which can adapt to the out-of-order writing of source data by the host or hard disk; 2. The data readout interface of the MM2S ring buffer queue of the present invention adopts the data flow main interface, which can greatly simplify the data readout control logic and meet the requirements of the verification engine for sequential reading of source data.

[0020] 3. The MM2S_BUF of this invention contains a monitoring circuit that can automatically monitor the writing and reading of data, ensuring that the source data written out of order is read out in ascending order of address, thus simplifying the complexity of the interface control of the verification engine.

[0021] 4. The RAM of this invention is used in the source data cache of the RAID parity engine. By adding interface conversion circuits and read / write monitoring circuits at both ends of the RAM, it automatically realizes the function of out-of-order data writing and sequential reading, and provides a simpler control interface. The MM2S ring buffer queue monitoring circuit monitors the data, mainly using three pointers, two status flags, and one bitmap to realize the read / write monitoring of the MM2S ring buffer queue.

[0022] 5. This invention uses multiple MM2S circular cache queues for multi-channel source data caching. The verification engine can read source data from multiple channels simultaneously in parallel. Compared to solutions using external DDR for data caching, this invention can save approximately half the data access time, allowing the verification engine to quickly complete verification or inverse operations. This invention achieves parallel reading of multi-channel source data through a multi-path MM2S_BUF parallel cache architecture, thereby reducing data reading time and accelerating verification or inverse operations.

[0023] 6. Through the management of the cache allocation and reclamation control circuit, this invention can ensure that each circular cache queue is allocated and used in ascending order of address, and is reclaimed and released in ascending order of address, thereby realizing the orderly and efficient cyclic use of cache space. Attached Figure Description

[0024] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. It is obvious that the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings.

[0025] Figure 1 This is a diagram illustrating how an existing RAID controller caches data via an external high-speed cache. Figure 2 This is a flowchart illustrating a parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue, according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a multi-channel MM2S circular buffer queue according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the MM2S circular buffer queue according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the MM2S ring buffer queue monitoring circuit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the multi-channel MM2S_BUF cache allocation and reclamation control circuit according to an embodiment of the present invention; Figure 7This is a schematic diagram of DDR sequential write and sequential read operations according to an embodiment of the present invention; Figure 8 This is a schematic diagram of sequential writing and parallel reading of multi-channel MM2S_BUF according to an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts disclosed in this invention.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The terms "installed," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of methods and systems consistent with some aspects of the invention as detailed in the appended claims.

[0030] This invention proposes a parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue. It is a multi-channel parallel data caching method based on a ring buffer queue (MM2S ring buffer queue, or Memory Mapped to Stream) with dual-port RAM memory-mapped interface to data stream interface. This method can solve the problems of large read latency and complex control logic of cached source data, and improve the efficiency of RAID parity operation or inverse operation.

[0031] This invention enables the caching of source data during the verification value calculation or inverse calculation process of the hardware RAID controller. It is a verification calculation / inverse calculation processing method for RAID verification source data parallel caching based on a multi-channel MM2S ring buffer queue.

[0032] like Figure 2 As shown, this invention proposes a parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue, comprising: S1, the RAID controller allocates multi-channel MM2S_BUF cache space based on the received write data command or recovery data request, and generates read source data command and verification engine operation request.

[0033] In this step, the RAID controller allocates multi-channel MM2S_BUF cache space according to the write data command or recovery data request, generates and pushes sub-commands to read source data from each hard drive and / or read source data from the host, and generates and pushes the calculation request of the verification engine.

[0034] The multi-channel MM2S_BUF cache space of the present invention uses multiple MM2S circular cache queues (MM2S_BUF) of the same depth to cache the verification source data of multiple channels in parallel.

[0035] like Figure 3 As shown, the multi-channel MM2S_BUF cache space includes multiple MM2S circular cache queues of the same depth, which are used to cache the verification source data of multiple channels in parallel.

[0036] Each channel's MM2S circular cache queue uses a memory-mapped interface for data writing. Multiple channels' memory-mapped interfaces are interconnected with the hard disk data write bus and the host data write bus via a bus interconnect module. Source data from the hard disk and / or host can be written to each cache space in a serial, out-of-order manner.

[0037] The data read interface of each channel's MM2S circular buffer queue adopts a data stream interface. The data stream interface of each channel is interconnected with the verification engine. The verification engine does not need to care about the data address, thus simplifying the data read control logic. After the source data of multiple MM2S_BUF buffer channels are ready, the verification engine reads the source data of multiple channels simultaneously in parallel, reducing the source data read latency and enabling the verification engine to quickly complete the verification value calculation or inverse calculation.

[0038] S2, according to the read source data instruction, writes the source data to the specified cache address of the MM2S circular cache queue of each channel through the memory mapping interface.

[0039] In this step, when the RAID controller receives a write data command, it reads the corresponding data from the host memory and writes it to the designated cache address of each MM2S_BUF channel. Depending on the host write command parameters and RAID configuration, in some cases, the relevant hard drives may also need to write the corresponding data to the designated cache address of the corresponding MM2S_BUF channel.

[0040] When the RAID controller receives a recovery data request, the relevant hard drives write the corresponding data to the designated cache address of each MM2S_BUF channel.

[0041] S3, the verification engine receives and parses the operation request. When it is determined that the source data of each channel in the operation request is ready, it reads the source data in the MM2S ring buffer queue of each channel in parallel through the data flow interface to perform verification value operation or inverse operation, and writes the completed verification data or recovery data into the corresponding buffer address.

[0042] Specifically, after the verification engine determines that the source data of each channel in the operation request is ready, it reads the source data of each MM2S_BUF channel in parallel to perform verification value operation or inverse operation, and writes the completed verification data or recovery data to the specified cache address.

[0043] This invention uses multiple MM2S circular buffer queues to cache multi-channel source data. The verification engine can read source data from multiple channels simultaneously in parallel, shortening data access time and enabling the verification engine to quickly complete verification or inverse operations.

[0044] S4, the RAID controller sends a write data command to the parity hard drive to write the parity data to the parity hard drive to complete the write command; or it sends a write data command to a newly added hard drive to write the recovery data to the newly added hard drive to rebuild the RAID system.

[0045] S5, after the verification data or recovery data is written, release the corresponding multi-channel MM2S_BUF cache space.

[0046] This invention uses a cache allocation and reclamation control circuit to allocate and reclaim cache space for multiple MM2S circular cache queues. The cache space of the multi-ring cache queues is allocated and used in ascending order of address, and each circular cache queue is reclaimed and released in ascending order of address, thus achieving orderly and efficient cyclic use of cache space.

[0047] The parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue of the present invention can be implemented in hardware such as FPGA, CPU, ASIC, DPU or GPU. Preferably, the method of the present invention is implemented in an FPGA.

[0048] FPGAs typically contain a large number of BRAMs (Block RAM) or URAMs (Ultra RAM) for high-speed data caching within the FPGA. These hardware resources can be instantiated as dual-port RAMs for use. By adding relevant interface circuits and control circuits to the dual-port RAMs, an MM2S circular buffer queue can be implemented.

[0049] The structure of the MM2S circular buffer queue is described below.

[0050] like Figure 4 As shown, the MM2S ring buffer queue includes: a dual-port RAM, a memory-mapped slave interface, a data stream master interface, and a ring buffer queue monitoring circuit.

[0051] 1. Dual-port RAM A dual-port RAM includes a RAM write port A and a RAM read port B. The RAM write port A is used for source data write operations, while the RAM read port B can simultaneously perform source data read operations.

[0052] These are two independent memory access interfaces, each of which can independently perform write or read data operations on the memory.

[0053] 2. Memory mapping from the interface The memory mapping interface connects to the memory mapping interface, converting the read and write operations of the memory mapping interface into read and write operations of RAM write port A, and executing write operations of host or hard disk source data.

[0054] The source data write interface of the MM2S circular cache queue adopts a memory-mapped slave interface, which can adapt to the cache access method of writing data to the hard disk and the host in out-of-order address order.

[0055] 3. Data Flow Main Interface The source data read interface of the MM2S circular cache queue adopts the data stream main interface. Compared with the memory-mapped interface, this interface does not require attention to the data address, which can greatly simplify the data read control logic, facilitate the verification engine to read data efficiently and quickly, meet the verification engine's requirement for sequential reading of source data, and thus quickly complete the verification operation or inverse operation.

[0056] The main data stream interface connects to the data stream interface, reads the stored source data sequentially from RAM read port B in ascending order of address, and outputs it through the data stream interface for use by the RAID verification engine to read the source data.

[0057] 4. Circular buffer queue monitoring circuit The ring buffer queue monitoring circuit controls the monitoring logic of the ring buffer queue's read / write pointers, status flags, and cache bitmaps. It can automatically monitor data writing and reading, ensuring that out-of-order source data is read out in ascending order of address, thus simplifying the complexity of the verification engine's interface control.

[0058] In this invention, the MM2S ring buffer queue monitoring circuit includes 3 pointers, 2 queue status flags and 1 buffer bitmap.

[0059] (1) Pointers to the circular buffer queue The MM2S ring buffer queue monitoring circuit includes a memory-mapped write pointer MM_WR_PTR, a head pointer QH_PTR, and a tail pointer QT_PTR.

[0060] 1) Memory-mapped write pointer MM_WR_PTR: The memory-mapped write pointer MM_WR_PTR is the ring buffer queue slot number pointed to by the write data address of the memory-mapped interface.

[0061] 2) Queue head pointer QH_PTR: The initial value of the queue head pointer QH_PTR is 0; when the main interface of the data stream finishes reading the specified amount of data, the queue head pointer QH_PTR is incremented by 1 (when the pointer value increases to N, the pointer value rolls back to 0); otherwise, the pointer value remains unchanged.

[0062] 3) Tail pointer QT_PTR: The initial value of the tail pointer QT_PTR is 0; when the memory-mapped interface completes writing a specified amount of data to the cache slot outside the cache queue, the value of the tail pointer QT_PTR is updated to MM_WR_PTR+1 (when the pointer value increases to N, the pointer value rolls back to 0); otherwise, the pointer value remains unchanged.

[0063] like Figure 5As shown, this invention constructs a circular cache area by concatenating the storage addresses of the dual-port RAM end-to-end. The cache area has N cache slots, numbered from 0 to N-1, and each cache slot can cache a specified amount of data (e.g., 4KB). The storage space from the head pointer QH_PTR to the tail pointer QT_PTR in ascending order of slot number constitutes the MM2S circular cache queue.

[0064] (2) Empty / full flags of the circular buffer queue The MM2S ring buffer queue monitoring circuit includes a ring buffer queue empty flag and a ring buffer queue full flag.

[0065] 1) Queue empty flag: The queue empty flag is set high when the tail pointer QT_PTR is equal to the head pointer QH_PTR; otherwise, the queue empty flag is low.

[0066] 2) Queue full flag: When the tail pointer QT_PTR+1 equals the head pointer QH_PTR, the queue full flag is set high; otherwise, the queue full flag is low.

[0067] (3) Cache Bitmap The circular buffer queue monitoring circuit includes a buffer bitmap with N bits. Each bit represents whether the data in the corresponding buffer slot is valid. If the data in the buffer slot is valid, the corresponding bit is set to 1; if the data in the buffer slot is invalid, the corresponding bit is set to 0. That is, 1 represents that the data in the buffer slot is valid, and 0 represents that the data in the buffer slot is invalid.

[0068] When the memory-mapped interface finishes writing a specified amount of data into a cache slot, the bit of the corresponding slot in the cache bitmap is set to 1; when the main data stream interface finishes reading a specified amount of data from the cache slot pointed to by the head pointer, the bit of the corresponding slot in the cache bitmap is cleared to 0.

[0069] The memory-mapped interface of a circular cache queue can write source data to different cache slots in an out-of-order manner, but data in the same cache slot must be written in ascending order of address. When source data from the host or hard drive is written to the cache queue, the memory-mapped write pointer resolves the address to be written to the circular cache queue slot number MM_WR_PTR based on the address it is writing to.

[0070] If MM_WR_PTR is in the cache queue (i.e., the head pointer QH_PTR ≤ the memory-mapped write pointer MM_WR_PTR, and the memory-mapped write pointer MM_WR_PTR < the tail pointer QT_PTR), then the specified amount of data is directly written to the cache slot pointed to by MM_WR_PTR. After the data is written, the tail pointer QT_PTR remains unchanged, and the cache bitmap sets the bit pointed to by MM_WR_PTR to 1.

[0071] If MM_WR_PTR is outside the cache queue (i.e., the head pointer QH_PTR > the memory-mapped write pointer MM_WR_PTR, or the memory-mapped write pointer MM_WR_PTR ≥ the tail pointer QT_PTR), then the specified amount of data is written to the cache slot pointed to by MM_WR_PTR. After the data is written, the tail pointer QT_PTR is updated to MM_WR_PTR+1 (when the pointer value increases to N, the pointer value rolls back to 0), and the cache bitmap BitMap sets the bit pointed to by MM_WR_PTR to 1.

[0072] It's important to note that the MM2S cache queue allows some slots in the queue (the cache space between the head and tail pointers) to have data already written to them, while other slots remain unwritten. When writing data to a slot in the queue that hasn't yet received data, the tail pointer of the queue remains unchanged; when writing data to a cache slot outside the queue, the tail pointer is updated to MM_WR_PTR+1. This allows for adaptation to out-of-order writes from the host or hard drive to the cache slots.

[0073] The main data stream interface of the circular buffer queue reads data sequentially from the buffer slots in ascending order of slot number. The main data stream interface continuously checks the empty flag signal of the queue and the bit status in the buffer bitmap pointed to by the queue head pointer QH_PTR. When the buffer queue is not empty and the bit in the buffer bitmap pointed to by the queue head pointer QH_PTR is 1, the main data stream interface sets the m_axis_tvalid signal high, indicating that the data is ready for transmission. After the verification engine determines that the source data for each channel is ready, it sets the m_axis_tready signal of each channel's data stream interface high simultaneously, allowing the verification source data for all channels to be read out simultaneously. When the main data stream interface finishes reading the specified amount of data from the buffer slot pointed to by the queue head pointer, the buffer bitmap clears the bit pointed to by the queue head pointer QH_PTR to 0, and simultaneously updates the value of the queue head pointer QH_PTR to QH_PTR+1 (when the pointer value increases to N, the pointer value rolls back to 0).

[0074] Through the control of the above monitoring circuit, it can be ensured that the source data written out of order in each ring buffer queue is read out simultaneously in ascending order of address. Compared with the DDR serial reading of data from each channel, this greatly reduces the data reading time and improves the processing speed of the verification engine.

[0075] The MM2S circular buffer queue of the present invention further includes a multi-channel MM2S_BUF buffer allocation and reclamation control circuit. Since the multiple MM2S_BUFs are used and released synchronously during RAID parity operations or inverse operations, the multi-channel MM2S_BUF buffer allocation and reclamation control circuits are managed synchronously by the same set of control circuits.

[0076] like Figure 6 As shown, the MM2S_BUF cache allocation and reclamation control circuit mainly includes a cache space allocation table DBUF_Table, a cache queue head pointer DBUF_HPTR, a cache queue tail pointer DBUF_TPTR, a cache queue empty flag DBUF_Empty, a cache queue full flag DBUF_Full, a cache queue occupancy count value DBUF_Occupied_Count, and a cache queue free count value DBUF_Free_Count.

[0077] The cache allocation table DBUF_Table is a memory with a width of 1 and a depth of N (the depth is the same as the number of cache slots in MM2S_BUF). Each bit represents the occupancy flag of the cache slot at the same location in MM2S_BUF; a flag of 1 indicates that the cache slot has been allocated and is occupied; a flag of 0 indicates that the cache slot has been reclaimed and released. The initial value of DBUF_Table is all 0s.

[0078] The empty queue flag DBUF_Empty is set high when the tail pointer DBUF_TPTR equals the head pointer DBUF_HPTR; otherwise, it is set low.

[0079] The full queue flag DBUF_Full: The full queue flag is set high when the tail pointer DBUF_TPTR+1 equals the head pointer DBUF_HPTR; otherwise, the full queue flag is low.

[0080] The cache queue occupancy count value DBUF_Occupied_Count is calculated as follows: when the tail pointer DBUF_TPTR is greater than the head pointer DBUF_HPTR, DBUF_Occupied_Count = DBUF_TPTR - DBUF_HPTR; otherwise, DBUF_Occupied_Count = DBUF_TPTR + ~DBUF_HPTR + 1.

[0081] The cache queue free count value DBUF_Free_Count: DBUF_Free_Count = cache queue depth N - DBUF_Occupied_Count.

[0082] When the RAID controller receives a write data command or a data recovery request, it generates a buffer space allocation request of length n (i.e., a request to allocate n consecutive buffer slots) based on the length of the operation data and the RAID stripe size. If the buffer space allocation table DBUF_Table determines that the current free slot count DBUF_Free_Count > n (i.e., a request to allocate n consecutive buffer slots and the current free slot count is greater than n), then DBUF_Table allocates the buffer space of n consecutive slots starting from the buffer slot x pointed to by the tail pointer DBUF_TPTR to the command, sets the corresponding bit in DBUF_Table to 1 (i.e., n consecutive bits from x to x+n-1), and updates the tail pointer DBUF_TPTR to x+n. Other empty / full flags and count values ​​are updated accordingly according to their generation logic.

[0083] The tail pointer DBUF_TPTR of the cache queue is initially set to 0. When the RAID controller generates a cache space allocation request of length n and the current cache queue free slot count DBUF_Free_Count > n (i.e., requesting allocation of n consecutive cache slots and the current cache queue free slot count is greater than n), the value of the tail pointer DBUF_TPTR is updated to DBUF_TPTR + n; otherwise, the pointer value remains unchanged. This invention allocates cache space in ascending address order.

[0084] After the RAID controller writes the parity data or recovery data processed by the parity engine to the SSD, it immediately requests the cache allocation and reclamation control circuit to release the cache space corresponding to the command (i.e., n consecutive cache slots starting from x). The cache space allocation table DBUF_Table clears the bit corresponding to the cache space to 0 (i.e., n consecutive bits from x to x+n-1). In other cases, the DBUF_Table value remains unchanged, and other empty / full flag signals and count values ​​are updated according to their generation logic.

[0085] Through the management of the above cache allocation and reclamation control circuit, it can be ensured that each circular cache queue is allocated and used in ascending order of address, and reclaimed and released in ascending order of address, so as to achieve orderly and efficient cyclic use.

[0086] Regarding the cache queue's head pointer DBUF_HPTR: the initial value of DBUF_HPTR is 0; when the queue is detected to be non-empty and the DBUF_Table flag pointed to by the head pointer DBUF_HPTR is 0, the head pointer DBUF_HPTR is incremented by 1 (when the pointer value increases to N, the pointer value rolls back to 0); otherwise, the pointer value remains unchanged. This invention reclaims cache space in ascending address order.

[0087] This invention employs multiple MM2S ring buffer queues to cache the source data of multiple channels in parallel. The multi-channel MM2S ring buffer queues can read the source data of multiple channels simultaneously in parallel. Compared with the traditional scheme of reading multiple channel data serially through external DDR, this invention can save about half of the source data access time, thereby greatly improving the performance of RAID data writing or recovery.

[0088] The following is for reference. Figure 7 and Figure 8 The caching scheme of this application and the DDR caching scheme are compared and analyzed to verify the source data access time.

[0089] Taking a RAID5 array of 12 SSDs as an example for comparison, the cache path required for parity calculation or inverse calculation is 11 paths. Figure 7 and Figure 8 The 11 data blocks are written sequentially in ascending order of channel number, but in reality, the 11 channels can be written in random order.

[0090] from Figure 7 and Figure 8 The comparison reveals the following: In the DDR sequential write and sequential read scheme, it takes approximately 22∆T time from writing 11 data blocks to reading 11 data blocks and completing the verification operation.

[0091] In the multi-channel MM2S_BUF sequential write parallel read scheme of this application, it takes about 12∆T time from writing 11 channel data blocks to reading 11 channel data blocks and completing the verification operation. Compared with the traditional DDR cache scheme, it reduces the source data access time by about half. Therefore, the method of this invention can greatly speed up the verification engine's verification operation or inverse operation process.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue, characterized in that, include: S1, the RAID controller allocates multi-channel MM2S_BUF cache space according to the received write data command or recovery data request, and generates read source data command and verification engine operation request; The multi-channel MM2S_BUF cache space includes multiple MM2S circular cache queues of the same depth, used for parallel caching of the verification source data of multiple channels; the data writing interface of the MM2S circular cache queue of each channel adopts a memory-mapped interface; the data reading interface of the MM2S circular cache queue of each channel adopts a data stream interface. S2, according to the read source data instruction, write the source data to the specified cache address of the MM2S circular cache queue of each channel through the memory mapping interface; S3, the verification engine receives and parses the operation request. When it is determined that the source data of each channel in the operation request is ready, the source data in the MM2S ring buffer queue of each channel is read out in parallel through the data flow interface to perform verification value operation or inverse operation, and the completed verification data or recovery data is written into the corresponding buffer address. S4, the RAID controller sends a write data command to the verification hard drive to write the verification data to the verification hard drive; or sends a write data command to the newly added hard drive to write the recovery data to the newly added hard drive to rebuild the RAID system; S5, after the verification data or recovery data is written, release the corresponding multi-channel MM2S_BUF cache space.

2. The RAID parity source data parallel caching method based on a multi-channel MM2S ring buffer queue according to claim 1, characterized in that, The memory-mapped interface of each channel is interconnected with the hard disk data write bus and the host data write bus via bus interconnect, and the data stream interface of each channel is interconnected with the verification engine.

3. The RAID parity source data parallel caching method based on a multi-channel MM2S ring buffer queue according to claim 1, characterized in that, The MM2S ring buffer queue includes: a dual-port RAM, a memory-mapped slave interface, a data stream master interface, and a ring buffer queue monitoring circuit, wherein, The dual-port RAM includes a RAM write port and a RAM read port to independently complete write and read operations; The memory mapping slave interface is connected to the memory mapping interface, and the read and write operations of the memory mapping interface are converted into read and write operations of the RAM write port to execute the write operation of host or hard disk source data; The main data stream interface is connected to the data stream interface, and reads the stored source data from the RAM read port in ascending order of address, and outputs it through the data stream interface so that the verification engine can read the source data. The ring buffer queue monitoring circuit controls the read / write pointers, status flags, and buffer bitmap of the ring buffer queue to read out the out-of-order source data in ascending order of address.

4. The RAID parity source data parallel caching method based on a multi-channel MM2S ring buffer queue according to claim 3, characterized in that, The ring buffer queue monitoring circuit includes a memory-mapped write pointer MM_WR_PTR, a head pointer QH_PTR, and a tail pointer QT_PTR. Wherein, the memory-mapped write pointer MM_WR_PTR is the ring cache queue slot number pointed to by the memory-mapped interface write data address; The initial value of the queue head pointer QH_PTR is 0. When the main interface of the data stream finishes reading the specified amount of data, the queue head pointer QH_PTR is incremented by 1. The tail pointer QT_PTR is initially set to 0. When the memory mapping interface completes writing a specified amount of data to a cache slot outside the cache queue, the value of the tail pointer QT_PTR is updated to MM_WR_PTR+1.

5. A RAID parity source data parallel caching method based on a multi-channel MM2S ring buffer queue according to claim 4, characterized in that, The storage addresses of the dual-port RAM are connected end to end to construct a circular buffer area. The circular buffer area has N cache slots, and the cache slot numbers are from 0 to N-1. Each cache slot caches source data. The storage space from the head pointer QH_PTR to the tail pointer QT_PTR in the direction of increasing slot number constitutes the MM2S circular cache queue.

6. The RAID parity source data parallel caching method based on a multi-channel MM2S ring buffer queue according to claim 4, characterized in that, The ring buffer queue monitoring circuit includes a ring buffer queue empty flag and a ring buffer queue full flag. Specifically, when the tail pointer QT_PTR equals the head pointer QH_PTR, the circular buffer queue's empty flag is set high; otherwise, the circular buffer queue's empty flag is set low. When the tail pointer QT_PTR+1 equals the head pointer QH_PTR, the full flag of the circular buffer queue is set high; otherwise, the full flag of the circular buffer queue is set low.

7. A parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue according to claim 3, characterized in that, The ring-shaped cache queue monitoring circuit includes a cache bitmap, which has N bits. Each bit represents whether the data in the corresponding cache slot is valid. If the data in the cache slot is valid, the corresponding bit is set to 1; if the data in the cache slot is invalid, the corresponding bit is set to 0.

8. A parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue according to claim 7, characterized in that, The main data stream interface of the circular buffer queue reads data from the buffer slots in ascending order of slot number. The main data stream interface continuously judges the empty flag signal of the queue and the bit status of the buffer bit map pointed to by the queue head pointer QH_PTR. When the buffer queue is not empty and the bit in the buffer bitmap pointed to by the queue head pointer QH_PTR is 1, it indicates that the data is ready and data transfer is allowed.

9. A parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue according to claim 1, characterized in that, When the RAID controller receives a write data command or a data recovery request, it generates a cache space allocation request of length n based on the length of the operation data and the RAID stripe size. If the cache space allocation table DBUF_Table determines that the current cache queue free slot count value DBUF_Free_Count > n, it allocates n consecutive cache slots starting from the cache slot x pointed to by the tail pointer DBUF_TPTR to the request.

10. A parallel caching method for RAID parity source data based on a multi-channel MM2S ring buffer queue according to claim 1, characterized in that, After the RAID controller writes the verification data or recovery data processed by the verification engine to the hard disk, it immediately requests the release of the corresponding multi-channel MM2S ring cache space. The cache space allocation table DBUF_Table clears the bit corresponding to the cache space to zero. The cache space of the multiple MM2S ring cache queues is released and reclaimed in ascending order of address.

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