A sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms

Abstract

The application provides a sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms, determines a target sorting algorithm corresponding to a target sorting task command through a command decoder module; generates sorting task execution logic of the target sorting algorithm through a sorting network tree traversal module; generates a task allocation result as control information according to a preset allocation rule through a task allocator module according to the sorting task execution logic, predetermined sorting modes of each sorting processing module and load states of each sorting processing module; and forwards current data to be sorted to a corresponding sorting processing module for sorting processing according to the control information through a data exchange and load storage module. Through integrated management and control of sorting data and sorting processes, the application improves the overall throughput and resource utilization of hardware sorting, reduces invalid overheads of off-chip bandwidth, on-chip storage and computing power, and overcomes problems such as poor adaptability, resource waste and idle computing power of traditional fixed sorting hardware.

Description

Technical Field

[0001] This invention relates to the field of dynamic scheduling for accelerating sorting, and in particular to a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms. Background Technology

[0002] With the development of applications such as AI retrieval, recommendation ranking, image search, and large-scale data analysis, the demand for hardware-accelerated sorting is constantly increasing. In real-world business scenarios, there are often sorting requirements for fixed-scale data, as well as sorting requirements with various output goals, including Top1, Top2, dynamic TopK filtering, and full sorting. Traditional sorting hardware is usually optimized for fixed data scales, fixed TopK ranges, or single sorting networks. When facing large-scale data processing, dynamically variable TopK tasks, and scenarios requiring compatibility with multiple sorting network algorithms, problems such as wasted hardware resources, insufficient architectural scalability, and poor adaptability to sorting algorithms are prone to occur.

[0003] Currently, existing sorting hardware architectures can be mainly divided into five categories: First, fully expanding the various operational steps of the sorting network into a multi-level cascaded pipeline structure, configuring dedicated hardware sorting circuits for each stage of operation; Second, using a single set of sorting hardware for time-division multiplexing, serially executing comparison and exchange logic of different steps; Third, replicating multiple sets of identical hardware sorting units in the step dimension, improving overall processing throughput through hardware parallel stacking; Fourth, deploying multiple sorting hardware in the TopK task dimension, with each hardware branch responsible for filtering and calculating a portion of the TopK results; Fifth, splitting the sorting network into independent sorting networks and merging networks, respectively undertaking the functions of sorting locally disordered data and merging multiple ordered sequences. While the above-mentioned hardware architecture solutions can meet basic sorting requirements in specific scenarios, they still have significant technical limitations in complex scenarios such as large-scale sorting, full sorting, and dynamic TopK.

[0004] First, as the sorting scale increases, traditional hardware sorting structures typically face the problem of rapidly increasing off-chip bandwidth, external storage, and computing power consumption when handling large-scale full sorts. To support larger-scale sorts, larger comparator arrays, deeper pipelines, and more off-chip memory accesses are often required, leading to increased bandwidth consumption and enhanced external storage dependence. At the same time, data access conflicts and storage conflicts further reduce bandwidth utilization.

[0005] Secondly, existing hardware sorting structures are typically optimized only for a fixed TopK range. When the actual task only requires Top1, Top2, or a smaller TopK, this large-granularity sorting hardware is still invoked, resulting in processing time, bandwidth consumption, and storage consumption being similar to when processing a fixed TopK, leading to significant resource waste. When the target task is a larger TopK or a full sort, relying on fixed sorting hardware to repeatedly perform local sorting and merging will result in excessively long sorting times and excessive bandwidth and storage overhead.

[0006] Furthermore, existing large-scale sorting network hardware often only supports one or a few sorting network algorithms. Different sorting network algorithms have their own advantages and disadvantages under different data distributions and different task objectives. Supporting only a single sorting network will result in the inability to achieve optimal performance in certain tasks. In addition, existing sorting network hardware generally lacks the ability to dynamically traverse, dynamically schedule, and reconstruct data paths for sorting networks. It is difficult to select the optimal execution order according to the actual task characteristics, which can easily lead to problems such as duplicate data transmission, additional intermediate buffers, data dependency conflicts, underutilization of bandwidth, and idle computing power. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms. This system addresses the technical problems of existing sorting networks having fixed granularity, single and fixed sorting network types, difficulty in adapting to multiple sorting algorithms and dynamic TopK requirements, low hardware resource utilization, poor scalability, high bandwidth and storage overhead, and insufficient flexibility in intermediate data scheduling.

[0008] To achieve the above and other related objectives, this application provides a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms. The system comprises: a command decoder module, a sorting network tree traversal module, a task allocator module, a data exchange and loading / storage module, and multiple sorting processing modules; wherein each sorting processing module supports at least one predetermined sorting mode; the command decoder module is used to receive and parse target sorting task commands to obtain the identification information of the corresponding target sorting algorithm; the sorting network tree traversal module, connected to the command decoder module, is used to match and obtain the corresponding sorting task execution logic based on the identification information of the target sorting algorithm; the task allocator module... The task allocation module, connected to the sorting network tree traversal module, is used to generate task allocation results according to preset allocation rules based on the sorting task execution logic, the predetermined sorting modes of each sorting processing module, and the load status, and transmit the task allocation results as control information to the data exchange and loading storage module. The data exchange and loading storage module, connected to the task allocation module and the multiple sorting processing modules respectively, is used to forward the currently unsorted data to the corresponding sorting processing module according to the received control information. The multiple sorting processing modules are used to sort the received currently unsorted data according to their supported predetermined sorting modes to complete the corresponding target sorting task.

[0009] In some embodiments of the first aspect of this application, the sorting network tree traversal module is pre-configured with multiple sorting network algorithms, each sorting network algorithm has a corresponding network tree, and each network tree is composed of multiple sorting mode nodes and the dependencies between the nodes; the execution process of the sorting network tree traversal module includes: based on the received identification information of the target sorting algorithm, matching the corresponding network tree in the pre-configured network trees of multiple sorting network algorithms, and using a depth-first traversal strategy with configurable maximum depth to traverse each sorting mode node in the matched network tree; and generating the sorting task execution logic of the target sorting algorithm according to the sorting mode nodes and the dependencies between the nodes obtained by traversal.

[0010] In some embodiments of the first aspect of this application, the system further includes a mode conversion module connected to the data exchange and loading storage module; the mode conversion module receives current data to be sorted from the data exchange and loading storage module and performs mode conversion on it; the sorting processing module obtains the converted data and performs sorting processing; the type of the mode conversion module includes a read / write controller or a KLOS network converter.

[0011] In some embodiments of the first aspect of this application, when the mode conversion module is a read / write controller, multiple read / write controllers are connected to the data exchange and loading storage module, and each read / write controller is connected to a sorting processing module. The read / write controller is used to receive the current data to be sorted forwarded by the data exchange and loading storage module, and to perform read / write control mode conversion on the received current data to be sorted to obtain corresponding read / write control conversion data, and to transmit the read / write control conversion data to the corresponding sorting processing module for sorting processing.

[0012] In some embodiments of the first aspect of this application, when the mode conversion module is a Kloss network converter, the Kloss network converter is connected to the data exchange and loading storage module, and is used to receive the current unsorted data forwarded by the data exchange and loading storage module, and to perform Kloss network mode conversion on the received current unsorted data to obtain the corresponding Kloss network converted data; the Kloss network converter transmits the Kloss network converted data to the data exchange and loading storage module, and the data exchange and loading storage module forwards the Kloss network converted data to the corresponding sorting processing module for sorting processing.

[0013] In some embodiments of the first aspect of this application, the task allocator module generates a task allocation result as control information according to the sorting task execution logic, the predetermined sorting mode of each sorting processing module, and the load status, in accordance with a preset allocation rule; wherein, the preset allocation rule includes: if there is a sorting processing module that supports the target sorting mode in the sorting task execution logic, the data exchange and loading storage module forwards the currently unsorted data directly to the corresponding sorting processing module for sorting processing according to the task allocation result; if there is no sorting processing module that supports the target sorting mode in the sorting task execution logic, and the read / write controller satisfies the preset mode conversion rule, The data exchange and loading / storage module forwards the currently unsorted data to the corresponding read / write controller for read / write control mode conversion based on the task allocation result, and transmits the converted read / write control mode conversion data to the corresponding sorting module for sorting. If there is no sorting module that supports the target sorting mode in the sorting task execution logic, and the read / write controller does not meet the preset mode conversion rules, the data exchange and loading / storage module forwards the currently unsorted data to the Kloss network converter for Kloss network mode conversion based on the task allocation result, and transmits the converted Kloss network mode conversion data to the corresponding sorting module for sorting.

[0014] In some embodiments of the first aspect of this application, each read / write controller includes a first storage bank and a second storage bank; the first storage bank and the second storage bank are used to cache and control the current data to be sorted during the read / write control mode conversion process, so as to support the read / write controller to convert the target sorting mode corresponding to the current data to be sorted into a predetermined sorting mode supported by the corresponding sorting processing module.

[0015] In some embodiments of the first aspect of this application, the process by which each read / write controller performs read / write control mode conversion on the currently unsorted data forwarded by the data exchange and loading storage module includes: logically dividing the currently unsorted data according to a preset segmentation size to obtain multiple logically segmented data segments; adjusting the address order of the multiple logically segmented data segments according to a preset address adjustment order to obtain logically segmented data segments with adjusted address order; writing the logically segmented data segments with adjusted address order into the first storage bank and the second storage bank respectively; reading data from the first storage bank and the second storage bank according to the data reading order control instruction of the sorting network tree traversal module to obtain logically segmented data segments after data reading; and performing data splicing processing on the logically segmented data segments after data reading to obtain the read / write control conversion data.

[0016] In some embodiments of the first aspect of this application, the multiple logically segmented data segments are adjusted in address order according to a preset address adjustment order to obtain logically segmented data segments with adjusted address order. The process includes: obtaining the target element comparison distance of the target sorting mode corresponding to the current data to be sorted and the predetermined element comparison distance of the predetermined sorting mode supported by the corresponding sorting processing module; determining the sequence number interval of the logically segmented data segments that need to be adjusted in address order in the logical partitioning sequence according to the multiple relationship between the target element comparison distance and the predetermined element comparison distance; and adjusting the address order of the logically segmented data segments that need to be adjusted in address order according to the sequence number interval to obtain logically segmented data segments with adjusted address order.

[0017] In some embodiments of the first aspect of this application, the Kloss network converter is further configured to filter and rearrange the sorting results after the sorting processing module has completed the sorting processing, and output the filtered and rearranged data as the target result.

[0018] As described above, the sorting acceleration system of this application, which supports dynamic scheduling and is compatible with multiple sorting network algorithms, has the following beneficial effects: The invention parses the user-issued target sorting task command through a command decoder module to determine the target sorting algorithm; a sorting network tree traversal module generates the sorting task execution logic of the target sorting algorithm based on the pre-configured sorting mode nodes and inter-node dependencies of multiple sorting network algorithms; a task allocator module generates task allocation results as control information according to preset allocation rules based on the sorting task execution logic, the predetermined sorting modes of each sorting processing module, and the load status of each sorting processing module; and a data exchange and loading / storage module forwards the currently unsorted data to the corresponding sorting processing module for sorting processing based on the control information. This invention improves the overall throughput and resource utilization of hardware sorting by integrating the management of sorting data and the sorting process, reduces the ineffective overhead of off-chip bandwidth, on-chip storage, and computing power, and overcomes the technical problems of poor hardware adaptability, resource waste, and idle computing power in traditional fixed sorting systems. Attached Figure Description

[0019] Figure 1 The diagram shown is a structural schematic of a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms, according to an embodiment of the present invention.

[0020] Figure 2 The diagram shows the execution logic of a sorting task generated by a Step-dimensional depth-first traversal strategy in a sorting network tree traversal module according to an embodiment of the present invention.

[0021] Figure 3 The diagram shown is a structural schematic of a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms, including a mode conversion module, according to an embodiment of the present invention.

[0022] Figure 4 The diagram shows a flow chart of the read / write controller performing read / write control mode switching in one embodiment of the present invention.

[0023] Figure 5 The diagram shows a flowchart illustrating the process of adjusting the address order of multiple logically segmented data segments according to a preset address adjustment order in one embodiment of the present invention.

[0024] Figure 6a This diagram illustrates the read / write control mode conversion required for the next round of sorting of the output data after the sorting module 15 completes the current round of sorting, as shown in a specific example of the present invention.

[0025] Figure 6bThe diagram shows a flowchart illustrating how the output data after sorting by the sorting module 15 in a specific example of the present invention is converted into a predetermined sorting mode supported by the sorting module 15 through a read / write controller.

[0026] Figure 7a This diagram illustrates the read / write control mode conversion required for the target sorting mode in a specific example of the present invention to sort the current data to be sorted.

[0027] Figure 7b This is a schematic diagram illustrating the process of converting the current data to be sorted into a predetermined sorting mode supported by the sorting processing module 15 through the read / write controller, as shown in a specific example of the present invention.

[0028] Figure 7c This is a flowchart illustrating how, in a specific example of the present invention, the current data to be sorted, after being adjusted according to the depth-first traversal strategy rules of the sorting network tree traversal module, is converted by the read / write controller into a predetermined sorting mode supported by the sorting processing module 15.

[0029] Figure 8a This is a schematic diagram illustrating how the CLOS network converter filters and rearranges the Top1 sorting results in a specific example of the present invention.

[0030] Figure 8b This is a schematic diagram illustrating the filtering and rearrangement of the Top 2 sorting results by the CLOS network converter in a specific example of the present invention.

[0031] Figure 9 The diagram shown is a structural schematic of a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms, according to a specific embodiment of the present invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0033] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of this application. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of this application. The following detailed description should not be considered limiting, and the scope of the embodiments of this application is defined only by the claims of the published patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0034] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," and "holding" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data used can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising,” “including,” indicate the presence of the stated features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. It should be further understood that the terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will only occur if the combination of elements, functions, or operations is inherently mutually exclusive in some way.

[0036] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0037] <1> Step: refers to the first level of comparison and exchange in the sorting network. Each Step corresponds to a set of comparison and exchange operations with the same comparison distance and the same connection relationship. It contains multiple parallel comparators and is the basic traversal unit of the sorting network tree traversal module.

[0038] <2> Pattern: refers to the comparator connection relationship and data comparison distance corresponding to a certain step in the sorting network. It is used to characterize the comparison and exchange operation characteristics that need to be performed at that step. Each pattern can contain multiple parallel comparison and exchange operations.

[0039] <3> P1: refers to the sorting processing module in this system that supports a predefined sorting mode with an element comparison distance of 1, or refers to the target sorting mode with an element comparison distance of 1, used to perform comparison and swap operations with the corresponding step size.

[0040] <4> P2: Refers to the sorting processing module in this system that supports a predetermined sorting mode with an element comparison distance of 2, or refers to the target sorting mode with an element comparison distance of 2, used to perform comparison and swap operations with the corresponding step size.

[0041] <5> P3: Refers to the sorting processing module in this system that supports a predetermined sorting mode with an element comparison distance of 4, or refers to the target sorting mode with an element comparison distance of 4, used to perform comparison and swap operations with the corresponding step size.

[0042] <6> P4: Refers to the sorting processing module in this system that supports a predetermined sorting mode with an element comparison distance of 8, or to the target sorting mode with an element comparison distance of 8, used to perform comparison and swap operations with the corresponding step size.

[0043] <7> P5: Refers to the sorting processing module in this system that supports a predetermined sorting mode with an element comparison distance of 16, or refers to the target sorting mode with an element comparison distance of 16, used to perform comparison and swap operations with the corresponding step size.

[0044] <8> Step 1: refers to the comparison exchange level in the sorting network where the element comparison distance is 1. In this level, the two elements in each comparison exchange pair are separated by 1 element position in the data sequence.

[0045] <9> Step 2: refers to the comparison exchange level in the sorting network where the element comparison distance is 2. In this level, the two elements in each comparison exchange pair are separated by 2 element positions in the data sequence.

[0046] <10> Step 3: refers to the comparison exchange level in the sorting network where the element comparison distance is 4. In this level, the two elements in each comparison exchange pair are separated by 4 element positions in the data sequence.

[0047] <11> Step 4: This refers to the comparison exchange level in the sorting network where the element comparison distance is 8. In this level, the two elements in each comparison exchange pair are separated by 8 element positions in the data sequence.

[0048] <12> Step 5: This refers to the comparison exchange level in the sorting network where the element comparison distance is 16. In this level, the two elements in each comparison exchange pair are separated by 16 element positions in the data sequence.

[0049] <13> Comparison swap pair: refers to a data pair formed by two elements that need to be compared and swapped in a certain step of the sorting network. The two elements in the data pair are compared according to a predetermined sorting pattern, and the result of the comparison determines whether to swap their positions.

[0050] <14> Element: refers to the basic data unit in the sorting process, and is the smallest object in the sorting network for comparison and exchange operations.

[0051] <15> Element comparison distance: Element comparison distance refers to the number of elements in the data sequence between two elements that need to be compared and swapped in a certain comparison swapping step of the sorting network. For example, a comparison distance of 4 means that the two elements in each comparison swapping pair in the current step are 4 positions apart.

[0052] <16> Element comparison connection relationship: refers to the connection between comparison exchange pairs in a certain comparison exchange step of the sorting network, used to determine which elements need to be paired for comparison and exchange operations.

[0053] <17> Bank conflict refers to a situation where multiple access requests simultaneously access the same memory bank in a multi-bank memory system, causing these requests to be processed serially instead of in parallel.

[0054] <18> Clos Network: refers to a multi-level non-blocking switching network composed of a three-level crossbar switch matrix. In this application, its flexible switching capability is used to realize the conversion and adaptation of complex data sorting patterns.

[0055] <19> Bitonic Sort Network: A parallel sorting network based on bitonic sequences. It sorts data by constructing and merging bitonic sequences step by step. It has the characteristics of fixed connection rules and suitability for parallel hardware implementation.

[0056] <20> Merge Sort Network: A parallel sorting network based on a divide-and-conquer strategy. It divides the data into multiple subsequences, sorts them separately, and then merges them level by level to finally generate a complete ordered sequence.

[0057] <21> Odd-Even Mergesort Network: This refers to a parallel sorting network based on an odd-even merging strategy. It divides the data sequence into odd-even subsequences, sorts them separately, and then merges them. It has the characteristics of regular structure and suitability for hardware implementation.

[0058] <22> Balanced Sorting Networks: These are parallel sorting networks that reduce the number of comparisons and optimize sorting efficiency by designing a balanced comparator connection structure.

[0059] This invention provides a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms. It is suitable for various scenarios requiring hardware-accelerated sorting, such as artificial intelligence retrieval, image search, database processing, recommendation sorting, and large-scale data analysis. Specifically, the invention's technical solution involves: a command decoder module parsing the user-issued target sorting task command to determine the target sorting algorithm; a sorting network tree traversal module generating the sorting task execution logic of the target sorting algorithm based on pre-configured sorting mode nodes and inter-node dependencies of multiple sorting network algorithms; a task allocator module generating task allocation results as control information according to preset allocation rules based on the sorting task execution logic, the predetermined sorting modes of each sorting processing module, and the load status of each sorting processing module; and a data exchange and loading / storage module forwarding the currently unsorted data to the corresponding sorting processing module for sorting processing based on the control information.

[0060] The technical solutions in the embodiments of the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the invention.

[0061] like Figure 1 The diagram shows a structural schematic of a sorting acceleration system 10 that supports dynamic scheduling and is compatible with multiple sorting network algorithms according to an embodiment of the present invention. The system includes: a command decoder module 11, a sorting network tree traversal module 12, a task allocator module 13, a data exchange and loading storage module 14, and multiple sorting processing modules 15.

[0062] The command decoder module 11 is used to receive and parse the target sorting task command input from the outside to obtain the identification information of the corresponding target sorting algorithm.

[0063] Specifically, when the command decoder module 11 receives an externally issued command, it first parses and verifies the received command. The parsing and verification include identifying the command type, checking whether the command format is standardized, verifying the validity of the command parameters (ensuring that the parameters are within the preset valid range), and eliminating invalid or illegal commands. For valid commands that pass the verification, the command decoder module 11 parses out the target sorting algorithm to be executed for this sorting task, such as the Bitonic sorting algorithm or the merge sorting algorithm.

[0064] After determining the target sorting algorithm to be executed in this sorting task, the command decoder module 11 transmits the identification information of the target sorting algorithm to the sorting network tree traversal module 12, so that it can generate the sorting task execution logic corresponding to the target sorting algorithm. It should be noted that the command decoder module 11 can be implemented using any command decoder or command parsing circuit known in the art, as long as it can realize the functions of receiving external commands, parsing command types, extracting command parameters, and configuring other hardware modules. This invention does not make any specific limitations in this regard.

[0065] The sorting network tree traversal module 12 is connected to the command decoder module 11 and is used to match and obtain the corresponding sorting task execution logic based on the identification information of the target sorting algorithm received from the command decoder module 11.

[0066] In some optional implementations, to achieve compatibility and flexible invocation of multiple sorting network algorithms, the sorting network tree traversal module 12 is pre-configured with multiple sorting network algorithms. Each sorting network algorithm has a corresponding network tree, and each network tree consists of multiple sorting pattern nodes and the dependencies between the nodes. These multiple sorting network algorithms include: Bitonic Sort Network, Merge Sort Network, Odd-Even Mergesort Network, Balanced Sorting Networks, etc. It should be noted that each sorting pattern node corresponds to a target sorting pattern in the sorting task execution process. Each target sorting pattern defines the element comparison connection relationships and element comparison distances required for a certain comparison exchange step. In the sorting network, each comparison exchange step corresponds to a set of comparison exchange operations with the same element comparison distance and the same element comparison connection relationship. The data dependencies between nodes are used to define the execution order of each sorting pattern node, ensuring that the sorting task progresses step by step according to the correct logic.

[0067] Specifically, the execution process of the sorting network tree traversal module includes the following steps: After receiving the identification information of the target sorting algorithm transmitted by the command decoder module 11, the sorting network tree traversal module 12 performs the following: First, in the pre-configured network trees of various sorting network algorithms, it matches the network tree corresponding to the target sorting algorithm; then, it uses a depth-first traversal strategy with configurable maximum depth, preferably a depth-first traversal strategy based on the Step dimension with configurable maximum depth, to traverse each sorting pattern node in the matched network tree. During the traversal, it strictly follows the data dependency relationship between each node to ensure that no order disorder occurs; finally, through the above traversal process, the sorting network tree traversal module 12 obtains all sorting pattern nodes required by the target sorting algorithm and the execution order of each node, and then generates the sorting task execution logic corresponding to the target sorting algorithm.

[0068] It should be noted that the configurable maximum depth based on the Step dimension depth-first traversal strategy refers to using the Step (comparison-commutation level) in the network tree as the basic traversal unit. Starting from the initial Step of the network tree, it prioritizes traversing downwards along the data dependencies between nodes until a preset maximum depth is reached or it cannot continue to traverse further. Then, it backtracks to the previous Step to continue traversing other branches. This traversal strategy differs from the cascading order of nodes in the original sorting mode of the corresponding sorting network algorithm. Its advantage lies in prioritizing the execution of independently achievable task branches without disrupting data dependencies, thereby releasing storage resources in advance and reducing subsequent computational load.

[0069] To facilitate understanding by those skilled in the art, the following is combined with Figure 2 The following is an illustrative example of the sorting task execution logic for generating the corresponding target sorting algorithm using the above-described traversal strategy in the sorting network tree traversal module 12. It should be specifically noted that this example is merely one feasible implementation of the sorting task execution logic and does not constitute a limitation of the present invention. Figure 2 The diagram illustrates the execution logic of the sorting task generated by the sorting network tree traversal module 12 in this example, which employs a depth-first traversal strategy based on the Step dimension with configurable maximum depth. (See example...) Figure 2In the diagram, numbers 1 to 20 represent the order of sorting mode nodes that can be executed serially in the sorting task execution logic, obtained by the sorting network tree traversal module 12 using this traversal strategy. That is, the corresponding sorting mode nodes are executed sequentially in ascending order of their numbers. Steps 1 to 5 represent comparison exchange levels with element comparison distances of 1, 2, 4, 8, and 16, respectively. The numbers below each Step represent the sorting mode nodes that need to be executed within that Step. P1, P2, and P3 represent sorting processing modules 15 that support predetermined sorting modes with element comparison distances of 1, 2, and 4, respectively. The sorting mode node corresponding to Step 1 can be executed by P1, the sorting mode node corresponding to Step 2 can be executed by P2, and the sorting mode node corresponding to Step 3 can be executed by P3. If the system only has sorting processing modules 15 with three predetermined sorting modes (P1, P2, and P3), then the sorting mode nodes corresponding to Step 4 and Step 5 need to be converted by the mode conversion module 16 before being assigned to the corresponding sorting processing module 15 for sorting processing. Each rectangle in the diagram represents an independent sorting pattern node, and the lines inside the rectangles represent swapped pairs to be compared. From Figure 2 It is evident that the 20 sorting pattern nodes are not arranged in the natural hierarchical order of Step1, Step2, Step3, Step4, Step5, but rather in a depth-first traversal strategy.

[0070] It should be noted that the subsequent task allocator module 13 will dynamically allocate the data to be sorted to the corresponding hardware modules based on the target sorting mode corresponding to each sorting mode node in the sorting task execution logic, and in conjunction with the resource usage of the hardware modules (such as the sorting processing module 15) corresponding to the target sorting mode. If the target sorting mode corresponds to multiple hardware modules, or if different target sorting modes have corresponding available hardware modules, then the sorting mode nodes corresponding to the above-mentioned serially running sorting task execution logic can be run in parallel on the hardware modules.

[0071] The task allocator module 13 is connected to the sorting network tree traversal module 12. It is used to generate task allocation results according to the sorting task execution logic of the target sorting algorithm, the predetermined sorting mode and load status of each sorting processing module 15, and according to the preset allocation rules, and transmit the task allocation results as control information to the data exchange and loading storage module 14.

[0072] Specifically, after receiving the sorting task execution logic transmitted by the sorting network tree traversal module 12, the task allocator module 13 first parses the target sorting mode corresponding to each sorting mode node one by one. Simultaneously, it acquires two key pieces of information from each sorting processing module 15 in real time: first, the predetermined sorting modes supported by each sorting processing module 15, used to determine whether the sorting processing module 15 can adapt to the target sorting mode corresponding to each sorting mode node, ensuring the adaptability of task allocation; second, the real-time load status of each sorting processing module 15 (e.g., the length of the pending task queue, resource utilization, etc.), to avoid allocating sorting tasks to sorting processing modules 15 that are under load, thus ensuring the overall execution efficiency of the sorting tasks. Subsequently, the task allocator module 13 determines whether there is a sorting processing module 15 in the current acceleration system that supports the corresponding target sorting mode, based on the target sorting mode corresponding to each sorting mode node, the predetermined sorting mode of each sorting processing module 15, and the load status of each sorting processing module 15. The judgment logic of the task allocator module 13 includes: if there is a sorting processing module 15 that supports the target sorting mode, then based on the load status of each sorting processing module 15, the sorting processing module 15 with the lowest current load is selected first to generate a directly assigned task allocation result; if there is no sorting processing module 15 that supports the target sorting mode, it is determined whether the sorting mode can be converted through the read / write controller. If the read / write controller meets the preset mode conversion rules, a task allocation result after conversion by the read / write controller is generated; if the read / write controller does not meet the preset mode conversion rules, a task allocation result after conversion by the CLOS network converter is generated. The CLOS network is also known as a CLOS network, and for convenience, it will be referred to as a CLOS network in the following text. The preset mode conversion rules include that the read / write controller can successfully convert the target sorting mode to a predetermined sorting mode supported by a certain sorting processing module 15 through address order adjustment.

[0073] The task allocator module 13 transmits the task allocation results as control information to the data exchange and loading / storage module 14. The control information includes at least: the identifier of the sorting processing module 15, a data forwarding path indication, and the required sorting mode conversion type (e.g., no conversion, read / write control mode conversion, CLOS network mode conversion). Based on the received control information, the data exchange and loading / storage module 14 executes the corresponding data forwarding operation, thereby completing the dynamic allocation of sorting tasks.

[0074] In some optional implementations, to further clarify the preset allocation rules and facilitate understanding and implementation by those skilled in the art, the preset allocation rules are further detailed as follows, which are consistent with the judgment logic above, and specifically include the following three cases:

[0075] In the first scenario: if there is a sorting processing module 15 that supports the target sorting mode in the sorting task execution logic, the data exchange and loading storage module 14 will directly forward the current data to be sorted to the corresponding sorting processing module 15 for sorting processing according to the task allocation result.

[0076] In the second scenario: if there is no sorting processing module 15 that supports the target sorting mode in the sorting task execution logic, and the read / write controller meets the preset mode conversion rules, the data exchange and loading storage module 14 forwards the current data to be sorted to the corresponding read / write controller for read / write control mode conversion according to the task allocation result, and transmits the converted read / write control conversion data to the corresponding sorting processing module 15 for sorting processing.

[0077] The third scenario: If there is no sorting processing module 15 that supports the target sorting mode in the sorting task execution logic, and the read / write controller does not meet the preset mode conversion rules, the data exchange and loading storage module 14 forwards the current data to be sorted to the CLOS network converter for CLOS network mode conversion according to the task allocation result, and transmits the converted CLOS network data to the corresponding sorting processing module 15 for sorting processing.

[0078] The data exchange and loading storage module 14 is connected to the task allocator module 13 and the plurality of sorting processing modules 15 respectively, and is used to forward the currently unsorted data to the corresponding sorting processing module 15 according to the received control information.

[0079] Specifically, after receiving the control information transmitted by the task allocator module 13, the data exchange and loading storage module 14 first parses the key instructions contained in the control information (such as the identifier of the sorting processing module 15, data forwarding path indication, sorting mode conversion type, etc.); then, according to the parsing result, it forwards the current data to be sorted to the corresponding sorting processing module 15. Forwarding the current data to be sorted to the corresponding sorting processing module 15 according to the parsing result includes: if the control information indicates that no sorting mode conversion is required, the current data to be sorted is directly forwarded to the corresponding sorting processing module 15; if the control information indicates that a read / write control mode conversion or a CLOS network mode conversion is required, the current data to be sorted is first forwarded to the corresponding mode conversion module (read / write controller or CLOS network converter), and after the mode conversion is completed, the converted data is then forwarded to the corresponding sorting processing module 15.

[0080] In one embodiment of this application, the data exchange and loading storage module 14 is also connected to an external memory, responsible for data write-back and reloading operations with the external memory. Specifically, the data exchange and loading storage module 14 achieves bidirectional data interaction through its connection with the external memory: when external data needs to be called during the execution of the sorting task, the module reads memory data from the external memory (i.e., loads the required data) into the system for use by various hardware modules; when the target sorting task is completed, the module writes the final sorting result into memory (i.e., writes it back to the external memory) for storage, thereby achieving secure data retention and reuse.

[0081] In one embodiment of this application, as Figure 3 As shown, the sorting acceleration system also includes a mode conversion module 16; the mode conversion module 16 is connected to the data exchange and loading storage module; the mode conversion module 16 receives the current data to be sorted from the data exchange and loading storage module and performs mode conversion on it; the sorting processing module obtains the converted data and performs sorting processing; the mode conversion module 16 can be of the type of read / write controller or CLOS network converter.

[0082] In some optional implementations, when the mode conversion module 16 is a read / write controller, multiple read / write controllers are connected to the data exchange and loading storage module 14, and each read / write controller is connected to a corresponding sorting processing module 15. The read / write controller receives the currently unsorted data forwarded by the data exchange and loading storage module 14, performs read / write control mode conversion on the received data, converts the target sorting mode corresponding to the currently unsorted data to a predetermined sorting mode supported by the corresponding sorting processing module 15, ultimately obtains the corresponding read / write control conversion data, and transmits the read / write control conversion data to the corresponding sorting processing module 15.

[0083] In one embodiment of this application, each read / write controller includes a first storage bank and a second storage bank. The first storage bank and the second storage bank serve as data caches and read / write control carriers during the read / write control mode conversion process, providing hardware support for the read / write controller to complete the sorting mode conversion. They are used to temporarily cache and precisely control the current data to be sorted during the conversion process, so as to support the read / write controller in converting the target sorting mode corresponding to the current data to be sorted into a predetermined sorting mode supported by the corresponding sorting processing module 15.

[0084] It should be noted that the interface width of the first and second storage banks is half the width of the data to be sorted, ensuring that the total interface width of the first and second storage banks matches the width of the data to be sorted. This interface width design allows the dual storage banks to achieve parallel read and write operations without sacrificing total bandwidth, avoiding data transmission anomalies caused by interface width mismatch.

[0085] In some alternative implementations, such as Figure 4 As shown, the process by which each read / write controller switches the read / write control mode for the currently unsorted data forwarded by the data exchange and loading storage module 14 specifically includes the following steps:

[0086] Step S41: Logically divide the current data to be sorted according to a preset segmentation size to obtain multiple logically segmented data segments.

[0087] It should be noted that the number of elements that each sorting processing module 15 can process at one time (hereinafter referred to as N_harware for ease of description) can be the same or different, but preferably the N_harware of each sorting processing module 15 is in a multiple relationship. The preset segmentation size is related to the N_harware of the sorting processing module 15 corresponding to the read / write controller. The principle of segmentation is to ensure that the segmented data segments can be adapted to the single processing capacity of the corresponding sorting processing module 15. For example, it can be logically divided according to the size of N_harware / 2.

[0088] Step S42: Adjust the address order of the multiple logically segmented data segments according to a preset address adjustment order to obtain the logically segmented data segments with adjusted address order.

[0089] It should be noted that the preset address adjustment order is not randomly set, but rather matches the difference in element comparison distance between the target sorting mode corresponding to the current data to be sorted and the predetermined sorting mode of the sorting processing module 15 corresponding to the read / write controller. The core purpose is to utilize this difference to specifically adjust the address order of the logically segmented data segments, thereby achieving the conversion and adaptation from the target sorting mode to the predetermined sorting mode of the corresponding sorting processing module 15.

[0090] Step S43: Write the logically segmented data segments with adjusted address order into the first memory bank and the second memory bank respectively. By using parallel caching across dual memory banks, the efficiency of data storage and subsequent retrieval can be significantly improved, avoiding load saturation of a single memory bank. Furthermore, the independent storage structure of the dual memory banks facilitates subsequent adjustment of the address order based on the data's storage address, supporting the conversion from the target sorting mode to the predetermined sorting mode.

[0091] Step S44: According to the data reading order control instruction of the sorting network tree traversal module 12, data is read from the first storage and the second storage to obtain the logically segmented data segment after data reading.

[0092] It should be noted that the data reading order control instruction is generated by the sorting network tree traversal module 12 according to the sorting task execution logic. The reading process, according to the requirements of this instruction, ensures that the SWAP data pair corresponding to the read data (i.e. the element pair that the subsequent sorting processing module 15 needs to compare and exchange during the sorting process) is completely consistent with the SWAP data pair before the read / write control mode conversion, so as to ensure that the core comparison logic of the sorting task is not changed and to avoid the sorting result deviation due to the data reading order error.

[0093] Step S45: Perform data concatenation processing on the logically segmented data segments after data reading to obtain the read / write control conversion data. The concatenated data can be directly adapted to the predetermined sorting mode supported by the corresponding sorting processing module 15, and then transmitted to the corresponding sorting processing module 15 for subsequent sorting processing.

[0094] In some alternative implementations, such as Figure 5 As shown, the process of adjusting the address order of the multiple logically segmented data segments according to a preset address adjustment order to obtain logically segmented data segments with adjusted address order specifically includes the following steps:

[0095] Step S51: Obtain the target element comparison distance of the target sorting mode corresponding to the current data to be sorted and the predetermined element comparison distance of the predetermined sorting mode supported by the corresponding sorting processing module 15.

[0096] It should be noted that element comparison distance refers to the number of elements in the data sequence between two elements that need to be compared and swapped in a certain comparison swapping step of the sorting network. For example, a comparison distance of 4 means that the two elements in each comparison swapping pair in the current step are 4 positions apart. The target element comparison distance refers to the element comparison distance required by the target sorting pattern corresponding to the current data to be sorted; the predetermined element comparison distance refers to the element comparison distance supported by the sorting processing module 15.

[0097] Step S52: Based on the multiple relationship between the target element comparison distance and the predetermined element comparison distance, determine the sequence number interval of the logically segmented data segments that need address order adjustment in the logical partitioning sequence. The sequence number interval refers to the difference in sequence numbers between two logically segmented data segments that need address order adjustment in the logical partitioning sequence.

[0098] Step S53: According to the sequence number interval, adjust the address order of the logically segmented data segment that needs to be adjusted to obtain the logically segmented data segment after address order adjustment.

[0099] Specifically, according to the specified sequence number interval, logically segmented data segments that need address order adjustment are determined in the logical partitioning sequence, and their storage addresses are swapped in order to obtain logically segmented data segments with adjusted address order.

[0100] In some optional implementations, the sequence number interval of the logically segmented data segments requiring address order adjustment in the logical partitioning sequence is calculated using the following formula:

[0101] ; (Formula 1)

[0102] In formula 1, The interval is the sequence number; Compare the distances between the target elements corresponding to the target sorting pattern; Compare the distances between the predetermined elements corresponding to the predetermined sorting pattern.

[0103] It should be noted that Formula 1 above applies only when... Divide by This applies when the quotient is an integer. When the quotient is not an integer, the read / write controller cannot complete the read / write control mode conversion through address order adjustment. In this case, the system will automatically call the CLOS network converter for processing.

[0104] To facilitate understanding by those skilled in the art, the process of read / write control mode switching by address order adjustment of the read / write controller is illustrated below with reference to Examples 1 and 2. It should be specifically noted that this example is only a feasible implementation of read / write control mode switching by address order adjustment of the read / write controller and does not constitute a limitation of the present invention.

[0105] Example 1:

[0106] In this Example 1, the system has three sorting processing modules 15: P1 (with a predetermined element comparison distance of 1), P2 (with a predetermined element comparison distance of 2), and P3 (with a predetermined element comparison distance of 4). Each of the three sorting processing modules can process 8 elements at a time, N_harware. In this Example 1, the task allocator module 13 determines to convert the target sorting pattern with an element comparison distance of 8 into the predetermined sorting pattern with an element comparison distance of 4 supported by the P3 sorting processing module.

[0107] like Figure 6aAs shown, this illustrates the read / write control mode conversion required for the next round of sorting of the output data after the sorting module completes the current round of sorting. The target sorting mode corresponds to an element comparison distance of 8. This output data serves as the current data to be sorted in the next round of sorting. Figure 6b The example illustrates the specific process by which the output data after sorting by the sorting module (i.e., the current data to be sorted in the next round of sorting) is converted into a predetermined sorting pattern supported by the P3 sorting module via the read / write controller. Figure 6a In the example, the current unsorted data is divided into four logical segments according to the N_harware / 2 partitioning rule: Block1, Block2, Block3, and Block4. Figure 6b In this process, since the element comparison distance corresponding to the target sorting pattern is 8, and the element comparison distance of the predetermined sorting pattern supported by the P3 sorting module is 4, according to the aforementioned Formula 1, the sequence interval of the logically segmented data segments that need to have their address order swapped is 1. Therefore, before writing the data to RAM, the address order of Block 3 and Block 4 is swapped; then Block 1 and Block 4 are written to RAM0, and Block 2 and Block 3 are written to RAM1. During the data reading stage, for the data in RAM0, the data of Block 1 is read first, followed by the data of Block 4; for the data in RAM1, the data of Block 3 is read first, followed by the data of Block 2, to ensure that the SWAP data pair corresponding to the data after the read / write control mode conversion is completely consistent with the SWAP data pair corresponding to the data before the read / write control mode conversion; finally, the read data is concatenated and transmitted to the P3 sorting module for sorting processing. Figure 6b Block5, Block6, Block7, and Block8 represent another logical segment of data to be sorted. Their data partitioning logic and read / write control mode conversion are the same as those described above, and will not be repeated here.

[0108] Example 2:

[0109] In Example 2, the system has three sorting processing modules 15: P1 (with a predetermined element comparison distance of 1), P2 (with a predetermined element comparison distance of 2), and P3 (with a predetermined element comparison distance of 4). Each of the three modules can process 8 elements at a time, N_harware. In this example, the task allocator module determines to convert the target sorting pattern with an element comparison distance of 16 into the predetermined sorting pattern with a comparison distance of 4 supported by the P3 sorting module.

[0110] like Figure 7a As shown, this illustrates the read / write control mode conversion required for the target sorting pattern of the current data to be sorted. The element comparison distance for this target sorting pattern is 16. Figure 7b The example illustrates the specific process by which the data to be sorted is converted into a predetermined sorting pattern supported by the P3 sorting module through the read / write controller. Figure 7a In the example, the current unsorted data is divided into 8 logical segments according to the N_harware / 2 partitioning rule, namely Block1, Block2, Block3, Block4, Block5, Block6, Block7, and Block8. Figure 7b In this process, since the element comparison distance corresponding to the target sorting pattern is 16, and the element comparison distance of the predetermined sorting pattern supported by the P3 sorting processing module is 4, according to the aforementioned Formula 1, the sequence interval of the logical segmented data segments that need to have their address order swapped is 3. Therefore, before writing the data to RAM, the address order of Block2 and Block5, and Block4 and Block7 are swapped respectively. Then, according to the logical segmented data segment sequence in ascending order, Block1, Block2, Block3, and Block4 are written to RAM0, and Block5, Block6, Block7, and Block8 are written to RAM1. During the data reading stage, the read / write controller reads data from the dual RAMs according to the data usage order, and finally concatenates the read data before transmitting it to the P3 sorting processing module for sorting.

[0111] It should be noted that in Example 2, there is also a case where the data to be sorted transmitted to the read / write controller is data adjusted according to the depth-first traversal strategy rules of the sorting network tree traversal module 12, such as... Figure 7cThe diagram illustrates the specific process by which the current data to be sorted, adjusted according to the depth-first traversal strategy of the sorting network tree traversal module 12, is converted by the read / write controller into a predetermined sorting pattern supported by the P3 sorting processing module. In this case, the current data to be sorted received by the read / write controller is not arranged in the natural order of the logically segmented data segments (Block1, Block2, Block3, Block4, Block5, Block6, Block7, Block8), but rather in a depth-first order of Block1, Block2, Block5, Block6, Block3, Block4, Block7, Block8. During the data writing phase, the read / write controller writes Block1, Block3, Block5, and Block7 to RAM0 in ascending order of the logically segmented data segment sequence, and writes Block2, Block4, Block6, and Block8 to RAM1. Figure 7c In this process, Blocks 1 and 2, along with Blocks 3 and 4, occupy the same address area in RAM0 and RAM1. This is because when Blocks 3 and 4 are generated and ready to be written to RAM, Blocks 1 and 2 have already completed caching and been transferred for the next level of sorting, and their corresponding storage address space has been released. Blocks 3 and 4 can then reuse this storage address space. During the data reading phase, the read / write controller reads data from both RAMs according to the order in which the data is used. Finally, the read data is concatenated and transmitted to the P3 sorting module for sorting.

[0112] In some optional implementations, when the mode conversion module 16 is a CLOS network converter, the CLOS network converter is connected to the data exchange and loading storage module 14, and is used to receive the current unsorted data forwarded by the data exchange and loading storage module 14, and to perform CLOS network mode conversion on the received current unsorted data to obtain the corresponding CLOS network converted data; the CLOS network converter transmits the CLOS network converted data to the data exchange and loading storage module 14, and the data exchange and loading storage module 14 forwards the CLOS network converted data to the corresponding sorting processing module 15.

[0113] It should be noted that the CLOS network (also known as the Kloss network) is a multi-level non-blocking switching network structure, consisting of three levels of cross-connected switch matrices: input level, intermediate level, and output level. This application utilizes the flexible switching capability of the CLOS network to realize the mode conversion of complex data. In this application, the CLOS network converter serves as a high-order, backup mode conversion unit of the read / write controller. Its application scenarios mainly include: (1) When the target element comparison distance of the target sorting mode corresponding to the current data to be sorted is not an integer multiple of the predetermined element comparison distance of the predetermined sorting mode supported by the corresponding sorting processing module 15, the read / write controller cannot complete the read / write control mode conversion by adjusting the address order. At this time, the CLOS network converter is switched to perform the mode conversion; (2) When the target sorting task requires complex data sorting of the data to be sorted, such as the specific data arrangement required by certain special sorting algorithms, and the specific data arrangement differs greatly from the predetermined sorting mode inherently supported by the sorting processing module 15 in this system, exceeding the mode conversion capability range of the read / write controller, the CLOS network converter needs to complete the corresponding mode conversion.

[0114] In one embodiment of this application, the CLOS network converter, in addition to implementing the CLOS network mode conversion function, is also used to filter and rearrange the sorting results after the sorting processing module 15 has completed the sorting processing, and output the filtered and rearranged data as the target result.

[0115] It should be noted that this filtering and rearrangement function is mainly applied to small-scale TopK output scenarios. Specifically, when the target output size K is less than the number of elements N_hardware that the sorting module 15 can process at one time, the ordered data output by the sorting module 15 after sorting will contain K target output elements and (N_hardware-K) non-target redundant elements. In this case, it is not necessary to output all ordered elements completely. After receiving the sorting result, the CLOS network converter will filter the sorting result according to preset filtering rules (e.g., only retaining the first K smallest elements, only retaining the first K largest elements, or filtering target elements according to a preset threshold), and rearrange the filtered K target elements in order according to the preset output format. Finally, the filtered and rearranged K elements are output as the target result. In this way, the system does not need to output all ordered data completely, thereby reducing the data transmission volume and computational overhead of subsequent processing stages.

[0116] To facilitate understanding by those skilled in the art, the following is combined with Figure 8a and Figure 8bThe following example illustrates the function of the CLOS network converter in filtering and rearranging the sorted results after sorting by the sorting module 15. It should be specifically noted that this example is merely one feasible implementation of the filtering and rearranging function of the CLOS network converter and does not constitute a limitation of the present invention. Figure 8a As shown, this example demonstrates how the CLOS network converter filters and rearranges the Top 1 ranking results; for instance... Figure 8b As shown, this example demonstrates how the CLOS network converter filters and rearranges the Top 2 sorting results.

[0117] Multiple sorting processing modules 15, each supporting at least one predetermined sorting mode, are used to sort the received current data to be sorted according to the predetermined sorting mode they support, so as to complete the corresponding target sorting task.

[0118] Specifically, the sorting processing module 15 is the computing unit in this sorting acceleration system, responsible for performing the actual element comparison and swap operations. Each sorting processing module 15 integrates multiple comparators, which can perform parallel comparison and swapping of input data according to its supported predetermined sorting patterns (such as the element comparison connection relationship and element comparison distance corresponding to a certain level Step in the Bitonic sorting network).

[0119] In this embodiment, the input data sources of the sorting processing module 15 mainly include the following three cases: first, the current data to be sorted is directly forwarded by the data exchange and loading storage module 14 without mode conversion; second, the read / write control conversion data is transmitted after the read / write controller completes the read / write control mode conversion; and third, the CLOS network conversion data is forwarded by the data exchange and loading storage module 14 after the CLOS network converter completes the CLOS network mode conversion. After the sorting processing module 15 completes the sorting processing of the received data, it transmits the sorting result as the current data to be sorted to the data exchange and loading storage module 14 for subsequent processing according to the actual situation. The subsequent processing includes: continuing to the next level of sorting processing; transmitting to the CLOS network converter for filtering and rearrangement processing; and outputting as the final sorting result.

[0120] It should be noted that different sorting processing modules 15 can support different predetermined sorting modes. For example, some sorting processing modules 15 support a sorting mode with an element comparison distance of 2, some support a sorting mode with an element comparison distance of 4, and some support a sorting mode with an element comparison distance of 8, etc. The predetermined sorting modes supported by each sorting processing module 15 are predetermined during system design and recorded in the configuration information of the task allocator module 13 for querying and matching when the task allocator module 13 performs task allocation. Preferably, the element comparison distances of the predetermined sorting modes supported by each sorting processing module 15 are in a multiple relationship, so as to facilitate mode conversion by adjusting the address order of the read / write controller.

[0121] It is worth emphasizing that the sorting acceleration system 10 provided in this application, which supports dynamic scheduling and is compatible with multiple sorting network algorithms, effectively solves the limitations of existing sorting hardware through multi-module collaboration, dynamic scheduling, and address optimization, and achieves at least the following significant effects:

[0122] 1. It enables flexible switching of sorting modes to adapt to different data scales and task requirements, avoiding the adaptation problems caused by fixed hardware.

[0123] 2. It reduces redundant operations during data transmission, lowers bandwidth usage, and improves data processing efficiency;

[0124] 3. Supports multiple sorting algorithms, and can flexibly select the optimal sorting logic according to task requirements to ensure the accuracy and efficiency of sorting results;

[0125] 4. Through reasonable cache management and data path optimization, invalid data transmission is reduced, hardware computing power is fully utilized, and resource waste is avoided.

[0126] To better describe the specific implementation scheme of the sorting acceleration system, we will now combine... Figure 9The specific implementation is described below: Command decoder module 11 (corresponding to the Command decoder in the figure) receives the target sorting task command and determines the corresponding target sorting algorithm according to the target sorting task command; Sorting network tree traversal module 12 (corresponding to the Net TreeScheduler in the figure) generates the sorting task execution logic of the target sorting algorithm according to the sorting mode nodes and the dependencies between nodes of various pre-configured sorting network algorithms; Task assigner module 13 (corresponding to the Task in the figure) The router generates task allocation results according to the sorting task execution logic of the target sorting algorithm, the predetermined sorting modes of each sorting processing module 15 (corresponding to P1, P2, and P3 in the figure), and the load status of each sorting processing module 15, in accordance with preset allocation rules. The task allocation results include: if there is a sorting processing module 15 that supports the target sorting mode, then based on the load status of each sorting processing module 15, the sorting processing module 15 with the lowest current load is selected first to generate a directly allocated task allocation result; if there is no sorting processing module 15 that supports the target sorting mode, it is determined whether the sorting mode can be converted through the read / write controller. If the read / write controller meets the preset mode conversion rules, a task allocation result after conversion by the read / write controller is generated; if the read / write controller does not meet the preset mode conversion rules, a task allocation result after conversion by the CLOS network converter (corresponding to the CLOS network in the figure) is generated; the data exchange and load / store module 14 (corresponding to the Data Switch & Load / Store in the figure) generates a task allocation result after conversion by the CLOS network converter (corresponding to the CLOS network in the figure). The Unit (LSU) forwards the current data to be sorted to the corresponding sorting module 15 for sorting based on the received task allocation result, or forwards it to the corresponding read / write controller for read / write control mode conversion before transmitting it to the corresponding sorting module 15 for sorting, or forwards it to the CLOS network converter for CLOS network mode conversion before transmitting it to the corresponding sorting module 15 for sorting, and finally completes the corresponding target sorting task.

[0127] In summary, this invention provides a sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms. The system uses a command decoder module to parse user-issued target sorting task commands and determine the target sorting algorithm. A sorting network tree traversal module generates the execution logic for the target sorting algorithm based on pre-configured sorting mode nodes and inter-node dependencies for multiple sorting network algorithms. A task allocator module generates task allocation results as control information according to the sorting task execution logic, the predetermined sorting modes of each sorting processing module, and the load status of each sorting processing module, following preset allocation rules. A data exchange and loading / storage module forwards the currently unsorted data to the corresponding sorting processing module for sorting processing based on the control information. This invention improves the overall throughput and resource utilization of hardware sorting by integrating the management of sorting data and the sorting process, reducing the ineffective overhead of off-chip bandwidth, on-chip storage, and computing power, and overcoming the technical problems of poor hardware adaptability, resource waste, and idle computing power in traditional fixed sorting systems.

[0128] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0129] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A sorting acceleration system that supports dynamic scheduling and is compatible with multiple sorting network algorithms, characterized in that, include: The system includes a command decoder module, a sorting network tree traversal module, a task allocator module, a data exchange and loading / storage module, and multiple sorting processing modules; each sorting processing module supports at least one predefined sorting mode. The command decoder module is used to receive and parse the target sorting task command to obtain the identification information of the corresponding target sorting algorithm; The sorting network tree traversal module is connected to the command decoder module and is used to match the corresponding sorting task execution logic according to the identification information of the target sorting algorithm. The task allocator module is connected to the sorting network tree traversal module. It is used to generate task allocation results according to the sorting task execution logic of the target sorting algorithm, the predetermined sorting mode and load status of each sorting processing module, and according to the preset allocation rules. The task allocation results are then transmitted to the data exchange and loading storage module as control information. The data exchange and loading / storage module is connected to the task allocator module and the plurality of sorting processing modules respectively, and is used to forward the current data to be sorted to the corresponding sorting processing module according to the received control information; The plurality of sorting processing modules are used to sort the received current data to be sorted according to the predetermined sorting modes they support, so as to complete the corresponding target sorting task.

2. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 1, characterized in that, The sorting network tree traversal module pre-configures multiple sorting network algorithms, each with a corresponding network tree, and each network tree consists of multiple sorting pattern nodes and the dependencies between these nodes. The execution process of the sorting network tree traversal module includes: Based on the received identification information of the target sorting algorithm, the corresponding network tree is matched among a variety of pre-configured sorting network algorithms, and a depth-first traversal strategy with configurable maximum depth is used to traverse each sorting pattern node in the matched network tree. Based on the sorting pattern nodes obtained through traversal and the data dependencies between nodes, the sorting task execution logic of the target sorting algorithm is generated.

3. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 1 or 2, characterized in that, The system further includes a mode conversion module, which is connected to the data exchange and loading storage module. The mode conversion module receives the current data to be sorted from the data exchange and loading storage module and performs mode conversion on it. The sorting processing module obtains the converted data and performs sorting processing. The mode conversion module includes read / write controllers and / or Kloss network converters.

4. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 3, characterized in that, When the mode conversion module is a read / write controller, multiple read / write controllers are connected to the data exchange and loading storage module, and each read / write controller is connected to a sorting processing module. The read / write controller receives the current data to be sorted forwarded by the data exchange and loading storage module, performs read / write control mode conversion on the received current data to be sorted to obtain corresponding read / write control conversion data, and transmits the read / write control conversion data to the corresponding sorting processing module for sorting processing.

5. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 3, characterized in that, When the mode conversion module is a Kloss network converter; the Kloss network converter is connected to the data exchange and loading storage module, and is used to receive the current unsorted data forwarded by the data exchange and loading storage module, and to perform Kloss network mode conversion on the received current unsorted data to obtain the corresponding Kloss network converted data. The Kloss network converter transmits the Kloss network converted data to the data exchange and loading storage module, which then forwards the Kloss network converted data to the corresponding sorting processing module for sorting processing.

6. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 3, characterized in that, The task allocator module generates a task allocation result as control information according to the sorting task execution logic, the predetermined sorting mode of each sorting processing module, and the load status, following preset allocation rules; wherein, the preset allocation rules include: If there is a sorting processing module that supports the target sorting mode in the sorting task execution logic, the data exchange and loading storage module will forward the current data to be sorted directly to the corresponding sorting processing module for sorting processing according to the task allocation result. If there is no sorting processing module that supports the target sorting mode in the sorting task execution logic, and the read / write controller meets the preset mode conversion rules, the data exchange and loading storage module forwards the current data to be sorted to the corresponding read / write controller for read / write control mode conversion according to the task allocation result, and transmits the converted read / write control conversion data to the corresponding sorting processing module for sorting processing. If there is no sorting processing module that supports the target sorting mode in the sorting task execution logic, and the read / write controller does not meet the preset mode conversion rules, the data exchange and loading storage module forwards the current data to be sorted to the Kloss network converter for Kloss network mode conversion according to the task allocation result, and transmits the generated Kloss network converted data to the corresponding sorting processing module for sorting processing.

7. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 4, characterized in that, Each read / write controller includes a first storage bank and a second storage bank; The first storage bank and the second storage bank are used to cache and control the current data to be sorted during the read and write control mode conversion process, so as to support the read and write controller to convert the target sorting mode corresponding to the current data to be sorted into a predetermined sorting mode supported by the corresponding sorting processing module.

8. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 7, characterized in that, The process by which each read / write controller switches read / write control modes for the currently unsorted data forwarded by the data exchange and loading storage module includes: The current data to be sorted is logically divided according to a preset segmentation size to obtain multiple logically segmented data segments; The multiple logically segmented data segments are adjusted in address order according to a preset address adjustment order to obtain logically segmented data segments with adjusted address order. The logically segmented data segments with the address order adjusted are written into the first memory bank and the second memory bank respectively; According to the data reading order control instruction of the sorting network tree traversal module, data is read from the first storage and the second storage to obtain the logically segmented data segment after data reading; The logically segmented data segments after the data is read are concatenated to obtain the read / write control conversion data.

9. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 8, characterized in that, The process of adjusting the address order of the plurality of logically segmented data segments according to a preset address adjustment order to obtain logically segmented data segments with adjusted address order includes: Get the target element comparison distance of the target sorting pattern corresponding to the current data to be sorted and the predefined element comparison distance of the predefined sorting pattern supported by the corresponding sorting processing module; Based on the multiple relationship between the target element comparison distance and the predetermined element comparison distance, determine the sequence interval of the logically segmented data segment that needs address order adjustment in the logical partitioning sequence. Based on the specified sequence number interval, the addresses of the logically segmented data segments that require address order adjustment are adjusted to obtain the logically segmented data segments with adjusted address order.

10. The sorting acceleration system supporting dynamic scheduling and compatible with multiple sorting network algorithms according to claim 5, characterized in that, The Kloss network converter is also used to filter and rearrange the sorting results after the sorting module has completed the sorting process, and output the filtered and rearranged data as the target result.

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