Circuit for reducing the number of iterations of a pipelined cordic and method of implementation thereof

Abstract

The application relates to a circuit for reducing the number of CORDIC pipeline iterations and a method for implementing the same. The method combines multiple iterations in the same clock margin safety window at the initial stage of iteration by accurately evaluating the cumulative delay of each stage of iteration, realizes dynamic redivision of the physical boundary of the pipeline, breaks through the mapping limit of the single-stage pipeline, effectively reduces the total iteration number of the system, and significantly reduces the data processing delay of the system end to end. The dynamic division method of the pipeline boundary based on delay accumulation takes the critical path delay of the maximum bit width pipeline stage as a global constraint condition, dynamically evaluates and optimizes the insertion position of the register through a greedy strategy, fully transforms the early idle timing margin under the premise of not reducing the highest working frequency of the system, solves the problem of serious imbalance of the timing between the pipeline stages, and significantly reduces the data processing delay of the system end to end while further compressing the chip area and dynamic power consumption.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, and relates to a circuit and its implementation method for reducing the number of CORDIC pipeline iterations. Background Technology

[0002] The Coordinate Rotation Digital Computation (CORDIC) algorithm replaces complex multiplication with simple shifting and addition / subtraction to implement various elementary and transcendental functions, and is widely used in digital signal processing, communication, and embedded systems. In hardware implementation, standard CORDIC algorithms are typically mapped into pipelined architectures to achieve high throughput, and traditional designs often use a uniform maximum bit width configuration across all stages of the pipeline. To address the hardware area redundancy issue caused by a uniform bit width, Figure 1 A pipelined CORDIC architecture based on progressively increasing bit width is presented. This architecture employs an external multiplication compensation strategy and an integer initialization method, which frees the early stages of iteration from the constraint of the full word length.

[0003] Taking a progressively increasing CORDIC architecture with a target maximum bit width of 8 bits, 6 iterations, and an initial input decimal width of 0 bits as an example, the critical paths of its first three pipeline stages are as follows: Figure 2 As shown. Although the above-described pipelined CORDIC architecture based on progressively increasing bit width effectively reduces the hardware area, the non-uniform increase in data bit width at each iteration stage results in extremely uneven allocation of combinational logic resources to each pipeline stage. This leads to the following significant drawbacks in practical engineering applications: (1) Severe timing imbalance between stages, resulting in a significant waste of timing margin. In digital circuits, the critical path of a single-stage pipeline is mainly determined by the propagation delay of the adder carry chain, and the delay of each stage is linearly positively correlated with the bit width. The critical paths of each stage of a CORDIC pipeline with progressively increasing bit width are as follows: Figure 2 As shown by the red dashed line, in the early stages of iteration (such as Stage 1 and Stage 2), due to the narrow data bit width, the adder carry propagation chain is extremely short, and its critical path latency is significantly lower than that of subsequent iteration stages that reach the maximum bit width. If the system clock cycle is determined by the longest bit width iteration stage, the early narrow bit width pipeline stages will generate a huge timing slack. The existing architecture forces the allocation of a full clock cycle for these short-latency operations, resulting in serious idle and wasted time resources.

[0004] (2) The pipeline stages are lengthy, resulting in excessive data processing latency. Although the existing bit-width incrementing architecture reduces the bit width of a single-stage pipeline register, the system still needs to forcibly connect N pipeline stages to complete N algorithm iterations. This results in high latency from input to output, and these dense inter-stage pipeline registers still bring significant dynamic switching power consumption. Summary of the Invention

[0005] To address the timing imbalances and redundant pipeline stages in the existing CORDIC architecture with progressively increasing bit widths, this invention proposes a circuit and its implementation method to reduce the number of pipeline CORDIC iterations.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a circuit implementation method for reducing the number of CORDIC pipeline iterations is provided, including the following steps: Step 1: Obtain the path delay constant, total number of iterations N, and target maximum bit width for each basic logic gate in the standard cell library used for pipelined CORDIC hardware design with progressively increasing bit width.

[0007] Step 2: Determine the maximum allowable path delay based on the path delay constant of each basic logic gate and the target maximum bit width.

[0008] Step 3: Initialize the current accumulation delay, set the initial pipeline register insertion position set to an empty set, set the current pipeline stage to the first pipeline stage, and set the current iteration index. n =1, .

[0009] Step 4: Use a delay-accumulation-based dynamic pipeline boundary partitioning method to determine the set of pipeline register insertion positions. The dynamic pipeline boundary partitioning method uses the maximum allowable path delay as a global clock cycle constraint and dynamically evaluates the cumulative delay of the current pipeline stage iteration using a greedy strategy. When the condition is met, the current iteration index is stored in the set of pipeline register insertion positions. n is incremented by 1, the current pipeline stage is updated to the next pipeline stage, and the next iteration begins, until n>N, thus obtaining the set of pipeline register insertion positions.

[0010] Step 5: Based on the set of pipeline register insertion positions, reconstruct the pipelined CORDIC architecture with progressively increasing bit width to obtain a pipelined CORDIC circuit with reduced iteration stages.

[0011] On the other hand, a circuit for reducing the number of CORDIC pipeline iterations is also provided, which is designed using the above-described method for implementing the circuit for reducing the number of CORDIC pipeline iterations.

[0012] One of the above technical solutions has the following advantages and beneficial effects: The circuit and its implementation method for reducing the number of CORDIC pipeline iterations described above, by accurately evaluating the cumulative delay of each iteration, merges multiple iterations within the same clock margin safety window in the early stage of the iteration, realizing the dynamic redrawing of the pipeline physical boundary, breaking through the single-stage pipeline mapping limitation, effectively reducing the total number of system iterations, and thus significantly reducing the end-to-end data processing latency of the system; the pipeline boundary dynamic partitioning method based on delay accumulation, using the critical path delay of the maximum bit width pipeline stage as a global constraint, dynamically evaluates and optimizes the insertion position of the register through a greedy strategy, and fully utilizes the early idle timing margin without reducing the system's highest operating frequency, solving the problem of severe timing imbalance between pipeline stages, thereby significantly reducing the end-to-end data processing latency of the system while further compressing chip area and dynamic power consumption. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a CORDIC pipeline architecture based on progressively increasing bit width in one embodiment; Figure 2 This is a schematic diagram of the first three critical paths of a CORDIC system with progressively increasing bit width in one embodiment. Figure 3 This is a flowchart illustrating a circuit implementation method for reducing the number of CORDIC pipeline iterations in one embodiment. Figure 4 This is a schematic diagram of the critical path after merging the first two levels in one embodiment; Figure 5 This is a flowchart illustrating the logic for calculating the pipeline register insertion position in one embodiment. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0017] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0018] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0019] The circuit implementation method for reducing the number of pipeline CORDIC iterations proposed in this application solves the timing imbalance and pipeline redundancy problems existing in the existing CORDIC architecture with progressively increasing bit width. It breaks the mapping method of single-stage pipeline single iteration, and merges multiple iterations that are within the same clock margin safety window in the early stage of the iteration by accurately evaluating the cumulative delay of each stage of the iteration. It aims to transform the idle early timing margin into a reduction in the total number of system iterations by dynamically redrawing the physical boundaries of the pipeline, thereby significantly reducing the end-to-end data processing latency of the system while further compressing the chip area and dynamic power consumption.

[0020] In one embodiment, such as Figure 3 As shown, a circuit implementation method for reducing the number of CORDIC pipeline iterations is provided, which may include the following processing steps 1 to 5: Step 1: Obtain the path delay constant, total number of iterations N, and target maximum bit width for each basic logic gate in the standard cell library used for pipelined CORDIC hardware design with progressively increasing bit width.

[0021] Specifically, the pipelined CORDIC architecture based on progressively increasing bit width, such as... Figure 1 As shown, this architecture establishes a progressively increasing bit width model. The effective data bit width in the early stages of the CORDIC iteration increases with the number of iterations. It grows in two stages until it reaches the system's preset maximum bit width.

[0022] Based on this characteristic, the architecture refactors the traditional unified maximum bit width pipeline into a step-by-step bit width increasing architecture. In implementation, the hardware only needs to instantiate pipeline registers and adders that can cover the current effective bit width, so that the hardware scale increases step by step in the early stages of iteration, thereby eliminating unnecessary area overhead in the early stages at the physical level.

[0023] In a standard CORDIC hardware iteration, a single-stage data path mainly consists of shifters, inverters, XOR gates (used for sign bit extension or addition / subtraction control), and adders. Since shift operations are typically implemented via hardware wiring, there is no physical gate delay; therefore, the maximum delay in a single iteration is... It mainly depends on the control logic composed of inverters and XOR gates and the carry chain propagation of the adder.

[0024] Step 2: Determine the maximum allowable path delay based on the path delay constant of each basic logic gate and the target maximum bit width.

[0025] Step 3: Initialize the current accumulation delay, set the initial pipeline register insertion position set to an empty set, set the current pipeline stage to the first pipeline stage, and set the current iteration index. n =1, .

[0026] Step 4: Use a delay-accumulation-based dynamic pipeline boundary partitioning method to determine the set of pipeline register insertion positions. The dynamic pipeline boundary partitioning method uses the maximum allowable path delay as a global clock cycle constraint and dynamically evaluates the cumulative delay of the current pipeline stage iteration using a greedy strategy. When the condition is met, the current iteration index is stored in the set of pipeline register insertion positions. n is incremented by 1, the current pipeline stage is updated to the next pipeline stage, and the next iteration begins, until n>N, thus obtaining the set of pipeline register insertion positions.

[0027] Specifically, dynamically optimizing inter-stage timing balance greatly improves timing resource utilization: In traditional incremental bit-width architectures, the narrow data bit width and short adder carry propagation chain in the early stages of iteration generate a huge timing margin. Forcing the allocation of a full clock cycle leads to severe waste of time resources and inter-stage timing imbalance. This invention designs a pipeline boundary dynamic partitioning method based on delay accumulation, using the critical path delay of the maximum bit-width pipeline stage... Using global constraints, a greedy strategy is employed to dynamically evaluate and optimize the insertion position of registers. This method fully utilizes early idle timing margins without reducing the system's maximum operating frequency, thus resolving the problem of severe timing imbalance between pipeline stages.

[0028] Breaking through the limitations of single-stage pipeline mapping, this method significantly reduces end-to-end processing latency: Existing architectures use N-stage pipelines to complete N algorithm iterations, resulting in excessively high processing latency from input to output. This approach breaks away from the traditional fixed mapping method by accurately evaluating the cumulative latency of each iteration. This approach merges multiple iterations that occur within the same clock margin safety window during the initial iteration phase across different stages. This dynamic redrawing of the pipeline's physical boundaries effectively reduces the total number of iterations in the system, thereby significantly reducing end-to-end data processing latency.

[0029] Step 5: Based on the set of pipeline register insertion positions, reconstruct the pipelined CORDIC architecture with progressively increasing bit width to obtain a pipelined CORDIC circuit with reduced iteration stages.

[0030] Specifically, by streamlining inter-stage registers, hardware area and dynamic power consumption are further reduced: In existing architectures, dense inter-stage registers not only occupy physical space but also introduce significant dynamic switching power consumption. Based on the physical mapping rules of this invention, within the reconstructed merging stage, each iteration is directly cascaded with pure combinational logic, and no flip-flops for timing isolation are instantiated between stages. This strategy successfully translates the ample timing margin of the preceding stages into a significant reduction in the number of hardware inter-stage registers, effectively reducing system dynamic power consumption while further compressing chip area overhead.

[0031] The circuit implementation method described above for reducing the number of CORDIC pipeline iterations achieves dynamic redrawing of the pipeline physical boundary by accurately evaluating the cumulative delay of each iteration stage and merging multiple iterations within the same clock margin safety window in the early stage of the iteration. This breaks through the single-stage pipeline mapping limitation, effectively reducing the total number of system iteration stages and thus significantly reducing the end-to-end data processing latency. The pipeline boundary dynamic partitioning method based on delay accumulation uses the critical path delay of the maximum bit-width pipeline stage as a global constraint. It dynamically evaluates and optimizes the insertion position of the register through a greedy strategy. Without reducing the system's highest operating frequency, it fully utilizes the early idle timing margin, solving the problem of severe timing imbalance between pipeline stages. This further reduces chip area and dynamic power consumption while significantly reducing the end-to-end data processing latency.

[0032] In one embodiment, step 2 includes: determining the maximum allowable path delay based on the path delay constant of each basic logic gate and the target maximum bit width. ; in, Indicates the maximum allowed path delay. Indicates inverter delay, Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay from carry input to sum output. Indicates the maximum bit width of the target.

[0033] In one embodiment, the current accumulated delay in step 3 is: ; in, Indicates the current accumulated delay. This indicates the initial input decimal place width. Indicates inverter delay, Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay between the carry input and the sum output.

[0034] In one embodiment, step 4 includes: for the current iteration index n, calculating the delay parameter of the effective bit width of the current pipeline stage corresponding to the current iteration; determining the additional delay introduced when adding the current iteration operation to the existing combinational logic path based on the delay parameter of the current pipeline stage and the delay of the existing combinational logic path; summing the current accumulated delay and the additional delay to obtain the total delay of the current pipeline stage; if the total delay of the current pipeline stage is not greater than the maximum allowed path delay, then there is no need to insert a pipeline register, and the current accumulated delay is updated to the total delay of the current pipeline stage; if the total delay of the current pipeline stage is greater than the maximum allowed path delay, then the current iteration index is updated to the maximum allowed path delay. Store the current accumulated delay in the pipeline register insertion position set, reset the current accumulated delay to the delay of the current iteration, increment the current iteration index n by 1, update the current pipeline stage to the next pipeline stage, and continue to execute the next iteration; until the current iteration index n>N, the pipeline register insertion position set is obtained.

[0035] Specifically, to accurately assess the cumulative delay of each iteration, this method first... Additional delay introduced during merging in the next iteration Modeling, Figure 4 This demonstrates how, in a progressively increasing bit-width architecture, the first and second iterations are merged into the same pipeline (i.e., Figure 4 The gate-level circuit schematic of stage 1. Figure 4 The red dashed line in the middle marks the longest timing delay path within this combinational logic block. In the cascaded state, the total delay of the merged logic is the full delay of the first stage, plus the delay of an XOR gate and the propagation delay required by the signal in the remaining full adders in the second stage. The propagation delay of the second-stage full adder chain before this point is completely hidden within the operation time of the first stage and is not added to the critical path delay. Therefore, the first... Additional delay introduced during merging in the next iteration Quantified as: The min function in the formula ensures that when the maximum value is reached in the later stage of the iteration (n-1), the additional delay is replaced by a fixed delay for a single iteration. Through the aforementioned precise timing modeling, this invention accurately identifies the timing margins hidden in early iterations, thus providing solid and reliable hardware theoretical support for the subsequent algorithm's aggressive "cross-stage merging" and register position optimization.

[0036] In one embodiment, for the current iteration index n, the delay parameters of the effective bit width of the current pipeline stage corresponding to the current iteration are calculated, including: based on the bit width increment model, calculating the minimum effective decimal bit width that the current pipeline stage must retain according to the current iteration index n and the initial input decimal bit width; determining the effective bit width of the current iteration according to the minimum effective decimal bit width and the target maximum bit width; and calculating the delay parameters of the current iteration stage according to the effective bit width of the current iteration and the path delay constant of each basic logic gate.

[0037] Specifically, definition For the first The minimum decimal places that must be retained in the next iteration are calculated using the following formula: ,in The number of significant decimal places in the initial coordinates. This indicates the current iteration number. After adding a sign bit and an integer bit, the effective total bit width for the nth iteration is... Since the data bit width cannot grow indefinitely, but is limited by the target maximum bit width initially set by the system. This is related to the target accuracy. Therefore, when the accumulated effective total bit width... Exceeding the target maximum bit width Subsequently, lower-order data will be considered invalid and truncated, while the bit width remains constant. Therefore A more precise calculation formula is: .

[0038] In one embodiment, the expression for the delay parameter in the current iteration phase is: ; in, This represents the delay parameter for the current iteration phase. Indicates inverter delay, Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay from carry input to sum output. Indicates the effective bit width of the current iteration.

[0039] Specifically, in the CORDIC architecture based on progressively increasing bit width, for an effective bit width of... The The delay of a single iteration in the next iteration The calculation formula is shown in the expression for the delay parameter in the current iteration phase.

[0040] The hardware physical mapping relationship of the expression for the delay parameter in the current iteration phase is as follows: This characterizes the fundamental delays in CORDIC rotation direction determination and operand sign processing. Adder carry chain delay: This method uses a full adder chain structure for modeling. Among them, This indicates the delay in the first full adder generating the initial carry; This indicates that the carry signal is in the middle. The delay accumulated during propagation in a full adder; This indicates the delay in the highest-order bit full adder calculating the summation result. The calculation formula shows that the delay at each stage is related to the bit width. They exhibit a linear positive correlation. Furthermore, due to the iterative bit width of the increasing bit width architecture... It will increase with the number of iterations The critical path delay increases with the increase of [variable name], therefore the critical path delay of each iteration increases with [variable name]. Rise step by step.

[0041] In one embodiment, the effective bit width of the current iteration is: ; in, Indicates the effective bit width of the current iteration. Indicates the maximum bit width of the target. Indicates the minimum number of significant decimal places.

[0042] In one embodiment, based on the latency parameter of the current pipeline stage and the latency of the existing combinational logic path, the additional latency introduced when adding the current iteration operation to the existing combinational logic path is determined as follows: ; in, Indicates additional delay, This represents the delay parameter for the current iteration phase. Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay from carry input to sum output, and n represents the current iteration index.

[0043] In one specific embodiment, to accurately find the optimal pipeline register insertion position and maximize the utilization of timing margin in the early stages of iteration without reducing the system's highest operating frequency, this invention designs a dynamic pipeline boundary partitioning method based on delay accumulation. This method uses the critical path delay of the maximum bit-width pipeline stage as a global constraint and dynamically evaluates the cumulative delay of each iteration stage using a greedy strategy, as shown in the pseudocode of Algorithm 1 in Table 1.

[0044] Table 1. Pseudocode for Algorithm 1

[0045] To more intuitively illustrate the automatic calculation process of the pipeline register insertion position in the embodiments of the present invention, please refer to... Figure 5 . Figure 5 The flowchart illustrates the logic for calculating the pipelined register insertion position. The specific steps for calculating the pipelined register insertion position include: (1) Obtain input parameters.

[0046] The system acquires initial physical parameters and target parameters for hardware pipeline design. The input parameters include: total number of iterations. N Target maximum bit width And the path delay constants of each basic logic gate in the standard cell library (including inverter delay). XOR gate delay And the propagation delay between the ports of the full adder: the delay from data input to carry output. Carry input to carry output delay Delay from carry input to sum output ).

[0047] (2) Perform initialization operations Based on the input parameters, the system calculates and initializes the global threshold and accumulated variables, specifically including: maximum allowed path delay. The calculation formula is as follows: At the same time, initialize the current accumulated delay. The calculation formula is as follows: (in (Initialize the input decimal width). Initialize a set of register insertion positions. and set it to an empty set. .

[0048] (3) Perform iterative delay evaluation and register location determination The system targets iterative indexes (in The value range is from 1 to ) Perform a loop traversal. For each given iteration index... Perform the following sub-steps: 1) Calculate the bit width of the current iteration.

[0049] Based on the bit-width increment model, calculate the minimum significant decimal places that must be retained. And based on this, determine the effective bit width of the current iteration. .

[0050] 2) Calculate the delay parameters for the current iteration stage.

[0051] Calculate the delay of the current iteration .

[0052] Calculate the additional latency introduced when adding the current iteration operation to an existing combinational logic path. .

[0053] 3) Determine and update the register status.

[0054] The system will accumulate the current delay. With the newly added additional delay Summing is performed, and this sum is compared with the maximum allowed path delay threshold. Comparison: If This indicates that the accumulated delay of the current logical path has not yet violated timing constraints, and there is no need to insert a register here. The system updates the accumulated delay, that is, updates the accumulated delay to the sum of the current accumulated delay and the newly added additional delay, and continues to execute the next iteration. If This indicates that the accumulated delay of the current logical path has exceeded the timing constraints, and the combinational logic path must be truncated, and the current iteration index must be changed. Store in the set of register insertion positions In, that is Then the current accumulated delay will be... Reset to the delay of the current iteration And continue to execute the next iteration.

[0055] (4) Output the calculation results.

[0056] When all are completed After the first iteration, the loop ends. The system outputs the final set of register insertion positions. The set records all the iteration index values, indicating which operational stages need to be physically interposed with pipeline registers during the actual hardware circuit generation.

[0057] The set of register insertion positions output by Algorithm 1 The CORDIC pipeline architecture, characterized by progressively increasing bit width, is restructured. This involves refactoring the set of register insertion locations. any element in Its physical mapping rule is: only in the first... A set of pipelined registers for timing isolation is inserted before the combinational logic of the next iteration. Based on this mapping rule, the reconstructed CORDIC circuit exhibits the following structural characteristics: In the early stages of system iteration, there exists a merged pipeline stage, formed by physically merging multiple iterations. Within the merged stage, each iteration is directly cascaded with pure combinational logic, without instantiating any flip-flops between stages. Data continuously passes through multiple iterations of logic within this clock cycle. In the later stages of system iteration, as the effective data bit width approaches or reaches the target bit width... The inherent delay of a single iteration Approaching At this point, the algorithm automatically triggers continuous truncation, and the circuit degenerates into a conventional pipeline structure with one pipeline stage and one iteration.

[0058] To further verify and illustrate the application effect of the algorithm described in this invention in practical digital integrated circuit design, an example is given below with a specific set of parameters. Taking the target bit width as an example... For 32-bit systems, the total number of iterations is [number missing]. For 30 iterations, the initial input decimal width is [number of decimal places]. Taking bit 0 as an example, the logic gate delay is set to It is 0.1ns. It is 0.12 ns. It is 0.18 ns. It is 0.08 ns. The value is 0.15 ns. Inputting the above parameters into the pipelined register insertion position calculation algorithm provided by this invention, the system automatically outputs the set of register insertion positions as follows: Based on this set, the original 30-iteration continuous combinational logic was restructured and divided into 26 pipeline stages. More specifically, the algorithm did not frequently insert registers in the early stages of iteration; the first to fourth iterations were cascaded within the same pipeline stage, with the first-stage register only inserted before the fifth iteration. This is because, in the progressively increasing bit-width architecture, the effective bit-width of the early iterations is extremely small, the adder chain involved in a single iteration is extremely short, and the accumulation latency is much lower than... Therefore, it is safe to hardware cascade multi-stage iterative logic without timing violations. Subsequently, the 5th and 6th iterations are combined into a second pipeline stage, and a register is inserted before the 7th iteration. From the 7th iteration to the 30th iteration, the algorithm forcibly inserts a pipeline register before each iteration. This is because the effective data bit width has gradually expanded and is approaching the target full bit width (32 bits), and the carry propagation of the long bit width data causes the delay of a single complete iteration to approach the system's allowed timing limit. A single-stage, single-stream structure must be adopted to meet the timing convergence requirement.

[0059] It should be understood that, although the above Figure 3 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, the above... Figure 3 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0060] In one embodiment, a circuit for reducing the number of CORDIC pipeline iterations is provided, which is designed using the circuit implementation method for reducing the number of CORDIC pipeline iterations described above.

[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A circuit implementation method for reducing the number of CORDIC pipeline iterations, characterized in that, Including the following steps: Step 1: Obtain the path delay constant, total number of iterations N, and target maximum bit width of each basic logic gate in the standard cell library used for pipelined CORDIC hardware design with progressively increasing bit width; Step 2: Determine the maximum allowable path delay based on the path delay constant of each basic logic gate and the target maximum bit width; Step 3: Initialize the current accumulation delay, set the initial pipeline register insertion position set to an empty set, set the current pipeline stage to the first pipeline stage, and set the current iteration index. n =1, ; Step 4: Determine the set of pipeline register insertion positions using a delay accumulation-based dynamic pipeline boundary partitioning method. This method uses the maximum allowable path delay as a global clock cycle constraint and dynamically evaluates the accumulated delay of the current pipeline iteration using a greedy strategy. When the condition is met, the current iteration index is stored in the pipeline register insertion position set. Then, n is incremented by 1, the current pipeline stage is updated to the next pipeline stage, and the next iteration begins, continuing until n > N, thus obtaining the pipeline register insertion position set. Step 5: Based on the set of pipeline register insertion positions, reconstruct the pipelined CORDIC architecture with progressively increasing bit width to obtain a pipelined CORDIC circuit with reduced iteration stages.

2. The circuit implementation method for reducing the number of CORDIC iterations in a pipeline according to claim 1, characterized in that, Step 2 includes: determining the maximum allowable path delay based on the path delay constant of each basic logic gate and the target maximum bit width. in, Indicates the maximum allowed path delay. Indicates inverter delay, Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay from carry input to sum output. Indicates the maximum bit width of the target.

3. The circuit implementation method for reducing the number of CORDIC iterations in a pipeline according to claim 1, characterized in that, The current accumulated delay in step 3 is: in, Indicates the current accumulated delay. This indicates the initial input decimal place width. Indicates inverter delay, Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay between the carry input and the sum output.

4. The circuit implementation method for reducing the number of CORDIC iterations in a pipeline according to claim 1, characterized in that, Step 4 includes: For the current iteration index n, calculate the delay parameter of the effective bit width of the current pipeline corresponding to the current iteration; Based on the latency parameters of the current pipeline stage and the latency of the existing combinational logic path, determine the additional latency introduced when adding the current iteration operation to the existing combinational logic path; The current accumulated delay is summed with the additional delay to obtain the current total pipeline stage delay. If the current pipeline stage total delay is not greater than the maximum allowed path delay, then there is no need to insert a pipeline register; the current accumulated delay is updated to the current pipeline stage total delay. If the current total pipeline delay is greater than the maximum allowed path delay, then the current iteration index will be adjusted. Store the current accumulated delay in the pipeline register insertion position set and reset it to the delay of the current iteration. Increment the current iteration index n by 1, update the current pipeline stage to the next pipeline stage, and continue to execute the next iteration; until the current iteration index n>N, and obtain the set of pipeline register insertion positions.

5. The circuit implementation method for reducing the number of CORDIC iterations in a pipeline according to claim 4, characterized in that, For the current iteration index n, calculate the delay parameters of the effective bit width of the current pipeline corresponding to the current iteration, including: Based on the bit-width incrementing model, the minimum significant decimal width that the current pipeline stage must retain is calculated according to the current iteration index n and the initial input decimal width. The effective bit width of the current iteration is determined based on the minimum significant decimal bit width and the target maximum bit width; The delay parameters for the current iteration stage are calculated based on the effective bit width of the current iteration and the path delay constant of each basic logic gate.

6. The circuit implementation method for reducing the number of CORDIC iterations in a pipeline according to claim 5, characterized in that, The delay parameter for the current iteration phase is: in, This represents the delay parameter for the current iteration phase. Indicates inverter delay, Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay from carry input to sum output. Indicates the effective bit width of the current iteration.

7. The circuit implementation method for reducing the number of CORDIC iterations in a pipeline according to claim 5, characterized in that, The effective bit width of the current iteration is: in, Indicates the effective bit width of the current iteration. Indicates the maximum bit width of the target. Indicates the minimum number of significant decimal places.

8. The circuit implementation method for reducing the number of CORDIC iterations in a pipeline according to claim 4, characterized in that, Based on the latency parameters of the current pipeline stage and the latency of the existing combinational logic path, the additional latency introduced by adding the current iteration operation to the existing combinational logic path is determined as follows: in, Indicates additional delay, This represents the delay parameter for the current iteration phase. Indicates XOR gate delay, This indicates the delay from data input to carry output. This indicates the delay from carry input to carry output. This indicates the delay from carry input to sum output, and n represents the current iteration index.

9. A circuit for reducing the number of CORDIC iterations in a pipeline, characterized in that, The circuit for reducing the number of CORDIC pipeline iterations is designed using the circuit implementation method for reducing the number of CORDIC pipeline iterations as described in any one of claims 1 to 8.

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