Method, apparatus and device for vectorizing conditional loop execution

Abstract

The application discloses a method, device and equipment for vector execution of conditional loop, and relates to the technical field of computers. The method comprises the following steps: obtaining a target conditional loop structure; controlling data channels in an active state in an active mask to participate in vector execution; generating an exit mask and a truncated mask or a mask based on the exit mask in the case that the data channels meet an exit condition; updating the active mask based on the truncated mask or the mask; and continuing to execute the target conditional loop structure based on the updated active mask until a loop end condition is met. By introducing a cross-iteration propagation mechanism of the active mask, the data channels meeting the exit condition continuously remain in an inactive state in subsequent iterations, thereby reducing invalid calculation and side effect propagation and ensuring that the vector execution result is consistent with the original conditional loop semantics.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a vectorized execution method, apparatus, and device for conditional loops. Background Technology

[0002] In existing compiler optimization techniques, multiple scalar iterations within a loop are typically mapped to single vector operations to improve the execution efficiency of loop structures. For loop structures with a fixed number of iterations and consistent control flow, existing vectorization techniques can achieve parallel execution quite well.

[0003] However, for conditional loop structures that include conditional branching or early exit semantics, the execution states of different data lanes may diverge during the loop execution, resulting in differences in the exit timing of each data lane. This makes it difficult to directly perform efficient vectorized execution of such loop structures.

[0004] In existing technologies, although some vector execution mechanisms support mask-based conditional execution, the relevant masks are usually only effective within the current iteration cycle, making it difficult to achieve continuous propagation of the exit state across multiple iterations. Therefore, during the vectorization of conditional loops, inactive data channels may still participate in subsequent vector calculations or memory accesses, leading to problems such as invalid calculations, abnormal memory accesses, side effect propagation, or inconsistent execution semantics.

[0005] Therefore, how to achieve cross-iteration dynamic convergence control based on exit state and improve the vectorized execution efficiency of conditional loops while ensuring the semantic consistency of the original execution of conditional loops has become an urgent technical problem to be solved. Summary of the Invention

[0006] This invention provides a vectorized execution method for conditional loops. While ensuring the consistency of the original execution semantics of the conditional loop, it realizes the vectorized execution of conditional loops containing conditional branches and / or early exit semantics, thereby improving the efficiency of vectorized execution of conditional loops.

[0007] A first aspect provides a vectorized execution method for conditional loops, the method comprising: obtaining a target conditional loop structure, the target conditional loop structure indicating a loop structure that satisfies vectorized execution conditions, and the target conditional loop structure including conditional branches and / or early exit semantics; controlling active data channels in an active mask to participate in the vectorized execution of the target conditional loop structure, wherein the active mask is used to identify the execution state of the corresponding data channel; during the vectorized execution, detecting exit conditions for the data channel, and generating an exit mask if there is a data channel that satisfies the exit conditions; generating a masking mask or a truncated mask based on the exit mask; updating the active mask based on the masking mask or the truncated mask; and continuing to execute the target conditional loop structure based on the updated active mask, so that the data channels that satisfy the exit conditions remain inactive in subsequent iterations until the loop termination condition is met. The active mask is used to identify whether the corresponding data channel participates in or does not participate in the vectorized execution.

[0008] This application achieves dynamic convergence control of conditional loops during vector execution by constructing an activity mask propagation mechanism based on exit states. During the vectorized execution of the conditional loop structure, an activity mask that can propagate across iterations is introduced, dynamically representing the execution state of each data channel. Combined with exit condition detection and activity mask updates, data channels that meet the exit condition remain inactive in subsequent iterations, thus achieving vectorized execution of the conditional loop structure while maintaining the semantic consistency of the original execution. Compared to traditional execution schemes that only support mask control for the current iteration, this application can continuously constrain the subsequent execution of the corresponding data channel after detecting an exit condition, thereby avoiding invalid computation and supporting early termination of the vector loop.

[0009] One possible implementation, whereby the above-mentioned generation of a masking mask or truncation mask based on the exit mask is specifically implemented as follows: A masking generation operation is performed on the exit mask to generate a masking mask or truncation mask used to restrict the corresponding data channel from participating in subsequent execution; wherein, the exit mask is used to identify the data channel that meets the exit condition in the current iteration. By constructing a collaborative relationship between the exit mask, masking mask, or truncation mask and the activity mask, each data channel can independently exit the subsequent iteration execution process according to its own execution state, thereby achieving fine-grained dynamic convergence control.

[0010] Another possible implementation is that the above masking generation operation can be specifically implemented as follows: determine the position of the first data channel that meets the exit conditions based on the exit mask; generate a truncation mask based on the position of the first data channel that meets the exit conditions, so as to keep the data channels before the position in an active state and mask the data channels after the position from participating in subsequent execution.

[0011] Another possible implementation, whereby updating the activity mask based on a masking mask or a truncated mask, can be specifically implemented as follows: A combined update operation is performed between the masking mask or truncated mask and the current activity mask to generate an updated activity mask. This updated activity mask is used to continuously constrain the vectorized execution of the corresponding data channel in subsequent iterations, thereby achieving cross-iteration propagation of the activity state. By combining and updating the activity mask, the exit state is continuously propagated across multiple iterations, ensuring that exited data channels remain inactive in subsequent execution processes, thus achieving global activity state maintenance across iterations.

[0012] In another possible implementation, the combined update operation includes a logical AND operation.

[0013] Another possible implementation is that the above loop termination condition includes at least one of the following: all data channels corresponding to the active mask are inactive; the loop of the target condition loop structure reaches the loop boundary.

[0014] Another possible implementation is that obtaining the target conditional loop structure described above can be specifically implemented as follows: obtaining the conditional loop structure; performing vectorized validity analysis on the conditional loop structure to obtain the target conditional loop structure that satisfies the vectorized execution conditions. By performing vectorized validity analysis on the conditional loop structure, target conditional loop structures that satisfy the vectorized execution conditions can be selected, thereby avoiding execution exceptions or program semantic errors caused by performing vectorized processing on loop structures that do not meet the vectorization conditions.

[0015] Another possible implementation is that the above vectorized legality analysis includes at least one of the following: cross-iteration dependency analysis; memory access safety analysis; early exit semantic analysis; control flow branch analysis.

[0016] Another possible implementation, the vectorized execution method of the conditional loop provided in this application, further includes: before vectorizing the execution of the target conditional loop structure, initializing the data channel corresponding to the activity mask to an active state.

[0017] Another possible implementation, the vectorized execution method for conditional loops provided in this application, further includes: after the target conditional loop structure ends, performing scalar processing or tail vector processing on the remaining unprocessed data elements; wherein, the scalar processing refers to processing only one data element at a time, and the vector length of the tail vector processing is less than the vector length during vectorized execution.

[0018] Secondly, a vectorized execution device for conditional loops is provided, the device comprising: an acquisition module, an execution control module, an exit detection module, a mask processing and cross-iteration state propagation module, and a dynamic convergence execution module.

[0019] The acquisition module is used to acquire the target conditional loop structure, which includes conditional branching and / or early exit semantics.

[0020] An execution control module is used to control the data channels in the active state of the activity mask to participate in the vectorized execution of the target conditional loop structure, wherein the activity mask is used to identify the execution state of the corresponding data channel.

[0021] An exit detection module is used to detect exit conditions for the data channel during the vectorized execution process, and generate an exit mask if there is a data channel that meets the exit conditions.

[0022] The mask processing and cross-iteration state propagation module is used to generate a masking mask or a truncated mask based on the exit mask, and update the activity mask based on the masking mask or the truncated mask.

[0023] The dynamic convergence execution module is used to continue executing the target conditional loop structure based on the updated activity mask, so that the data channel that meets the exit condition remains inactive in subsequent iterations until the loop termination condition is met.

[0024] The vectorized execution apparatus for conditional loops provided in the second aspect is used to execute the vectorized execution method for conditional loops provided in the first aspect or any possible implementation of the first aspect. The corresponding technical effects can be found in the relevant description in the first aspect above, and will not be repeated here.

[0025] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a vectorized execution method of a conditional loop as described above.

[0026] Fourthly, embodiments of this application provide a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a vectorized execution method for a conditional loop as described above.

[0027] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements a vectorized execution method for conditional loops as described above.

[0028] In a sixth aspect, embodiments of this application provide a chip including at least one processor, the processor being configured to execute program instructions to implement the vectorized execution method of conditional loops as described in any of the implementations of the first aspect above.

[0029] The solutions provided in aspects three through six above are used to implement the method provided in aspect one above, and their specific implementations will not be described in detail here. The technical effects corresponding to any implementation method of the solutions provided in aspects three through six above can be found in the technical effects corresponding to any implementation method in aspect one above, and will not be described in detail here.

[0030] It should be noted that any of the possible implementations of any of the above aspects can be combined, provided that the solutions do not contradict each other. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the architecture of a computing system provided in an exemplary embodiment of this application; Figure 2 This is a flowchart of a vectorized execution method for a conditional loop provided in an exemplary embodiment of this application; Figure 3 This is a flowchart of a vectorized execution method for a conditional loop provided in an exemplary embodiment of this application; Figure 4 This is a schematic diagram of a vectorized execution system architecture for conditional loops provided in an exemplary embodiment of this application; Figure 5 This is a flowchart of a vectorized execution process of a conditional loop provided in an exemplary embodiment of this application; Figure 6This is a schematic diagram of the structure of a vectorized execution device for a conditional loop provided in an exemplary embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this application; Figure 8 This is a schematic diagram of the structure of a chip system provided in an exemplary embodiment of this application. Detailed Implementation

[0033] In the embodiments of this application, in order to clearly describe the technical solutions of the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different. The technical features described by "first" and "second" have no sequential or size order.

[0034] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner to facilitate understanding.

[0035] In the embodiments of this application, at least one can also be described as one or more, and multiple can be two, three, four or more, and this application does not impose any restrictions.

[0036] Furthermore, the network architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0037] It should be noted that the information (including but not limited to device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the subject or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0038] In existing compiler optimization techniques, loop vectorization primarily targets loop scenarios with a fixed number of iterations and a regular control flow structure, improving execution efficiency by mapping multiple iterations to single vector operations. However, for conditional loop structures containing conditional branches or early exit semantics, existing techniques still have significant shortcomings in vectorization processing. For example, the loop body of a conditional loop structure contains conditional judgments based on data relevance; the loop may terminate early when a specific condition is met (such as break, return, etc.); and there may be inconsistencies in control flow between iterations.

[0039] To achieve loop vectorization, the industry typically employs several methods to vectorize conditional loop structures. The following is a brief description of several commonly used methods in the industry.

[0040] Method 1: For conditional loop structures with complex control flow or premature exit semantics, when the compiler cannot guarantee semantic equivalence after vectorization, the industry typically chooses to abandon vectorization and retain the loop in scalar execution. That is, dependency analysis and control flow analysis are performed on the loop structure. When a break, return, or data-related conditional branch is detected in the loop, it is determined to be "unsafe to vectorize," thus maintaining the original scalar execution path.

[0041] This method is simple to implement and can guarantee the semantic correctness of the program, but it cannot utilize vector processing units, resulting in limited performance improvement.

[0042] Method 2: For some conditional loop structures, the industry typically uses predication techniques to achieve vectorized processing. Specifically, by converting the conditional judgments in the conditional loop structure into a vector mask, all data channels corresponding to the conditional loop structure execute the vector instructions simultaneously. The mask controls whether each data channel participates in the result write-back or memory access. That is, the early exit semantics in the conditional loop structure are achieved by selectively applying the mask.

[0043] In this approach, each data channel typically executes under a unified control flow, with a mask controlling whether results are written back. However, for conditional loop structures containing early exit semantics, certain iterations should terminate execution immediately after the early exit condition is met. This approach can only control the effectiveness of a single instruction and cannot express the semantics of "a data channel remaining inactive throughout all subsequent iterations," thus making it difficult to correctly map early exit behavior.

[0044] Method 3: For partially conditional loop structures, the industry can also achieve vectorization through loop structure reconstruction. For example, the original loop can be split into multiple sub-loops; the vectorizable parts can be processed independently; and the remaining parts can be executed using scalars. This type of method usually includes: loop prologue, vectorized main loop, and loop epilogue.

[0045] This approach can balance vectorization efficiency and program correctness to some extent. However, optimization through loop decomposition (prologue / vector loop / eplogue, etc.) typically relies on the following prerequisites: clear loop boundaries, statically analyzeable exit conditions, and relatively simple control flow structure. Moreover, the unpredictable loop termination position and inconsistent exit behaviors of different data channels make this type of method difficult to apply and may even introduce additional control complexity.

[0046] In summary, existing technologies struggle to achieve efficient vectorized execution of conditional loop structures containing conditional branches or early exit semantics while ensuring the semantic correctness of the conditional loop structure itself. This is particularly true in vector processing architectures supporting parallel execution of SIMD (Single Instruction Multiple Data) or SIMT (Single Instruction Multiple Threads) protocols. The exit behaviors of different data channels may differ, making it difficult for traditional vector execution mechanisms based on single-round mask control to continuously propagate the exit state across multiple iterations. This can easily lead to problems such as invalid computation, abnormal memory access, side effect propagation, and inconsistent execution semantics.

[0047] Based on this, this application provides a vectorized execution scheme for conditional loops. This involves obtaining the target conditional loop structure; controlling the active data channels in the active mask to participate in the vectorized execution of the target conditional loop structure; detecting exit conditions for data channels during vectorized execution and generating an exit mask if a data channel meets the exit condition; generating a masking mask or truncated mask based on the exit mask and updating the active mask based on the masking mask or truncated mask; and continuing to execute the target conditional loop structure based on the updated active mask, so that data channels meeting the exit condition remain inactive in subsequent iterations until the loop termination condition is met. This application achieves dynamic convergence control of conditional loops during vectorized execution by constructing an active mask propagation mechanism based on the exit state. During the vectorized execution of the conditional loop structure, an active mask that can propagate across iterations is introduced, dynamically representing the execution state of each data channel. Combined with exit condition detection and active mask updates, data channels meeting the exit condition remain inactive in subsequent iterations, thus achieving vectorized execution of the conditional loop structure while ensuring the semantic consistency of the original execution of the conditional loop. Compared to traditional execution schemes that only support mask control for the current iteration, this application can continuously suppress the subsequent execution of the corresponding data channel after detecting the exit condition, thereby avoiding invalid calculations and supporting the early termination of vector loops.

[0048] The solutions provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0049] The solution provided in this application can be applied to Figure 1 An illustrated computing system. (e.g.) Figure 1 As shown, the computing system includes: electronic device 100.

[0050] In some embodiments, when executing the vectorized execution method of the conditional loop of this application, the execution subject may be a processor in the electronic device 100. The processor may be specifically implemented as at least one of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), and a tensor processing unit (TPU), but is not limited thereto. The embodiments of this application do not specifically limit this.

[0051] In some embodiments, the processor supports the RISC-V Vector Extension (RVV) instruction set and is capable of performing data channel control operations based on an active mask.

[0052] Specifically, the electronic device 100 acquires the target conditional loop structure and controls the data channels with active masks in an active state to participate in the vectorized execution of the target conditional loop structure. During the vectorized execution, an exit condition is detected for each data channel, and an exit mask is generated if a data channel that meets the exit condition exists. A masking mask or a truncated mask is generated based on the exit mask, and the active mask is updated based on the masking mask or truncated mask. The target conditional loop structure continues to be executed based on the updated active mask, so that the data channels that meet the exit condition remain inactive in subsequent iterations until the loop termination condition is met, and the execution result is obtained. For a detailed implementation, please refer to the description in the following embodiments.

[0053] It should be noted that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0054] Figure 2 A flowchart illustrating a vectorized execution method for a conditional loop provided in an exemplary embodiment of this application is shown. This embodiment uses this method to be executed by an electronic device. The electronic device can be... Figure 1 The electronic device 100 is shown in the diagram.

[0055] like Figure 2 As shown, the vectorized execution method of this conditional loop includes the following steps.

[0056] Step 202: Obtain the target conditional loop structure.

[0057] The target conditional loop structure indicates a conditional loop structure that satisfies the vectorized execution conditions; that is, the target conditional loop structure refers to a conditional loop structure that satisfies the vectorized execution conditions. The target conditional loop structure includes conditional branching and / or early exit semantics.

[0058] In some embodiments, the target conditional loop structure is obtained as follows: The conditional loop structure is obtained; a vectorized validity analysis (also known as vectorized execution judgment) is performed on the conditional loop structure to obtain the target conditional loop structure that satisfies the vectorized execution conditions. That is, before vectorizing the conditional loop structure, it is first determined whether the conditional loop structure can be vectorized. If the conditional loop structure can be vectorized, it is executed. If the conditional loop structure cannot be vectorized, it is not executed.

[0059] Among them, the conditional loop structure is used to indicate a loop structure with conditional branching and / or early exit semantics.

[0060] Early exit semantics refers to the use of specific statements to forcibly terminate the entire loop or skip the remaining part of the current iteration and proceed to the next iteration during the looping process of a conditional loop structure.

[0061] Vectorized legality analysis refers to the determination of whether a conditional loop structure can be executed in a vectorized manner. Optionally, vectorized legality analysis includes one or more of the following: cross-iteration dependency analysis, memory access safety analysis, early exit semantic analysis, and control flow branch analysis, but is not limited thereto, and the embodiments of this application do not specifically limit it.

[0062] Optionally, the statements corresponding to early exit semantics include, but are not limited to, the `break` statement, the `continue` statement, or the `return` statement, and this application embodiment does not specifically limit them. The `break` statement is used to indicate the complete termination of the entire loop and to continue execution of the next statement outside the loop. The `continue` statement is used to indicate skipping all subsequent statements in the current iteration and immediately starting the next loop condition evaluation or entering the next iteration. The `return` statement is used to indicate the immediate termination of the execution of the current function, ceasing further execution of the current function, and returning the specified value.

[0063] Specifically, the process of performing vectorized legality analysis on conditional loop structures is as follows: the electronic device extracts information from the conditional loop structure to obtain the loop metadata. Based on the loop metadata, vectorized legality analysis is performed to obtain the target conditional loop structure that satisfies the vectorized execution conditions.

[0064] Among them, loop metadata is used to describe the loop structure in the conditional loop structure.

[0065] Optionally, the loop metadata includes one or more of the following: loop iteration variables, boundary conditions, early exit paths, or early exit condition expressions, but is not limited thereto, and the embodiments of this application do not specifically limit this.

[0066] Loop iteration variables are variables that change within the loop. For example, `i` changes in each iteration. Boundary conditions are constraints that terminate the loop. For example, `i`... <N。

[0067] Vectorized execution conditions are constraints used for vectorized validity analysis.

[0068] Optionally, the vectorized execution conditions include one or more of the following: there are no cross-iteration dependencies; there are no abnormal memory access operations during the loop; there are no abnormal memory access operations that could cause inconsistencies in execution semantics, but are not limited thereto, and the embodiments of this application do not specifically limit this.

[0069] Cross-iteration dependency refers to whether the current iteration depends on the result of the previous iteration.

[0070] The vectorized execution method for conditional loops provided in this application analyzes the vectorization validity of the conditional loop structure to filter out target conditional loop structures that meet the vectorization execution conditions, thereby enabling vectorized execution of the target conditional loop structures that can be vectorized. Through vectorization validity analysis, the conditional loop structure can be initially screened, ensuring smooth vectorized execution and avoiding program errors caused by attempting to vectorize a conditional loop structure that does not support vectorized execution.

[0071] Step 204: Control the active data channels in the active mask to participate in the vectorized execution of the target conditional loop structure; during the vectorized execution, detect the exit conditions for the data channels, and generate an exit mask if there are data channels that meet the exit conditions.

[0072] The activity mask is used to identify whether a data channel participates in or does not participate in vectorized execution. For example, the activity mask can be represented by 0 / 1. When the activity mask of a data channel is 1, it indicates that the data channel can participate in vectorized execution. Conversely, when the activity mask of a data channel is 0, it indicates that the data channel cannot participate in vectorized execution. It should be noted that using 0 / 1 to represent the activity mask is only an exemplary implementation method. This application does not specifically limit the form of the activity mask. Furthermore, it is not limited to the fact that the activity mask of a data channel represents that the data channel can participate in vectorized execution when it is 1; the activity mask of a data channel can also represent that the data channel can participate in vectorized execution when it is 0. The representation of the activity mask can be set according to the actual situation, and this application does not specifically limit it.

[0073] Masking or truncation masks are used to restrict the participation of corresponding data channels in subsequent iterations. In other words, after generating a masking or truncation mask, data channels marked as inactive by the corresponding mask will no longer participate in subsequent vectorized execution.

[0074] Specifically, during the vectorized execution of the target conditional loop structure by the electronic device, the data channel with the control activity mask in an active state participates in the vectorized execution of the target conditional loop structure. During the vectorized execution, the exit condition is detected for the data channel.

[0075] In one possible implementation, during vectorized execution, an exit mask is generated if a data channel meeting the exit conditions exists. Based on the exit mask, a masking mask or a truncation mask is then generated.

[0076] The exit mask is used to identify the data channel that meets the exit conditions in the current iteration.

[0077] The electronic device performs a mask generation operation on the exit mask to generate a mask or truncation mask used to restrict the corresponding data channel from participating in subsequent execution. The mask generation operation includes: when generating the truncation mask, determining the position of the first data channel that meets the exit condition based on the exit mask, and generating a truncation mask based on the position to block the data channels after the position from participating in subsequent execution.

[0078] Specifically, when generating the truncation mask, based on the position of the exit mask, the position corresponding to the first data channel that meets the exit condition is located, and the active mask of the data channels before the first exit mask is retained as active, thus generating the truncation mask. Specifically, when a data channel meets the exit condition, to maintain consistency with scalar execution semantics, it is necessary to prohibit data channels after the corresponding exit position from continuing to participate in subsequent iterations. Therefore, a truncation mask can be generated based on the position of the first data channel that meets the exit condition, so that data channels after that position remain inactive in subsequent iterations. If a truncation mask is not generated, and subsequent data channels continue to participate in the loop, then the data channels after the truncation mask will execute the loop an extra time, which may not have occurred in the first place.

[0079] Optionally, when determining the first exit mask in this iteration, a vector first-position matching instruction can be used to return the position of the first exit mask. When generating a truncated mask based on the exit mask, a prefix mask generation instruction can be used to generate a mask where positions before the exit mask are active and positions after the exit mask are inactive, thus generating a truncated mask.

[0080] For example, the target conditional loop structure is shown below.

[0081] For (int i = 0; i <N;i++){ If (a[i]==0) break; b[i] = 1 / a[i]; } Assume the vector length is 4, meaning that 4 data elements are processed each time vectorization is performed. The values ​​of a[i] are [5,0,2,0].

[0082] During iteration, the active mask for each data channel is [1,1,1,1]. After iteration, data channel 0: a[0]=5, b[0]=0.2; data channel 1: a[1]=0, satisfying the exit condition; data channel 2: a[2]=2, b[2]=0.5; data channel 3: a[3]=0, satisfying the exit condition. Since the calculation results of data channel 1 and data channel 3 both satisfy the exit condition, the generated exit mask is [0,1,0,1]. When generating the truncated mask, based on the position of the exit mask, the first exit mask in this iteration is inverted, and the active mask of the data channel before the first exit mask is kept as active, generating the truncated mask, which is [1,0,0,0]. In subsequent iterations, only data channel 0 continues to participate in the loop, and the other data channels no longer participate in the loop.

[0083] The vectorized execution method for conditional loops provided in this application introduces an activity mask control mechanism during vector execution, enabling loop structures with conditional branching and / or early exit semantics to achieve vectorized execution without disrupting the original program semantics. Compared to traditional vectorized methods applicable only to rule-based loops, the vectorized execution method for conditional loops provided in this application significantly expands the applicability of vectorized execution loops and improves the support capability of electronic devices for complex control flow programs. Furthermore, by constructing a collaborative relationship between exit masks, truncation masks, and activity masks, each data channel can independently exit the iterative calculation process based on its own execution state, thereby achieving fine-grained dynamic convergence control. Compared to traditional schemes that require waiting for all data channels to complete or employ scalar backoff, this application significantly reduces invalid execution paths and improves vector execution efficiency.

[0084] Step 206: Generate a masking mask or a truncation mask based on the exit mask, and update the active mask based on the masking mask or the truncation mask.

[0085] Specifically, after obtaining the truncated mask, a combined update operation is performed on the current active mask and the masking mask or truncated mask to generate an updated active mask, thereby enabling cross-iteration propagation of the execution state of each data channel. The updated active mask represents the data channels that are still allowed to participate in vectorized execution during subsequent iterations.

[0086] The activity mask is persisted across different iterations and participates in subsequent vector execution control, thereby enabling the cross-iteration propagation of the exit state. In other words, once a data channel meets the exit condition, the corresponding data channel will remain inactive in subsequent iterations and will no longer participate in subsequent vectorized execution.

[0087] Optionally, the combined update operation includes a logical AND operation.

[0088] In some embodiments, in the data channels participating in vectorized execution, the active mask of other data channels following the data channel corresponding to the truncated mask is modified to an inactive state.

[0089] For example, the active mask of the data channel in this iteration is [1,1,1,1], the resulting truncation mask is [1,0,0,0], and the updated active mask is [1,0,0,0].

[0090] The vectorized execution method for conditional loops provided in this application achieves continuous propagation of the exit state across multiple iterations by combining and updating the activity mask, ensuring that exited data channels remain inactive throughout subsequent execution. This method overcomes the limitation of traditional masks only taking effect in a single execution round, achieving consistent global state maintenance across iterations and thus guaranteeing the correct execution of complex conditional loops. Furthermore, this application determines the position of the first data channel that meets the exit condition by probing the execution position of the exit mask, and generates a truncated mask accordingly, thereby achieving overall shielding of subsequent data channels. This mechanism can accurately simulate the "termination upon encountering an exit" semantics (early exit semantics) in scalar execution, further reducing unnecessary computational overhead while ensuring execution correctness.

[0091] Step 208: Continue executing the target conditional loop structure based on the updated activity mask, so that the data channel that meets the exit condition remains inactive in subsequent iterations until the loop termination condition is met.

[0092] The loop termination condition is used to indicate the constraint condition of the loop structure that terminates the execution of the target condition.

[0093] Optionally, the loop termination condition includes: all data channels corresponding to the active mask are in an inactive state, or the loop boundary condition corresponding to the target condition loop structure is reached, but it is not limited thereto, and the embodiments of this application do not specifically limit it.

[0094] The vectorized execution method for conditional loops provided in this application effectively avoids side effects such as invalid memory access, anomaly propagation, and erroneous write-backs because inactive data channels are continuously masked during vector execution. Compared to traditional speculative execution or vector execution methods without masking control, this application significantly improves the stability and security of the vector execution process.

[0095] In some embodiments, the vectorized execution of the target conditional loop structure is terminated when all data channels corresponding to the active mask are inactive, or when the loop boundary condition corresponding to the target conditional loop structure is met. After the target conditional loop structure ends, scalar processing or tail vector processing is performed on the remaining unprocessed data elements.

[0096] Scalar processing refers to processing only one data element at a time. The vector length for tail vector processing is shorter than the vector length during vectorized execution.

[0097] When dealing with unprocessed data elements remaining during the vectorized execution process, a scalar processing approach is used. For each unprocessed data element, only one data element is processed in each iteration until all remaining data elements are processed.

[0098] When using the tail vector processing method to process the remaining unprocessed data elements during the vectorization process, the remaining data elements can be processed in a single step by adjusting the vector length.

[0099] The vectorized execution method for conditional loops provided in this application detects the activity mask state and can immediately trigger the termination of the vector loop when all data channels have completed calculation, thereby avoiding the continuation of invalid iterations. This mechanism not only reduces the number of dynamic instructions executed but also releases processor resources in advance, improving the overall system throughput.

[0100] In summary, the technical solution provided in this application achieves dynamic convergence control of conditional loops during vector execution by constructing an activity mask propagation mechanism based on exit states. During the vectorized execution of the conditional loop structure, an activity mask that can propagate across iterations is introduced, dynamically representing the execution state of each data channel. Combined with exit condition detection and activity mask updates, data channels that meet the exit condition remain inactive in subsequent iterations, thus achieving vectorized execution of the conditional loop structure while ensuring the semantic consistency of the original execution of the conditional loop. Compared to traditional execution schemes that only support single-round mask control, this application can continuously suppress the subsequent execution of the corresponding data channel after detecting an exit condition, thereby avoiding invalid computation and supporting early termination of the vector loop.

[0101] Furthermore, this application significantly reduces redundant overhead in the processor's vector execution process by reducing invalid computations, suppressing side effects, and supporting early termination. Especially in scenarios involving irregular data flows or complex conditional branches, this application effectively improves vector unit utilization, thereby enhancing the overall processor execution efficiency and energy efficiency.

[0102] Furthermore, before executing the target conditional loop structure in a vectorized manner, the vectorized execution state also needs to be initialized.

[0103] like Figure 3 As shown, the vectorized execution method of this conditional loop also includes step 203.

[0104] Step 203: Before executing the target conditional loop structure in vectorized form, set all the activity masks corresponding to the target conditional loop structure to the active state.

[0105] Specifically, before entering the vectorized loop execution, the vector execution state can be initialized, including: (1) Activity mask initialization: initialize the activity mask corresponding to the current valid data channel to the active state; (2) Dynamic vector length configuration: configure the vector length corresponding to the current iteration according to the number of remaining data elements to be processed; (3) Execution state initialization: initialize the loop control variables and related vector registers to establish the running state required for subsequent iteration execution.

[0106] The vectorized execution method for conditional loops provided in this application pre-marks valid data channels using an activity mask and sets the activity masks of all valid data channels to an active state. This allows for unified processing of vector operations of different lengths, avoiding interference from uninitialized or invalid data channels in the calculation results. The activity mask enables dynamic masking of completed or invalid data channels during loop execution, facilitating the processing of remaining elements (such as tail value processing) or conditional execution without needing to split into scalar loops, thus improving the efficiency of vectorized processing.

[0107] The above embodiments mainly describe in detail the vectorized execution method of conditional loops. The following will describe in detail the system architecture of the vectorized execution of conditional loops that implements the vectorized execution method of conditional loops.

[0108] like Figure 4 The diagram shows a schematic of the vectorized execution system architecture for conditional loops. This architecture includes: a loop feature analysis and evaluation module, an execution context initialization module, a controlled vector execution and side effect suppression module, a masking and cross-iteration state propagation module, a dynamic convergence control and termination determination module, and a result consistency and tail processing module.

[0109] 1. Cyclic Feature Analysis and Evaluation Module.

[0110] The loop feature analysis and evaluation module is used to perform vectorized legality analysis on conditional loop structures to obtain target conditional loop structures that meet the vectorized execution conditions.

[0111] Specifically, the loop feature analysis and evaluation module analyzes the loop structure within conditional loop structures, identifies loops containing conditional branches and / or early exit semantics, and extracts loop iteration variables, boundary conditions, and exit condition expressions. It also analyzes cross-iteration data dependencies and potential memory access risks to determine the feasibility of vectorized execution. This module passes the analysis results as configuration information to the execution context initialization module.

[0112] In some embodiments, the loop feature analysis and evaluation module includes: a semantic parsing submodule, a dependency analysis submodule, and a speculative execution security evaluation submodule.

[0113] The semantic parsing submodule identifies early exit semantics in conditional loop structures, including `break`, `return`, or other control transfer paths, and extracts the corresponding conditional expressions. The dependency analysis submodule detects cross-iteration data dependencies in conditional loop structures to determine the legality of vectorized execution. The speculative execution safety assessment submodule identifies potential unsafe memory access operations in loops and generates corresponding side effect suppression strategies to ensure memory access safety during vectorized execution.

[0114] 2. Execute the context initialization module.

[0115] The execution context initialization module is used to establish a unified execution context before entering vectorized execution.

[0116] Specifically, before entering vectorized execution, the execution context initialization module initializes the activity mask, making the activity masks of all data channels active, configuring the vector length according to the vector execution environment, initializing the vector register and loop control variables, and then passes the initialized activity mask and vector length to the controlled vector execution and side effect suppression module.

[0117] In some embodiments, the execution context initialization module includes: an activity mask configuration unit, a vector length control unit, and a state initialization unit.

[0118] The activity mask configuration unit initializes the activity mask and sets it to a fully active state to identify the initial set of data channels participating in execution. The vector length control unit dynamically configures the effective vector length according to the vector execution environment to adapt to different iteration scales. The state initialization unit initializes the vector register, scalar control variables, and loop counter.

[0119] 3. Controlled vector execution and side effect suppression module.

[0120] The controlled vector execution and side effect suppression module is used to ensure the semantic correctness of the program during vectorized execution.

[0121] Specifically, this module is used to execute vectorized execution instructions under the constraint of an active mask. That is, all vector operations are controlled by the active mask, and only active data channels participate in the execution. Memory access operations are executed in a controlled manner to suppress abnormal or illegal access caused by inactive data channels. Write-back operations are masked to avoid side effects caused by invalid data channels. During vectorized execution, this module generates an exit mask based on the current loop body calculation result and passes the exit mask to the mask processing and cross-iteration state propagation module.

[0122] In some embodiments, the controlled vector execution and side effect suppression module includes: a masked controlled execution unit, a controlled memory access unit, and a side effect masking unit.

[0123] The mask-controlled execution unit executes vector instructions under the constraints of the active mask, ensuring that only active data channels participate in the computation. The controlled memory access unit constrains memory access operations that may cause anomalies or out-of-bounds access, suppressing abnormal or illegal access from inactive data channels. The side effect shielding unit controls write-back behavior based on the active mask, blocking the impact of invalid data channels on the storage system.

[0124] Alternatively, controlled memory access operations can be implemented using masked memory access or exception-suppressed memory access instructions.

[0125] 4. Masking and cross-iteration state propagation module.

[0126] The mask processing and cross-iteration state propagation module is used to achieve vectorized dynamic convergence of conditional loops through a truncated mask generation and cross-iteration propagation mechanism based on the exit position.

[0127] Specifically, the mask processing and cross-iteration state propagation module is the core of this embodiment. It is used to achieve dynamic convergence of the conditional loop through a mask truncation and cross-iteration propagation mechanism based on the exit position. After receiving the exit mask from the controlled vector execution and side effect suppression module, it performs a position detection operation (e.g., using a first-order matching logic circuit) based on the input exit mask to determine the position of the first data channel that meets the exit condition. A truncated mask is generated based on the exit position (e.g., using a prefix mask generation logic circuit). A combined update operation is performed on the truncated mask and the activity mask of the previous iteration to generate an updated activity mask, thereby achieving continuous cross-iteration propagation of the execution state of each data channel. Specifically, the combined update operation is used to merge the exit state of the current iteration with the activity state of previous iterations, ensuring that data channels that have triggered exit conditions remain inactive in subsequent iterations. The updated activity mask represents the set of data channels still participating in execution and gradually converges as the iteration progresses.

[0128] In some embodiments, the mask processing and cross-iteration state propagation module includes: an exit mask receiving unit, a position detection and truncation generation unit, and a mask cumulative update unit.

[0129] The exit mask receiving unit receives the exit mask generated in the current iteration. The position detection and truncation generation unit performs position detection on the exit mask to determine the location of the first data channel that meets the exit conditions, generates a truncation mask based on that location, and outputs the corresponding exit location index for use by subsequent modules.

[0130] Optionally, the position detection operation and truncation mask generation can be implemented using vector instructions.

[0131] The mask cumulative update unit is used to combine and update the truncated mask with the historical activity mask to achieve cross-iteration propagation of the execution state of the data channel.

[0132] Optionally, the updated activity mask has the following characteristics: data channels that have triggered exit conditions remain inactive in subsequent iterations; it supports the continuous accumulation of exit states in multiple iterations; and the set of active data channels gradually converges as the iteration progresses.

[0133] 5. Dynamic convergence control and termination determination module.

[0134] The dynamic convergence control and termination determination module is used to control the vector loop execution process.

[0135] Specifically, the dynamic convergence control and termination determination module is used to control the cyclic execution process according to the mask state control vector. It receives activity state information from the mask processing and cross-iteration state propagation module, detects the state of the active mask in real time, and generates a termination trigger signal when all data channels are detected to be inactive or the cycle boundary conditions are met. Simultaneously, this dynamic convergence control and termination determination module is also used to send a continue execution control signal to the controlled vector execution module when the termination conditions are not met, thus enabling continuous advancement of the cyclic iteration.

[0136] In some embodiments, the dynamic convergence control and termination determination module includes: a convergence detection unit, a boundary determination unit, and an execution control unit.

[0137] The convergence detection unit monitors the active mask status in real time, triggering vector loop termination when all data channels are detected to be inactive. The boundary determination unit uses the loop counter and boundary conditions to determine whether the loop termination condition has been met. The execution control unit switches between vector execution paths and scalar execution paths.

[0138] 6. Result Consistency and Tail Processing Module.

[0139] The result consistency and tail processing module is used to ensure that the vector execution result is consistent with the semantics of the original scalar.

[0140] Specifically, the result consistency and tail processing module is used to ensure that the execution result is consistent with the original scalar semantics after the vector loop terminates, to filter the vector result for validity based on the exit position, and to retain only the valid calculation result; to control the result write-back, and to submit only the data corresponding to the valid data channel; to perform tail processing or scalar supplement calculation on the remaining unprocessed data; and to ensure the integrity and consistency of the program execution result.

[0141] In some embodiments, the result consistency and tail processing module includes: a result truncation unit, a state write-back control unit, and a tail processing unit.

[0142] The result truncation unit filters the vector results based on the exit position index, retaining only data that meets semantic requirements. The status write-back control unit controls the write-back of results, submitting only the calculation results corresponding to valid data channels. The tail processing unit performs supplementary processing on any remaining unprocessed data elements after vector execution to ensure the integrity of the overall calculation results.

[0143] In summary, the vectorized execution system architecture for conditional loops described above introduces an activity mask that can propagate across iterations during the vectorized execution of the conditional loop structure. This activity mask dynamically represents the execution state of each data channel. Combined with early exit semantic detection and activity mask state updates, data channels that meet the early exit condition are continuously deactivated in subsequent iterations, thus achieving vectorized execution of the conditional loop and ensuring that inactive data channels after the early exit condition is triggered do not violate the original semantics of the conditional loop structure. Compared to traditional mask execution schemes, this application, upon detecting an early exit condition, can generate a truncated mask based on the exit position and continuously suppress the execution of the corresponding data channel in subsequent iterations, thereby avoiding invalid computation and supporting the early termination of the vector loop.

[0144] The above provides a brief description of the overall architecture of the vectorized execution system for conditional loops. The following section will describe the execution process of the vectorized execution method for conditional loops.

[0145] like Figure 5 The flowchart shown illustrates the vectorized execution process of a conditional loop. This embodiment uses the execution of this method by an electronic device as an example. This electronic device can be... Figure 1 The electronic device 100 is shown in the diagram.

[0146] Step 501: Loop structure analysis and vectorization determination.

[0147] Specifically, the conditional loop structure to be optimized is analyzed to identify the conditional branches and / or loops with early exit semantics contained in the conditional loop structure, including break, return, or other control transfer paths, and the corresponding conditional expressions are extracted.

[0148] Simultaneously, data dependency analysis is performed on the loop body to detect whether there are cross-iteration dependencies and to assess the safety of memory access operations in order to determine whether the conditions for vectorized execution are met.

[0149] When a conditional loop structure can be semantically equivalent through masking, it is marked as the target conditional loop structure.

[0150] Step 502: Vector execution state initialization.

[0151] Specifically, before entering vectorized execution, the vectorized execution environment is initialized. This includes: initializing the activity mask to make the activity masks of all data channels active; configuring the vector length according to the remaining iterations of the current loop and the processor's vector execution capability; initializing the vector registers and related control variables; and after initialization, entering the vectorized loop execution phase.

[0152] Step 503: Vectorized loop execution based on multi-mechanism collaboration.

[0153] Specifically, in this step, the dynamic convergence of the conditional loop is achieved through the synergistic effect of controlled execution, exit detection, and mask propagation mechanisms.

[0154] Step 504: If the exit conditions are met during vectorized execution, generate an exit mask.

[0155] Specifically, under the constraints of the current active mask, the vectorized loop body instructions are executed, allowing only active data channels to participate in the computation. During execution, the corresponding exit conditions are calculated for each data channel, and an exit mask is generated.

[0156] The exit mask is used to identify data channels within the current vector segment that meet the exit conditions.

[0157] Step 505: Based on the exit mask, generate a masking mask or a truncation mask, and update the active mask.

[0158] Specifically, a position detection operation is performed based on the exit mask to determine the location of the first data channel that meets the exit conditions. In some implementations, a truncation mask is generated based on the exit location, marking data channels after the exit location as inactive. In other implementations, a mask generation operation is performed on the exit mask to generate a masking mask used to prevent data channels that meet the exit conditions from participating in subsequent execution.

[0159] Subsequently, a combined update operation is performed on the truncated mask or the truncated mask and the current active mask to generate an updated active mask. The update process includes: preserving the execution state of data channels that have not triggered exit conditions; maintaining data channels that have triggered exit conditions in an inactive state in subsequent iterations; achieving continuous propagation and accumulation of data channel execution states across multiple iterations; and using the updated active mask to constrain the next round of vector execution, thereby gradually converging the set of data channels participating in execution as the iteration progresses.

[0160] Furthermore, the activity mask is continuously retained across different iterations and participates in subsequent vector execution control, thereby enabling the cross-iteration propagation of the exit state.

[0161] Step 506: Determine whether the loop termination condition is met.

[0162] Specifically, the subsequent vector iterations are performed based on the updated activity mask, and it is determined whether the current vector iteration satisfies the loop termination condition.

[0163] If the loop termination condition is met, proceed to step 507. If the loop termination condition is not met, proceed to step 503.

[0164] Step 507: Result consistency processing and loop termination.

[0165] Specifically, after each round of vector iteration, the execution status is checked. Vector loop execution terminates when all active masks are inactive or when the loop boundary condition is reached. Upon termination, the vector execution results are processed according to the exit position, including: valid filtering of the vector register results, retaining only valid calculation results; controlling the write-back of results to avoid data submission from inactive data channels; and performing tail processing or scalar supplementation calculations on the remaining unprocessed data to ensure that the final execution result is consistent with the original scalar semantics.

[0166] Step 508: End.

[0167] This embodiment further details the activity mask cross-iteration propagation mechanism based on exit state in the vectorized execution method for conditional loops provided in this application. This mechanism is applicable to scenarios where multiple independent data streams or multiple control flow tasks are processed in parallel in a vector register, aiming to achieve dynamic convergence control of the execution state of each data channel.

[0168] In this embodiment, the following mask variable is introduced.

[0169] Activity mask: Used to identify the set of active data channels currently participating in vector execution.

[0170] Exit mask: Used to identify the data channel that meets the exit conditions in the current iteration.

[0171] Masking mask: Generated based on the exit mask, used to block the corresponding data channel from participating in execution in subsequent iterations.

[0172] Truncation mask: Generated based on the exit position, used to completely mask the data channel after the exit position.

[0173] Exit Position Index: Used to record the data channel position that triggers the exit condition, for use in result write-back control and execution termination determination.

[0174] Each mask is a bit vector corresponding to the length of the effective vector.

[0175] During the execution of the vectorized loop, the following steps are performed for each iteration.

[0176] Step 1: Exit mask generation.

[0177] Execute a vectorized loop under the constraints of the current mask. Evaluate the exit conditions for each data channel separately and generate an exit mask.

[0178] When a data channel meets the exit condition, the corresponding bit in its exit mask is set to a valid state. For data channels that do not meet the exit condition or are currently in an inactive state, the corresponding bit is set to an invalid state.

[0179] Step 2: Generate a mask or truncation mask.

[0180] In some implementations, a bitwise NOT or equivalent logical operation is performed on the exit mask to generate a masking mask.

[0181] In other implementations, a position detection operation is performed on the exit mask to determine the location of the first data channel that meets the exit conditions, and a truncation mask is generated based on that location to achieve overall shielding of subsequent data channels.

[0182] At the same time, the exit status information of the corresponding data channel can be recorded according to the exit position index.

[0183] Step 3: Activity mask combination update and cross-iteration propagation.

[0184] A combined update operation is performed between the generated mask or truncated mask and the currently active mask to generate an updated active mask. In some implementations, the combined update operation includes a logical AND operation. For example: Mactive_new = Mactive&Mmask Where: Mactive_new represents the updated active mask; Mactive represents the current active mask; Mmask represents the mask or truncated mask.

[0185] Specifically: for data channels that have triggered the exit condition, their corresponding mask bits are cleared to zero and remain inactive in subsequent iterations; for data channels that have not triggered the exit condition, their corresponding mask bits remain active and continue to participate in subsequent calculations. The updated active mask is retained across different iterations and used to constrain subsequent vector execution, thereby achieving cross-iteration propagation of the exit state.

[0186] Step 4: Dynamic convergence execution of the data channel.

[0187] As the iteration progresses, the set of active data channels in the active mask gradually decreases according to their respective processing progress, thus forming a dynamic convergence process.

[0188] For example, assuming the vector length is 4, the initial state of the activity mask is 1111 (all four data channels start executing simultaneously). Iteration 1: Data channel 1 meets the exit condition, the exit mask is 0100, and the updated activity mask is 1011. Iteration 2: Data channel 2 meets the exit condition, the exit mask is 0010, and the updated activity mask is 1001. Iteration 3: Both data channels 0 and 3 meet the exit condition, the exit mask is 1001, and the updated activity mask is 0000.

[0189] When all active masks are detected to be inactive, the overall vector loop terminates prematurely.

[0190] In summary, in any two adjacent iterations, the set of active data channels corresponding to the updated activity mask is a subset of the set of active data channels in the previous round. Through this mechanism, even if the branch paths and execution cycles corresponding to different data channels differ, the overall vector execution process can still maintain stable convergence. Furthermore, through a dynamic masking mechanism based on the activity mask, this embodiment achieves mutual isolation between the execution states of different data channels. When a data channel completes execution, its corresponding data channel can be promptly masked, thereby avoiding side effects such as invalid memory access, anomaly propagation, or erroneous write-backs caused by inactive data channels in subsequent iterations.

[0191] Compared to solutions that require the complete execution of all paths or use scalar rollback to handle complex control flows, this embodiment can reduce invalid computations at the data channel granularity and support early termination of loops after all data channels have been executed, thereby reducing processor execution overhead and improving vector execution efficiency and resource utilization.

[0192] The foregoing mainly describes the method provided in this application. Accordingly, this application also provides a vectorized execution apparatus for conditional loops, which is used to implement the above-described method embodiments.

[0193] In some embodiments, the vectorized execution device for the conditional loop includes hardware structures and / or software modules corresponding to the execution of each function in order to achieve the above-described functions. Those skilled in the art will readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0194] This application embodiment can divide the vectorized execution device for conditional loops into functional modules according to the above method embodiment. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0195] In some embodiments, this application provides a vectorized execution apparatus for conditional loops. For example... Figure 6 The diagram shows a schematic of the structure of the vectorized execution device for a conditional loop. The vectorized execution device for a conditional loop may include: an acquisition module 601, an execution control module 602, an exit detection module 603, a mask processing and cross-iteration state propagation module 604, and a dynamic convergence execution module 605.

[0196] The acquisition module 601 is used to acquire the target conditional loop structure, which includes conditional branching and / or early exit semantics.

[0197] The execution control module 602 is used to control the data channels in the active state of the active mask to participate in the vectorized execution of the target conditional loop structure.

[0198] The exit detection module 603 is used to detect exit conditions for the data channel during vectorized execution and generate an exit mask if there is a data channel that meets the exit conditions.

[0199] The mask processing and cross-iteration state propagation module 604 is used to generate a masking mask or a truncated mask based on the exit mask, and to update the active mask across iterations based on the masking mask or the truncated mask.

[0200] The dynamic convergence execution module 605 is used to continue executing the target conditional loop structure based on the updated activity mask, so that the data channel that meets the exit condition remains inactive in subsequent iterations until the loop termination condition is met.

[0201] One possible implementation is a mask processing and cross-iteration state propagation module 604, which performs a mask generation operation on the exit mask to generate a mask or truncation mask for restricting the corresponding data channel from participating in subsequent execution; wherein the exit mask is used to identify the data channel that meets the exit condition in the current iteration.

[0202] Another possible implementation is that the masking generation operation includes: determining the position of the first data channel that meets the exit conditions based on the exit mask, and generating a truncation mask based on the position to block the data channels after the position from participating in subsequent execution.

[0203] Another possible implementation is a mask processing and cross-iteration state propagation module 604, which performs a combined update operation on the current active mask and the masking mask or truncated mask to generate an updated active mask; wherein the updated active mask is continuously retained between different iterations and used to continuously constrain the vectorized execution of the corresponding data channel in subsequent iterations.

[0204] Another possible implementation involves combining update operations, including logical AND operations.

[0205] Another possible implementation includes at least one of the following loop termination conditions: all data channels corresponding to the active mask are inactive; the loop boundary condition corresponding to the target condition loop structure is reached.

[0206] Another possible implementation is that the acquisition module 601 is used to: acquire the conditional loop structure; perform vectorized legality analysis on the conditional loop structure to obtain the target conditional loop structure that satisfies the vectorized execution conditions; wherein the vectorized legality analysis includes at least one of the following: cross-iteration dependency analysis; memory access safety analysis; early exit semantic analysis; control flow branch analysis.

[0207] Another possible implementation, the vectorized execution device for conditional loops provided in this application, further includes a result consistency and tail processing module 606. The result consistency and tail processing module 606 is used to perform validity control on the vector execution result after the target conditional loop structure ends, and to perform scalar processing or tail vector processing on the remaining unprocessed data elements.

[0208] The vectorized execution device for conditional loops provided in this application embodiment is used to implement the vectorized execution method for conditional loops in the above method embodiments. Its implementation principle and technical effects can be found in the relevant descriptions in the above method embodiments, and will not be repeated here.

[0209] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7 As shown, the electronic device may include a processor 710, a communications interface 720, a memory 730, and a communication bus 740. The processor 710, communications interface 720, and memory 730 communicate with each other via the communication bus 740. The processor 710 can call logical instructions from the memory 730 to execute a vectorized execution method for conditional loops.

[0210] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0211] In some embodiments, this application also provides a chip including at least one processor, the processor being configured to execute program instructions to perform the methods provided in the above embodiments.

[0212] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory and / or non-volatile memory. Non-volatile memory can be ROM, Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), or flash memory. Volatile memory can be RAM. For example, RAM can be used as an external cache. By way of example and not limitation, RAM includes various forms such as: Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchlink Dynamic Random Access Memory (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0213] like Figure 8 This application provides a chip system 800. The chip system 800 (or processing system) includes logic circuitry 810 and an input / output interface 820. The logic circuitry 810 can be a processing circuit or an interface circuit within the chip system 800. The logic circuitry 810 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 800 to implement the methods and functions of the embodiments of this application. The input / output interface 820 can be an input / output circuit within the chip system 800, outputting processed information or inputting data or signaling information to be processed into the chip system 800 for processing.

[0214] As one approach, the chip system 800 is used to implement the operations described in the various method embodiments above. For example, the logic circuit 810 is used to implement the relevant operations performed by each execution entity in the method embodiments above; the input / output interface 820 is used to implement the sending and / or receiving related operations performed by each execution entity in the method embodiments above.

[0215] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer is able to execute the vectorized execution method of the conditional loop provided by the above methods.

[0216] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a vectorized execution method for performing conditional loops provided by the methods described above.

[0217] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0218] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0219] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vectorized execution method for conditional loops, characterized in that, The method includes: Obtain the target conditional loop structure, which includes conditional branching and / or early exit semantics; The active data channel lane in the control activity mask participates in the vectorized execution of the target conditional loop structure, wherein the activity mask is used to identify the execution status of the corresponding data channel; During the vectorized execution process, an exit condition is detected for the data channel, and an exit mask is generated if there is a data channel that meets the exit condition. A masking mask or a truncation mask is generated based on the exit mask, and the activity mask is updated based on the masking mask or the truncation mask. The masking mask is used to block the corresponding data channel from participating in the execution in subsequent iterations, and the truncation mask is used to block the data channel after the exit position as a whole. The target conditional loop structure continues to be executed based on the updated activity mask, so that the data channel that meets the exit condition remains inactive in subsequent iterations until the loop termination condition is met.

2. The method according to claim 1, characterized in that, The process of generating a masking mask or truncation mask based on the exit mask includes: Perform a mask generation operation on the exit mask to generate a mask or truncation mask used to restrict the corresponding data channel from participating in subsequent execution; The exit mask is used to identify the data channel that meets the exit condition in the current iteration.

3. The method according to claim 2, characterized in that, The shielding generation operation includes: The exit mask is used to determine the location of the first data channel that meets the exit conditions, and a truncation mask is generated based on the location to block the data channels after the location from participating in subsequent execution.

4. The method according to claim 1, characterized in that, The step of updating the active mask based on the masking mask or truncation mask includes: Perform a combined update operation on the current active mask and the masking mask or truncated mask to generate an updated active mask; The updated activity mask is used to continuously constrain the vectorized execution of the corresponding data channel in subsequent iterations, so as to achieve cross-iteration propagation of the activity state.

5. The method according to claim 4, characterized in that, The combined update operation includes a logical AND operation.

6. The method according to claim 1, characterized in that, The loop termination condition includes at least one of the following: The data channels corresponding to the active mask are all inactive. The loop boundary conditions corresponding to the target condition loop structure are achieved.

7. The method according to claim 1, characterized in that, The target condition loop structure includes: Get the conditional loop structure; Perform vectorized validity analysis on the conditional loop structure to obtain the target conditional loop structure that satisfies the vectorized execution conditions; The vectorized legality analysis includes at least one of the following: Cross-iteration dependency analysis; Memory access security analysis; Exit semantic analysis early; Control flow branch analysis.

8. The method according to claim 1, characterized in that, The method further includes: After the target condition loop structure ends, scalar processing or tail vector processing is performed on the remaining unprocessed data elements.

9. A vectorized execution device for conditional loops, characterized in that, The device includes: The acquisition module is used to acquire the target conditional loop structure, which includes conditional branching and / or early exit semantics. The execution control module is used to control the data channels in the active state of the active mask to participate in the vectorized execution of the target conditional loop structure; An exit detection module is used to detect exit conditions for the data channel during the vectorized execution process, and generate an exit mask if there is a data channel that meets the exit conditions. The mask processing and cross-iteration state propagation module is used to generate a masking mask or a truncation mask based on the exit mask, and update the activity mask based on the masking mask or the truncation mask. The masking mask is used to block the corresponding data channel from participating in the execution in subsequent iterations, and the truncation mask is used to block the data channel after the exit position as a whole. The dynamic convergence execution module is used to continue executing the target conditional loop structure based on the updated activity mask, so that the data channel that meets the exit condition remains inactive in subsequent iterations until the loop termination condition is met.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the vectorized execution method of the conditional loop as described in any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the vectorized execution method of the conditional loop as described in any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the vectorized execution method of the conditional loop as described in any one of claims 1 to 8.

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