Chip computing method, device, medium and product based on register offset control

Abstract

Embodiments of the present application disclose a chip computing method and device based on register offset control, a medium and a product. The method comprises: performing matrix cutting on a left matrix and a right matrix of a matrix multiplication operation to obtain a left matrix block and a right matrix block; carrying the left matrix to a level one cache, and determining a target left matrix block and a target right matrix block in the matrix multiplication operation; carrying the target right matrix block to the level one cache, reading the target left matrix block and the target right matrix block from the level one cache to perform matrix multiplication to obtain a block operation result; determining a register offset address according to block information of the matrix block, and storing the block operation result to a register according to the register offset address; and when the matrix multiplication operation is determined to be completed, carrying the block operation result in the register to a level three cache to obtain a matrix multiplication result, so that an intermediate operation result is resident in the register and does not occupy the level one cache, the level one cache can cache the left matrix, and frequent data carrying overhead is avoided.

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