Instruction processing device, system, method, processor and electronic device

Abstract

The present disclosure relates to the technical field of integrated circuits, and proposes an instruction processing device, system, method, processor and electronic equipment. The device comprises an instruction scheduler and a register reading unit, the register reading unit comprising a cache unit. The instruction scheduler is configured to, in a case where at least one source operand address of a first instruction is reused by at least one second instruction following the first instruction, continuously schedule the first instruction and the at least one second instruction to the register reading unit; the first instruction and the second instruction correspond to the same thread bundle; and the register reading unit is configured to cache the source operand of the first instruction in the cache unit during processing of the first instruction, and reuse the cached source operand in the cache unit during processing of the second instruction. The instruction processing device of the present disclosure can improve the hit rate of the cache, reduce the number of register accesses, reduce register access conflicts, shorten the execution delay of instructions, and improve the performance of the processor.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an instruction processing apparatus, system, method, processor, and electronic device. Background Technology

[0002] Floating-point arithmetic, integer arithmetic, logical arithmetic, and other basic operations are very important and frequently used functions in graphics processing units (GPUs), and the efficiency of basic operations is an important indicator for measuring GPU performance.

[0003] The compilation module can first compile instructions that can be executed by the GPU and then send the compiled instructions to the GPU. Inside the GPU, after the instruction scheduler receives the operation instructions, it schedules the instructions to the register fetch unit. The register fetch unit reads the source operands corresponding to the instructions and then outputs the instructions and their corresponding source operands to the execution unit for execution.

[0004] Source operands are typically stored in the GPU's General Purpose Register (GPR). Normally, each register read operation can only access one GPR within a single memory location during the same cycle. If multiple source operands for a given instruction are stored in multiple GPRs within the same memory location, it may be impossible to retrieve all source operands for the instruction within a single cycle, resulting in excessively long instruction execution latency and reduced GPU performance. Summary of the Invention

[0005] In view of the above, this disclosure proposes an instruction processing apparatus, system, method, processor, and electronic device. The instruction processing apparatus of embodiments of this disclosure can use a cache to store source operands and prioritize scheduling instructions that reuse the same source operands, thereby improving cache hit rate, reducing the number of register accesses, reducing register access conflicts, shortening instruction execution latency, and improving processor performance.

[0006] According to one aspect of this disclosure, an instruction processing apparatus is provided, comprising an instruction scheduler and a register read unit, the register read unit including a cache unit, the instruction scheduler being configured to, when at least one source operand address of a first instruction is reused by at least one second instruction following the first instruction, consecutively schedule a first instruction and at least one second instruction to the register read unit; the first instruction and the second instruction correspond to the same thread bundle; the register read unit being configured to, during the processing of the first instruction, cache the source operand of the first instruction in the cache unit, and during the processing of the second instruction, reuse the source operand cached in the cache unit.

[0007] In one possible implementation, the instruction scheduler is used to schedule the first instruction and at least one second instruction consecutively to the register read unit when the source operand address in the first instruction carries a multiplexing identifier.

[0008] In one possible implementation, the register read unit is used to, in response to receiving a third instruction, detect whether the source operand of the third instruction is stored in the cache unit; the third instruction is any one of the first instruction and at least one second instruction; read the source operand of the third instruction that is not stored in the cache unit from the register; and store the read source operand into the cache unit.

[0009] In one possible implementation, the cache unit includes multiple cache lines, and the register read unit is used to detect in parallel whether the source operand of the third instruction is stored in the multiple cache lines.

[0010] In one possible implementation, each cache line includes multiple source operand storage locations, where the address of the xth source operand of the third instruction corresponds to the xth source operand storage location, and x is a positive integer; the register read unit is used to detect whether the xth source operand of the third instruction is stored at the xth source operand storage location in each cache line.

[0011] In one possible implementation, each cache line includes multiple source operand storage locations, and the register read unit is used to detect whether a source operand of a third instruction is stored at each source operand storage location in each cache line.

[0012] In one possible implementation, the register read unit is used to detect whether the source operand of the third instruction is stored at the k-th source operand storage location in each cache line, where k is an integer greater than 0 and less than or equal to N; if the source operand of the third instruction is not detected at the k-th source operand storage location in all cache lines, the unit continues to detect whether the source operand of the third instruction is stored at the (k+1)-th source operand storage location in each cache line.

[0013] In one possible implementation, each cache line includes multiple source operand storage locations and multiple tag storage locations, with each tag storage location corresponding one-to-one with a source operand storage location. The register read unit is further configured to, for each source operand read, select a source operand storage location from the allowed source operand storage locations and write the read source operand to the selected source operand storage location; when the source operand address corresponding to the read source operand is reused, write a reuse identifier to the tag storage location corresponding to the selected source operand storage location, the reuse identifier being used to indicate that the selected source operand storage location stores the reused source operand.

[0014] In one possible implementation, the x-th source operand address of the third instruction corresponds to the x-th source operand storage location and the x-th tag storage location, where x is a positive integer; when the source operand read corresponds to the x-th source operand address, the allowed source operand storage locations include the x-th source operand storage location of each cache line.

[0015] In one possible implementation, the allowed source operand storage locations include all source operand storage locations of the cache unit.

[0016] In one possible implementation, if there is a free source operand storage location among the allowed source operand storage locations, any free source operand storage location is selected; if there is no free source operand storage location among the allowed source operand storage locations, any source operand storage location whose corresponding tag storage location does not store the reuse identifier is selected.

[0017] In one possible implementation, the register read unit is further configured to, when detecting that any source operand storage location stores the source operand of the third instruction and the source operand address corresponding to the source operand is not reused, clear the reuse flag when the tag storage location corresponding to the source operand storage location stores a reuse flag.

[0018] In one possible implementation, the register read unit is further configured to, when detecting that any source operand storage location stores the source operand of the third instruction and the source operand address corresponding to the source operand is reused, write the reuse flag to the tag storage location if the tag storage location corresponding to the source operand storage location does not store the reuse flag.

[0019] In one possible implementation, the register read unit is also used to clear the source operands corresponding to the thread bundle stored in the cache unit after the last instruction in any thread bundle has been executed.

[0020] In one possible implementation, the first instruction and the second instruction correspond to different types of pipelines.

[0021] In one possible implementation, the register read unit is further configured to, after writing the read source operand to the selected source operand storage location, store at least one of the following: the type of the register storing the source operand, the offset of the source operand in the instruction, and the number of the current thread bundle, into the tag storage location corresponding to the selected source operand storage location; the type, offset, and number stored in any tag storage location are used to detect whether the source operand stored in the corresponding source operand storage location is the source operand of the third instruction.

[0022] According to another aspect of this disclosure, an instruction processing system is provided. The system includes a compilation module and an instruction processing apparatus. The apparatus includes an instruction scheduler and a register read unit. The register read unit includes a cache unit. The compilation module is configured to identify the address of a source operand that is multiplexed in a first instruction. The instruction scheduler is configured to schedule the first instruction and at least one second instruction consecutively to the register read unit if at least one source operand address of the first instruction is multiplexed by at least one second instruction following the first instruction. The register read unit is configured to cache the source operand of the first instruction in the cache unit during the processing of the first instruction and reuse the source operand cached in the cache unit during the processing of the second instruction.

[0023] In one possible implementation, the compiler module is used to add a reuse flag at the identified source operand address; the instruction scheduler is used to determine that the source operand address is reused by at least one second instruction following the first instruction when any source operand address of the first instruction carries the reuse flag.

[0024] According to another aspect of this disclosure, an instruction processing method is provided. The method is applied to an instruction processing apparatus, which includes an instruction scheduler and a register read unit. The register read unit includes a cache unit. The method includes: the instruction scheduler, when the address of at least one source operand of a first instruction is reused by at least one second instruction following the first instruction, consecutively scheduling the first instruction and at least one second instruction to the register read unit; the first instruction and the second instruction correspond to the same thread bundle; the register read unit caches the source operand of the first instruction in the cache unit while processing the first instruction, and reuses the cached source operand in the cache unit while processing the second instruction.

[0025] In one possible implementation, the method further includes: when the source operand address in the first instruction carries a multiplexing identifier, the instruction scheduler schedules the first instruction and at least one second instruction consecutively to the register read unit.

[0026] In one possible implementation, the method further includes: in response to receiving a third instruction, the register read unit detects whether the source operand of the third instruction is stored in the cache unit; the third instruction is any one of the first instruction and at least one second instruction; reads the source operand of the third instruction that is not stored in the cache unit from the register; and stores the read source operand into the cache unit.

[0027] In one possible implementation, the cache unit includes multiple cache lines, and detecting whether the source operand of the third instruction is stored in the cache unit includes: detecting whether the source operand of the third instruction is stored in multiple cache lines in parallel.

[0028] In one possible implementation, each cache line includes multiple source operand storage locations, where the address of the xth source operand of the third instruction corresponds to the xth source operand storage location, and x is a positive integer; detecting whether the source operand of the third instruction is stored in the cache unit includes: detecting whether the xth source operand of the third instruction is stored at the xth source operand storage location in each cache line.

[0029] In one possible implementation, each cache line includes multiple source operand storage locations. Detecting whether a source operand of a third instruction is stored in a cache unit includes: at each source operand storage location in each cache line, detecting whether a source operand of a third instruction is stored.

[0030] In one possible implementation, at each source operand storage location in each cache line, it is checked whether a source operand of a third instruction is stored, including: at the k-th source operand storage location in each cache line, it is checked whether a source operand of a third instruction is stored, where k is an integer greater than 0 and less than or equal to N; if no source operand of a third instruction is detected at the k-th source operand storage location in all cache lines, it is continued to check whether a source operand of a third instruction is stored at the (k+1)-th source operand storage location in each cache line.

[0031] In one possible implementation, each cache line includes multiple source operand storage locations and multiple tag storage locations, with each tag storage location corresponding one-to-one with a source operand storage location. Storing read source operands into the cache unit includes: for each read source operand, selecting a source operand storage location from the allowed selections, and writing the read source operand to the selected source operand storage location; when the source operand address corresponding to the read source operand is reused, writing a reuse identifier to the tag storage location corresponding to the selected source operand storage location, the reuse identifier indicating that the selected source operand storage location stores the reused source operand.

[0032] In one possible implementation, the x-th source operand address of the third instruction corresponds to the x-th source operand storage location and the x-th tag storage location, where x is a positive integer; when the source operand read corresponds to the x-th source operand address, the allowed source operand storage locations include the x-th source operand storage location of each cache line.

[0033] In one possible implementation, the allowed source operand storage locations include all source operand storage locations of the cache unit.

[0034] In one possible implementation, selecting a source operand storage location from the allowed source operand storage locations includes: if there is a free source operand storage location among the allowed source operand storage locations, selecting any free source operand storage location; if there is no free source operand storage location among the allowed source operand storage locations, selecting any source operand storage location whose corresponding tag storage location does not store a reuse identifier.

[0035] In one possible implementation, the method further includes: when it is detected that any source operand storage location stores the source operand of the third instruction, and the source operand address corresponding to the source operand is not reused, the register read unit clears the reuse flag when the tag storage location corresponding to the source operand storage location stores a reuse flag.

[0036] In one possible implementation, the method further includes: when it is detected that any source operand storage location stores the source operand of the third instruction, and the source operand address corresponding to the source operand is reused, the register read unit writes the reuse flag to the tag storage location when the tag storage location corresponding to the source operand storage location does not store the reuse flag.

[0037] In one possible implementation, the method further includes: after the last instruction in any thread bundle has been executed, the register read unit clears the source operands corresponding to the thread bundle stored in the cache unit.

[0038] In one possible implementation, the first instruction and the second instruction correspond to different types of pipelines.

[0039] In one possible implementation, the method further includes: after writing the read source operand to the selected source operand storage location, the register reading unit stores at least one of the following: the type of the register storing the source operand, the offset of the source operand in the instruction, and the number of the current thread bundle, into the tag storage location corresponding to the selected source operand storage location; the type, offset, and number stored in any tag storage location are used to detect whether the source operand stored in the corresponding source operand storage location is the source operand of the third instruction.

[0040] According to another aspect of this disclosure, a processor is provided, including the instruction processing means described in any of the preceding claims.

[0041] According to another aspect of this disclosure, an electronic device is provided, including the instruction processing system described above, or including the processor described above.

[0042] An instruction processing apparatus according to an embodiment of the present disclosure includes an instruction scheduler and a register fetch unit. The register fetch unit includes a cache unit. The instruction scheduler is configured to, when at least one source operand address of a first instruction is reused by at least one second instruction following the first instruction, consecutively schedule a first instruction and at least one second instruction to the register fetch unit; the first instruction and the second instruction correspond to the same thread bundle; the register fetch unit is configured to, during the processing of the first instruction, cache the source operand of the first instruction in the cache unit, and during the processing of the second instruction, reuse the source operand cached in the cache unit. By storing the reusable source operand of the first instruction in the cache unit, it is possible to reduce the number of register accesses when processing a second instruction using the same source operand. By prioritizing the scheduling of instructions that reuse the source operands stored in the cache unit, the cache hit rate can be improved, further reducing the number of register accesses. Therefore, the instruction processing apparatus of the present disclosure can reduce the number of register accesses, reduce register access conflicts, shorten instruction execution latency, and improve processor performance.

[0043] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0044] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0045] Figure 1 An exemplary scenario of an instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0046] Figure 2 A schematic diagram showing the structure of an instruction processing apparatus according to an embodiment of the present disclosure is provided.

[0047] Figure 3 A schematic diagram showing the structure of a cache unit according to an embodiment of the present disclosure is provided.

[0048] Figure 4a This diagram illustrates the data storage situation before the cache unit processing instruction Instr1 according to an embodiment of the present disclosure.

[0049] Figure 4b This diagram illustrates the data storage situation after the cache unit processing instruction Instr1 according to an embodiment of the present disclosure.

[0050] Figure 4c This diagram illustrates another instance of data storage following the Instr1 instruction of the cache unit processing according to an embodiment of the present disclosure.

[0051] Figure 5 A schematic diagram illustrating the flow of an instruction processing method according to an embodiment of the present disclosure is shown.

[0052] Figure 6 A schematic diagram showing the structure of an instruction processing system according to an embodiment of the present disclosure is provided. Detailed Implementation

[0053] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0054] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0055] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0056] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0057] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0058] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0059] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0060] Figure 1 An exemplary scenario of an instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0061] like Figure 1 As shown, the first device may include a compilation module, a first processor, and a storage module. The first processor includes an instruction processing unit and multiple pipelines, such as an integer arithmetic pipeline, a floating-point arithmetic pipeline, and a logic arithmetic pipeline. Each pipeline may include an execution unit (not shown) for executing arithmetic instructions. The storage module includes multiple storage units (storage unit 0-storage unit 3), and each storage unit includes multiple general-purpose registers.

[0062] The compiler module is used to compile the source program (usually written in a high-level language) to obtain the set of instructions to be executed by the first processor, and to send the set of instructions to the first processor.

[0063] In the first processor, the instruction processing unit responds to each instruction in the instruction set by checking whether the source operand corresponding to the instruction is stored locally, and accessing the GPR to obtain the source operand that is not stored locally. Then, according to the type of instruction (integer arithmetic / floating-point arithmetic / logical arithmetic, etc.), the instruction and its corresponding source operand are output to the same type of pipeline, where they are executed by the execution unit.

[0064] In one example, the compilation module can be a hardware device with compilation capabilities, located in the central processing unit. The first processor can be a processor capable of executing arithmetic instructions, such as a graphics processing unit. This disclosure does not limit the specific types of the compilation module and the first processor.

[0065] Figure 2 A schematic diagram showing the structure of an instruction processing apparatus according to an embodiment of the present disclosure is provided.

[0066] like Figure 2 As shown, in one possible implementation, the device includes an instruction scheduler and a register read unit, the register read unit including a cache unit.

[0067] The instruction scheduler is used to schedule a first instruction and at least one second instruction consecutively to a register read unit when at least one source operand address of a first instruction is multiplexed by at least one second instruction following the first instruction; the first instruction and the second instruction correspond to the same thread bundle.

[0068] The register read unit is used to cache the source operand of the first instruction in the cache unit during the processing of the first instruction, and to reuse the source operand cached in the cache unit during the processing of the second instruction.

[0069] For example, the instruction processing apparatus may include an instruction scheduler and a register fetch unit. The register fetch unit may include a cache unit for storing source operands.

[0070] The instruction scheduler first receives the instruction set from the compiler module. The instruction set may include multiple wave bundles, and each wave bundle may contain multiple instructions. The following illustrates an exemplary method by which the compiler module compiles the instruction set.

[0071] The compilation module can first compile the source program to obtain instructions that include multiple source operand addresses, destination operand addresses, and operation types. The compilation module can then update the instructions in the same thread bundle based on the source operand address reuse information of the compiled instructions.

[0072] Specifically, for a compiled thread bundle, if the first instruction and at least one subsequent second instruction reuse the address of any source operand of the first instruction, a reuse flag can be added to the reused source operand address in the first instruction. The first instruction can be any instruction in the thread bundle.

[0073] In one example, assume the thread binding instructions include instructions Instr1-Instr3. Where:

[0074] Instr1: FMA R3,R0,R1,R2;

[0075] Instr2: FMUL R6,R1,R4,R2;

[0076] Instr3: FMUL R7,R0,R4.

[0077] FMA indicates that the source operands are floating-point numbers, and multiplication and addition operations are performed on the source operands. FMUL indicates that the source operands are floating-point numbers, and multiplication operations are performed on the source operands.

[0078] The source operand addresses for the instruction Instr1 include R0, R1, and R2, and the destination operand address includes R3.

[0079] The source operand addresses for the instruction Instr2 include R1, R4, and R2, and the destination operand address includes R6.

[0080] The source operand addresses for the instruction Instr3 include R0 and R4, and the destination operand address includes R7.

[0081] Below is an example of an instruction in the compilation module that updates a thread bundle.

[0082] The compiler module can identify the reused source operand addresses in the first instruction. Specifically, if the x-th source operand address of the first instruction is the same as the x-th source operand address of a subsequent second instruction, it is considered that the x-th source operand address of the first instruction has been reused by the second instruction. When updating instructions in a thread bundle, the compiler module can add a reuse flag (reuse) to the reused source operand addresses in the first instruction.

[0083] For example, the compilation module first uses Instr1 as the first instruction and Instr2 and Instr3 as the second instructions. Since the first source operand address of both Instr1 and Instr3 is R0, the source operand address R0 of Instr1 is reused by Instr3, and a reuse flag is added to the source operand address R0 in Instr1. Since the third source operand address of both Instr1 and Instr2 is R2, the source operand address R2 of Instr1 is reused by Instr2, and a reuse flag is added to the source operand address R2 in Instr1. At this point, the instructions in the thread bundle are updated as follows:

[0084] Instr1: FMA R3, R0.reuse, R1, R2.reuse;

[0085] Instr2: FMUL R6, R1, R4, R2;

[0086] Instr3: FMUL R7, R0, R4.

[0087] Using Instr2 as the first instruction and Instr3 as the second instruction, since the second source operand address of both Instr2 and Instr3 is R4, the source operand address R4 in Instr2 is reused by Instr3. Therefore, a reuse flag is added to the source operand address R4 in Instr2. At this point, the instructions in the thread bundle are updated as follows:

[0088] Instr1: FMA R3, R0.reuse, R1,R2.reuse;

[0089] Instr2: FMUL R6, R1, R4.reuse, R2;

[0090] Instr3: FMUL R7, R0, R4.

[0091] Since Instr3 is the last instruction in the thread bundle, there is no second instruction that can reuse the source operand address of Instr3. Therefore, once the instructions in the current thread bundle are updated, the compiler module can continue to update the instructions in the next thread bundle.

[0092] In practical scenarios, to reduce the workload of the compilation module, when updating instructions in a thread bundle, we can only consider the reuse of source operands between the first instruction and the subsequent k second instructions. k can be a positive integer.

[0093] The embodiments disclosed herein do not restrict the method for determining the reuse of source operand addresses between instructions. For example, if the xth source operand address of the first instruction is the same as any one of the source operand addresses of the second instruction, it can be considered that the second instruction reuses the xth source operand address of the first instruction.

[0094] The compiler module can be configured to output the thread bundle to the instruction scheduler after all instructions in each thread bundle have been updated. Alternatively, it can be configured to output each instruction to the instruction scheduler after it has been updated. The instruction scheduler determines the source operand multiplexing status of an instruction based on the multiplexing flag carried by the instruction. This is how the source operand multiplexing status of an instruction is communicated to the instruction scheduler.

[0095] The compiler module can also choose not to update the instructions in the thread bundle, but instead record the source operand reuse status of each instruction using an array. For example, each thread bundle corresponds to an array, with each row of the array corresponding to one instruction in the thread bundle and each column corresponding to the address of a source operand of the instruction. Taking the instruction corresponding to any row as the first instruction, if a source operand address of the first instruction is reused by at least one subsequent second instruction, the value of the element corresponding to the source operand address in that row is set to 1; if a source operand address of the first instruction is not reused by at least one subsequent second instruction, the value of the element corresponding to the source operand address in that row is set to 0. The array corresponding to the thread bundle is sent to the instruction scheduler, which can determine the source operand reuse status of the instruction based on the array. This method can also be used to transmit the source operand reuse status of the instruction to the instruction scheduler. This embodiment of the present disclosure does not limit the specific method by which the compiler module transmits the source operand reuse status of the instruction to the instruction scheduler.

[0096] The instruction scheduler is responsible for scheduling instruction sets to register fetch locations. Specifically, if the instruction scheduler determines that in a given thread bundle, the source operand address of the first instruction is multiplexed by at least one second instruction following the first instruction, it may choose to schedule the first instruction and at least one second instruction consecutively to register fetch locations. This allows instructions that multiplex the same source operand as the first instruction to be scheduled earlier.

[0097] The register fetch unit is also used to output instructions and their corresponding source operands to the execution unit. The register fetch unit first checks whether the cache unit stores the source operands of the instruction. If the source operands are not stored in the cache unit, it needs to access the registers to fetch them and write the fetched operands into the cache unit. If the source operands are already stored in the cache unit, it is not necessary to access the registers again.

[0098] When the source operand address of the first instruction is reused by at least one second instruction following the first instruction, the instruction scheduler will schedule the first instruction and at least one second instruction to the register read unit consecutively. Therefore, the probability of consecutive instructions received by the register reuse the same source operand address is greatly increased, the cache hit rate is improved, and the number of register accesses is reduced.

[0099] For example, the instruction scheduler schedules instructions Instr1, Instr2, and Instr3 consecutively to the register fetch unit. During the processing of instruction Instr1, the register fetch unit uses a cache to store the source operands corresponding to source operand addresses R0, R1, and R2. When the register fetch unit receives instruction Instr2, it finds that the cache already stores the source operand corresponding to source operand address R2 in instruction Instr2, and therefore does not need to access the register to fetch the source operand corresponding to source operand address R2.

[0100] Due to the data locality of instructions, when the second instruction is closer to the first instruction, the second instruction is more likely to include the same source operand as the first instruction. Furthermore, when the first instruction and at least one second instruction are consecutively scheduled to the register read unit, the second instruction that is closer to the first instruction is scheduled earlier, resulting in higher data utilization of the cache.

[0101] For example, when the instruction scheduler schedules instructions Instr1, Instr2, and Instr3 consecutively, the scheduling order can be Instr1, Instr2, and Instr3.

[0102] An instruction processing apparatus according to an embodiment of the present disclosure includes an instruction scheduler and a register fetch unit. The register fetch unit includes a cache unit. The instruction scheduler is configured to, when at least one source operand address of a first instruction is reused by at least one second instruction following the first instruction, consecutively schedule a first instruction and at least one second instruction to the register fetch unit; the first instruction and the second instruction correspond to the same thread bundle; the register fetch unit is configured to, during the processing of the first instruction, cache the source operand of the first instruction in the cache unit, and during the processing of the second instruction, reuse the source operand cached in the cache unit. By storing the reusable source operand of the first instruction in the cache unit, it is possible to reduce the number of register accesses when processing a second instruction using the same source operand. By prioritizing the scheduling of instructions that reuse the source operands stored in the cache unit, the cache hit rate can be improved, further reducing the number of register accesses. Therefore, the instruction processing apparatus of the present disclosure can reduce the number of register accesses, reduce register access conflicts, shorten instruction execution latency, and improve processor performance.

[0103] In one possible implementation, the instruction scheduler is used to schedule the first instruction and at least one second instruction consecutively to the register read unit when the source operand address in the first instruction carries a multiplexing identifier.

[0104] For example, as described above, the compiler module can add a reuse flag to the source operand address that is reused in the first instruction. When the instruction scheduler recognizes that the source operand address in the first instruction carries a reuse flag, it can determine that at least one source operand address of the first instruction is reused by at least one second instruction following the first instruction, and schedule the first instruction and at least one second instruction consecutively to the register read unit.

[0105] In one possible implementation, the register read unit is used to, in response to receiving a third instruction, detect whether the source operand of the third instruction is stored in the cache unit; the third instruction is any one of the first instruction and at least one second instruction; read the source operand of the third instruction that is not stored in the cache unit from the register; and store the read source operand into the cache unit.

[0106] For example, each time the register read unit receives a third instruction, it can check whether the cache unit stores each source operand of the third instruction. The third instruction is any one of the first instruction and at least one second instruction.

[0107] If the cache unit stores a source operand of the third instruction, there is no need to access the register to retrieve that source operand. If the cache unit does not store a source operand of the third instruction, the register can be accessed to retrieve that source operand. In other words, the register fetch unit will read the source operand of the third instruction that is not stored in the cache unit from the register.

[0108] The register read unit can store the read source operand into the cache unit to improve the cache hit rate.

[0109] The following describes an exemplary method for the register read unit to detect whether the source operand of a third instruction is stored in the cache unit.

[0110] In one possible implementation, the cache unit includes multiple cache lines, and the register read unit is used to detect in parallel whether the source operand of the third instruction is stored in the multiple cache lines.

[0111] This method can improve detection efficiency.

[0112] In one possible implementation, each cache line includes multiple source operand storage locations, where the address of the x-th source operand of the third instruction corresponds to the x-th source operand storage location, and x is a positive integer. The register read unit is used to detect whether the x-th source operand of the third instruction is stored at the x-th source operand storage location in each cache line. x is an integer greater than or equal to 1.

[0113] Figure 3 A schematic diagram showing the structure of a cache unit according to an embodiment of the present disclosure is provided.

[0114] like Figure 3 As shown, the cache unit includes 2 (M=2) cache lines, and each cache line includes 3 (N=3) source operand storage locations. In this case, the cache unit can store a maximum of 6 source operands. The number of cache lines and the number of source operand storage locations per cache line can be set according to application requirements, and this embodiment does not impose any limitations on this.

[0115] The address of the x-th source operand in the third instruction corresponds to the storage location of the x-th source operand in each cache line. That is, the x-th source operand in the instruction will only be stored in the x-th storage location of a given cache line. In this case, the register read unit simply checks whether the x-th source operand of the third instruction is stored at the x-th source operand storage location in each cache line. The register read unit can check the x-th source operand storage locations in multiple cache lines in parallel.

[0116] by Figure 3For example, after the Instr1 instruction is processed, the source operand corresponding to source operand address R0 (e.g., A0) is stored in the first source operand storage location of the first cache line, the source operand corresponding to source operand address R1 (e.g., A1) is stored in the second source operand storage location of the first cache line, and the source operand corresponding to source operand address R2 (e.g., A2) is stored in the third source operand storage location of the first cache line.

[0117] When processing the Instr2 instruction, you can first check the storage location of the first (x=1) source operand in two cache lines in parallel, targeting the source operand address R1 in the Instr2 instruction. See also Figure 3 The detection results show that the source operand corresponding to source operand address R1 is not stored at the first source operand storage location in either of the two cache lines. Therefore, the detection continues for the source operand address R4 in instruction Instr2, checking the second (x=2) source operand storage location in both cache lines in parallel. See [link to documentation]. Figure 3 The detection results showed that the source operand corresponding to source operand address R4 was not stored at the second source operand storage location in either of the two cache lines. Continuing with the source operand address R2 in instruction Instr2, the storage location of the third (x=3) source operand in both cache lines was detected in parallel. See [link to documentation]. Figure 3 The detection result indicates that the source operand corresponding to source operand address R2 is stored at the storage location of the third source operand in the first cache line. Therefore, the source operands corresponding to source operand addresses R1 and R4 are read from the register and stored in the cache unit.

[0118] This approach reduces the number of tests, is more friendly to hardware design and timing, requires fewer physical connections, and occupies less chip area.

[0119] In one possible implementation, each cache line includes multiple source operand storage locations, and the register read unit is used to detect whether a source operand of a third instruction is stored at each source operand storage location in each cache line.

[0120] For example, each cache line includes multiple source operand storage locations; an exemplary structure can be found in [reference needed]. Figure 3 There is no restriction that the x-th source operand of an instruction must be stored in a specific source operand storage location; the x-th source operand of an instruction may be stored in any source operand storage location in the cache unit. Accordingly, the register read unit can check whether the source operand of the third instruction is stored at each source operand storage location in each cache line.

[0121] In one possible implementation, the register read unit is used to detect whether the source operand of the third instruction is stored at the k-th source operand storage location in each cache line, where k is an integer greater than 0 and less than or equal to N; if the source operand of the third instruction is not detected at the k-th source operand storage location in all cache lines, the unit continues to detect whether the source operand of the third instruction is stored at the (k+1)-th source operand storage location in each cache line.

[0122] by Figure 3 For example, after the Instr1 instruction is processed, the source operand corresponding to source operand address R0 (e.g., A0) is stored in the first source operand storage location of the first cache line, the source operand corresponding to source operand address R1 (e.g., A1) is stored in the second source operand storage location of the first cache line, and the source operand corresponding to source operand address R2 (e.g., A2) is stored in the third source operand storage location of the first cache line.

[0123] When processing the instruction Instr2, we can first check the storage location of the first (k=1) source operand in two cache lines in parallel, targeting the source operand address R1 in Instr2. See also Figure 3 If neither of the first source operand storage locations in the two cache lines stores the source operand corresponding to source operand address R1, then the detection of the second (k=2) source operand storage locations in the two cache lines continues in parallel. If the second source operand storage location in the first cache line stores the source operand corresponding to source operand address R11 (e.g., A1), then the detection of the first (k=1) source operand storage location in the two cache lines continues for the source operand address R4 in instruction Instr2.

[0124] Similarly, it is possible to detect whether a cache unit stores each source operand in instruction Instr2.

[0125] This method allows for the detection of more source operand storage locations, increasing the probability of detecting source operands of third instructions stored in cache units, and reducing the number of register accesses.

[0126] The following describes an exemplary method by which the register read unit stores the read source operand into the cache unit.

[0127] In one possible implementation, each cache line includes multiple source operand storage locations and multiple tag storage locations, with each tag storage location corresponding one-to-one with a source operand storage location. The register read unit is further configured to, for each source operand read, select a source operand storage location from the allowed source operand storage locations and write the read source operand to the selected source operand storage location; when the source operand address corresponding to the read source operand is reused, write a reuse identifier to the tag storage location corresponding to the selected source operand storage location, the reuse identifier being used to indicate that the selected source operand storage location stores the reused source operand.

[0128] For example, each cache line may include multiple source operand storage locations and multiple tag storage locations, with each tag storage location corresponding one-to-one with a source operand storage location.

[0129] Figure 4a This diagram illustrates the data storage situation before the cache unit processing instruction Instr1 according to an embodiment of the present disclosure.

[0130] Figure 4b This diagram illustrates the data storage situation after the cache unit processing instruction Instr1 according to an embodiment of the present disclosure.

[0131] Figure 4c This diagram illustrates another instance of data storage following the Instr1 instruction of the cache unit processing according to an embodiment of the present disclosure.

[0132] like Figures 4a-4c As shown, the cache unit includes 2 (M=2) cache lines, and each cache line includes 3 (N=3) source operand storage locations and 3 tag storage locations. The source operand storage locations are used to store the source operands, and the tag storage locations are used to store the tags of the source operands. At this time, the cache unit can store a maximum of 6 source operands and 6 tags. Each tag may include at least one tag.

[0133] The allowed source operand storage locations can be preset. The register read unit can select a source operand storage location from the allowed locations and write the read source operand to the selected location.

[0134] In one example, each source operand is allowed to be written to one of the source operand storage locations in the cache unit. For example, it can be preset that the second source operand of each instruction is allowed to be written to the second source operand storage location of any cache line. Then, for any instruction's second source operand, when you want to write the source operand to the storage unit, the allowed source operand storage location is the second source operand storage location of each cache line.

[0135] In another example, each source operand can be written to one of the full source operand storage locations in the cache unit. For instance, when writing the second source operand of any instruction to a storage unit, the allowed source operand storage locations are the full source operand storage locations for each cache line.

[0136] When the address of the source operand corresponding to the read source operand is reused, the reused source operand is written to the selected source operand storage location. The reuse identifier can be used as a tag and written to the tag storage location corresponding to the selected source operand storage location. In this way, the register read unit can distinguish which source operand storage locations store source operands that will be reused soon and which source operand storage locations store source operands that will not be reused soon.

[0137] In one possible implementation, the register read unit is used to: select any free source operand storage location when there is a free source operand storage location among the allowed source operand storage locations; and select any source operand storage location whose corresponding tag storage location does not store the multiplexing identifier when there is no free source operand storage location among the allowed source operand storage locations.

[0138] If a free source operand storage location exists among the allowed selections, it should be chosen preferentially. If no free source operand storage location exists among the allowed selections, the read source operand will overwrite the original source operand stored in that location, regardless of which location is selected. In this case, overwriting source operands that will not be reused in the near future can achieve a higher cache hit rate. As mentioned above, if a tag storage location stores a reuse identifier, it means that the corresponding source operand storage location stores a reused source operand. Therefore, among the allowed selections, any source operand storage location that does not store a reuse identifier should be chosen preferentially.

[0139] In one example, the tags stored in the tag storage location may also include timestamps to indicate the time when the source operand storage location corresponding to that tag storage location was last written to the source operand. If there are no free source operand storage locations among the allowed selections, and the corresponding tag storage locations all store reuse identifiers, the source operand storage location where the source operand was first stored can be selected to store the read source operand based on the timestamps stored in each tag storage location corresponding to the allowed selections. Due to data locality, the reuse probability of source operands stored earlier in the cache unit is lower than that of source operands stored later in the cache unit, thereby improving the cache unit hit rate.

[0140] In one possible implementation, the x-th source operand address of the third instruction corresponds to the x-th source operand storage location and the x-th tag storage location, where x is a positive integer; when the source operand read corresponds to the x-th source operand address, the allowed source operand storage locations include the x-th source operand storage location of each cache line.

[0141] As mentioned above, selecting a suitable source operand storage location from the allowed choices requires determining whether the source operand location is free and whether the corresponding tag storage location has a reuse flag. Therefore, when the number of allowed source operand storage locations is limited, the implementation complexity of selecting a suitable source operand storage location is lower. Based on this, when the read source operand corresponds to the x-th source operand address, the allowed source operand storage locations can be set to include the x-th source operand storage location of each cache line.

[0142] Suppose that during the processing of the instruction Instr1, the register read unit reads source operand A0 (the first source operand address of instruction Instr1) from the register, source operand A1 (the second source operand address of instruction Instr1) from the register, and source operand A2 (the third source operand address of instruction Instr1) from the register. The register read unit needs to store source operands A0, A1, and A2 into the cache unit.

[0143] See Figure 4a Before processing the Instr1 instruction, the source operands stored in the cache unit include source operand A11, source operand A21, and source operand A31.

[0144] For source operand A0, the allowed source operand storage location is the first source operand storage location of the two cache lines. Since the first source operand storage locations of the two cache lines are not idle, and the first tag storage location of the first cache line does not store a reuse identifier, source operand A0 can be stored in the first source operand storage location of the first cache line, overwriting the source operand A11 originally stored in that location. Source operand address R0 is the address of the reused source operand, and the reuse identifier can be stored in the first tag storage location of the first cache line.

[0145] For source operand A1, the allowed source operand storage location is the second source operand storage location within two cache lines. Since the second source operand storage location in the first cache line is free, source operand A1 can be stored in the second source operand storage location of the first cache line. Source operand address R1 is not the address of a reused source operand; therefore, the reuse flag is not stored in the second tag storage location of the first cache line.

[0146] For source operand A2, the allowed source operand storage location is the third source operand storage location of the two cache lines. Since the third source operand storage locations of the two cache lines are both free, source operand A2 can be stored in the third source operand storage location of the first cache line. The source operand address R2 is the address of the reused source operand, and the reuse flag can be stored in the third tag storage location of the first cache line.

[0147] After the Instr1 instruction is processed, the data storage status of the cache unit is as follows: Figure 4b As shown.

[0148] In one possible implementation, the allowed source operand storage locations include all source operand storage locations of the cache unit.

[0149] It should be understood that, without replacing the source operands already stored in the cache unit, the fewer free source operand storage locations in the cache unit, the higher the cache unit hit rate. Based on this, for any source operand read, the allowed source operand storage locations can be set to include all source operand storage locations in the cache unit.

[0150] Suppose that during the processing of the instruction Instr1, the register read unit reads source operand A0 (the first source operand address of instruction Instr1) from the register, source operand A1 (the second source operand address of instruction Instr1) from the register, and source operand A2 (the third source operand address of instruction Instr1) from the register. The register read unit needs to store source operands A0, A1, and A2 into the cache unit.

[0151] See Figure 4a Before processing the Instr1 instruction, the source operands stored in the cache unit include source operand A11, source operand A21, and source operand A31. In the cache unit, the storage locations of the second and third source operands in the first cache line and the storage location of the third source operand in the second cache line are free.

[0152] The source operand A0 can be stored in the second source operand storage location of the first cache line. The source operand address R0 is the address of the reused source operand. The reuse identifier can be stored in the second tag storage location of the first cache line.

[0153] The source operand A1 can be stored in the third source operand storage location of the first cache line. If the source operand address R1 is not the address of the reused source operand, the reuse flag will not be stored in the third tag storage location of the first cache line.

[0154] The source operand A2 can be stored in the third source operand storage location of the second cache line. The source operand address R2 is the address of the reused source operand. The reuse identifier can be stored in the third tag storage location of the second cache line.

[0155] After the Instr1 instruction is processed, the data storage status of the cache unit is as follows: Figure 4c As shown. and Figure 4b In contrast, the source operand A11 was not overwritten, therefore Figure 4c The cache unit shown stores more source operands and has a higher hit rate.

[0156] The following describes an exemplary method for managing the reuse identifier in the cache unit by the register read unit.

[0157] In one possible implementation, the register read unit is further configured to, when detecting that any source operand storage location stores the source operand of the third instruction and the source operand address corresponding to the source operand is not reused, clear the reuse flag when the tag storage location corresponding to the source operand storage location stores a reuse flag.

[0158] For example, as mentioned above, instructions Instr1 through Instr3 are consecutively scheduled to the register read unit. The register read unit can determine that the source operand address R2 in instruction Instr1 is reused by instruction Instr2 but not by instruction Instr3. In other words, after instruction Instr1 completes execution, the source operand corresponding to source operand address R2 (e.g., source operand A2) will be reused for instruction Instr2 for a short period. In this case, retaining the source operand corresponding to source operand address R2 in the cache unit is more efficient in reducing register accesses. After instruction Instr2 completes execution, the source operand corresponding to source operand address R2 will not be reused for instruction Instr3, and retaining the source operand corresponding to source operand address R2 in the cache unit is less efficient in reducing register accesses.

[0159] Therefore, when the register read unit processes the Instr2 instruction, if it detects that any source operand storage location stores the source operand A2 and the source operand address R2 corresponding to the source operand A2 is not reused, the reuse flag can be cleared if the tag storage location corresponding to the source operand storage location stores a reuse flag.

[0160] by Figure 4b For example, after the register read unit processes the instruction Instr1, the source operand A2 corresponding to the source operand address R2 is stored in the third source operand storage location of the first cache line, and the third tag storage location of the first cache line stores the reuse identifier.

[0161] When the register read unit processes the Instr2 instruction, it can determine that the source operand address R2 is not reused. The register read unit will detect that the source operand A2 is stored at the third source operand storage location of the first cache line, and that a reuse flag is stored at the third tag storage location of the first cache line. At this time, the reuse flag stored at the third tag storage location of the first cache line can be cleared.

[0162] In this case, other source operands read from the register can overwrite the source operand stored at the third source operand storage location of the first cache line, thereby improving the efficiency of the cache unit in reducing the number of register accesses.

[0163] In one possible implementation, the register read unit is further configured to, when detecting that any source operand storage location stores the source operand of the third instruction and the source operand address corresponding to the source operand is reused, write the reuse flag to the tag storage location if the tag storage location corresponding to the source operand storage location does not store the reuse flag.

[0164] For example, as mentioned above, when a source operand stored at a certain source operand storage location is no longer reused, the reuse flag stored in the tag storage location corresponding to that source operand storage location can be cleared. Conversely, if the reuse flag stored in the tag storage location corresponding to a certain source operand storage location is cleared, and the source operand stored at that source operand storage location is reused before other source operands are written to that source operand storage location, then the reuse flag can be re-added at the tag storage location corresponding to that source operand storage location.

[0165] For example, suppose the data storage in the cache unit is as follows before processing the third instruction: Figure 4aAs shown. Upon responding to the third instruction, it is discovered that the address of the x-th source operand is reused, and the source operand A11 corresponding to that source operand address is stored in the first source operand storage location of the first cache line. Since the reuse identifier is not stored in the first tag storage location of the first cache line, the reuse identifier is written to that tag storage location.

[0166] This method prevents reused source operands from being overwritten by other source operands, thus improving cache hit rate.

[0167] In one possible implementation, the register read unit is also used to clear the source operands corresponding to the thread bundle stored in the cache unit after the last instruction in any thread bundle has been executed.

[0168] For example, the instruction set includes multiple thread bundles, each of which is scheduled to and processed by the register read unit. To avoid passing incorrect source operands to the execution unit, the register read unit is also used to clear the source operands corresponding to the thread bundle stored in the cache unit after the last instruction in any thread bundle has been executed.

[0169] Similarly, if the currently processed instruction is found to be a jump instruction, or if the instruction contains an error, the source operand of the instruction cannot be obtained, or the activity mask of the execution unit (indicating whether the execution unit is active) is inconsistent with the actual activity of the execution unit, the cache unit can also be cleared.

[0170] In this way, the correctness of the source operands obtained by the execution unit can be guaranteed.

[0171] In one possible implementation, the first instruction and the second instruction correspond to different types of pipelines.

[0172] The same thread bundle includes instructions corresponding to different types of pipelines. Embodiments of this disclosure support the reuse of source operand addresses between instructions corresponding to different types of pipelines. For example, operands can be reused between a floating-point (FOP) pipeline and an integer (INT) pipeline, or between a floating-point pipeline and a type conversion (CVT) pipeline. The first instruction and the second instruction correspond to different types of pipelines.

[0173] In one example, the thread bundle includes instructions Instr11 and Instr12. Wherein:

[0174] Instr11: FMA R3, R0, R1, R2;

[0175] Instr12: IADD R4, R0, null, R2.

[0176] FMA indicates that the source operand is a floating-point number, and multiplication and addition operations are performed on the source operand. IADD indicates that the source operand is an integer, and addition operations are performed on the source operand. null indicates that there is no source operand address at this location.

[0177] The source operand addresses for the Instr11 instruction include R0, R1, and R2, and the destination operand address includes R3.

[0178] The source operand addresses for the Instr12 instruction include R0 and R2, and the destination operand address includes R4.

[0179] The compiler module can update the instructions in the thread bundle, and the instructions in the thread bundle are updated to:

[0180] Instr11: FMA R3, R0.reuse, R1, R2.reuse;

[0181] Instr12: IADD R4, R0, null, R2.

[0182] Instr11 is a floating-point pipeline instruction, and Instr12 is an integer pipeline instruction. This approach can further reduce repeated reads of registers, thereby reducing register bank conflicts and improving overall execution efficiency.

[0183] In one example, the type of register to be reused can be configured, not only as a vector register, but also as a constant register, a scaler register, or any other type of register. This disclosure does not limit this.

[0184] It should be understood that the first instruction and the second instruction can also correspond to the same type of pipeline. For example, the instructions Instr1, Instr2, and Instr3 in the example above are instructions corresponding to the same type of pipeline (floating-point arithmetic). This disclosure does not limit the specific type of pipeline corresponding to the first instruction and the second instruction.

[0185] In one possible implementation, the register read unit is further configured to, after writing the read source operand to the selected source operand storage location, store at least one of the following: the type of the register storing the source operand, the offset of the source operand in the instruction, and the number of the current thread bundle, into the tag storage location corresponding to the selected source operand storage location; the type, offset, and number stored in any tag storage location are used to detect whether the source operand stored in the corresponding source operand storage location is the source operand of the third instruction.

[0186] For example, after the register read unit writes the read source operand to the selected source operand storage location, it stores at least one of the following as tags in the tag storage location corresponding to the source operand storage location: the type of the register storing the source operand (e.g., constant register / scalar register / vector register), the offset of the source operand in the instruction (e.g., the 1st / 2nd / 3rd source operand in the instruction), and the number of the current thread bundle.

[0187] Specifically, the type, offset, and number stored in any tag storage location are used to detect whether the source operand stored in the corresponding source operand storage location is the source operand of the third instruction. For example, the address of a source operand in the third instruction can indicate the type of the register storing the source operand corresponding to that address. If the type indicated by the source operand address matches the type stored in the tag storage location, the offset of the source operand in the instruction also matches the offset stored in the tag storage location, and the number of the current thread bundle also matches the number stored in the tag storage location, then the source operand stored in the source operand storage location corresponding to the tag storage location is considered to be the source operand of the third instruction.

[0188] Those skilled in the art will understand that, in practical applications, using tags to detect whether the source operand stored at the source operand storage location is the source operand of the third instruction can also be implemented in other existing ways. For example, if the type indicated by the source operand address matches the type stored at the tag storage location, and the current thread bundle number also matches the number stored at the tag storage location, then the source operand stored at the source operand storage location corresponding to the tag storage location is considered to be the source operand of the third instruction.

[0189] Those skilled in the art will understand that, in practical applications, the tag storage location can store more or fewer tags. For example, the tag storage location can also store an active mask indicating whether the execution unit is active. When the active mask indicates that the execution unit is active, the third instruction is then processed. This disclosure does not limit the content stored in the tag storage location, as long as the tags stored in the tag storage location can be used to accurately detect whether the corresponding source operand stored in the source operand storage location is the source operand of the third instruction.

[0190] This disclosure also proposes an instruction processing method. Figure 5 A schematic diagram illustrating the flow of an instruction processing method according to an embodiment of the present disclosure is shown.

[0191] like Figure 5 As shown, in one possible implementation, the method is applied to an instruction processing apparatus, which includes an instruction scheduler and a register fetch unit, the register fetch unit including a cache unit, and the method includes:

[0192] In step S51, if the address of at least one source operand of the first instruction is multiplexed by at least one second instruction following the first instruction, the instruction scheduler will schedule the first instruction and at least one second instruction to the register read unit consecutively; the first instruction and the second instruction correspond to the same thread bundle.

[0193] In step S52, the register read unit caches the source operand of the first instruction in the cache unit during the processing of the first instruction, and reuses the source operand cached in the cache unit during the processing of the second instruction.

[0194] In one possible implementation, the method further includes: when the source operand address in the first instruction carries a multiplexing identifier, the instruction scheduler schedules the first instruction and at least one second instruction consecutively to the register read unit.

[0195] In one possible implementation, the method further includes: in response to receiving a third instruction, the register read unit detects whether the source operand of the third instruction is stored in the cache unit; the third instruction is any one of the first instruction and at least one second instruction; reads the source operand of the third instruction that is not stored in the cache unit from the register; and stores the read source operand into the cache unit.

[0196] In one possible implementation, the cache unit includes multiple cache lines, and detecting whether the source operand of the third instruction is stored in the cache unit includes: detecting whether the source operand of the third instruction is stored in multiple cache lines in parallel.

[0197] In one possible implementation, each cache line includes multiple source operand storage locations, where the address of the xth source operand of the third instruction corresponds to the xth source operand storage location, and x is a positive integer; detecting whether the source operand of the third instruction is stored in the cache unit includes: detecting whether the xth source operand of the third instruction is stored at the xth source operand storage location in each cache line.

[0198] In one possible implementation, each cache line includes multiple source operand storage locations. Detecting whether a source operand of a third instruction is stored in a cache unit includes: at each source operand storage location in each cache line, detecting whether a source operand of a third instruction is stored.

[0199] In one possible implementation, at each source operand storage location in each cache line, it is checked whether a source operand of a third instruction is stored, including: at the k-th source operand storage location in each cache line, it is checked whether a source operand of a third instruction is stored, where k is an integer greater than 0 and less than or equal to N; if no source operand of a third instruction is detected at the k-th source operand storage location in all cache lines, it is continued to check whether a source operand of a third instruction is stored at the (k+1)-th source operand storage location in each cache line.

[0200] In one possible implementation, each cache line includes multiple source operand storage locations and multiple tag storage locations, with each tag storage location corresponding one-to-one with a source operand storage location. Storing read source operands into the cache unit includes: for each read source operand, selecting a source operand storage location from the allowed selections, and writing the read source operand to the selected source operand storage location; when the source operand address corresponding to the read source operand is reused, writing a reuse identifier to the tag storage location corresponding to the selected source operand storage location, the reuse identifier indicating that the selected source operand storage location stores the reused source operand.

[0201] In one possible implementation, the x-th source operand address of the third instruction corresponds to the x-th source operand storage location and the x-th tag storage location, where x is a positive integer; when the source operand read corresponds to the x-th source operand address, the allowed source operand storage locations include the x-th source operand storage location of each cache line.

[0202] In one possible implementation, the allowed source operand storage locations include all source operand storage locations of the cache unit.

[0203] In one possible implementation, selecting a source operand storage location from the allowed source operand storage locations includes: if there is a free source operand storage location among the allowed source operand storage locations, selecting any free source operand storage location; if there is no free source operand storage location among the allowed source operand storage locations, selecting any source operand storage location whose corresponding tag storage location does not store a reuse identifier.

[0204] In one possible implementation, the method further includes: when it is detected that any source operand storage location stores the source operand of the third instruction, and the source operand address corresponding to the source operand is not reused, the register read unit clears the reuse flag when the tag storage location corresponding to the source operand storage location stores a reuse flag.

[0205] In one possible implementation, the method further includes: when it is detected that any source operand storage location stores the source operand of the third instruction, and the source operand address corresponding to the source operand is reused, the register read unit writes the reuse flag to the tag storage location when the tag storage location corresponding to the source operand storage location does not store the reuse flag.

[0206] In one possible implementation, the method further includes: after the last instruction in any thread bundle has been executed, the register read unit clears the source operands corresponding to the thread bundle stored in the cache unit.

[0207] In one possible implementation, the first instruction and the second instruction correspond to different types of pipelines.

[0208] In one possible implementation, the method further includes: after writing the read source operand to the selected source operand storage location, the register reading unit stores at least one of the following: the type of the register storing the source operand, the offset of the source operand in the instruction, and the number of the current thread bundle, into the tag storage location corresponding to the selected source operand storage location; the type, offset, and number stored in any tag storage location are used to detect whether the source operand stored in the corresponding source operand storage location is the source operand of the third instruction.

[0209] In some embodiments, the specific implementation of the method provided in this disclosure can be referred to the description of the device embodiments above, and for the sake of brevity, it will not be repeated here.

[0210] This disclosure also proposes an instruction processing system. Figure 6 A schematic diagram showing the structure of an instruction processing system according to an embodiment of the present disclosure is provided.

[0211] like Figure 6 As shown, in one possible implementation, the system includes a compilation module and an instruction processing unit. The unit includes an instruction scheduler and a register fetch unit, and the register fetch unit includes a cache unit.

[0212] The compiler module is used to identify the addresses of the source operands that are reused in the first instruction;

[0213] The instruction scheduler is used to schedule a first instruction and at least one second instruction consecutively to a register read unit when at least one source operand address of a first instruction is multiplexed by at least one second instruction following the first instruction.

[0214] The register read unit is used to cache the source operand of the first instruction in the cache unit during the processing of the first instruction, and to reuse the source operand cached in the cache unit during the processing of the second instruction.

[0215] In one possible implementation, the compiler module is used to add a reuse flag at the address of the identified source operand;

[0216] The instruction scheduler is used to determine, when any source operand address of the first instruction carries a multiplexing identifier, that the source operand address is multiplexed by at least one second instruction following the first instruction.

[0217] Examples of the working functions of the compiler module, instruction scheduler, and register fetch unit can be found above. Figures 1-5 Related descriptions.

[0218] This disclosure also proposes a processor including the instruction processing apparatus described above. The processor may be a graphics processor or other processor capable of executing instructions including source operands; this disclosure does not limit the specific type of processor.

[0219] This disclosure also proposes an electronic device, including the instruction processor or instruction processing system described above. The electronic device may be a terminal device or a server; this disclosure does not limit the specific type of electronic device.

[0220] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0221] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An instruction processing device, characterized in that, The device includes an instruction scheduler and a register read unit, the register read unit including a cache unit. The instruction scheduler is configured to, when at least one source operand address of a first instruction is multiplexed by at least one second instruction following the first instruction, consecutively schedule the first instruction and at least one second instruction to the register read unit. The first instruction and the second instruction correspond to the same thread bundle; The register read unit is used to cache the source operands of the first instruction in the cache unit during the processing of the first instruction, and to reuse the source operands cached in the cache unit during the processing of the second instruction.

2. The apparatus according to claim 1, characterized in that, The instruction scheduler is used to schedule the first instruction and at least one second instruction consecutively to the register read unit when the source operand address in the first instruction carries a multiplexing identifier.

3. The apparatus according to claim 1, characterized in that, The register read unit is used for, In response to receiving a third instruction, it is detected whether the source operand of the third instruction is stored in the cache unit; the third instruction is any one of the first instruction and at least one of the second instructions; Read the source operand of the third instruction that is not stored in the cache unit from the register; The read source operands are stored in the cache unit.

4. The apparatus according to claim 3, characterized in that, The cache unit includes multiple cache lines, and the register read unit is used for... The source operand of the third instruction is detected in parallel in the multiple cache lines.

5. The apparatus according to claim 3, characterized in that, Each cache line includes multiple source operand storage locations, where the address of the x-th source operand of the third instruction corresponds to the x-th source operand storage location, and x is a positive integer; the register read unit is used for, At the storage location of the xth source operand in each cache line, check whether the xth source operand of the third instruction is stored.

6. The apparatus according to claim 3, characterized in that, Each cache line includes multiple source operand storage locations, and the register read unit is used for... At each source operand storage location in each cache line, check whether the source operand of the third instruction is stored.

7. The apparatus according to claim 6, characterized in that, The register read unit is used for, At the k-th source operand storage location in each cache line, check whether the source operand of the third instruction is stored, where k is an integer greater than 0 and less than or equal to N; If the source operand of the third instruction is not detected at the k-th source operand storage location in all cache lines, continue to check whether the source operand of the third instruction is stored at the (k+1)-th source operand storage location in each cache line.

8. The apparatus according to claim 4, characterized in that, Each cache line includes multiple source operand storage locations and multiple tag storage locations, wherein the multiple tag storage locations correspond one-to-one with the multiple source operand storage locations. The register read unit is also used for... For each source operand read, select a source operand storage location from the allowed source operand storage locations, and write the read source operand to the selected source operand storage location; When the source operand address corresponding to the read source operand is reused, a reuse identifier is written to the tag storage location corresponding to the selected source operand storage location. The reuse identifier is used to indicate that the selected source operand storage location stores the reused source operand.

9. The apparatus according to claim 8, characterized in that, The address of the xth source operand of the third instruction corresponds to the storage location of the xth source operand and the storage location of the xth tag, where x is a positive integer; When the source operand read corresponds to the address of the xth source operand, the allowed source operand storage locations include the xth source operand storage location of each cache line.

10. The apparatus according to claim 8, characterized in that, The allowed source operand storage locations include all source operand storage locations of the cache unit.

11. The apparatus according to any one of claims 8-10, characterized in that, The register read unit is used for, If there is a free source operand storage location among the allowed source operand storage locations, select any free source operand storage location; If there is no free source operand storage location among the allowed source operand storage locations, select any source operand storage location that does not store the reuse identifier in the corresponding tag storage location.

12. The apparatus according to claim 8, characterized in that, The register reading unit is also used for, If a source operand of the third instruction is detected in any source operand storage location, and the source operand address corresponding to the source operand is not reused, the reuse identifier is cleared when the tag storage location corresponding to the source operand storage location stores the reuse identifier.

13. The apparatus according to claim 8, characterized in that, The register reading unit is also used for, If it is detected that the source operand of the third instruction is stored in any source operand storage location, and the source operand address corresponding to the source operand is reused, the reuse identifier is written to the tag storage location if the tag storage location corresponding to the source operand storage location does not store the reuse identifier.

14. The apparatus according to claim 1, characterized in that, The register reading unit is also used for, After the last instruction in any thread bundle has been executed, the source operands corresponding to the thread bundle stored in the cache unit are cleared.

15. The apparatus according to claim 1, characterized in that, The first instruction and the second instruction correspond to different types of pipelines.

16. The apparatus according to claim 9, characterized in that, The register reading unit is also used for, After writing the read source operand to the selected source operand storage location, at least one of the following is stored in the tag storage location corresponding to the selected source operand storage location: the type of the register storing the source operand, the offset of the source operand in the instruction, and the number of the current thread bundle. The type, offset, and number stored in any tag storage location are used to detect whether the source operand stored in the corresponding source operand storage location is the source operand of the third instruction.

17. An instruction processing system, characterized in that, The system includes a compilation module and an instruction processing unit. The instruction processing unit includes an instruction scheduler and a register reading unit. The register reading unit includes a cache unit. The compilation module is used to identify the addresses of the source operands that are reused in the first instruction; The instruction scheduler is configured to schedule the first instruction and at least one second instruction consecutively to the register read unit when at least one source operand address of the first instruction is multiplexed by at least one second instruction following the first instruction. The first instruction and the second instruction correspond to the same thread bundle; The register read unit is used to cache the source operands of the first instruction in the cache unit during the processing of the first instruction, and to reuse the source operands cached in the cache unit during the processing of the second instruction.

18. The system according to claim 17, characterized in that, The compilation module is used to add a reuse identifier at the address of the identified source operand; The instruction scheduler is configured to determine that, when any source operand address of the first instruction carries the multiplexing identifier, the source operand address is multiplexed by at least one second instruction following the first instruction.

19. A processor, characterized in that, The instruction processing apparatus includes any one of claims 1-16.

20. An electronic device, characterized in that, It includes the instruction processing system of claim 17 or 18, or the processor of claim 19.

21. An instruction processing method, characterized in that, The method is applied to an instruction processing apparatus, the apparatus including an instruction scheduler and a register read unit, the register read unit including a cache unit, the method comprising: If the address of at least one source operand of the first instruction is reused by at least one second instruction following the first instruction, the instruction scheduler will consecutively schedule the first instruction and at least one second instruction to the register read unit; the first instruction and the second instruction correspond to the same thread bundle. The register read unit caches the source operands of the first instruction in the cache unit during the processing of the first instruction, and reuses the cached source operands in the cache unit during the processing of the second instruction.

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