Multicore processor device using multithreading

Abstract

The present invention relates to multi-core processor devices that use multi-threaded processing. Multi-core processors are provided that are configured to improve processing performance in certain computing scenarios. The multi-core processors include a plurality of processing cores that implement bucketed thread processing to execute multiple instruction threads in parallel while ensuring the effects of idle instructions or threads are minimized on the performance of the processor. The plurality of cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate cache coherency issues. The bucketed thread processing can minimize latency effects associated with the shared data cache. In some examples, the multi-core processor can also include a serial processor that is configured to execute single-threaded program code that can not produce satisfactory performance in a processing environment that employs bucketed thread processing.

Description

[0001] This application is a divisional application of the application filed on June 10, 2016, with application number 202111143789.2 and entitled "Multi-core processor device using multi-threaded processing".

[0002] The application filed on June 10, 2016, with application number 202111143789.2 and titled "Multi-core processor device using multi-threaded processing", is a divisional application of the application filed on June 10, 2016, with application number 201680046182.3 and titled "Multi-core processor device using multi-threaded processing". Cross-references to related applications

[0003] This application claims priority to the following patents: U.S. Provisional Patent Serial No. 62 / 173,389, filed June 10, 2015; U.S. Provisional Patent Serial No. 62 / 173,392, filed June 10, 2015; U.S. Provisional Patent Serial No. 62 / 290,383, filed February 2, 2016; U.S. Provisional Patent Serial No. 62 / 290,389, filed February 2, 2016; and U.S. Provisional Patent Serial No. 62 / 290,392, filed February 2, 2016. The entire contents of U.S. Provisional Patent Serial No. 62 / 290,395, filed February 2, 2016; U.S. Provisional Patent Serial No. 62 / 290,400, filed February 2, 2016; U.S. Provisional Patent Serial No. 62 / 293,145, filed February 9, 2016; U.S. Provisional Patent Serial No. 62 / 293,147, filed February 9, 2016; and U.S. Provisional Patent No. 62 / 293,908, filed February 11, 2016, are incorporated herein by reference. Background of this disclosure

[0004] Many types of computer architectures are available. Processor performance is typically evaluated in terms of its speed, efficiency, memory consumption, and power consumption. However, processor performance is highly context-dependent, depending on these factors. A processor can exhibit superior performance in a computing environment where only one thread of instructions is available to be processed at any given time. The same processor may exhibit below-standard performance in computing environments that require multiple threads of instructions to be processed simultaneously. Therefore, adapting the processor architecture to the computing environment in which it will operate can result in improved performance. This improved performance can include, for example, increased computational speed and more efficient use of memory and power.

[0005] The speed at which memory can be accessed is often inversely related to its capacity. Therefore, it can be advantageous to use relatively fast but limited memory (e.g., cache) to store local copies of shared data for processors in a multiprocessor system. This allows processors to perform operations much faster than if they had to rely on accessing data from a relatively large, slow central memory. However, when creating local copies of shared data, there is a significant risk that these copies will become out of sync (or “inconsistent”). This is because processors often run processes that modify the data copies in their local caches, making the original data stored in the slower central memory obsolete. In particular, processes may not update the original copies of the data in external or main memory with their changes before other processes access the data from main memory. This can lead to wasted effort and inefficiency. Perhaps worse, processes can perform operations on obsolete or incorrect data and then write the incorrect results to main or external memory. Other processes can then save the incorrect data to their respective processors' local caches, operate on the incorrect data, and propagate the error throughout the system. This can produce errors that are difficult or impossible to detect.

[0006] Hardware and software systems can be used to address these cache coherence problems. While such systems can successfully handle data coherence, they often introduce inefficiencies into multiprocessor systems. For example, a "fully cache-coherent" system requires additional hardware support to accommodate various frequent data sharing scenarios. Fully cache-coherent systems are typically designed to be flexible in adapting to different scenarios that may occur during data sharing. This additional flexibility requires additional complex hardware. That additional hardware can sometimes slow down operations that do not heavily or frequently rely on data sharing between processes running on different processors.

[0007] Furthermore, processor performance is typically evaluated in terms of its speed, efficiency, memory consumption, and power consumption. However, processor performance based on these factors is highly context-dependent. A processor may exhibit superior performance in a computational environment where only one instruction thread is available to be processed at any given time. The same processor may demonstrate below-standard performance in a computational environment that requires multiple instruction threads to be processed simultaneously. Therefore, adapting the processor architecture to the computational environment in which it will operate can result in improved performance. This improved performance can include, for example, increased computational speed and more efficient use of memory and power.

[0008] As electronic devices become smaller and more mobile, the need for power efficiency (i.e., the ability to perform its functions with minimal power consumption) becomes increasingly important. One way to make electronic devices more power efficient is through power gating. Power gating can refer to the practice of making a device fully or partially idle during periods of inactivity. In electronic devices with embedded memory, power gating can corrupt the memory whenever it is powered on again after a power outage. The power-on process can cause memory errors and may also lead to slow operation of any software / firmware interacting with the memory, as the software may have to wait for the memory to be reinitialized. Therefore, to allow power gating on devices that include memory, memory read operations can be modified to minimize memory errors while allowing for fast reads of the memory after power-on. Overview of this disclosure

[0009] Any combination of any subject matter that can be claimed.

[0010] Any method and / or combination of method steps disclosed in any of the accompanying drawings and / or in the specification may be provided.

[0011] Any combination of any unit, device, and / or component disclosed in any of the accompanying drawings and / or the specification may be provided. Non-limiting examples of such units include collection units, image processors, etc.

[0012] This disclosure relates to a multi-core computer processor that utilizes barrel-style threading and a shared data cache to improve processor performance. This system can be applied, for example, to computational environments in which multiple software loops with largely independent iterations exist. Multi-core processors can achieve performance gains superior to other multi-threaded processing architectures, in part because each core operates on threads using a barrel-style threading approach. Barrel-style threading can be particularly used to mask or hide memory latency (i.e., minimize its impact on efficiency). Minimizing the impact of latency allows the use of a shared data cache. The combination of barrel-style threading and a shared data cache in a multi-core architecture can therefore provide an improved computational environment.

[0013] This disclosure relates to a multi-core computer processor that can utilize instruction chaining by combining, for example, bucket threading and shared data caching. Reducing the number of clock cycles required to process multiple interdependent instructions via instruction chaining can result in faster processing times. This system can be applied in computational environments where multiple software loops with independent iterations exist. Multi-core processors can achieve performance gains superior to other multi-threaded processing architectures, in part because each core operates on threads using a bucket threading approach. Bucket threading can also mask or hide memory latency (i.e., minimize its impact on efficiency). Minimizing the impact of latency allows for the use of more efficiently accessed memory, such as shared data caches. The combination of bucket threading, shared data caching, and instruction chaining in a multi-core architecture can therefore provide an improved computational environment.

[0014] This disclosure relates to systems comprising hardware and / or software that facilitate consistent sharing of data across multiple processor devices. The system may include restricted access to data for concurrently running processes. The system may also include relatively limited or simplified hardware for running systems with such restricted data access. Additionally, the system may include various hardware implementations that store indicators of the write status of copies of data saved to local memory. These systems can be implemented on multi-core computer processors that can utilize bucketed thread processing and shared data caches. The system can be applied to computational environments in which multiple software loops with independent iterations exist. Therefore, the combination of cache-coherent systems, bucketed thread processing, and shared data caches in a multi-core architecture can provide an improved computational environment.

[0015] This disclosure relates to an architecture and method for retrieving data from memory. This disclosure can be used in conjunction with a vector processor to perform clustered memory retrieval, which, among other things, can retrieve data stored at multiple memory locations. The system can be used in conjunction with many other computing systems. For example, the system can be used in conjunction with a computing system containing multiple software loops with independent iterations. This architecture and method can achieve performance gains superior to other architectures and methods, in part, by facilitating nearest-neighbor memory accesses that may lead to increased throughput and / or efficiency.

[0016] This disclosure relates to a processor that can use a data processing subsystem with address generation capabilities. The processor may be a vector processor. The system can be applied in computational environments, for example, where multiple software loops with independent iterations exist. The processor can achieve performance gains superior to other architectures, in part because a dedicated address generation unit can provide addresses to the data processing subsystem for efficient evaluation of data within the loops. The system can achieve pipelined instruction evaluation in the data processing subsystem with higher efficiency and higher throughput.

[0017] This disclosure relates to a multi-core computer processor that utilizes bucket-based threading and a shared data cache to improve processor performance. This system can be applied in computational environments, for example, where multiple software loops with independent iterations exist. Multi-core processors can achieve performance gains superior to other multi-threaded processing architectures, in part because each core operates on threads using a bucket-based threading approach. Bucket-based threading can also be used to mask or hide memory latency (i.e., minimize its impact on efficiency). Minimizing the impact of latency allows for the use of more efficiently accessed memory, such as shared data cache memory. The combination of bucket-based threading and a shared data cache in a multi-core architecture can therefore provide an improved computational environment.

[0018] This disclosure relates to a memory device that can utilize a read mask, which specifies a particular byte within a word to be read. In this way, when a byte of memory specified by the read mask is read, the parity bit associated with the specific byte in memory can be checked to determine if the byte has been corrupted due to a soft error. The read mask can minimize soft errors caused by memory not being initialized after power loss, thus allowing memory reinitialization after a power loss, which can consume a considerable amount of time. Therefore, the read mask can minimize memory soft errors while allowing the memory to be powered on more efficiently.

[0019] According to embodiments of the present invention, a memory device may be provided, which may include a memory module, an error control circuit, and a memory controller. The memory device may include a memory module that is volatile and configured to operate in a reduced power mode and exit the reduced power mode to operate in a normal power mode; an error control circuit; and a memory controller configured to: write a first-size data unit to the memory module after the memory module exits the reduced power mode, wherein the data unit is located within a second-size memory segment; receive a read command to read the data unit from the memory module; read the memory segment content stored in the memory segment; send the memory segment content to the error control circuit; and transmit a read mask to the error control circuit, wherein the read mask indicates one or more redundant bits associated with the data unit; wherein the error control circuit is configured to: receive the memory segment content and the read mask; and check for one or more errors in the data unit based on one or more redundant bits associated with the data unit, while ignoring redundant bits associated with one or more portions of the memory segment content that differ from the data unit. Exiting the reduced power mode does not follow with initialization of the entire memory module.

[0020] Read masks can also indicate the location of data units.

[0021] According to embodiments of the present invention, a memory device may be provided, which may include a memory module, an error control circuit, and a memory controller, configured to: operate in a reduced power mode, return to a normal power mode, write data bytes to the memory module, wherein the data bytes are located in data words stored on the memory module, receive a read command to read data bytes from the memory module, read data words stored on the memory module, transmit a read mask to the error control circuit, and receive a soft error indication from the error control circuit, wherein the soft error indication is based on one or more parity bits associated with the data bytes, and wherein the one or more parity bits associated with the data bytes are determined using one or more parity bits associated with the data words and the transmitted read mask.

[0022] According to embodiments of the present invention, a method for implementing a memory device can be provided, the method comprising: operating a memory controller and a memory module in a reduced power mode; returning the memory controller and memory module to a normal power mode; writing a data byte to the memory module, wherein the data byte is located in a data word stored on the memory module; receiving a read command to read the data byte from the memory module; reading the data word stored on the memory module; transmitting a read mask to an error control circuit; and receiving a soft error indication from the error control circuit, wherein the soft error indication is based on one or more parity bits associated with the data byte, and wherein the one or more parity bits associated with the data byte are determined using one or more parity bits associated with the data word and the transmitted read mask.

[0023] According to embodiments of the present invention, a non-transitory computer-readable storage medium may be provided having stored thereon an instruction set for processing multiple threads of a software program, the instruction set causing the computing device, when executed by a computing device, to: operate a memory controller and a memory module in a reduced power mode; return the memory controller and the memory module to a normal power mode; write data bytes to the memory module, wherein the data bytes are located within data words stored on the memory module; receive a read command to read data bytes from the memory module; read data words stored on the memory module; transmit a read mask to an error control circuit; and receive a soft error indication from the error control circuit, wherein the soft error indication is based on one or more parity bits associated with the data byte, and wherein the one or more parity bits associated with the data byte are determined using one or more parity bits associated with the data word and the transmitted read mask.

[0024] An apparatus may be provided comprising: at least one input register, at least one addressable register, and at least one processing unit configured to generate a histogram by: receiving a data vector via the input register, the data vector comprising a plurality of data points; matching the plurality of data points with a plurality of bars (bins) of the histogram; searching for contention when the plurality of data points include data points belonging to the same bar; when a contention is detected, serially calculating the address of a given memory entry for storing data points belonging to the same bar and storing the data points belonging to the same bar at the given memory entry; and when no contention is detected, parallelly calculating the address of some memory entries for storing the plurality of data points and storing the plurality of data points at some memory entries.

[0025] A method may be provided that generates a histogram by: receiving a data vector via an input register, the data vector comprising a plurality of data points; matching the plurality of data points with a plurality of bars of the histogram; searching for race conditions when the plurality of data points include data points belonging to the same bar; when a race condition is detected, serially calculating the address of a given memory entry for storing data points belonging to the same bar and storing the data points belonging to the same bar at the given memory entry; and when no race condition is detected, parallelly calculating the addresses of certain memory entries for storing the plurality of data points and storing the plurality of data points at certain memory entries.

[0026] A non-transitory computer-readable storage medium may be provided having an instruction set thereon for storing instructions for processing a software program, which, when executed by a computing device, causes the computing device to generate a histogram by: receiving a data vector via an input register, the data vector comprising a plurality of data points; matching the plurality of data points with a plurality of bars in the histogram; searching for race conditions when the plurality of data points include data points belonging to the same bar; when a race condition is detected, serially calculating the address of a given memory entry for storing data points belonging to the same bar and storing the data points belonging to the same bar at the given memory entry; and when no race condition is detected, parallelly calculating the addresses of certain memory entries for storing the plurality of data points and storing the plurality of data points at certain memory entries.

[0027] According to embodiments of the present invention, the following also applies: 1) A multi-core processor device comprising: a plurality of processing cores configured to execute a plurality of threads of a software program using bucket thread processing; and a shared data cache configured to send data to at least two of the plurality of processing cores and receive data from at least two of the plurality of processing cores, the shared data cache storing data associated with the execution of a first instruction in at least one of the plurality of threads, the shared data cache and the plurality of processing cores interacting without relying on a private data cache.

[0028] 2) The device according to 1), wherein the plurality of processing cores comprises: a plurality of thread register files, wherein at least one of the plurality of thread register files is associated with a thread among the plurality of threads; an instruction memory, wherein the instruction memory stores one or more instructions associated with the plurality of threads; one or more arithmetic logic units; and a bucket scheduler, wherein the bucket scheduler receives a first clock signal, loads a first instruction from the one or more instructions from the instruction memory, and executes the first instruction by: retrieving data from a first thread register file, wherein the first thread register file is associated with a thread associated with the first instruction; and sending the received data to the one or more arithmetic logic units for processing.

[0029] 3) The device according to 2), wherein the bucket scheduler receives a second clock signal, loads a second instruction from the one or more instructions from the instruction memory, and executes the second instruction by: retrieving data from a second thread register file, wherein the second thread register file is associated with the thread associated with the second instruction; and sending the received data to the one or more arithmetic logic units for processing.

[0030] 4) The device according to 3), wherein each of the plurality of thread register files is configured to load data associated with the thread associated with the thread register file.

[0031] 5) The device according to 3), wherein the plurality of processing cores execute the plurality of threads simultaneously.

[0032] 6) The device according to 1), wherein one or more of the plurality of processing cores transmit data to and receive data from the shared data cache, and wherein the shared data cache is configured to store data for executing the plurality of threads.

[0033] 7) The device according to 1), including a serial processor configured to execute single-threaded program code.

[0034] 8) A method for processing multiple threads, the multiple threads being instruction program threads, the method comprising: executing the multiple threads using multiple processing cores, wherein the multiple processing cores use bucketed thread processing to execute the multiple threads; and sending data to and receiving data from at least two of the multiple processing cores using a shared data cache, the shared data cache storing data associated with the execution of a first instruction in at least one of the multiple threads, the shared data cache and the multiple processing cores interacting without relying on a private data cache.

[0035] 9) The method according to 8), wherein the method includes: receiving a first clock signal at a bucket scheduler of the plurality of processing cores; loading a first instruction from an instruction memory, wherein the instruction memory stores one or more instructions associated with the plurality of threads; and executing the first instruction by: retrieving data from a first thread register file, wherein the first thread register file is associated with an instruction thread associated with the first instruction, and sending the received data to one or more arithmetic logic units for processing.

[0036] 10) The method according to 9), wherein the bucket scheduler receives a second clock signal, loads a second instruction from the one or more instructions from the instruction memory, and executes the second instruction by: retrieving data from a second thread register, wherein the second thread register file is associated with the thread associated with the second instruction, and sending the received data to the one or more arithmetic logic units for processing.

[0037] 11) The method according to 10), wherein each of the plurality of thread register files loads data associated with the thread associated with the thread register file.

[0038] 12) According to the method described in 10), wherein the plurality of processing cores execute the plurality of threads simultaneously.

[0039] 13) The method according to 8), wherein one or more of the plurality of processing cores transmit data to and receive data from the shared data cache, and wherein the shared data cache is configured to store data necessary for the execution of the plurality of threads.

[0040] 14) The method described in 8) includes using a serial processor to execute one or more single-threaded program codes.

[0041] 15) A non-transitory computer-readable storage medium having stored thereon an instruction set for processing multiple threads of a software program, the instruction set causing the computing device, when executed by a computing device, to: execute the multiple threads using multiple processing cores, wherein the multiple processing cores use bucketed thread processing to execute the multiple threads, and to send data to and receive data from at least two of the multiple processing cores using a shared data cache, the shared data cache storing data associated with the execution of a first instruction in at least one of the multiple threads, the shared data cache and the multiple processing cores interacting without relying on a private data cache.

[0042] 16) The non-transitory computer-readable storage medium according to 15), wherein the computing device is configured to: receive a first clock signal at a bucket scheduler of the plurality of processing cores, load a first instruction from an instruction memory, wherein the instruction memory stores one or more instructions associated with the plurality of threads, and execute the first instruction by: retrieving data from a first thread register, wherein the first thread register is associated with the instruction thread associated with the first instruction, and sending the received data to one or more arithmetic logic units for processing.

[0043] 17) The non-transitory computer-readable storage medium according to 16), wherein the bucket scheduler receives a second clock signal, loads a second instruction from the one or more instructions from the instruction memory, and executes the second instruction by: retrieving data from a second thread register, wherein the second thread register is associated with the instruction thread associated with the second instruction, and sending the received data to the one or more arithmetic logic units for processing.

[0044] 18) The non-transitory computer-readable storage medium according to 17), wherein each of the plurality of thread registers loads data associated with the instruction thread associated with the thread register.

[0045] 19) The non-transitory computer-readable storage medium according to 17), wherein the plurality of processing cores execute the plurality of threads simultaneously.

[0046] 20) The non-transitory computer-readable storage medium according to 15), wherein one or more of the plurality of processing cores transmit data to and receive data from the shared data cache, and wherein the shared data cache is configured to store data for executing the plurality of threads.

[0047] 21) The non-transitory computer-readable storage medium according to 15), wherein the computing device is configured to: execute one or more single-threaded program codes using a serial processor.

[0048] 22) A multi-core processor device, comprising: a plurality of processing cores configured to execute multiple threads of a software program using simultaneous multi-threaded processing; and a shared data cache configured to send data to at least two of the plurality of processing cores and receive data from at least two of the plurality of processing cores, the shared data cache storing data associated with the execution of a first instruction in at least one of the plurality of threads, the shared data cache and the plurality of processing cores interacting without relying on a private data cache.

[0049] 23) A multi-core processor device, comprising: a plurality of processing cores configured to execute a plurality of instruction threads of a software program using bucket thread processing, wherein the plurality of processing cores are configured to execute a chain of instructions associated with a first thread of the plurality of instruction threads by: loading the chain of instructions into a first instruction memory during a first time period, wherein the chain of instructions includes an independent instruction portion and a dependent instruction portion; transferring the independent instruction portion and one or more operands associated with the independent instruction portion to one or more execution units during the first time period; transferring the dependent instruction portion to a chained instruction register during the first time period; executing the independent instruction portion by the one or more execution units during the first time period; writing the result of the independent instruction portion to a first intermediate register during the first time period; transferring the dependent instruction portion, one or more operands associated with the dependent instruction portion, and the result of the independent instruction portion to the one or more execution units during a second time period; and executing the dependent instruction portion during the second time period.

[0050] 24) The device according to 23), wherein the device processes instructions associated with a second thread of the plurality of instruction threads in parallel with the execution of the subordinate instruction portion of the chained instructions during the second time period.

[0051] 25) The device according to 24), wherein one or more operands associated with the subordinate instruction portion include input operands, and wherein executing the subordinate instruction portion includes overwriting the input operands with the result of executing the subordinate instruction portion.

[0052] 26) The apparatus of claim 24) includes a multiplexer configured to determine which of the one or more execution units will execute the subordinate instruction portion of the chained instructions, and which of the one or more execution units will execute the instructions associated with the second thread.

[0053] 27) The device according to 24) includes a shared data cache configured to send data to at least two of the plurality of processing cores and receive data from at least two of the plurality of processing cores, the shared data cache storing data associated with the execution of instructions in at least one of the plurality of instruction threads, the shared data cache and the plurality of processing cores interacting without relying on a private data cache.

[0054] 28) The device according to 24), wherein the one or more operands associated with the subordinate instruction portion are stored in a first register file during the second time period, and wherein the instruction associated with the second thread includes one or more operands stored in a second register file during the second time period.

[0055] 29) The device according to 23) includes a register file, a chained instruction register, and an intermediate register associated with each of the plurality of instruction threads.

[0056] 30) The device according to 23), wherein the device processes another independent instruction portion associated with the first thread in parallel with the execution of the subordinate instruction portion of the chained instructions during the second time period.

[0057] 31) The device according to 30), wherein each processing core includes a first execution unit for executing an independent instruction portion of the first thread and a second execution unit for executing a subordinate instruction portion of the first thread.

[0058] 32) A method for executing chained instructions in a bucket-threaded processor configured to execute multiple instruction threads, the method comprising: loading the chained instructions into a first instruction memory during a first time period, wherein the chained instructions include an independent instruction portion and a dependent instruction portion; transferring the independent instruction portion and one or more operands associated with the independent instruction portion to one or more execution units during the first time period; transferring the dependent instruction portion to a chained instruction register during the first time period; executing the independent instruction portion by the one or more execution units during the first time period; writing a result of the independent instruction portion to a first intermediate register during the first time period; transferring the dependent instruction portion, one or more operands associated with the dependent instruction portion, and the result of the independent instruction portion to the one or more execution units during a second time period; and executing the dependent instruction portion during the second time period.

[0059] 33) The method according to 32), wherein the chained instructions are associated with a first thread of the plurality of instruction threads, and wherein the method includes processing instructions associated with a second thread of the plurality of instruction threads in parallel with the execution of the subordinate instruction portion of the chained instructions during the second time period.

[0060] 34) The method according to 33), wherein one or more operands associated with the subordinate instruction portion include input operands, and wherein executing the subordinate instruction portion includes overwriting the input operands with the result of executing the subordinate instruction portion.

[0061] 35) The method according to 33) includes determining which of the one or more execution units will execute the subordinate instruction portion of the chained instructions and the instructions associated with the second thread.

[0062] 36) The method according to 33) includes sending data to at least two of a plurality of processing cores and receiving data from at least two of the plurality of processing cores using a shared data cache, the shared data cache storing data associated with the execution of a first instruction in at least one of the plurality of instruction threads, the shared data cache and the plurality of processing cores interacting without relying on a private data cache.

[0063] 37) The method according to 33), wherein the one or more operands associated with the subordinate instruction portion are stored in a first register file during the second time period, and wherein the instruction portion associated with the second thread includes one or more operands stored in a second register file during the second time period.

[0064] 38) The method according to 37), wherein each of the plurality of instruction threads has its own register file, a chained instruction register and an intermediate register associated therewith.

[0065] 39) The method according to 33) includes processing another independent instruction portion associated with the first thread in parallel with the execution of the subordinate instruction portion of the chained instructions during the second time period.

[0066] 40) The method according to 39), wherein each processing core includes a first execution unit and a second execution unit, wherein the method includes an independent instruction portion of the first thread executed by the first execution unit and a subordinate instruction portion of the first thread executed by the second execution unit.

[0067] 41) A non-transitory computer-readable storage medium storing a set of instructions for processing a software program, the set of instructions, when executed by a computing device, causes the computing device to: load the chained instructions into a first instruction memory during a first time period, wherein the chained instructions include an independent instruction portion and a dependent instruction portion; transfer the independent instruction portion and one or more operands associated with the independent instruction portion to one or more execution units for execution during the first time period; transfer the dependent instruction portion to a chained instruction register during the first time period; execute the independent instruction portion by the one or more execution units during the first time period; write the result of the independent instruction portion to a first intermediate register during the first time period; transfer the dependent instruction portion, one or more operands associated with the dependent instruction portion, and the result of the independent instruction portion to the one or more execution units during a second time period; and execute the dependent instruction portion during the second time period.

[0068] 42) The non-transitory computer-readable storage medium according to 41), wherein the chained instructions are associated with a first thread of a plurality of threads, and wherein the computing device is configured to process instructions associated with a second thread of the plurality of threads in parallel with the execution of the subordinate instruction portion of the chained instructions during the second time period.

[0069] 43) The non-transitory computer-readable storage medium according to 42), wherein one or more operands associated with the subordinate instruction portion include input operands, and wherein executing the subordinate instruction portion includes overwriting the input operands with the result of executing the subordinate instruction portion.

[0070] 44) The non-transitory computer-readable storage medium according to 42), wherein the computing device is configured to determine which of the one or more execution units will execute the subordinate instruction portion of the chained instructions and the instructions associated with the second thread.

[0071] 45) The non-transitory computer-readable storage medium according to 42), wherein the computing device is configured to send data to at least two of a plurality of processing cores and receive data from at least two of the plurality of processing cores using a shared data cache, the shared data cache storing data associated with the execution of a first instruction in at least one of the plurality of threads, the shared data cache and the plurality of processing cores interacting without relying on a private data cache.

[0072] 46) The non-transitory computer-readable storage medium according to 42), wherein the one or more operands associated with the subordinate instruction portion are stored in a first register file during the second time period, and wherein the instruction associated with the second thread includes one or more operands stored in a second register file during the second time period.

[0073] 47) The non-transitory computer-readable storage medium according to 42), wherein each of the plurality of threads has its own register file, chained instruction register and associated intermediate registers.

[0074] 48) An apparatus comprising: a plurality of processors executing a plurality of processes; a plurality of caches associated with the plurality of processors, the plurality of caches including at least a first cache associated with a first processor; and a memory accessed by the plurality of processors and storing a plurality of variables, wherein the plurality of processors execute at least one of the plurality of processes by: initiating a first process of the plurality of processes on the first processor by storing a subset of the plurality of variables into the first cache; terminating the first process by writing an updated copy of the subset to the memory; and restricting access to the subset by the plurality of processes other than the first process during execution of the first process.

[0075] 49) The apparatus according to 48), wherein: the plurality of processes includes a second process, the execution of the first process on the first processor is initiated by the second process executed on the second processor, terminating the execution of the first process includes the first process invalidating the first cache and signaling completion to the second process, and upon receiving the signal, the second process accesses the subset.

[0076] 50) The device according to 48), wherein the device includes an indicator that provides indication of at least a first state and a second state, in the first state the first processor has not written bytes of data in the first cache, and in the second state the first processor has written bytes of data in the first cache.

[0077] 51) The device according to 50), wherein the indicator comprises a single bit.

[0078] 52) The device according to 50), wherein the indicator is stored in the first cache.

[0079] 53) The apparatus according to 50), wherein the apparatus is arranged to terminate the execution of the first process by writing an updated copy of the subset by: generating a request for a line of the first cache containing bytes of data in the first cache; writing the line to the memory during the first state such that the bytes of cached data in the memory corresponding to the bytes of cached data in the first cache are substantially unchanged; and writing the line to the memory during the second state to overwrite the bytes of data in the memory corresponding to the bytes of data in the first cache.

[0080] 54) The device according to 48), wherein: the plurality of processors includes a plurality of cores, and the plurality of cores share the plurality of caches.

[0081] 55) The device according to 48), wherein the I / O coherence protocol enables the device to connect to another device via an interface.

[0082] 56) A method for executing a plurality of processes in a device having a plurality of processors and a plurality of caches, the plurality of caches including at least a first cache, the method comprising: storing a plurality of variables in memory accessed by the plurality of processors; initiating a first process of the plurality of processes on a first processor by storing a subset of the plurality of variables in the first cache; terminating the first process by writing an updated copy of the subset to the memory; and restricting access to the subset by the plurality of processes other than the first process during execution of the first process.

[0083] 57) The method according to 56) includes: executing a second process of the plurality of processes on a second processor, starting the first process via the second process, terminating the first process by invalidating the first cache and signaling completion to the second process, and accessing the subset via the second process upon receiving the signal.

[0084] 58) The method according to 56) includes: providing an indicator that provides indication of at least a first state and a second state, in the first state the first processor has not written bytes of data in the first cache, and in the second state the first processor has written bytes of data in the first cache.

[0085] 59) The method according to 58), wherein the indicator comprises a single bit.

[0086] 60) The method according to 58), wherein terminating the execution of the first process by writing an updated copy of the subset comprises: generating a request for a line of the first cache containing bytes of data in the first cache, writing the line to external memory during the first state such that the bytes of cached data in the memory corresponding to the bytes of cached data in the first cache are substantially unchanged, and writing the line to the memory during the second state to overwrite the bytes of data in the memory corresponding to the bytes of data in the first cache.

[0087] 61) The method according to 56) includes sharing the plurality of caches among the plurality of cores of the plurality of processors.

[0088] 62) The method according to 56) includes enabling the device to connect to another device via an interface through an I / O coherence protocol.

[0089] 63) A non-transitory computer-readable storage medium having an instruction set thereon for processing instructions for a software program, the instruction set causing the device, when executed by a device having a plurality of processors and a plurality of caches, to: store a plurality of variables in memory accessed by the plurality of processors; initiate a first process in a plurality of processes on a first processor by storing a subset of the plurality of variables in a first cache, the first cache being one of a plurality of caches in the device; terminate the first process by writing an updated copy of the subset to the memory; and restrict access to the subset by the plurality of processes other than the first process during execution of the first process.

[0090] 64) The non-transitory computer-readable storage medium according to 63), wherein the instructions cause the device to: execute a second process in the plurality of processes on a second processor, initiate the first process by the second process, invalidate the first cache and signal completion to the second process, and terminate the first process by accessing the subset through the second process when the signal is received.

[0091] 65) The non-transitory computer-readable storage medium according to 63), wherein the instructions cause the device to: store an indicator that provides indication of at least a first state and a second state, in the first state in which the first processor has not written bytes of data in the first cache, and in the second state in which the first processor has written bytes of data in the first cache.

[0092] 66) The non-transitory computer-readable storage medium according to 65), wherein the indicator comprises a single bit.

[0093] 67) The non-transitory computer-readable storage medium according to 65), wherein the indicator is stored in the first cache.

[0094] 68) According to the non-transitory computer-readable storage medium of 65), wherein terminating the execution of the first process by writing an updated copy of the subset comprises: generating a request for a line of the first cache containing bytes of data in the first cache; during the first state, writing the line to the memory such that the bytes of cached data in the memory corresponding to the bytes of cached data in the first cache are substantially unchanged; and during the second state, writing the line to the memory to overwrite the bytes of data in external memory corresponding to the bytes of data in the first cache.

[0095] 69) The non-transitory computer-readable storage medium according to 63), wherein the instructions cause the device to share the plurality of caches among the plurality of cores of the plurality of processors.

[0096] 70) The non-transitory computer-readable storage medium according to 63), wherein the instructions cause the device to connect to another device via an interface through an I / O coherence protocol.

[0097] 71) An apparatus comprising: one or more memory groups, one or more registers, a connector connecting the one or more memory groups to the one or more registers, and one or more queues storing a set of addresses for accessing data from the one or more memory groups, the set of addresses being selected from the data request based on whether the selected address is substantially the same as other addresses in the data request.

[0098] 72) The device according to 71), wherein: the selection includes selecting the set of addresses based on the diagonal elements of the indicator matrix, and the diagonal elements indicate whether the address in the data request is the lowest index nearest neighbor or has no nearest neighbor.

[0099] 73) The device according to 72), wherein the selection includes selecting at least one of the following: an address that is not substantially the same as any other address in the data request, or an address that is substantially the same as a set of addresses in the data request and has the lowest index of the address in the set of addresses.

[0100] 74) The device according to 72), wherein the selection includes determining whether any address in the address in the data request corresponds to the same word in the same memory group stored in the one or more memory groups.

[0101] 75) The device according to 72), wherein the connector provides data to the one or more registers based on the indicator matrix.

[0102] 76) The device according to 75), wherein providing data to the one or more registers based on the indicator matrix comprises: determining, via the indicator matrix, one or more addresses in the data request that are not substantially the same as any other address in the data request or substantially the same as a set of other addresses in the data request and have the lowest index of the address in the set of other addresses, and providing data associated with the determined one or more addresses to the one or more registers.

[0103] 77) The apparatus according to 76) includes one or more multiplexers, wherein the determination is performed by the one or more multiplexers.

[0104] 78) A method for processing data, comprising: determining an indicator matrix indicating whether an address in a data request is substantially the same as other addresses in the data request; selecting a set of addresses for accessing data from one or more memory groups based on the indicator matrix; storing the selected set of addresses in one or more queues; and retrieving data corresponding to the selected set of addresses from the one or more memory groups based on the one or more queues.

[0105] 79) The method according to 78), wherein the selection includes selecting the set of addresses based on the diagonal elements of the indicator matrix, and the diagonal elements indicate whether the address in the data request is the lowest index nearest neighbor or has no nearest neighbor.

[0106] 80) The method according to 78), wherein the selection includes selecting at least one of the following: an address that is not nearly identical to any other address in the data request, or an address that is nearly identical to a set of addresses in the data request and has the lowest index of the address in the set of addresses.

[0107] 81) The method according to 78), wherein the selection includes determining whether any address in the address in the data request corresponds to the same word in the same memory group stored in the one or more memory groups.

[0108] 82) The method according to 78) further includes providing data to one or more registers via a connector based on the indicator matrix.

[0109] 83) The method according to 82), wherein providing data to the one or more registers based on the indicator matrix comprises: determining, via the indicator matrix, one or more addresses in the data request that are not substantially the same as any other address in the data request or substantially the same as a set of other addresses in the data request and have the lowest index of the address in the set of other addresses, and providing data associated with the determined one or more addresses to the one or more registers.

[0110] 84) The method according to 83), wherein the determination of the one or more addresses is performed by one or more multiplexers.

[0111] 85) A non-transitory computer-readable storage medium having stored thereon an instruction set of a software program, the instruction set causing the computing device, when executed by a computing device, to: determine an indicator matrix indicating whether an address in a data request is substantially the same as other addresses in the data request; select a set of addresses for accessing data from one or more memory groups based on the indicator matrix; store the selected set of addresses in one or more queues; and retrieve data corresponding to the selected set of addresses from the one or more memory groups based on the one or more queues.

[0112] 86) The non-transitory computer-readable storage medium according to 85), wherein: the selection includes selecting the set of addresses based on the diagonal elements of the indicator matrix, and the diagonal elements indicate whether the address in the data request is the lowest index nearest neighbor or has no nearest neighbor.

[0113] 87) The non-transitory computer-readable storage medium according to 85), wherein the instruction set causes the computing device to select at least one of the following: an address that is not substantially the same as any other address in the data request, or an address that is substantially the same as a set of addresses in the data request and has the lowest index of the address in the set of addresses.

[0114] 88) The non-transitory computer-readable storage medium according to 85), wherein the selection includes determining whether any address in the address of the data request corresponds to the same word in the same memory group stored in the one or more memory groups.

[0115] 89) The non-transitory computer-readable storage medium according to 85), wherein the instruction set enables the computing device to provide data to one or more registers via a connector based on the indicator matrix.

[0116] 90) According to the non-transitory computer-readable storage medium of 89), wherein providing data to the one or more registers based on the indicator matrix comprises: determining, via the indicator matrix, one or more addresses in the data request that are not substantially identical to any other address in the data request or substantially identical to a set of other addresses in the data request and have the lowest index of an address in the set of other addresses, and providing data associated with the determined one or more addresses to the one or more registers.

[0117] 91) The non-transitory computer-readable storage medium according to 90), wherein the determination of the one or more addresses is performed by one or more multiplexers.

[0118] 92) An apparatus comprising: a memory; a data processing subsystem including at least one data processing unit and at least one address generation unit for generating a first set of addresses in the memory based on a first set of parameters; a control subsystem for providing the first set of parameters and a second set of parameters to the data processing subsystem; and a queue for storing the first set of parameters and the second set of parameters and providing the second set of parameters to the address generation unit when the data processing unit processes data using the first set of addresses.

[0119] 93) The apparatus according to 92), wherein: the data processed by the data processing unit includes at least one image window, at least one of the first set of addresses corresponds to a location in the memory storing a first portion of the at least one image window, and the address generation unit generates the first set of addresses by iterating over the at least one image window using image parameters, the image parameters including an address in the memory storing a second portion of the at least one image window.

[0120] 94) The apparatus according to 93), wherein the data processing subsystem includes a scalar processor that provides the image parameters to the address generation unit.

[0121] 95) The apparatus according to 92), wherein the data processing unit includes at least one vector processor, and the data processed by the data processing unit includes vector data.

[0122] 96) The apparatus according to 93), wherein the data processing subsystem retrieves data from the memory incrementally, and the data processing unit uses an offset to concatenate unaligned vector data in the retrieved data, the offset indicating how the unaligned vector data is unaligned in the memory with respect to the increment.

[0123] 97) The device according to 96), wherein the address generation unit calculates the offset used by the data processing unit in the cascading.

[0124] 98) The device according to 97), wherein: the address generation unit generates a first set of addresses by iterating over portions of the at least one image window, and the offset includes an iteration-invariant parameter.

[0125] 99) A method for processing data, comprising: providing a first set of parameters and a second set of parameters to a data processing subsystem via a control subsystem, the data processing subsystem including at least one data processing unit and at least one address generation unit; storing the first set of parameters and the second set of parameters in a queue; generating a first set of addresses in memory based on the first set of parameters via the address generation unit; and providing the second set of parameters to the address generation unit via the queue when the data processing unit processes data using the first set of addresses.

[0126] 100) The method according to 99), wherein the data processed by the data processing unit includes at least one image window, wherein at least one of the first set of addresses corresponds to a location in the memory storing a first portion of the at least one image window, and the method includes generating the first set of addresses via the address generation unit by iterating over the at least one image window using image parameters, the image parameters including an address in the memory storing a second portion of the at least one image window.

[0127] 101) The method according to 100) includes providing the image parameters to the address generation unit via a scalar processor of the data processing subsystem.

[0128] 102) The method according to 99) wherein the processing of the data includes processing the vector data by at least one vector processor.

[0129] 103) The method according to 100) includes: retrieving data from the memory incrementally via the data processing subsystem, and concatenating unaligned vector data in the retrieved data via the data processing unit using an offset, the offset indicating how the unaligned vector data is unaligned in the memory with respect to the increment.

[0130] 104) The method according to 103) includes calculating the offset used by the data processing unit in the concatenation via the address generation unit.

[0131] 105) The method according to 103) includes generating a first set of addresses by iterating over portions of the at least one image window via the address generation unit, and the offset includes an iteration-invariant parameter.

[0132] 106) A non-transitory computer-readable storage medium having stored thereon an instruction set of a software program, the instruction set causing the computing device, when executed by a computing device, to: provide a first set of parameters and a second set of parameters to a data processing subsystem via a control subsystem, the data processing subsystem including at least one data processing unit and at least one address generation unit; store the first set of parameters and the second set of parameters in a queue; generate a first set of addresses in memory based on the first set of parameters via the address generation unit; and provide the second set of parameters to the address generation unit via the queue when the data processing unit processes data using the first set of addresses.

[0133] 107) The non-transitory computer-readable storage medium according to 106), wherein: the data processed by the data processing unit includes at least one image window, at least one of the first set of addresses corresponds to a location in the memory storing a first portion of the at least one image window, and the instruction set causes the computing device to generate the first set of addresses by the address generation unit iterating over the at least one image window using image parameters, the image parameters including an address in the memory storing a second portion of the at least one image window.

[0134] 108) The non-transitory computer-readable storage medium according to 107), wherein the data processing subsystem includes a scalar processor that provides the image parameters to the address generation unit.

[0135] 109) The non-transitory computer-readable storage medium according to 106), wherein the data processing unit includes at least one vector processor, and the data processed by the data processing unit includes vector data.

[0136] 110) The non-transitory computer-readable storage medium according to 107), wherein the instruction set causes the computing device to: retrieve data from the memory incrementally via the data processing subsystem, and concatenate unaligned vector data in the retrieved data using an offset via the data processing unit, the offset indicating how the unaligned vector data is unaligned in the memory with respect to the increment.

[0137] 111) The non-transitory computer-readable storage medium according to 110), wherein the instruction set causes the computing device to calculate the offset used by the data processing unit in the cascade via the address generation unit.

[0138] 112) The non-transitory computer-readable storage medium according to 111), wherein: the instruction set causes the computing device to generate a first set of addresses by iterating over portions of the at least one image window via the address generation unit, and the offset includes an iteration-invariant parameter.

[0139] 113) An apparatus comprising: at least one input register, at least one addressable register, and at least one processing unit configured to generate a histogram by: receiving a data vector via the input register, the data vector comprising a plurality of data points; matching the plurality of data points with a plurality of bars of the histogram; determining whether there is contention among the matched plurality of data points; if there is contention among the matched plurality of data points, serially classifying at least two data points of the data vector into a plurality of memory locations; and if there is no contention among the matched plurality of data points, parallelly classifying at least two data points of the data vector into a plurality of memory locations.

[0140] 114) The apparatus according to 113), wherein serially classifying two or more data points of the data vector into the plurality of memory locations if contention exists among the matched plurality of data points comprises: updating a histogram array associated with at least one bar of the histogram during a first time period; generating a first address location corresponding to a first data point of the data vector, the first address location being based on an updated histogram array updated during the first time period; writing the first data point to the addressable register based on the generated first address location; updating the histogram array during a second time period; generating a second address location corresponding to a second data point of the data vector, the second address location being based on an updated histogram array updated during the second time period; and writing the second data point to the addressable register based on the generated second address location.

[0141] 115) The device according to 113), wherein classifying two or more data points of the data vector in parallel if there is no contention among the matched plurality of data points comprises: updating a first histogram array associated with a first bar of the histogram during a first time period; updating a second histogram array associated with a second bar of the histogram during the first time period; generating a first address location corresponding to a first data point of the data vector, the first address location being based on the updated first histogram array; generating a second address location corresponding to a second data point of the data vector, the second address location being based on the updated second histogram array; writing the first data point to the addressable register based on the generated first address location during a second time period; and writing the second data point to the addressable register based on the generated second address location during the second time period.

[0142] 116) The device according to 113), wherein determining whether there is address contention among the matched plurality of data points includes determining whether two or more of the plurality of data points match a common bar of the plurality of bars of the histogram.

[0143] 117) The device according to 114), wherein generating the first address location and generating the second address location includes adding the value of the histogram array to a base address associated with at least one bar of the histogram.

[0144] 118) The device according to 117), wherein generating the first address location includes adding the value of the updated first histogram array to a base address associated with a first bar of the histogram, and wherein generating the second address location includes adding the value of the updated second histogram array to a base address associated with a second bar of the histogram.

[0145] 119) The device according to 113), wherein matching the plurality of data points with the plurality of bars of the histogram includes associating each of the plurality of data points with a bar of the plurality of bars of the histogram.

[0146] 120) A method comprising: receiving a data vector via an input register, the data vector including a plurality of data points; matching the plurality of data points with a plurality of bars of a histogram; determining whether there is contention among the matched plurality of data points; if there is contention among the matched plurality of data points, serially classifying at least two data points of the data vector into a plurality of memory locations; and if there is no contention among the matched plurality of data points, parallelly classifying at least two data points of the data vector into a plurality of memory locations.

[0147] 121) The method according to 120), wherein serially classifying two or more data points of the data vector into the plurality of memory locations if it is determined that there is contention among the matched plurality of data points comprises: updating a histogram array associated with at least one bar of the histogram during a first time period; generating a first address location corresponding to a first data point of the data vector, the first address location being based on an updated histogram array updated during the first time period; writing the first data point to an addressable register based on the generated first address location; updating the histogram array during a second time period; generating a second address location corresponding to a second data point of the data vector, the second address location being based on an updated histogram array updated during the second time period; and writing the second data point to the addressable register based on the generated second address location.

[0148] 122) According to the method of 120), wherein classifying two or more data points of the data vector in parallel if there is no contention among the matched plurality of data points comprises: updating a first histogram array associated with a first bar of the histogram during a first time period; updating a second histogram array associated with a second bar of the histogram during the first time period; generating a first address location corresponding to a first data point of the data vector, the first address location being based on the updated first histogram array; generating a second address location corresponding to a second data point of the data vector, the second address location being based on the updated second histogram array; writing the first data point to an addressable register based on the generated first address location during a second time period; and writing the second data point to the addressable register based on the generated second address location during the second time period.

[0149] 123) According to the method of 120), wherein determining whether there is address contention among the matched plurality of data points includes determining whether two or more of the plurality of data points match a common bar of the plurality of bars of the histogram.

[0150] 124) The method according to 121), wherein generating the first address location and generating the second address location includes adding the value of the histogram array to a base address associated with at least one bar of the histogram.

[0151] 125) The method according to 124), wherein generating the first address location includes adding the value of the updated first histogram array to the base address associated with the first bar of the histogram, and wherein generating the second address location includes adding the value of the updated second histogram array to the base address associated with the second bar of the histogram.

[0152] 126) According to the method of 120), wherein matching the plurality of data points with the plurality of bars of the histogram includes associating each of the plurality of data points with a bar in the plurality of bars of the histogram.

[0153] 127) A non-transitory computer-readable storage medium having stored thereon an instruction set for processing a software program, the instruction set, when executed by a computing device, causing the computing device to: receive a data vector via an input register, the data vector comprising a plurality of data points; match the plurality of data points with a plurality of bars of a histogram; determine whether there is a contention among the matched plurality of data points; if there is a contention among the matched plurality of data points, serially classify at least two data points of the data vector into a plurality of memory locations; and if there is no contention among the matched plurality of data points, parallelly classify at least two data points of the data vector into a plurality of memory locations.

[0154] 128) The non-transitory computer-readable storage medium according to 127), wherein serially classifying two or more data points of the data vector into the plurality of memory locations if contention is determined to exist among the matched plurality of data points comprises: updating a histogram array associated with at least one bar of the histogram during a first time period; generating a first address location corresponding to a first data point of the data vector, the first address location being based on an updated histogram array updated during the first time period; writing the first data point to an addressable register based on the generated first address location; updating the histogram array during a second time period; generating a second address location corresponding to a second data point of the data vector, the second address location being based on an updated histogram array updated during the second time period; and writing the second data point to the addressable register based on the generated second address location.

[0155] 129) The non-transitory computer-readable storage medium according to 127), wherein classifying two or more data points of the data vector in parallel if there is no contention among the matched plurality of data points comprises: updating a first histogram array associated with a first bar of the histogram during a first time period; updating a second histogram array associated with a second bar of the histogram during the first time period; generating a first address location corresponding to a first data point of the data vector, the first address location being based on the updated first histogram array; generating a second address location corresponding to a second data point of the data vector, the second address location being based on the updated second histogram array; writing the first data point to an addressable register based on the generated first address location during a second time period; and writing the second data point to the addressable register based on the generated second address location during the second time period.

[0156] 130) The non-transitory computer-readable storage medium according to 127), wherein determining whether there is an address contention among the matched plurality of data points includes determining whether two or more of the plurality of data points match a common bar of the plurality of bars of the histogram.

[0157] 131) The non-transitory computer-readable storage medium according to 128), wherein generating the first address location and generating the second address location includes adding the value of the histogram array to a base address associated with at least one bar of the histogram.

[0158] 132) The non-transitory computer-readable storage medium according to 131), wherein generating the first address location includes adding the updated value of the first histogram array to a base address associated with a first bar of the histogram, and wherein generating the second address location includes adding the updated value of the second histogram array to a base address associated with a second bar of the histogram.

[0159] 133) The non-transitory computer-readable storage medium according to 127) wherein matching the plurality of data points with the plurality of bars of the histogram includes associating each of the plurality of data points with a bar of the plurality of bars of the histogram.

[0160] 134) A memory device comprising: a memory module that is volatile and configured to operate in a reduced power mode and exit the reduced power mode to operate in a normal power mode; an error control circuit; and a memory controller configured to: write a data unit of a first size to the memory module after the memory module returns to the normal power mode, wherein the data unit is located within a memory segment of a second size; receive a read command to read the data unit from the memory module, read memory segment content stored in the memory segment, and send the memory segment content to the error control circuit; and transmit a read mask to the error control circuit, wherein the read mask indicates one or more redundant bits associated with the data unit; wherein the error control circuit is configured to: receive the memory segment content and the read mask; and check for one or more errors in the data unit based on the one or more redundant bits associated with the data unit, while ignoring redundant bits associated with one or more portions of the memory segment content that are different from the data unit; wherein exiting the reduced power mode is not followed by initialization of the entire memory module.

[0161] 135) The memory device according to 134), wherein the data unit has a width of one byte, and wherein the memory segment content has a width of one word.

[0162] 136) A method for error correction, the method comprising: operating a memory module in a reduced power mode, and operating the memory module in a normal power mode after exiting operation of the memory module in the reduced power mode; writing a data unit of a first size to the memory module, wherein the data unit is located within a memory segment of a second size; receiving a read command to read the data unit from the memory module; reading memory segment content stored in the memory segment, and sending the memory segment content to an error control circuit; transmitting a read mask to the error control circuit, wherein the read mask indicates one or more redundant bits associated with the data unit; receiving the memory segment content and the read mask by the error control module; and checking one or more errors in the data unit based on the one or more redundant bits associated with the data unit, while ignoring redundant bits associated with one or more portions of the memory segment content that are different from the data unit; wherein exiting operation of the memory module in the reduced power mode is not followed by initialization of the entire memory module.

[0163] 137) The method according to 136), wherein the data unit has a width of one byte, and wherein the memory segment content has a width of one word.

[0164] 138) A non-transitory computer-readable storage medium storing a set of instructions for processing multiple threads of a software program, the set of instructions, when executed by a computing device, causing the computing device to: operate a memory module in a reduced power mode, and, after exiting operation of the memory module in the reduced power mode, operate the memory module in a normal power mode; write data units of a first size to the memory module, wherein the data units are located within memory segments of a second size; receive a read command to read the data units from the memory module, read memory segment contents stored in the memory segments, and send the memory segment contents to an error control circuit; transmit a read mask to the error control circuit, wherein the read mask indicates one or more redundant bits associated with the data units; receive the memory segment contents and the read mask by the error control module; and check for one or more errors in the data units based on the one or more redundant bits associated with the data units, while ignoring redundant bits associated with one or more portions of the memory segment contents that are different from the data units; wherein exiting operation of the memory module in the reduced power mode is not followed by initialization of the entire memory module.

[0165] 139) The non-transitory computer-readable storage medium according to 138), wherein the data unit has a width of one byte, and wherein the memory segment content has a width of one word.

[0166] 140) A multi-core processor device comprising: a plurality of processing cores configured to execute a software program using bucket thread processing; one or more data caches; one or more instruction memories; and an inter-thread communication module including an atomic counter portion and a data lock portion for synchronization among the plurality of threads.

[0167] 141) The multi-core processor device according to 140) wherein the inter-thread communication module is not part of the plurality of processing cores, the one or more data caches and the one or more instruction memories.

[0168] 142) The multi-core processor device according to 140), wherein the data lock portion includes a plurality of data locks, wherein each data lock includes a mask for masking a request to lock the data lock, a mask encoder for changing the mask over time, a first priority encoder for selecting a selected mask request to lock the data lock, and a second priority encoder for selecting a request to lock the data lock regardless of the mask.

[0169] 143) The multi-core processor device according to 142) wherein the first priority encoder and the second priority encoder apply the same arbitration scheme.

[0170] 144) The multi-core processor device according to 142) wherein the first priority encoder and the second priority encoder apply different arbitration schemes.

[0171] 145) The multi-core processor device according to 140), wherein the plurality of processing cores includes a data lock requester; wherein each data lock requester is configured to execute a state machine for controlling the sending of a request to lock a data lock, the sending of a request to unlock the data lock, and selectively blocking the execution of threads.

[0172] 146) In the multi-core processor device according to 140), different data locks point to the start of different threads.

[0173] 147) The multi-core processor device according to 140), wherein the atomic counter portion includes a memory module, a discriminator, and a processor, the memory module including a plurality of entries for storing a plurality of atomic counter values, the discriminator for periodically selecting up to a single request for updating a given atomic counter, and the processor for updating the given atomic counter.

[0174] 148) The multi-core processor device according to 147), wherein the number of the plurality of entries is less than the number of data locks in the data lock portion.

[0175] 149) A method comprising executing multiple threads as instruction threads by multiple processing cores using bucket thread processing, wherein the execution of the multiple threads includes synchronizing the execution of the threads by utilizing data locks and atomic counters of an inter-thread communication module.

[0176] 150) According to the method of 149), wherein the inter-thread communication module does not belong to the plurality of processing cores, one or more data caches and one or more instruction memories.

[0177] 151) The method according to 149), wherein synchronization between the execution of the threads includes managing multiple data locks, wherein the management of the data locks includes masking requests for locking the data locks by means of a mask, the mask being changed by a mask encoder over time, a first priority encoder selecting a selected mask request for locking the data locks, and a second priority encoder selecting a request to lock the data locks regardless of the mask.

[0178] 152) The method according to 151) includes applying the same arbitration scheme by the first priority encoder and the second priority encoder.

[0179] 153) The method according to 151) includes applying different arbitration schemes by the first priority encoder and the second priority encoder.

[0180] 154) The method according to 149), wherein the plurality of processing cores includes a data lock requester; wherein the method includes each data lock requester executing a state machine for controlling the sending of requests to lock the data lock, sending of requests to unlock the data lock, and selectively blocking the execution of threads.

[0181] 155) According to the method described in 149), different data locks point to the start of different threads.

[0182] 156) According to the method of 149), wherein the atomic counter portion of the inter-thread communication module includes a memory module, a discriminator, and a processor, the memory module includes multiple entries for storing multiple atomic counter values, the discriminator is used to periodically select up to a single request for updating a given atomic counter, and the processor is used to update the given atomic counter.

[0183] 157) According to the method described in 156), the number of the plurality of entries is less than the number of data locks in the data lock portion of the inter-thread communication module.

[0184] 158) A non-transitory computer-readable storage medium having an instruction set stored thereon, the instruction set being used by multiple processing cores to execute multiple threads as instruction threads using bucket thread processing, wherein the execution of the multiple threads includes synchronizing the execution of the threads by utilizing data locks and atomic counters of an inter-thread communication module.

[0185] 159) The non-transitory computer-readable storage medium according to 158) wherein the inter-thread communication module is not part of the plurality of processing cores, one or more data caches and one or more instruction memories.

[0186] 160) According to the non-transitory computer-readable storage medium of 158), wherein synchronization between the execution of the threads includes managing a plurality of data locks, wherein the management of the data locks includes masking requests for locking the data locks by means of a mask, the mask being changed by a mask encoder over time, a first priority encoder selecting a selected mask request for locking the data locks, and a second priority encoder selecting a request to lock the data locks regardless of the mask.

[0187] 161) The non-transitory computer-readable storage medium according to 160) has an instruction set stored thereon for applying the same arbitration scheme by the first priority encoder and the second priority encoder.

[0188] 162) The non-transitory computer-readable storage medium according to 160) has an instruction set stored thereon for applying different arbitration schemes by the first priority encoder and the second priority encoder.

[0189] 163) The non-transitory computer-readable storage medium according to 158), wherein the plurality of processing cores include a data lock requester; wherein the non-transitory computer-readable storage medium has a set of instructions stored thereon for executing a state machine by each data lock requester, the state machine being used to control the sending of requests to lock a data lock, the sending of requests to unlock the data lock, and to selectively prevent the execution of threads.

[0190] 164) A non-transitory computer-readable storage medium as described in 158), wherein different data locks point to the start of different threads.

[0191] 165) The non-transitory computer-readable storage medium according to 158) wherein the atomic counter portion includes a memory module, a discriminator, and a processor, the memory module including a plurality of entries for storing a plurality of atomic counter values, the discriminator for periodically selecting up to a single request for updating a given atomic counter, and the processor for updating the given atomic counter.

[0192] 166) The non-transitory computer-readable storage medium according to 165) wherein the number of the plurality of entries is less than the number of data locks in the data lock portion of the inter-thread communication module.

[0193] 167) A floating-point processor including addition and subtraction units and a format converter, wherein the format converter is configured to convert integers into floating-point numbers using exponential bias, and wherein the addition and subtraction units include an exception block configured to generate an invalid exception when an input operand as a denormalized number is received.

[0194] 168) The floating-point processor according to 167), wherein the exception block is configured to treat input variables exceeding a size threshold as invalid numbers.

[0195] 169) The floating-point processor according to 167) is configured to compute a result by applying addition or subtraction operations; generate an exception when the result is a denormalized number; and output a number to zero and an exception flag.

[0196] 170) The floating-point processor according to 167) further includes: an exponent comparator configured to compare the exponents of two input operands; an initial mantissa calculator configured to add or subtract the mantissas of the two input operands after aligning the exponents of the two input operands between the mantissas of the two input operands to provide an initial mantissa result; and a mantissa formatting unit configured to find a leading set bit in the initial mantissa result and to shift the initial mantissa result such that the leading set bit is the most significant bit of the mantissa of the result when the leading set bit is not the most significant bit of the initial mantissa result.

[0197] 171) The floating-point processor according to 170) further includes: an exponent selector for selecting between the exponents of two input operands to provide a selected exponent; an exponent modifier for modifying the selected exponent to compensate for the shift of the initial mantissa result to provide a result exponent; and a sign selector for determining the sign of the result.

[0198] 172) The floating-point processor according to 167), wherein the format converter is configured to convert the floating-point number to an integer without generating an exception when the floating-point number is a denormalized number.

[0199] 173) A method for performing floating-point operations by a floating-point processor, wherein the method includes: adding or subtracting two input operands in floating-point format by an addition and subtraction unit; wherein adding or subtracting includes: generating an invalid number exception by an exception block of the addition and subtraction unit when at least one of the two input operands is a denormalized number; wherein generating the invalid number exception includes outputting a default value and setting an exception flag; and using an exponential bias to convert an integer to a floating-point number.

[0200] 174) The method according to 173) includes treating input variables that exceed a size threshold as invalid numbers by the exception block.

[0201] 175) The method according to 173) includes calculating the result by applying addition or subtraction; when the result is a denormalized number, generating an exception and outputting a number adjusted to zero and an exception flag.

[0202] 176) The method according to 173), wherein the addition or subtraction comprises: comparing the exponents of two input operands by an exponent comparator; adding or subtracting the mantissas of the two input operands by an initial mantissa calculator after aligning the exponents of the two input operands between the mantissas of the two input operands based on the exponents of the two input operands to provide an initial mantissa result; and formatting the mantissa result of the initial mantissa result by a mantissa formatting unit by finding a leading set bit in the initial mantissa result and shifting the initial mantissa result such that the leading set bit is the most significant bit of the output mantissa when the leading set bit is not the most significant bit of the initial mantissa result.

[0203] 177) The method according to 176) includes selecting between the exponents of two input operands by an exponent selector to provide a selected exponent; modifying the selected exponent by an exponent modifier to compensate for the shift of the initial mantissa result to provide an output exponent; and determining the sign of the output signal by a sign selector.

[0204] 178) The method according to 173) includes: when the floating-point number is a denormalized number, converting the floating-point number to an integer by a format converter without generating an exception.

[0205] 179) A non-transitory computer-readable storage medium having an instruction set stored thereon for performing floating-point operations by a floating-point processor, the floating-point operations comprising: adding or subtracting two input operands in floating-point format by addition and subtraction units; wherein the addition or subtraction comprises: generating an invalid number exception when at least one of the two input operands is a denormalized number; wherein generating the invalid number exception comprises outputting a default value and setting an exception flag; and converting an integer to a floating-point number using an exponential deviation via a format converter.

[0206] 180) The non-transitory computer-readable storage medium according to 179) has a set of instructions stored thereon for treating input variables exceeding a size threshold as invalid numbers by exception blocks of the addition and subtraction units.

[0207] 181) The non-transitory computer-readable storage medium according to 179) has a set of instructions stored thereon for performing the following operations: calculating a result by applying addition or subtraction, generating an exception when the result is a denormalized number, and outputting a number to zero and an exception flag.

[0208] 182) The non-transitory computer-readable storage medium according to 179), wherein the addition or subtraction comprises: comparing the exponents of two input operands by an exponent comparator; adding or subtracting the mantissas of the two input operands by an initial mantissa calculator after aligning the exponents of the two input operands between the mantissas of the two input operands to provide an initial mantissa result; and formatting the mantissa result of the initial mantissa result by a mantissa formatting unit by finding a leading set bit in the initial mantissa result and shifting the initial mantissa result such that the leading set bit is the most significant bit of the output mantissa when the leading set bit is not the most significant bit of the initial mantissa result.

[0209] 183) According to the non-transitory computer-readable storage medium of 182), having a set of instructions stored thereon for performing the following operations: selecting between the exponents of the two input operands by an exponent selector to provide a selected exponent, modifying the selected exponent by an exponent modifier to compensate for the shift of the initial mantissa result to provide an output exponent, and determining the sign of the output signal by a sign selector.

[0210] 184) The non-transitory computer-readable storage medium according to 179) has a set of instructions stored thereon for performing the following operations: when a floating-point number is a denormalized number, the format converter converts the floating-point number to an integer without generating an exception.

[0211] 185) An apparatus comprising: at least one input register, at least one addressable register, and at least one processing unit configured to generate a histogram by: receiving a data vector via the input register, the data vector comprising a plurality of data points; matching the plurality of data points with a plurality of bars of the histogram; searching for a race condition occurring when the plurality of data points include data points belonging to the same bar; when the race condition is detected, serially calculating an address for a given memory entry for storing the data points belonging to the same bar and storing the data points belonging to the same bar at the given memory entry; and when the race condition is not detected, parallelly calculating addresses for certain memory entries for storing the plurality of data points and storing the plurality of data points at the certain memory entries.

[0212] 186) A method comprising: generating a histogram by: receiving a data vector via an input register, the data vector including a plurality of data points; matching the plurality of data points with a plurality of bars of the histogram; searching for a race condition that occurs when the plurality of data points include data points belonging to the same bar; when the race condition is detected, serially calculating the address of a given memory entry for storing the data points belonging to the same bar and storing the data points belonging to the same bar at the given memory entry; and when the race condition is not detected, parallelly calculating the addresses of certain memory entries for storing the plurality of data points and storing the plurality of data points at the certain memory entries.

[0213] 187) A non-transitory computer-readable storage medium having stored thereon an instruction set for processing a software program, the instruction set, when executed by a computing device, causing the computing device to generate a histogram by: receiving a data vector via an input register, the data vector comprising a plurality of data points; matching the plurality of data points with a plurality of bars of the histogram; searching for a race condition when the plurality of data points include data points belonging to the same bar; when the race condition is detected, serially calculating the address of a given memory entry for storing data points belonging to the same bar and storing the data points belonging to the same bar at the given memory entry; and when the race condition is not detected, parallelly calculating the addresses of certain memory entries for storing the plurality of data points and storing the plurality of data points at the certain memory entries. Brief description of the attached diagram

[0214] The subject matter considered to be the present invention is specifically pointed out and clearly claimed in the concluding section of the specification. However, the invention relates to methods of operation and organization, as well as its objects, features, and advantages, and is discussed in conjunction with the appendix. Figure 1 The best way to understand this text is to refer to the following detailed description, in which: Figure 1 An exemplary system-on-chip (SoC) is shown according to an example of this disclosure; Figure 2 An exemplary multicore processor is shown according to an example of this disclosure; Figure 3A An exemplary multicore processor configured to perform bucket thread processing is shown according to an example of this disclosure; Figure 3B An exemplary multicore processor configured to perform bucket thread processing is shown according to an example of this disclosure; Figure 4 An exemplary timing diagram for the execution of an instruction thread in a bucket-threaded processor is shown according to an example of this disclosure; Figure 5AAn exemplary multicore processor, according to an example of this disclosure, is configured to perform bucket-threaded processing and utilize a shared data cache. Figure 6A An exemplary barrel-threaded multicore processor with a serial computer processing unit is shown according to an example of this disclosure; Figure 6B An exemplary barrel-threaded multicore processor with a serial computer processing unit is shown according to an example of this disclosure; Figure 6C An exemplary barrel-threaded multicore processor with a serial computer processing unit is shown according to an example of this disclosure; Figure 6D Display window; Figure 6E An exemplary barrel-threaded multicore processor with a serial computer processing unit is shown according to an example of this disclosure; Figure 6F This illustrates multithreaded communication according to an example of this disclosure; Figure 7 An exemplary dual-issue processor is shown according to an example of this disclosure; Figure 8 An exemplary dual-issue core processor configured to accept chained instructions is shown according to an example of this disclosure; Figure 9 An exemplary dual-issue core is shown in the example configuration according to this disclosure for bucket thread processing and accepting chained instructions; Figure 10A An exemplary chained instruction processing flow during a first clock cycle is shown according to an example of this disclosure; Figure 10B An exemplary chained instruction processing flow is shown during the second clock cycle, according to an example.

[0215] Figure 10C An exemplary dual-issue core is shown in the example configuration according to this disclosure for bucket thread processing and accepting chained instructions; Figure 11 An exemplary multiprocessor system having a local cache communicating with external memory is shown according to an example of this disclosure; Figure 12 Exemplary cache configurations or structures are shown according to examples of this disclosure; Figure 13A This illustrates a real-world data sharing among multiple processors according to an example of this disclosure; Figure 13B This illustrates pseudo-sharing across multiple processors.

[0216] Figure 14The hardware for resolving false sharing is shown according to an example of this disclosure; Figure 15 Exemplary use of "dirty bits" is shown in the example according to this disclosure; Figure 16A illustrates multiple process implementations with restricted data sharing according to an example of this disclosure; Figure 16B This is a timing diagram for the process shown in Figure 16A; Figure 16C This illustrates a data lock according to an example of this disclosure; Figure 16D This illustrates a state machine according to an example of this disclosure; Figure 16E A method according to an embodiment of the present invention is shown; Figure 17 An exemplary vector processor is shown according to an example of this disclosure; Figure 18 Exemplary memory groups and interconnect architectures are shown according to examples of this disclosure; Figure 19A An exemplary architecture is shown according to an example of this disclosure; Figure 19B Based on the examples of this disclosure regarding the use Figure 4 A flowchart of the system architecture; Figure 20 This illustration shows a portion of an array of indicators for one of a series of addresses, according to an example of this disclosure; Figure 21A This illustration shows a portion of an array of indicators for one of a series of nearly identical addresses, according to an example of this disclosure; Figure 21B This illustration shows a portion of an array of indicators for one of a series of nearly identical addresses, according to an example of this disclosure; Figure 21C This illustration shows a portion of an array of indicators for one of a series of nearly identical addresses, according to an example of this disclosure; Figure 22 An array of indicators representing eight unique addresses is shown according to an example of this disclosure; Figure 23 An array of indicators representing eight nearly identical addresses is shown according to an example of this disclosure; Figure 24 An array of pointers representing four pairs of nearly identical addresses is shown as an example according to this disclosure; Figure 25A This is an exemplary encoding scheme for assigning values ​​to elements of an array of indicators, according to examples of this disclosure; Figure 25BA method according to an embodiment of the present invention is shown; Figure 26 Examples shown according to this disclosure may be Figure 17 An exemplary control and processing subsystem of a portion of the logic and / or processing circuitry of the vector processor shown; Figure 27 This illustrates exemplary inputs to the address generation unit and exemplary outputs from the address generation unit according to an example of this disclosure; Figure 28 An exemplary control and processing subsystem with a parameter queue is shown according to an example of this disclosure; Figure 29 Exemplary images showing examples according to this disclosure; Figure 30 This shows an execution timeline for a data processing subsystem according to an example of this disclosure; Figure 31 Examples of this disclosure are shown for Figure 28 Execution timeline of the data processing subsystem in the middle; Figure 32 Examples of this disclosure are shown for Figure 28 Execution timeline of the data processing subsystem in the middle; Figure 33A This illustrates an exemplary 8-byte access to aligned data according to an example of this disclosure; Figure 33B An exemplary 8-byte access to unaligned data is shown according to an example of this disclosure; Figure 34A Exemplary combined features are shown according to examples of this disclosure; Figure 34B An exemplary method for processing data is shown according to an example of this disclosure; Figure 35 An exemplary method for serializing bucket sorting is shown according to an example of this disclosure; Figure 36 An exemplary method for vectorized bucket classification is shown according to examples of this disclosure; Figure 37 Another exemplary vectorized histogram bar classification algorithm is shown according to examples of this disclosure; Figure 38 An exemplary vectorized bucket classification algorithm capable of handling competition is shown according to examples of this disclosure; Figure 39 An exemplary memory device is shown according to an example of this disclosure; Figure 40 An exemplary memory device power gating method with memory initialization is shown according to an example of this disclosure; Figure 41 An exemplary memory device power gating method without memory initialization is shown according to an example of this disclosure; Figure 42 An exemplary memory device with read mask functionality is shown according to an example of this disclosure; Figure 43 An exemplary memory device power gating method with read masking capability and no memory initialization is shown according to an example of this disclosure; Figure 44 A method according to an embodiment of the present invention is shown; Figure 45 A memory module, a memory controller, and various data structures are illustrated according to embodiments of the present invention. Figure 46 An exemplary system-on-chip (SoC) is shown according to an example of this disclosure; Figure 47 A floating-point processor including addition and subtraction units and a format converter is shown according to an embodiment of the present invention; Figure 48 A method according to an embodiment of the present invention is shown; and Figure 49 A method according to an embodiment of the present invention is shown. Detailed description

[0217] In the following description of the examples, reference is made to the accompanying drawings, which form a part of the examples, and specific examples that may be implemented are shown by way of illustration. It will be understood that other examples may be used, and structural changes may be made without departing from the scope of the disclosed examples. Furthermore, while example backgrounds of how this disclosure may be implemented are provided, they are not intended to limit the scope of this disclosure to those backgrounds.

[0218] Any reference to the method in the specification shall be modified as necessary to apply to a memory device capable of executing the method, and shall be modified as necessary to apply to a non-transitory computer-readable medium storing instructions that, once executed by a computer, result in the execution of the method.

[0219] Any reference to a memory device in the specification shall be modified as necessary to apply to methods that can be executed by the memory device, and shall be modified as necessary to apply to a non-transitory computer-readable medium storing instructions that can be executed by the memory device.

[0220] Any reference in the specification to non-transitory computer-readable medium shall be modified as necessary to apply to memory devices capable of executing instructions stored in non-transitory computer-readable medium, and shall be modified as necessary to apply to methods executable by a computer that reads instructions stored in non-transitory computer-readable medium.

[0221] Some computer processors can utilize multiple cores to enable the processor to process multiple instruction threads at any given time, thereby increasing the speed at which the processor can execute algorithms or programs. However, in certain computing scenarios, the performance gains achieved by multi-core processors may be reduced. Therefore, this disclosure relates to multi-core processors that can utilize bucketed thread processing along with a data cache shared among multiple cores of the processor, in order to improve the performance of multi-core processors in computing environments where algorithms or programs require processing with multiple software loops that iterate independently.

[0222] Figure 1 An exemplary system-on-a-chip (SoC) according to examples of this disclosure is shown. It can be utilized in many computing scenarios. Figure 1 The system shown is an example of a non-limiting concept. Figure 1 The SoC 102 shown can be utilized in a computer vision system where a peripheral camera or multiple cameras capture images, which are then processed to reveal features embedded within each captured image. (Reference) Figure 1 Peripheral device 106 can represent one or more devices outside the system that can, for example, capture some form of data. In a computer vision context, such peripheral device 106 could be a camera capturing images of the surrounding environment. Data captured by peripheral device 106 can be input into SoC 102 via peripheral device controller 108. One or more peripheral device controllers 108 can receive data from peripheral device 106 and store the data in the memory within SoC 102. Additionally, peripheral device controller 108 can send output signals to peripheral device 106. Such output signals can include commands that cause peripheral device 106 to perform certain functions, or data provided to peripheral device 106.

[0223] Peripheral device controller 108 can be connected to other components of SoC 102 via on-chip interconnect 110. The on-chip interconnect can act as a switch for connecting components of SoC 102 when necessary. For example, the connection between peripheral device controller 108 and computer processing unit 104 can be facilitated via on-chip interconnect 110. Similarly, the connection between accelerators 114 and 116 and CPU 104 can also be facilitated via on-chip interconnect 104.

[0224] CPU 104 can act as a central processing unit coordinating the activities of all the various components within SoC 102. CPU 104 can determine which components will be assigned to perform various program tasks, or it can process instructions specifying which component of SoC 102 will handle various tasks. Alternatively, CPU 104 can also execute various tasks independently. For example, in a computer vision context, CPU 104 can execute various image processing algorithms independently without relying on other components.

[0225] However, for example, if and when such a task is better suited to be executed on an accelerator rather than a CPU, the CPU 104 can also rely on accelerators 112 and 114 to perform the processing task. Accelerators 112 and 114 can be dedicated computer hardware that can execute functions faster than if the function were performed by software running on a general-purpose computer processor. For example, accelerators 112 and 114 can be customized to handle computationally intensive algorithms that might otherwise operate slowly on a general-purpose CPU. Accelerators 112 and 114 can utilize various methods to accelerate such processing, such as leveraging concurrency (the ability to execute multiple tasks simultaneously) to speed up processing time.

[0226] SoC 102 can also be connected to external memory 118 via external memory controller 116. External memory 118 can store data necessary for performing functions and instructions on SoC 102. External memory can be solid-state memory, but conventionally it is random access memory (RAM) that can be read from and written to relatively quickly. External memory 118 can potentially be accessed by other components in SoC 102, such as CPU 104, peripheral controller 108, and accelerators 112 and 114.

[0227] Like in Figure 1 Accelerators like those shown in 112 and 114 can be customized to perform computationally intensive tasks and / or tasks requiring specialized processing that may not be available on general-purpose CPUs. Figure 2 Examples of hardware accelerators in the form of multi-core processors according to this disclosure are presented. A multi-core processor is a device having multiple independent processing units (referred to as "cores") that read and execute instructions contained within a software program in parallel with each other. By operating in parallel, the cores can simultaneously perform the independent tasks required by the algorithm, thereby reducing the amount of time necessary to implement the algorithm on a given dataset.

[0228] exist Figure 2In the example shown, the accelerator may include four cores 204a-d. Each core 204a-d may be connected to a private instruction memory 202a-d. Each instruction memory 202a-d is considered "private" to its corresponding core 204a-d because it can be dedicated to that corresponding core. In other examples, each core 204a-d may share a common instruction memory (see...). Figure 3B (Public instruction memory 6002). The decision to use a private or shared instruction memory can depend on, for example, the speed at which the memory needs to be accessed by the core. A private instruction memory can be implemented as a private instruction cache (i.e., a small area of ​​fast memory) to further accelerate the speed at which the memory can be accessed.

[0229] Each instruction memory 202a-d can correspond to one of the cores 204a-d. For example, and as... Figure 2 As shown, instruction memory 202a is coupled to core 204a, instruction memory 202b is coupled to core 204b, instruction memory 202c is coupled to core 204c, and so on. Each instruction memory 202a-d can store instructions that will be executed by its corresponding core 204a-d. When accessed by its corresponding core, the instruction memory can provide the next instruction in the instruction sequence that will be executed by the corresponding core.

[0230] Each core 204a-d can also be coupled to data caches 206a-d. Similar to instruction memories 202a-d, data caches 206a-206d can correspond to individual cores 204a-204d, thus making the data cache "private" (i.e., each core has its own corresponding data cache). The data cache can contain data that will be manipulated by the core, and can also store the results processed by each individual core.

[0231] For the purposes of explanation, focusing on a single core, core 204a can receive instructions from instruction memory 202a. Once an instruction from instruction memory 202a is loaded by core 204a, the core can access data cache 206a to retrieve the data to be manipulated by the instruction. Once the instruction has been executed, the result of the instruction can be written to data cache 206a. This process can then be repeated with the next instruction loaded by core 204a from instruction memory 202a. In some examples, data cache 206a and instruction memory 202a can exchange information during load and store instructions, where a load instruction copies data from memory to registers, and a store instruction transfers data from registers to memory.

[0232] The process described above for core 204a can also be run simultaneously on the other three cores 204b-d. Because each core runs its own instruction set concurrently, program execution can be sped up, unlike CPUs where a single processing core is operating.

[0233] A sequence of instructions can be called a "program," and a thread can be defined as a sequence of program instructions that can be independently managed by a scheduler. Accelerators can be customized based on the characteristics of the programs they process. As an example, the following pseudocode from a vision processing algorithm is used, Example 1:

[0234] The programming example above illustrates program code including conditional statements within a for loop. In this example, the conditional if / else statement (obj too small) is nested within the first for loop ("objects in array"). An additional conditional if / else statement ("obj nearly square") is further nested within the first conditional if / else statement. This programming example is common in vision processing contexts, where images with multiple pixels are analyzed to determine, for example, the presence of certain features or characteristics. In the field of autonomous vehicles, such vision processing might help distinguish lines on a road or other objects near a car. In computational environments such as vision processing, where program code will contain conditional statements within program loops, the fact that such code can be executed in many parallel steps can be used to customize hardware accelerators.

[0235] Figure 3A An exemplary multicore processor configured to perform bucket-thread processing is shown according to an example of this disclosure. Figure 3A In the example provided, core 304a-d is configured to use bucket threading to execute program threads. The concept of bucket threading can be illustrated by examining the timing of instruction execution within a single core.

[0236] Figure 4 An exemplary timing diagram is shown for the execution of an instruction thread in a bucket-threaded processor according to an example of this disclosure. Figure 4 The timing diagram shown illustrates that in Figure 3A The diagram illustrates the timing of thread execution within a single core of a multi-core processor, configured with eight threads (threads 1-8) multiplexed. Multi-core processor cores can be configured with more or fewer instruction threads multiplexed, and the eight threads should be understood as merely an example.

[0237] This diagram comprises 10 time periods, T1-T10. Each time period represents a single clock cycle of the processor core. At time T1, the first instruction (optionally referred to as the command "cmd") of the first thread (thread 1) can be executed by the core. At time T2, the first instruction of the second thread (thread 2) can be executed by the core. At time T3, the first instruction of the third thread can be executed by the core. At times T4-T8, the first instructions of threads 4-8 can be executed. At time T9, each thread has executed its first instruction. The processor core can then return to the first thread and execute its second instruction. At time T10, the core can return to the second thread and execute its second instruction. This process can be repeated until all instructions for each thread have been completed.

[0238] like Figure 4 As shown, bucket-based threading can improve processing efficiency by eliminating wasted clock cycles. Processing multiple commands in parallel can reduce the impact of latency on processing speed. For example, Figure 4 Any instruction in the process (“cmd”) can cause a pause or delay (“latency”) in the processing, which can be caused by, for example, cache misses, branching, floating-point operations, and division. Bucketed thread processing does not eliminate pauses or delays, but it greatly increases the likelihood that a pause or delay will not keep the core idle. Instead, the core remains idle for only one clock cycle, and then in a subsequent cycle, it will process the command from the next thread during the delay, such as... Figure 4 As shown. A single-threaded processor (i.e., a processor where instructions for a single thread are processed sequentially) will, in contrast, remain idle during the duration of a pause or delay. This can result in many wasted clock cycles (i.e., clock cycles in which no instruction execution occurs). During these wasted clock cycles, the processor must halt the execution of the program thread to wait for the individual instruction to complete before it can proceed to the next instruction in the sequence. This can lead to delays in the processing time for a particular thread and in the overall execution of the program or algorithm.

[0239] Even when the latency lasts for more cycles compared to the existing thread latency, bucket-threaded processors can help mask the effects of latency. In one example, if a cache miss causes a latency of 100 cycles, but there are only eight hardware threads in a given core, the latency might only cause 100 / 8 cycles to be missed, rather than the 100 cycles that would be missed in a non-bucket-threaded process.

[0240] More specifically, bucket thread processing can mitigate wasted clock cycles by switching to another thread while the first thread is waiting or idle. Using Figure 4For example, while thread 1 is executing instructions, thread 2 can execute instructions as long as the instructions of thread 2 do not depend on the result of thread 1.

[0241] However, any subsequent instruction must wait until the instruction preceding it has been executed. For example, at time T9, if the instruction executing at T1 has not yet finished, the instruction at T9 cannot be executed; it must wait until the instruction executing at T1 has been executed. Therefore, during T9, the processor cannot do anything, and then at T10 it will continue to execute the second instruction of the second thread.

[0242] In some cases, the processor can fill any stalled cycle with the next instruction to be executed instead of doing nothing at T9. Referring back to the example above, nothing is done at T9; the processor can execute the second instruction of the first thread. In this way, the impact of stalled threads on throughput can be minimized. This approach can be called Simultaneous Multithreading (SMT).

[0243] In SMT, instructions from more than one thread can be executed at any given time interval. Therefore, if a particular thread is paused for a specific time interval, it is not doing nothing; rather, SMT allows instructions from another thread to be executed during the paused period.

[0244] In this way, if a specific instruction of a thread takes less than eight cycles to execute, the instruction will be executed when the core processor returns to the thread, and the thread can proceed to execute the next instruction. In one example, if a cache miss takes 80 cycles to resolve, the thread will lose 10 turns. This is because the bucket-threaded core returns to the thread every 8 cycles. Conversely, in a serially threaded processor, the core must wait 80 cycles and remain idle before it can execute the next instruction. In the case of bucket-threaded processing, the processor is not idle. The bucket-threaded system will execute other instructions from other threads while the cache miss is resolved.

[0245] Bucket-based thread processing is advantageous in computing environments with many active threads. Return to Figure 4For example, in some cases, only four out of a total of eight threads may be active. In this case, the processor cores will be idle during time T5-T8. This will result in only 50% efficiency (i.e., 4 / 8 cycles are active). If a single active thread exists, this below-average performance will be even worse. In this case, the processor will only be 12.5% ​​effective. Bucket thread processing avoids many of the costs associated with operating a processor with a serial CPU. Therefore, bucket thread processing is most suitable for computing environments with many active threads.

[0246] The example program code described above (Example 1) (a loop with independent iterations and embedded conditional statements) can be distributed to run in several threads, with different threads performing different iterations, and thus bucket-based threading can improve processor performance in such computing environments.

[0247] In a for loop, each iteration exists within an independent computational environment, allowing different threads to execute different iterations of the loop. This type of processing environment can be defined by... Figure 3A The system described in the text executes effectively.

[0248] Return to Figure 3A Each core 304a-d can implement bucketed threading. Using the first core 304a as an example, the core can implement bucketed threading by utilizing the bucket scheduler 310a. The bucket scheduler 310a can be connected to multiple thread registers 308a labeled T0-TM-1, where M indicates the thread registers related to T0-TM-1. Figure 4 The number of threads being looped through during the described bucket thread processing.

[0249] Each thread register file 308a includes multiple registers that can store information related to the thread corresponding to the thread register file. The registers within each thread register file may contain data processed by the processor according to instructions executed by the thread, and the register file also contains a program counter register, which records which instructions in the thread will be executed next. Figure 3A In this context, the program counter points to instructions stored in the core's instruction memory. Figure 3B In the thread register, the program counter points to the instructions stored in the common instruction memory 6002.

[0250] Data from components outside the multi-core processor can be loaded into the thread register via the private data cache 306a.

[0251] The bucket scheduler 310a can begin the process by first accessing the thread register file 308a corresponding to the first thread of the multiple threads to be processed. Figure 3A In this example, the first thread register is labeled T0. The program counter located in the memory of the thread register file T0 can signal the bucket scheduler 310a to indicate which instruction is popped from the instruction memory 302a for execution. Based on the instruction received from the instruction memory 302a, the bucket scheduler can load the appropriate data from the thread register file T0 and pass this information to the arithmetic logic unit 312a, which then executes the instruction.

[0252] On the next clock cycle, the bucket scheduler can initiate the same process on thread register file T1, and on each subsequent cycle, it can initiate processes for thread register files T2 through TM-1, where M equals the number of threads the core can handle. Once the instructions from each thread have been processed, the bucket scheduler 302a can return to the first thread by accessing thread register file T0 and determining whether the first instruction has completed. If it has, the bucket scheduler can process the second instruction from the first thread. If it has not completed, the bucket scheduler can proceed to the second thread, performing no execution in this cycle.

[0253] This process can be repeated until all instructions in each thread have been executed by core 304a. In parallel, the other cores 304b-d can also perform the same bucket-thread processing on their respective program threads. Thus, as an example, in a quad-core processor (each containing 8 thread registers), cores 304a-d can operate in parallel on 32 separate threads (4 cores × 8 threads / core). In this way, processing program code containing conditional statements embedded within loops with largely independent iterations can be done faster than using a single-core processor that operates serially on only one thread.

[0254] Besides utilizing bucketed thread processing, the operation of multi-core processors can be further improved by employing a shared data cache. The shared data cache is accessed by every core of the multi-core processor. Figure 5A An exemplary multicore processor configured to perform bucketed thread processing and utilize a shared data cache is shown as an example according to this disclosure. Figure 5A The multi-core processor shown is similar to Figure 3A A multi-core processor. Specifically, the core 504a-d and... Figure 3A The core 304a-d is similarly configured. The instruction memory 502a-d, thread register file 508a-d, bucket scheduler 510a-d, and arithmetic logic unit 512a-d can be connected to... Figure 3A Their counterparts are the same, and therefore in the above regarding Figure 3ADiscussions about their functions can be found in the discussion.

[0255] In contrast to the private data cache 306a-d (where each core has a private data cache associated with it), Figure 5A Multi-core processors include a shared data cache 514. Generally, a private data cache can be implemented without the overhead necessary to make memory accessible to several processors, thus allowing each core of a multi-core processor to access the data cache with minimal memory latency. However, a private data cache can cause inter-core cache coherence issues when it may contain inconsistent (out-of-sync) versions of data. Addressing these cache coherence issues can incur additional chip space, power, and clock cycles, thus degrading efficiency.

[0256] When a multi-core processor performs image processing, the pixels of the processed image are stored in a shared cache memory according to a predetermined scheme known to all cores. This allows different cores to easily access the same pixels and reduces cache misses. A non-limiting example of the predetermined scheme is to store the pixels belonging to the image contiguously within the shared memory cache.

[0257] As an example, in a visual processing computing environment as discussed above, each core of a multi-core processor can process different parts of an image simultaneously, storing the processed portion of the image in its own private data cache. However, if external memory needs the latest image, each data cache must be accessed to see which private data cache has the latest portion of the image. This process must be placed appropriately to ensure that the copy of data held by each private data cache is up-to-date. This process of ensuring inter-cache consistency can be expensive from a power and latency standpoint, as the additional power and time must be spent on inter-cache consistency.

[0258] However, using a shared data cache will avoid the consistency requirements between these caches. For example... Figure 5A As shown, each core 504a-d can connect to a shared data cache 514. The shared data cache 514 can contain multiple sets $0-$K-1. Each core 504a-d can write data to and load data from these multiple sets $0-$K-1. Because each core now shares the data contained within the shared data cache 514, instead of maintaining its own single copy of the data in a private data cache, the complexity associated with resolving inter-cache consistency issues is eliminated.

[0259] While shared data caches can eliminate the complexity associated with inter-cache coherence issues caused by private data caches, they can also lead to longer memory latency. In other words, it may take the kernel longer to read from and write to the shared data cache than to read from and write to the private data cache.

[0260] In hardware accelerators utilizing multi-core architectures with bucket-based threading, the increased memory latency created by adding shared data caches may not significantly degrade performance. (See above regarding...) Figure 3A and Figure 4 In the bucket-based threaded processor discussed here, after a thread executes an instruction, that thread must wait a predetermined number of clock cycles before the bucket scheduler returns to the thread to execute the next instruction in the instruction sequence. The predetermined amount of time depends on the number of threads that can be processed by the core. Figure 3A and Figure 4 In the example, there are eight thread registers, so the core that processes eight threads will not return every eight clock cycles to execute instructions from the threads.

[0261] The fact that there is a predetermined amount of time between the execution of subsequent instructions between threads may cause the increased memory latency associated with shared data caches to be inconclusive from a performance standpoint. This is likely because the amount of time between the execution of subsequent instructions within a thread may be greater than the amount of time required to access the shared data cache. Therefore, the fact that the shared data cache takes a longer amount of time to access compared to the private data cache is not significant, because by the time the next instruction in the thread is ready to be executed, sufficient time has elapsed to allow the kernel to access the shared data cache.

[0262] Another potential advantage of using a shared data cache is that it can minimize the number of cache misses. A cache miss occurs when a processor core cannot find the required data in its data cache and must retrieve the required data from another level of cache or external memory. Because private data caches are smaller in capacity than shared data caches, the chance that the required data may not be available in a private data cache is higher than if a larger shared data cache were used. Furthermore, if different threads are processing related data items, one thread bringing data into the cache may help another thread that needs the data in the same cache line. With a private data cache, two or more physical copies of the data will exist, one copy in the cache of each core that needs it, thus wasting cache memory space and the time required to fetch the data into several caches instead of just one.

[0263] While barrel-threaded multi-core processors with shared inter-core data caches can offer greater processing efficiency in terms of power and speed, as discussed above, they may not be ideal for serial computing environments. If a program or code has a mix of tasks that can be parallelized and tasks that must be processed serially, barrel-threaded multi-core processors may oscillate between periods of optimal efficiency and below-standard efficiency. The advantages of barrel-threaded processors can be realized when operating on threads that can run in parallel. However, the processor may become relatively inefficient when serial code is being processed. Therefore, including a separate serial processor optimized for operating on code that must run serially may be advantageous.

[0264] Figure 6A An exemplary barrel-threaded multicore processor with a serial computer processing unit is shown as an example according to this disclosure. Figure 6A Examples and about Figure 5A The example multi-core processor discussed is the same, except that a serial processor 616 is added. Therefore, the discussion of the individual units not described below can be made with reference to those discussed above. Figure 5A Discussions of their counterparts were found.

[0265] Figure 6A Examples of multi-core processors include a serial processor 616 that can be used to process single-threaded program code. The serial processor will need to communicate with all the other cores in order to exchange data. For example, in one instance, the serial processor 616 could receive data prepared by cores 604a-d, process it serially, and compute the results that cores 604a-d could subsequently access.

[0266] This data exchange between the serial processor 616 and the core 604a-d can be implemented in various ways. For example, the core 604a-d and the serial processor 616 can share local memory. Figure 6B (6004 in the example). In another example, core 604a-d can write data to a first-in-first-out (FIFO) queue (…). Figure 6C In the 6006), the serial processor 616 can then read data from the FIFO queue and write the result of its calculation to another FIFO queue (not shown). In another example, the cores 604a-d and the serial processor 616 can directly read their data and write their data externally using a direct memory access controller (DMA) or its own data cache (not shown).

[0267] Serial processors can improve the efficiency of a SoC by preventing multi-core processors from having to communicate with the SoC's main CPU whenever they need to perform serial computations, or from having to run serial computations on a barrel-threaded processor (where such serial computations would run inefficiently).

[0268] Using a shared cache is highly beneficial when different threads apply image processing algorithms that handle overlapping or partially overlapping pixels. For example, the FAST corner detector (see http: / / www.wikipedia.org; "Fusing points and lines for high-performance tracking" by Edward Rosten and Tom Drummond, October 2015, IEEE International Conference on Computer Vision, pp. 1508-1511, and "Machine learning for high-speed corner detection" by Edward Rosten and Tom Drummond, May 2006, European Conference on Computer Vision, pp. 430-443) uses a 16-pixel circle (a Bresenham circle with a radius of 3, see...) Figure 6D To classify whether a candidate point p is actually an angle, we use an integer from 1 to 16 clockwise. Each pixel in the circle is labeled with an integer from 1 to 16. If the set of N consecutive pixels in the circle is greater than the intensity of the candidate pixel p (as determined by I...), then the candidate pixel is considered an angle. p If a pixel is brighter than a candidate pixel p by adding a threshold t, or if the pixel is darker than the candidate pixel p by subtracting the threshold t, then p is classified as a corner.

[0269] The condition can be written as: a. Condition 1: A set S of N consecutive pixels, x∈S, the intensity of x (I x ) > I P + Threshold t b. Condition 2: A set S of N consecutive pixels, x∈S,I x < I P - t Therefore, candidate p can be classified as a corner when either of the two conditions is met. There is a trade-off between choosing N, the number of consecutive pixels, and the threshold t. On the one hand, the number of detected corners should not be too large; on the other hand, high performance should not be achieved at the expense of computational efficiency. Without the improvement of machine learning, N is usually chosen to be 12. High-speed testing methods can be applied to exclude non-corner points.

[0270] The high-speed test for rejecting non-corner points operates by examining four sample pixels (i.e., pixels 1, 9, 5, and 13). Since there should be at least 12 consecutive pixels, whether they are all brighter or darker than the candidate corner, at least three of these four sample pixels must be either brighter or darker than the candidate corner.

[0271] First check pixels 1 and 9. If both I1 and I9 are in [I... P -t, I P If the candidate point p is within [+t], then it is not an angle.

[0272] Otherwise, further examine pixels 5 and 13 to check three of them compared to I. P Is +t brighter than I? P -t means darker. If three of them are either brighter or darker, the remaining pixels are checked to reach a final conclusion.

[0273] Furthermore, according to the inventor, in his first paper, an average of 3.8 pixels were needed to check candidate corner pixels. Compared to 8.5 pixels for each candidate corner, 3.8 is a significant reduction that can greatly improve performance.

[0274] However, this testing method has several weaknesses: a. For N < 12, the high-speed test cannot be generalized well. If N < 12, then the candidate point p is a corner and only 2 out of the 4 example test pixels are larger than I. P +t is brighter or brighter than I P -t will be darker, which will be possible.

[0275] b. The efficiency of the detector depends on the selection and ordering of these chosen test pixels. However, the selected pixels are unlikely to be optimal, which involves the distribution of angular appearance.

[0276] c. Multiple features were detected to be adjacent to each other.

[0277] Leveraging improvements in machine learning To address the first two weaknesses of high-speed testing, a machine learning approach is introduced to help improve the detection algorithm. This machine learning approach operates in two phases. First, corner detection is performed on a selected set of training images from the target application domain using a given N. Corner detection is achieved through a very simple implementation that essentially extracts a 16-pixel loop and compares the intensity value to an appropriate threshold.

[0278] For a candidate p, every position x ∈ {1, 2, 3, ..., 16} on the circle can be represented by p → x. The state S of each pixel... p→x It must be in one of the following three states: d, I p→x ≤I P -t (darker) s, I P -t≤I p→x ≤I P +t (similar) b, I p→x ≥I P +t (brighter) Then, x (which is the same for all p) is chosen to divide P (the set of all pixels in all training images) into 3 distinct subsets Pi. d P s P b ,in: P d = {p∈P:S p→x = d} P s = {p∈P:S p→x = s} P b = {p∈P:S p→x = b} Secondly, the decision tree algorithm, ID3, is applied to 16 locations to achieve maximum information gain. Let K... p It is a Boolean variable that indicates whether p is an angle, and then K P The entropy is used to measure information about the angle p. For a set of pixels Q, K Q The total entropy (unnormalized) is: H(Q)=(c+n)log2(c+n)-clog2 c-nlog2n; Where, c = |{i∈Q:K i =True}|(number of angles); Where, n = |{i∈Q:K i =False}|(Non-angle quantity).

[0279] Then, the information gain can be expressed as: H g = H(P) - H(P) b )-H(P s )-H(P d ).

[0280] A recursive process is applied to each subset to select each x that maximizes the information gain. For example, x is first selected to partition P into P's with the most information. d P s P b Then for each subset P d Ps and P b , select another y to produce the most information gain (note that y can be the same as x). This recursive process ends when the entropy is zero, such that all pixels in the subset are either corners or non-corners.

[0281] The generated decision tree can then be converted into program code, such as C and C++, which is just a bunch of nested if-else statements. For optimization purposes, profile-guided optimization is used to compile the code. The encoded code is later used as a corner detector for other images.

[0282] Note that the corners detected using this decision tree algorithm should be slightly different from the results using the piecewise test detector. This is because the decision tree model depends on the training data, which cannot cover all possible corners.

[0283] A multi-core processor enables each thread (regardless of which core the thread is on) to process a subset of the image rows:

[0284] It should be noted that the inner "for" loop and the "if / else" within the inner loop are standard C that is compiled into standard types of assembly instructions.

[0285] Using a parallel for is a less common type of construct, but there are standards for this type of thing (e.g., OpenMP).

[0286] Two interesting alternatives regarding parallel for are static vs dynamic work partitioning.

[0287] Static partitioning works by implementing the parallel for as "for (y = my_thread_id(); y < height; y += total_num_threads)". In this way, using a total of 32 threads (on an MPC, this is the result of 4 cores × 8 threads per core), thread 0 processes rows 0, 32, 64...; thread 1 processes rows 1, 33, 65,... etc. ...

[0288] Dynamic partitioning works by implementing the parallel_for as "for (y = atomic_add(counter, 1); y < height; y = atomic_add(counter, 1)".

[0289] When applying dynamic partitioning, the SoC doesn't know which thread processes which row until runtime (hence the name "dynamic partitioning"), they all share an atomic counter, and whenever a thread finishes a row, it increments the counter.

[0290] The advantage of dynamic partitioning is that if there is significantly less work in some parts of the image than in others, then the thread that gets the "easy" rows will simply process more rows overall, while the thread that gets more "difficult" rows will process fewer rows overall, but they will all finish at approximately the same time, without any fast threads idly waiting for the laggards. Therefore, dynamic partitioning is better for dynamic workloads.

[0291] However, static partitioning has the following advantages: SoC does not have atomic counters, but uses thread-local simple counters, which are very inexpensive (1-2 cycles to increment the counter vs. possibly tens or hundreds of cycles).

[0292] Each processor supports atomic counters slightly differently.

[0293] Multi-core processors can have a fixed number of atomic counters in dedicated hardware. According to another embodiment of the invention, the atomic counters can be implemented by storing the counters in shared memory.

[0294] You might prefer a list with corner-x,y coordinates rather than producing a wide x-height Boolean matrix corner[x,y]. This is because most pixels aren't corners, so a list of coordinates is a more compact representation than a Boolean matrix, making it a better choice in terms of memory usage in common cases. Then you'd want something like "if (evaluate_decision_tree(x, y)) { corner_list[index++] = (x, y);}". To make this work, you again need an atomic counter, hence atomic_add(index, 1) instead of index++, because you have multiple threads updating the index.

[0295] Figure 6E Showing a multi-core processor, which is related to Figure 6A The difference with multi-core processors is the inclusion of Inter-Thread Communication (ITC) 8000 for facilitating synchronization between different threads executed by multiple cores (when applied in...). Figure 6A On multi-core processors) or (such as Figure 6E As shown, this facilitates synchronization between different threads executed by multiple cores and serial processors.

[0296] The ITC 8000 can store atomic counters and / or data locks.

[0297] The ITC 8000 can be coupled to processor cores 606a-d and serial processors 616 via interconnect 8030 or in any other way (and especially to FIFO 698a-e).

[0298] Each atomic counter update request may include an opcode (increment, decrement, or reset), an atomic counter identifier to identify the atomic counter that should be updated, and a request identifier to identify the requesting unit (processor core or serial processor) and even the thread.

[0299] Figure 6F The various FIFOs 698a-e of processor cores 606a-d and serial processor 616 are shown. These FIFOs store requests for updating (incrementing, decrementing, or resetting) atomic counters.

[0300] FIFO 698a-e is read by discriminator 8010, which determines which request should be sent to input buffer 8012 of atomic counter region 8020 of ITC 8000. If two atomic counter requests for updating the same atomic counter are received in the same cycle, discriminator 8010 selects one of the atomic counter requests and sends the selected request to input buffer 8012 before sending the other atomic counter request to input buffer 8012.

[0301] The atomic counter region 8020 includes a memory module 8002, which includes multiple entries 8004a-n for storing multiple atomic counter values.

[0302] Memory module addresses 8004a-n are located between demultiplexer 8001 and multiplexer 8003. Following multiplexer 8003 is processor 8005, which increments, decrements, and resets the value of the atomic counter output by multiplexer 8003. The value of the atomic counter output by multiplexer 8003 can also be used as an output (sent via output 8008) to a core (or serial processor) requested to update or read the atomic counter. The output of the atomic counter may be the value before (as shown in the attached figure) or the value after the update.

[0303] The selected atomic counter value is used to control multiplexer 8003 to determine which atomic counter should be fed to processor 8005. The opcode for the atomic counter update request is fed to processor 8005 and controls the operation performed by processor 8005. The selected atomic counter value is also used to control demultiplexer 8001 to determine where the updated atomic counter (which memory entry in memory module 8002) is stored. The requester identifier is used to determine the fate of the updated atomic counter output via output 8008 and propagated via interconnect 8030. Demultiplexer 8001 may be a line encoder.

[0304] Although Figure 6FA single processor 8005 is shown for updating up to one atom counter per cycle, but the ITC8000 may include multiple processors 8005 and / or any other circuitry for updating multiple different atom counters per cycle.

[0305] According to embodiments of the invention, atomic counters represent different threads. By ensuring that only a single component can update a particular atomic counter at a time, a conflict-free thread allocation process is provided.

[0306] An atomic counter can point to an address in the instruction memory (which can represent the start of a thread), a data unit, and so on.

[0307] Using a dedicated cell (ITC) for storing atomic counters prevents conflicts and bottlenecks associated with accessing memory cells that store data processed during the execution of a thread.

[0308] Implementing atomic counters using dedicated hardware has been found to be ten times faster than implementing them using general-purpose processors.

[0309] It has been found that updating a single atom counter per cycle provides sufficient system performance when using simple single-processor hardware.

[0310] Atomic counters can also be used to calculate histograms. An atomic counter can store the counts (frequency) of bars and / or point to the destination of data cells within a memory area allocated to the data cells of a bar.

[0311] When multiple data units belonging to the same straight bar are received in the same period, an atomic counter can be used to update the count and / or calculate the destination address of the multiple data units without error, so that the counter will be updated by the number of multiple data units, and each of the multiple data units receives a different destination address.

[0312] Therefore, based on the foregoing, some examples of this disclosure pertain to a multi-core processor device comprising: a plurality of processing cores configured to execute a plurality of instruction threads of a software program using bucket thread processing; and a shared data cache configured to send data to at least two of the plurality of processing cores and receive data from at least two of the plurality of processing cores, the shared data cache storing data associated with the execution of a first instruction in at least one of the plurality of instruction threads. In addition to one or more examples disclosed above, or as an alternative, in some examples, the plurality of processing cores comprises: a plurality of thread registers, wherein at least one of the plurality of thread registers is associated with an instruction thread among the plurality of instruction threads; an instruction memory, wherein the instruction memory stores one or more instructions associated with the plurality of instruction threads, one or more arithmetic logic units, and a bucket scheduler, wherein the bucket scheduler receives a first clock signal, loads a first instruction from one or more instructions from the instruction memory, and executes the first instruction by retrieving data from a first thread register, wherein the first thread register is associated with the instruction thread associated with the first instruction, and sending the received data to one or more arithmetic logic units for processing. In addition to one or more examples disclosed above, or as an alternative, in some examples, the bucket scheduler receives a second clock signal, loads a second instruction from one or more instructions from the instruction memory, and executes the second instruction by retrieving data from a second thread register, wherein the second thread register is associated with the instruction thread associated with the second instruction, and sends the received data to one or more arithmetic logic units for processing. In addition to one or more examples disclosed above, or as an alternative, in some examples, each of a plurality of thread registers is configured to load data associated with the instruction thread. In addition to one or more examples disclosed above, or as an alternative, in some examples, multiple processing cores execute multiple instruction threads simultaneously. In addition to one or more examples disclosed above, or as an alternative, in some examples, one or more of the multiple cores transfer data to and receive data from a shared data cache, wherein the shared data cache is configured to store data generated from the execution of the multiple instruction threads. In addition to one or more examples disclosed above, or as an alternative, in some examples, the device includes a serial processor configured to execute single-threaded program code.

[0313] Some examples of this disclosure relate to a method for processing multiple instruction threads of a software program, the method comprising: executing multiple instruction threads using multiple processing cores, wherein the multiple processing cores use bucket thread processing to execute the multiple instruction threads, and sending data to and receiving data from at least two of the multiple processing cores using a shared data cache, wherein the shared data cache stores data associated with the execution of a first instruction in at least one of the multiple instruction threads. In addition to one or more examples disclosed above, or as an alternative, in some examples, the method comprises: receiving a first clock signal at a bucket scheduler of the multiple processing cores; loading a first instruction from an instruction memory, wherein the instruction memory stores one or more instructions associated with the multiple instruction threads; executing the first instruction by: retrieving data from a first thread register, wherein the first thread register is associated with the instruction thread associated with the first instruction; and sending the received data to one or more arithmetic logic units for processing. In addition to or as an alternative to the examples disclosed above, in some examples, the bucket scheduler receives a second clock signal, loads a second instruction from one or more instructions from the instruction memory, and executes the second instruction by retrieving data from a second thread register, wherein the second thread register is associated with the instruction thread associated with the second instruction, and sends the received data to one or more arithmetic logic units for processing. In addition to or as an alternative to the examples disclosed above, in some examples, each of a plurality of thread registers loads data associated with the instruction thread. In addition to or as an alternative to the examples disclosed above, in some examples, multiple processing cores execute multiple instruction threads simultaneously. In addition to or as an alternative to the examples disclosed above, in some examples, one or more of the multiple cores transfer data to and receive data from a shared data cache, wherein the shared data cache is configured to store data generated from the execution of the multiple instruction threads. In addition to or as an alternative to the examples disclosed above, in some examples, the method includes: executing one or more single-threaded program codes using a serial processor.

[0314] Some examples of this disclosure relate to a non-transitory computer-readable storage medium having stored a set of instructions for processing a software program's multiple instruction threads. When executed by a computing device, these instructions cause the computing device to: execute the multiple instruction threads using multiple processing cores, wherein the multiple processing cores use bucket thread processing to execute the multiple instruction threads; and send data to and receive data from at least two of the multiple processing cores using a shared data cache, wherein the shared data cache stores data associated with the execution of a first instruction in at least one of the multiple instruction threads. In addition to one or more examples disclosed above, or as an alternative, the computing device may: receive a first clock signal at a bucket scheduler of the multiple processing cores; load a first instruction from an instruction memory, wherein the instruction memory stores one or more instructions associated with the multiple instruction threads; execute the first instruction by: retrieving data from a first thread register, wherein the first thread register is associated with the instruction thread associated with the first instruction; and sending the received data to one or more arithmetic logic units for processing. In addition to or as an alternative to one or more examples disclosed above, the bucket scheduler receives a second clock signal, loads a second instruction from one or more instructions from the instruction memory, and executes the second instruction by retrieving data from a second thread register, wherein the second thread register is associated with the instruction thread associated with the second instruction, and sends the received data to one or more arithmetic logic units for processing. In addition to or as an alternative to one or more examples disclosed above, in some examples, each of a plurality of thread registers loads data associated with the instruction thread. In addition to or as an alternative to one or more examples disclosed above, in some examples, multiple processing cores execute multiple instruction threads simultaneously. In addition to or as an alternative to one or more examples disclosed above, in some examples, one or more of the plurality of cores transfers data to and receives data from a shared data cache, wherein the shared data cache is configured to store data generated from the execution of the multiple instruction threads. In addition to or as an alternative to one or more examples disclosed above, in some examples, the computing device uses a serial processor to execute one or more single-threaded program codes.

[0315] Multithreaded core using instruction chaining Using the processor architecture described above, in a quad-core processor utilizing bucket-based threading, the processor as a whole can execute four instructions during a single clock cycle. In other words, each core of the processor executes a single instruction during one clock cycle. One way to increase the number of instructions executed during a single clock cycle is to increase the number of cores within the processor. However, adding more cores within each processor to increase the number of instructions executed during a single clock cycle also leads to increased power consumption and a larger package size for the processor.

[0316] One way to increase processing throughput during a single clock cycle without increasing the amount of hardware within each processor is to increase the number of instructions that a single core of the processor can run in parallel during a single clock cycle. By taking advantage of common or shared characteristics of some instructions encountered by the processor, a single core can execute multiple instructions during a single clock cycle.

[0317] Take the following pseudocode example ("Example 2"): i. a = OP2(OP1(b,c),d) The example above involves nested instructions, referred to in this paper as an "instruction chain." The result of the first instruction OP1(b, c) is used as input to instruction OP2. In a conventional processor, the above encoded example could be executed as two separate instructions. In the first instruction, operation 1 (OP1) is performed on inputs b and c. The result is then written to memory. In the second instruction, operation 2 (OP2) can be performed on input d, and the result of OP1 can be stored in memory.

[0318] Writing the result of operation 1 to external memory might be wasteful, since that result is not needed by the user or program, but only as input to the second operation. In other words, the user or program doesn't need this "intermediate result"—the output produced by OP2. Because the user or program doesn't need the output of OP2, it might be useful to reduce the number of instructions required to implement the chained instructions.

[0319] Figure 7 An exemplary conventional dual-issue processor is shown according to an example of this disclosure. Figure 7 Examples can demonstrate how such a conventional processor can handle chained instructions. Figure 7 The dual-issue processor may include a program memory / instruction memory 602 that can be coupled to multiple instruction registers 604a-b. Each instruction register 604a-b may be further coupled to a register file 606.

[0320] Two independent instructions can be read from program memory 602 into instruction registers 604a and 604b. One instruction can be loaded into instruction register 604a, and the other into instruction register 604b. Once instruction registers 604a and 604b are loaded, they can pass the operands of the instruction to be executed to register file 606.

[0321] Using instruction register 604a as an example, once an instruction from program memory 602 is loaded into instruction register 604a, the register can pass the operands to be operated on to register file 606, and at the same time pass the instruction to be executed to execution unit 608.

[0322] In one example, execution unit 608 may include one or more arithmetic logic units, load memory units, etc., which can execute instructions provided to it by instruction registers 604a-b. Execution unit 608 may have symmetric or asymmetric capabilities along with logic for determining which unit in execution unit 608 will perform a given operation.

[0323] Register file 708 can load the operands to be executed into execution unit 608. Figure 7 In the example, execution unit 608 may have four read ports (e.g., two read ports for each instruction register) to read operands of instructions from input, and two write ports (one write port for each instruction) to write the results of instructions to register file 606.

[0324] In the example of chained instructions, instruction registers 604a and 604b can each receive an opcode. Using the naming convention of Example 2 above, the first instruction register 604a can receive OP1, while the second instruction register 604b can receive OP2. Execution unit 608 can receive two separate opcodes, one from each instruction register. Therefore, in a conventional processor, chained instructions might require a total of six register file ports (four inputs and two outputs), and program memory could require two instructions to be read per cycle.

[0325] However, if chained instructions can be encoded so that they use only one opcode and no unused results (such as intermediate results) are written to registers, the overall overhead of a dual-issue processor can be reduced in terms of preserving register file ports and program memory bandwidth.

[0326] Figure 8 An exemplary dual-issue core processor configured to accept chained instructions is shown as an example according to this disclosure. Figure 8The processor shown is configured to process one thread at a time and therefore has only one instruction register 704.

[0327] Use the following example operation ("Example 3"): i. a=b*c+d By convention, the above equation can be encoded in two separate instructions. The first instruction (i.e., the first instruction to be executed) could be tmp = b * c, where "tmp" represents temporary memory or a variable. The second instruction could be a = tmp + d. Figure 7 In the configuration shown, these instructions will be operated sequentially / serially. Since the second instruction depends on the result of the first instruction, it would be impossible to execute them simultaneously. Instead, a linked processor can encode two instructions associated with the above equation into a single instruction.

[0328] exist Figure 8 In the example, a processor utilizing compact chained instruction encoding (where "compact chained instruction encoding" and "instruction linking" are used interchangeably) can encode the equation a = b*c + d into a single instruction. In the first cycle, instruction register 704 can contain the chained instruction from Example 3 above. The operand associated with the first independent instruction (i.e., b*c) can be sent to register file 708, and the multiplication instruction can be sent from instruction register 704 to execution unit 712. In parallel with the above actions, instruction register 704 can send the operand and instruction (i.e., a, d, and +) associated with a second dependent instruction to chained instruction register 706. Chained instruction register 706 can receive the dependent portion of the chained instruction and, once the independent portion of the chained instruction has been executed, send the instruction to the appropriate execution unit for processing. Still within the first cycle, one of the units of execution unit 712 calculates b*c and stores the result in intermediate register 710.

[0329] At the next cycle, the execution unit of execution unit 712 can obtain operands from intermediate register 710 (which contains b*c in the example above) and from chain instruction register 706 (which contains a, d and + in the example above) and execute the + instruction at one of the execution units 712.

[0330] Furthermore, during the same cycle, instruction register 704 can load a new instruction, which is then sent to execution unit 712 for execution. Therefore, within a single cycle, two operations (the dependent portion of a chained instruction and the new instruction) can occur in parallel. In this way, even though a chained instruction is presented to execution unit 712, the two operations can still occur in parallel at any given cycle, thus maintaining increased throughput for the processor.

[0331] As demonstrated in the example above, encoding chained operations as a single operation instead of two separate operations can reduce the use of instruction register space and memory bandwidth, while simultaneously reducing the number of read and write ports required to execute chained instructions.

[0332] Some of the advantages that chained instruction encoding gives to processors can be amplified in barrel-threaded processors. For example, the reduction in the number of input and output ports in the register file due to compact encoding can be amplified in barrel-threaded processors, where the cost of additional read ports will be multiplied by the number of register files in the barrel-threaded processor. (See above regarding...) Figure 5A The barrel-threaded processor under discussion will have eight register files. Therefore, the fact that output and input ports can be saved by using chained instruction encoding means that in a barrel-threaded processor with eight threads, the port savings caused by one register file can be multiplied by the multiple register files utilized by the barrel-threaded processor.

[0333] Figure 9 An exemplary dual-issue core configured for bucket thread processing and accepting chained instructions is shown according to an example of this disclosure. Figure 9 Examples can be compared with those in Figure 8 The publicly disclosed examples operate in essentially the same way. One difference could be that, due to the fact that each thread operates only once every N cycles, the additional input ports of the register file can be maintained, where N equals the number of threads manipulated by the bucket-threaded processor (i.e., in...). Figure 5A In the example, it's eight. Because of this fact, operands associated with chained operations (such as slave instructions) can be read in during a cycle when a particular thread is idle.

[0334] Go to Figure 9 And utilize, as in Figure 7 In the example instruction a=b*c+d (Example 3), at the first cycle, the chain of instructions containing the command to execute a=b*c+d can be loaded from program memory 802 into instruction register 804. Instruction register 804 can then send operands b and c to register file 806a, which may correspond to the instruction register used by the first of N threads to be executed by the processor, and send the addition instruction (+) to execution unit 812. Simultaneously, instruction register 804 can also send the operands and instructions (d and +) for the chained command to chained instruction register 808a.

[0335] During cycle 1, the multiplication of b*c can be performed by execution unit 812, and the result can be stored in intermediate register 810a. Intermediate register 810a can be dedicated to storing intermediate results of the first thread (e.g., results that the program or user does not need). In this way, each thread can have its own intermediate register (i.e., thread N can have intermediate register 810n as shown).

[0336] At the next cycle, the contents of the chain instruction register 808a corresponding to a and d can be sent to register file 806a, while the + operand can be sent to execution unit 812. As discussed above, by the time cycle 2 begins, the result of b*c can be stored in intermediate register 810a. Therefore, at cycle 2, the processor can begin processing the second part of the chained instructions.

[0337] Meanwhile, new instructions from the second thread can be processed by the processor in the same way as b*c was processed in cycle 1. Therefore, in the second cycle, the two operations can occur simultaneously. The chained operation of the first thread can be accomplished by adding b*c stored in intermediate register 810a to operand d loaded from the chained instruction register 808a by register file 806a.

[0338] In this way, it is not necessary to wait until the first thread's round recurs (at cycle N+1) to execute the second part of the chained instructions, which can be executed concurrently with the instructions associated with another thread during the execution of the chained instructions.

[0339] Figure 9 The processor may also include a multiplexer 814. The multiplexer 814 may contain logic that determines which individual execution unit of execution unit 812 will operate on the operands.

[0340] Figure 10A and Figure 10B This illustrates the operations that occur during the first and second time periods, respectively, while the processor is processing chained instructions. Figure 9 The processor described herein can be "clocked," meaning that a clock signal is fed to some or all of its components. The clock signal helps synchronize the various components of the processor. When the processor's components are clocked, the functions performed by the processor can be described as occurring within a clock cycle or time period. For example, a first time period can describe the time period between the receipt of a first clock signal and a second clock signal. A second time period can describe the time period between the receipt of a second clock signal and a third clock signal, and so on.

[0341] Figure 10AAn exemplary chained instruction processing flow during a first clock cycle is illustrated according to an example of this disclosure. (The following will be discussed regarding...) Figure 9 The hardware diagrams provided in the document describe Figure 10A The processing flow is as follows. In step S902, the chained instructions can be loaded from program memory 802 into instruction register 804. A chained instruction can consist of two parts: an independent instruction part and a dependent instruction part. The independent instruction part refers to the portion of the chained instruction that can be executed without first waiting for an intermediate result. In the example a = b*c + d (Example 3), b*c can refer to the "independent part." The dependent instruction part refers to the portion of the chained instruction that must wait for an intermediate result before it can be executed. In the above equation, operands a and d, as well as the [+] operation, can all represent dependent parts. It should be noted that a chained instruction can have more than one independent and one dependent instruction part.

[0342] At step S904, the independent instruction portion and its associated operands can be transferred to the execution unit 812 for processing. The operands of the independent instruction portion can be transferred from the instruction register 804 to the register file 806a, while the instruction itself can be transferred from the instruction register 804 to the execution unit 812. The execution unit 812 can load the appropriate operands of the independent instruction portion from the register file 806a to execute the independent instruction portion.

[0343] At step S906, the subordinate instruction portion is transferred to the chain instruction register 808a and stored there when the execution of the independent instruction portion occurs. At step S908, the independent instruction portion is executed, and at step S910, the result is stored in the intermediate register 810a.

[0344] Figure 10B An exemplary chained instruction processing flow is shown during the second clock cycle, according to an example. Figure 10B In the processing flow, two processes can occur in parallel: 1) in steps S912-S918 ( Figure 10B The processing of the subordinate part of the chained instructions in the left side), and 2) in steps S920-S926 ( Figure 10B The processing of instructions from the second thread (on the right side of the image). As discussed above, in a bucket-threaded processor, a single processor can process instructions from another thread in each clock cycle. In an eight-threaded bucket processor, instructions from the first thread can be processed in the first clock cycle; instructions from the second thread can be processed in the second clock cycle, and so on. In the ninth clock cycle, the first thread can again “receive a turn” and execute the next instruction in the thread, or do nothing if the previous instructions were stalled for any reason.

[0345] Return to Figure 10B ,exist Figure 10A The processing of the dependent portion of the chained instructions discussed herein begins at step S912. At step S912, the dependent portion can be transferred to the execution unit 812 via register file 806a, and the operands associated with the dependent instruction portion can be transferred to register file 806a. At step S914, the result of the independent instruction portion can be transferred from intermediate register 810a to the execution unit 812. At step S916, the dependent instruction portion can be executed on the execution unit, and at step S918, the result can be stored in register file 806a.

[0346] As discussed previously, in a barrel-threaded processor, each individual thread can receive one round during one clock cycle. Therefore, in the second clock cycle, the instructions of the second thread can be executed in parallel with the execution of the dependent instruction portion of the chained instructions of the first thread.

[0347] At step S920, instructions from the second thread can be loaded into register file 806b (not shown). Register file 806b may represent a register file dedicated to operands originating from the second thread. At step S922, the instructions and operands associated with the second thread can be transferred to execution unit 812 for execution, which may occur at step S924. Finally, at step S926, the result of the instructions from the second thread can be stored in register file 806b.

[0348] Allowing subordinate instructions from the first thread to be executed in parallel with instructions from the second thread can result in increased processor throughput. Chained instructions can be executed in a single turn, rather than consuming two "turns" of threads to execute them.

[0349] Instruction chaining can also be applied in cases where there are more than two instruction sections and multiple operands, as in the following pseudocode example ("Example 4"): i. A=OP1(OP2(OP3(B,C)+d)+e) In the pseudocode example above, OP2 depends on the execution of OP3, while OP1 depends on the execution of OP2. Figure 8 The processor example can also handle these types of chained operations by ensuring that each intermediate result is stored in an intermediate register and operates during a clock cycle associated with another thread of the program.

[0350] In some examples, the read of operand d (the second part of the chained instruction) can occur during cycle 2 instead of cycle 1. While this example eliminates the need to send the operand from the chained instruction register to the register file, it may not change the number of read ports required by the register file, since three read ports are the maximum number of ports the register file needs to perform all necessary operations. Whether the operand associated with the chained instruction comes from the chained instruction register or the instruction register does not change the number of read ports required by the register file.

[0351] In some examples, the amount of operands sent to register file 806a can be changed by employing implicit linking. Implicit linking can be utilized by overwriting the operands of a chained instruction with the result of the chained instruction. Therefore, using Example 3 above, instead of encoding the operation as a = b * c + d, the operation can be encoded as a = b * c + a. In this example, the input operand a is overwritten after the result of the chained instruction is produced. In this way, instead of having to send four operands (a, b, c, d) to the register file, only three operands (a, b, c) can be sent.

[0352] While barrel-threaded multi-core processors with shared inter-core data caches can offer greater processing efficiency in terms of power and speed, as discussed above, they may not be ideal for serial computing environments. If a program or code has a mix of tasks that can be parallelized and tasks that must be processed serially, barrel-threaded multi-core processors may oscillate between periods of optimal efficiency and below-standard efficiency. The advantages of barrel-threaded processors are realized when threads that can run in parallel are operating. However, the processor can become relatively inefficient when serial code is being processed. Therefore, including a separate serial processor optimized for operating code that must run serially can be advantageous.

[0353] Figure 10C An exemplary dual-issue core configured for bucket thread processing and accepting chained instructions is shown according to an example of this disclosure.

[0354] The dual-issue core includes a divider DIV 7026, a first ALU (AUA) 7036, a second ALU (AUB) 7038, a load memory unit 7054, an instruction register (IR) 7004, a chained instruction register (CIR) 7006, a thread register TID 7010, and includes register files RF0-n 7012.0-n, intermediate registers ITM 7014.0-n, a first register Rsc 7016.0-n, and a second register RFR. The 7018.0-n includes multiple sets of components, a first allocation logic 7020, first and second divider input buffers 7022 and 7024, a divider output buffer 7028, first and second AUA input buffers 7032 and 7034, an AUA output buffer 7037, first and second AUB input buffers 7042 and 7044, an AUB output buffer 7046, an output bus 7070, a write-back queue (WBQ) 7050, a controller 7060, and inter-thread communication 8000, which facilitates synchronization between different threads executed by multiple cores and optionally also between multiple cores and a serial processor.

[0355] Instructions are decoded by decoder 7011 and sent to the IR and / or CIR, unless they cannot be executed temporarily (e.g., the divider is too busy) and are then sent to the shadow IR and / or shadow CIR. Each thread may have one shadow IR and one CIR.

[0356] Each thread (out of (n+1) threads) is associated with a set of components, which includes intermediate registers, a register file (also known as the thread register file), its own first register, and its own second register.

[0357] The controller 7060 can implement bucket scheduling by controlling the flow of information between (a) a set of components associated with different threads and (b) any of the dividers DIV7026, AUA7036 and AUB7038.

[0358] According to an embodiment of the present invention, AUA 7036 is assigned to execute independent instructions, while AUB 7038 is assigned to execute chained (subordinate) instructions.

[0359] The AUA 7036 and AUB 7038 can operate in a pipelined manner, during which the AUA 7036 can execute independent instructions one after another for each thread, and the AUB 7038 can execute slave instructions one after another for the same thread.

[0360] Assume (a) there are eight threads ((n+1)=8), (b) controller 7060 performs bucket scheduling of the eight threads, and (c) the independent instruction of the first thread associated with register files RF0 7012.0, ITM 7014.0, Rsc 7016.0, and RFR 708.0 is executed during the first cycle. The two operands associated with the independent instruction are fed from RFR 7018.0 to the first and second input buffers 7032 and 7034 of AUA 7036.

[0361] Under these assumptions: AUA executes independent instructions during the first cycle. The results of the execution of the independent instructions are output by AUA 7036, fed to AUA output buffer 7038, via bus 7070 to WBQ 7050, and finally stored in ITM 7014.0 (after the first cycle is completed).

[0362] The next time any instructions from the first thread will be executed by core 7000 will be at the ninth cycle.

[0363] After the first cycle and before the ninth cycle, another operand required for the execution of the slave instruction is sent to Rsc 7016.6. Rsc 7016.0 and RFR 7018.0 can be fed using time-division multiplexing from the same output port of RFO 7012.0.

[0364] During the ninth cycle: (a) the contents of ITM 7014.0 and Rsc 7016.0 (via logic 7020) are fed to the first and second input buffers 7042 and 7044 of AUB 7046; (b) AUB 7046 executes a slave instruction. The result of the slave instruction execution is output by AUB 7046, fed to AUB output buffer 7048, via bus 7070 to WBQ 7050, and finally stored in RF0 7012.0.

[0365] During the ninth cycle, AUA can execute new independent commands for the first thread.

[0366] refer to Figure 10B Instead of fetching instructions from the second thread (S920), this method may include fetching the next instruction from the first thread and having the AUA execute that next instruction from the first thread (which should be a separate instruction), while the AUB (during the same cycle) executes the older subordinate instruction.

[0367] It should be noted that the execution of one or more threads may involve calculating division operations, which may involve accessing the divider DIV 7026.

[0368] Because division is a lengthy operation (it may last for, for example, dozens of cycles, such as 30 cycles), a divider can include multiple independent divider modules that can operate in parallel with each other and reduce the overall latency of the core.

[0369] Figure 10C The diagram illustrates a divider 7026, first and second divider input buffers 7022 and 7024, and two divider output buffers 7028.1 and 7028.2 according to an embodiment of the invention.

[0370] DIV 7026 includes first and second dividers 7026.6 and 7026.9, but may include more than two dividers.

[0371] Following the first and second divider input buffers 7022 and 7024 is the divider FIFO 7026.0, which can accumulate multiple pairs of operands. Figure 10C In the FIFO 7026.0 divider, the depth is two, but the FIFO 7026.0 divider may be deeper.

[0372] Following the divider FIFO 7026.0 is the demultiplexer 7026.2, which is used to assign a pair of operands (from the divider FIFO 7026.0) to one of the first and second dividers 7026.6 and 7026.9, specifically to one of the input buffer pairs (7026.3 and 7026.4, 7026.7 and 7026.8) preceding the first and second dividers 7026.6 and 7026.9.

[0373] The output of the first divider 7026.5 is fed to the output buffer 7028.1 and then to the bus 7070. The output of the second divider 7026.9 is fed to the output buffer 7028.2 and then to the bus 7070.

[0374] The divider controller 7026.1 controls the operation of DIV 7026, for example, by sending a selection signal to the demultiplexer 7026.2, by controlling the propagation of operand pairs through the divider FIFO, and by triggering the first and second dividers 7026.6 and 7026.9 to perform a division operation.

[0375] The divider controller 7026.1 can receive status indications (e.g., busy line signal and / or idle signal) from the first and second dividers 7026.6 and 7026.9.

[0376] When both the first and second dividers 7026.6 and 7026.9 are busy, the divider controller 7026.1 can notify ( Figure 10CThe controller 7060 does not send any operands to the divider 7026 until one or more of the first and second dividers 7026.6 and 7026.9 are not busy. The divider controller 7026.1 can prevent the sending of new operand pairs to the divider 7026 by any other means, such as by sending a busy line signal to logic 7020, to WBQ 7050, by sending an interrupt, etc.

[0377] The divider controller 7026.1 can instruct the demultiplexer 7026.2 to send a pair of operands to a non-busy divider and prevent sending a new pair of operands to an already busy divider.

[0378] Therefore, based on the foregoing, some examples of this disclosure pertain to a multi-core processor device comprising: a plurality of processing cores configured to execute a plurality of instruction threads of a software program using bucket thread processing, wherein the plurality of processing cores are configured to execute a chain of instructions associated with a first thread of the plurality of instruction threads by: loading the chain of instructions into a first instruction memory during a first time period, wherein the chain of instructions includes an independent instruction portion and a dependent instruction portion; transferring the independent instruction portion and one or more operands associated with the independent instruction portion to one or more execution units during the first time period; transferring the dependent instruction portion to a chained instruction register during the first time period; executing the independent instruction portion by one or more execution units during the first time period; writing the result of the independent instruction portion to a first intermediate register during the first time period; transferring the dependent instruction portion, one or more operands associated with the dependent instruction portion, and the result of the independent instruction to one or more execution units during a second time period; and executing the dependent instruction portion during the second time period. In addition to one or more examples disclosed above, or as an alternative, in some examples, the chained instructions are associated with a first thread of a plurality of threads, and the device processes the instructions associated with a second thread of a plurality of threads in parallel with the execution of the subordinate instruction portion of the chained instructions during a second time period. In addition to one or more examples disclosed above, or as an alternative, in some examples, one or more operands associated with the subordinate instruction portion include input operands, and executing the subordinate instruction portion includes overwriting the input operands with the result of the execution of the subordinate instruction portion. In addition to one or more examples disclosed above, or as an alternative, the device also includes a multiplexer configured to determine which execution unit will execute the subordinate instruction portion of the chained instructions, and which execution unit will execute the instructions associated with the second thread. In addition to one or more examples disclosed above, or as an alternative, the device also includes a shared data cache configured to send data to and receive data from at least two of the plurality of processing cores. This shared data cache stores data associated with the execution of instructions in at least one of the plurality of threads. The shared data cache and the plurality of processing cores interact without relying on a private data cache. In addition to one or more examples disclosed above, or as an alternative, one or more operands associated with a subordinate instruction portion are stored in a first register file during a second time period, and the instructions associated with a second thread include one or more operands stored in a second register file during the second time period. In addition to one or more examples disclosed above, or as an alternative, the device also includes a register file, a chained instruction register, and intermediate registers associated with each of the plurality of instruction threads.

[0379] Alternatively or additionally, the device processes another independent instruction portion associated with the first thread in parallel with the execution of the subordinate instruction portion of the chained instructions during the second time period. Alternatively or additionally, each processing core includes a first execution unit for executing the independent instruction portion of the first thread and a second execution unit for executing the subordinate instruction portion of the first thread.

[0380] Some examples of this disclosure relate to a method for executing chained instructions in a barrel-threaded processor configured to execute multiple instruction threads. A method is provided that includes: loading chained instructions into a first instruction memory during a first time period, wherein the chained instructions include an independent instruction portion and a dependent instruction portion; transferring the independent instruction portion and one or more operands associated with the independent instruction portion to one or more execution units during the first time period; transferring the dependent instruction portion to a chained instruction register during the first time period; executing the independent instruction portion by one or more execution units during the first time period; writing the result of the independent instruction portion to a first intermediate register during the first time period; transferring the dependent instruction portion, one or more operands associated with the dependent instruction portion, and the result of the independent instruction to one or more execution units during a second time period; and executing the dependent instruction portion during the second time period. In addition to one or more examples disclosed above, or as an alternative, in some examples, the chained instructions are associated with a first thread among multiple threads, and the method includes processing instructions associated with a second thread among multiple threads in parallel with the execution of the dependent instruction portion of the chained instructions during the second time period. In addition to one or more examples disclosed above, or as an alternative, in some examples, one or more operands associated with the dependent instruction portion include input operands, and wherein executing the dependent instruction portion includes overwriting the input operands with the result of executing the dependent instruction portion. In addition to one or more examples disclosed above, or as an alternative, in some examples, the method includes determining which execution unit will execute the dependent instruction portion of the chained instructions and the instructions associated with the second thread. In addition to one or more examples disclosed above, or as an alternative, in some examples, the method includes using a shared data cache to send data to at least two of a plurality of processing cores and receive data from at least two of a plurality of processing cores, the shared data cache storing data associated with the execution of a first instruction in at least one of a plurality of threads, the shared data cache and the plurality of processing cores interacting without relying on a private data cache. In addition to one or more examples disclosed above, or as an alternative, in some examples, during a second time period, one or more operands associated with the dependent instruction are stored in a first register file, and wherein the instruction portion associated with the second thread includes one or more operands stored in a second register file during the second time period. In addition to one or more of the examples disclosed above, or as an alternative, in some examples, each of the multiple instruction threads has its own register file, a chained instruction register, and intermediate registers associated with it.

[0381] Some examples of this disclosure relate to a non-transitory computer-readable storage medium storing a set of instructions for processing a software program, which, when executed by a computing device, cause the computing device to: load the chained instructions into a first instruction memory during a first time period, wherein the chained instructions include an independent instruction portion and a dependent instruction portion; transfer the independent instruction portion and one or more operands associated with the independent instruction portion to one or more execution units during the first time period; transfer the dependent instruction portion to a chained instruction register during the first time period; execute the independent instruction portion by one or more execution units during the first time period; write the result of the independent instruction portion to a first intermediate register during the first time period; transfer the dependent instruction portion, one or more operands associated with the dependent instruction portion, and the result of the independent instruction to one or more execution units during a second time period; and execute the dependent instruction portion during the second time period. In addition to one or more examples disclosed above, or as an alternative, the chained instructions are associated with a first thread of a plurality of threads, and wherein the computing device processes instructions associated with a second thread of a plurality of threads in parallel with the execution of the dependent instruction portion of the chained instructions during a second time period. In addition to one or more examples disclosed above, or as an alternative, one or more operands associated with the dependent instruction portion include input operands, and wherein executing the dependent instruction portion includes overwriting the input operands with the result of executing the dependent instruction portion. In addition to one or more examples disclosed above, or as an alternative, the device determines which execution unit will execute the dependent instruction portion of the chained instructions and the instructions associated with the second thread. In addition to one or more examples disclosed above, or as an alternative, the device uses a shared data cache to send data to at least two of a plurality of processing cores and receive data from at least two of a plurality of processing cores, the shared data cache storing data associated with the execution of a first instruction in at least one of a plurality of threads, the shared data cache and the plurality of processing cores interacting without relying on a private data cache. In addition to one or more examples disclosed above, or as an alternative, during a second time period, one or more operands associated with the dependent instruction are stored in a first register file, and wherein the instructions associated with the second thread include one or more operands stored in a second register file during the second time period. In addition to one or more of the examples disclosed above, or as an alternative, each of the multiple instruction threads has its own register file, a chained instruction register, and intermediate registers associated with it.

[0382] Cache coherence scheme for multi-processor systems Multiple accelerator devices and caches are used As above Figure 1 As discussed in the context, SoC 102 may have more than one accelerator, such as accelerators 112 and 114. Hardware accelerators 112 and 114 may further include multi-core processors, such as multi-core processors 204, 304 and 504 in multi-core accelerators 200, 300 and 500, respectively.

[0383] Figure 11 This is a generalized diagram illustrating a cache configuration 1600 for a system such as SoC 102 that can have multiple accelerators 1601a-n (each including processors 1604a-n). Note that... Figure 11 Some components that could be included in the accelerator or other devices configured with a cache 1600 can be omitted. Figure 11 The information disclosed herein is not intended to be restrictive. Furthermore, it should be noted that SoC 102 is merely an example of a system type, and 1600 can provide a cache configuration for that system. Processors 1604a-n can be, for example, multi-core processors, such as multi-core processors 204, 304, or 504. Optionally, multiple processors 1604a-n can be single-core processors or some combination of single-core and multi-core processors.

[0384] Each accelerator 1601a-n may also include a cache 1610a-n associated with its respective processor 1604a-n. Although in Figure 11 Each cache 1610a-n is represented as a single element, but in reality, each cache 1610a-n may include multiple separate caches for each individual core in the processor 1604a-n (e.g., like...). Figure 2 Private or "local" caches 206a-d. Optionally, each cache 1610a-n can be a single cache shared across multiple cores, such as a core-shared cache 514 ( Figure 5A Each accelerator 1601a-n can access external memory 1650, such as main memory or a higher-level cache. Typically, each accelerator 1601a-n copies variables from external memory 1650 to cache 1610a-n for relatively fast access by processors 1604a-n.

[0385] In either case, caches 1610a-n can maintain a local copy of the data corresponding to the address in external memory. For example, the local cache could be an L1 or L2 cache with a relatively limited capacity (e.g., 4-600Mb), but it can respond in significantly fewer clock cycles than external memory. Thus, the associated processor (e.g., 1604a-n) can access data much faster than by sending a request to external memory. If processor 1604a-n requests data not currently included in cache 1610a-n, it can fetch the data from external memory 1650 and save it to cache 1610a-n, making the next data access faster. Because cache 1610a-n can have a more limited capacity than external memory 1650, it can evict some data to make room for newly fetched data. If the data to be evicted is modified by the core (becomes "dirty"), the modified data needs to be written to external memory 1650 before evicting it, so that the work done on the cached data is not lost. This process will be described in more detail below.

[0386] Exemplary cache structure Figure 12 An exemplary cache structure 1700 (or “cache”) is shown according to certain examples disclosed herein. The exemplary cache structure 1700 may represent, for example... Figure 11 The structure refers to any of the caches 1610a-n in the exemplary cache structure 1700. In the exemplary cache structure 1700, cached data can be maintained in cache lines 1701a-n. Metadata corresponding to the cached data is also typically maintained in the exemplary cache structure 1700. The nature of this metadata can vary, but it typically includes address data (often referred to as "address bits" or "tags") 1703a-1703n. These address data 1703a-1703n can specify the address of their corresponding cache line 1701a-n in external or main memory. Other examples of metadata may include valid bits 1703a-n specifying the read / write conditions of data relative to external or main memory. The cache structure 1700 may also include dirty bits 1707a-n specifying whether a local write exists. In particular, the use of dirty bits 1707a-n will be explored in more detail below.

[0387] The Cache 1700 can manage data at the cache line granularity. For example, a Cache 1700 with a 64-byte line can fetch data in 64-byte portions. This can happen even when the processor requests less than 64 bytes of data (e.g., when the core requests only a single byte). Managing data at the cache line granularity can be efficient because the processor may access data close to what it has already accessed. For example, if the processor has already requested the byte at address X, it is more likely to subsequently access bytes at addresses X+1 and X+2 in external memory, where n >> 2, compared to the byte at X+n.

[0388] Immediately fetching the entire cache line allows the processor to locally access adjacent data within 64 bytes of the requested data. As discussed above, since the data is stored in the faster local cache 1700, this means the processor (e.g., processors 1604a-n) then accesses any data close to the requested data much faster. A similar effect can be achieved when the external memory is Dynamic Random Access Memory (DRAM), which only supports access to data in "bursts" of multiple bytes. The size of cache lines 1701a-n can be adjusted to be equal to or larger than a DRAM burst, providing local access to adjacent data. Furthermore, since cache 1700 typically stores metadata associated with each cache line 1701a-n (e.g., address data 1703a-n, validity data 1705a-n, and / or data indicating whether the line is dirty 1607a-n), a larger size allows for more efficient use of the metadata. For example, a cache 1700 operating at a 1-byte granularity instead of a 64-byte granularity must store external memory addresses 1603a-n for each byte. Because the cache is smaller than external memory, there may not be a one-to-one mapping between locations in cache memory and locations in external memory. Similar considerations apply to valid data 1705a-n and dirty data 1707a-n.

[0389] Cache Coherence: An Overview "Cache coherence" also involves, among other things, maintaining cache coherence to a practically feasible extent (e.g., Figure 11 This relates to data consistency issues between the CPU cache (1610a-n) and external memory. Cache consistency issues can arise when two processors use modified or differently updated copies of the same data from external memory.

[0390] Cache coherence problems can be described in terms of the context in which they occur. "True sharing" of cached data occurs when two different processors access and / or modify the same variable. True sharing can be intentional or accidental. Conversely, "false sharing" occurs when two different processors access and / or modify two different variables residing in or stored in the same cache lines 1601a-n. Each of these instances will be described in more detail below.

[0391] True sharing Figure 13A This displays the cache lines of two different processors participating in true sharing. Cache line 1810 is the local cache for processor 1801 (not shown), while cache line 1820 is the local cache for processor 1802 (not shown). Cache lines 1810 and 1820 store copies of the variable “X” in segments 1815 and 1825, respectively. The copies of X stored in 815 and 825 were originally retrieved from external memory (such as, for example...) Figure 11 The data is obtained from external memory (1650). Segments 1815 and 1825 can be of various sizes, but are typically multiple bytes of data.

[0392] Intentional true sharing occurs when a program running on processor 1801 needs to write to X, and a program running on processor 1802 requires this modified / written value of X instead of the value of X stored in its own cache 820 or external memory. Potential problems can arise if processor 1802 needs to access a copy of the modified value of X before processor 1801 has already written that modified value to external or main memory. In this case, the modified value of X exists only in segment 1815 of cache line 1810 (i.e., in processor 1801's cache), which cannot be directly accessed by processor 1802. The value of X in processor 1802's own cache (i.e., the value of X in segment 1825 of cache 1820) and the value in external memory will not be the most recent modification made by processor 1801. Instead, the only memory storing those most recent modifications of X might be segment 1815 in cache 1810. Therefore, in order to share the modified value of X between processors 1801 and 1802, a mechanism and / or protocol for transmitting the modified value of X needs to be implemented.

[0393] Accidental sharing is another potential true sharing problem. In accidental sharing, a program running on processor 1802 may not know that it needs or should use a version of X that has been modified by a program running on processor 801. Thus, the program running on processor 1802 can access an outdated copy of X and subsequently use that outdated value for calculations or determinations. Errors based on the use of outdated values ​​of X can then propagate to other programs and routines that interact with the program running on processor 1802.

[0394] The difference between accidental and intentional true sharing lies in the programmer's intent. In intentional true sharing, the code for a process running on two processors (e.g., processors 1801 and 1802) is written in a way that the need for communication between processors 1801 and 1802 via a variable (X in the example above) is known before the sharing occurs. In accidental true sharing, the programmer is unaware that two programs running simultaneously or in parallel will attempt to access the same data. In the case of accidental true sharing, simultaneous access occurs as a result of a program error.

[0395] In the context of intentional and unintentional true sharing, one way to record which data has been written and which data has not been written is by using the "dirty" bits 1835 and 1845 ( Figure 13A and 13B Note that the reference to "bit" is not intended to be limiting. A dirty "bit" can be larger than a single bit (in which case, "dirty bit" might be more appropriately called an "indicator") and can store information beyond what is described herein. A dirty bit typically stores one of two values: a first indicating that data was written during a certain time period (e.g., the time period since the dirty bit was last reset) or under specific conditions, and a second indicating that the same data has not yet been written during the same time period. Figure 13A and 13B In the example shown, dirty bits 1835 and 1845 are actually "dirty line bits," meaning that the "variables" (whose state is specified by dirty bits 1835 and 1845) are actually the entire cache lines 1810 and 1820, respectively. In other words, any segment written to cache lines 1810 or 1820, and not just 1815 or 1825, will set the corresponding dirty bit 1835 or 1845 to indicate that a write has occurred. Optionally, dirty bits can be assigned to specify the state of a separate variable X stored at segments 1815 and 1825. Figure 13A and 13B In the example shown, dirty bits 1835 and 1845 are used such that when they are set to "1", writes occur in the corresponding cache line. When they are set to "0", no writes have occurred since the last reset of dirty bits 1835 and 1845.

[0396] like Figure 13A As shown in the example, writing a "new" value to variable X at segment 1815 sets dirty bit 1835 to "1". This setting indicates that a write to cache line 1810 has occurred. Conversely, since no writes to any segments of cache line 1820 (including variable X stored in segment 1825) have occurred since the last reset, dirty bit 1845 remains set to "0". In this case, dirty bits 1835 and 1845 indicate that the data in cache lines 1810 and 1820 is out of sync. However, they do not indicate which(s) segments (i.e., segments 1815 and 1825 representing variable X) are out of sync.

[0397] fake sharing Figure 13B This illustrates that when two different variables in a copy of the same external memory cache line are written by processors 1801 and 1802, it may occur, for example... Figure 13A The configuration discussed herein involves a situation where "false sharing" occurs. Specifically, "false sharing" occurs when processor 1801 modifies variable X and processor 1802 modifies another variable Y stored in the same cache line in external or main memory. This can lead to the following consequences.

[0398] like Figure 13B As shown, local cache lines 1810 and 1820, which hold X and Y, are both "dirty," as indicated by bits 1835 and 1845, respectively. However, they are dirty for different reasons. Cache line 1810 is dirty because it contains a new or updated value of X at 1815. On the other hand, cache line 1820 is dirty because it contains a new or updated value of Y at 1827. Therefore, cache line 1810 contains an old or outdated copy of Y at 1817, and cache line 1820 contains an old or outdated copy of X at 1825. This means that processors 1801 and 1802 eventually write the contents of cache lines 1810 and 1820 back to external memory. Since cache lines 1810 and 1820 are both local copies of the same cache line in external memory, they need to be written to that same cache line in external memory. Since writes cannot be completed simultaneously, one write must overwrite the other. This leads to lost work and potential errors. If processor 1801 first writes back its value to cache line 1810, then processor 1802 will eventually use the old X stored in 1825 to overwrite the new (or newer) X stored in 1815. Conversely, if processor 1802 first writes back its data, then processor 1801 will use the old Y stored in 1817 to overwrite the new Y stored in 1827.

[0399] This overwriting and the resulting data loss is called "false sharing" because neither variable X nor Y is "true shared" between processors 1801 and 1802. Instead, X is accessed only by processor 1801, not 1802, and Y is accessed only by processor 1802, not 1801. This "false sharing" can lead to problems similar to those described in the context of true sharing above.

[0400] Solving the data consistency problem in true or false sharing As discussed in the background section above, both hardware and software systems can be used to address cache coherence problems. These systems (such as those implementing “full cache coherence”) often introduce additional complexity in terms of hardware, software, or both dedicated to sharing data between processes. In the embodiments described herein, additional hardware for addressing false sharing can be implemented alongside a software scheme for addressing true sharing. This software scheme can reduce the likelihood of problems associated with shared data by minimizing or eliminating data sharing between parallel processes. Therefore, the hardware and software described herein can potentially avoid or reduce many problems in cache coherence, even when running on a system, without the additional hardware and other complexities required to achieve data sharing under “full cache coherence.”

[0401] Hardware for solving false sharing Figure 14 This illustrates one way to resolve false sharing within the context of this disclosure. Figure 14 In the example, cache line 1910 is local to processor 1901, while cache line 1920 is local to processor 1902. Similarly, as in... Figure 13A and 13B In the context of this, cache lines 1910 and 1920 both store copies of the same external memory cache line (not shown) containing two variables X and Y. Note that, although Figure 14 Only a single cache line 1910 / 1920 for each cache is shown, but each cache may include multiple cache lines. For example... Figure 14As shown, cache lines 1910 and 1920 are both marked "dirty" by bits 1935 and 1945, respectively, because both contain newly modified or updated data that needs to be written back to external memory. This is because local caches 1910 and 1920 contain different updates to the data for X and Y, respectively. Specifically, cache 1910 contains the new or updated value for X at segment 1915, while cache 1920 contains the new or updated value for Y at 1927. Cache 1910 also contains a stale or unmodified copy of Y at 817, and cache 1920 contains a stale or unmodified copy of X at 1925.

[0402] like Figure 14 As shown, caches 1910 and 1920 also each contain additional arrays of bits at positions 1950 and 1951, respectively. These are collectively referred to as "dirty bits" associated with the individual bytes of their respective cache lines. Figure 14 In the example shown, for each byte in cache 1910 / 1920, there is a dirty bit in 1950 / 1951. This particular arrangement (one dirty bit per cache byte) helps to track the write status of each bit in the cache and thus each variable. However, it should be understood that other arrangements are possible, and there may be bytes in cache 1910 / 1920 without an associated dirty bit.

[0403] The dirty bit for each cache line byte can be used to monitor the write status of cache line bytes, as described below. For example, when cache line data is first fetched from external memory into cache lines 1910 / 1920, dirty bits 1950 / 1951 can initially be set to "0". Subsequently, when a byte in local cache lines 1910 / 1920 is modified, its corresponding dirty bit can be set to "1". This arrangement... Figure 15 As shown in the image.

[0404] Figure 14The example illustrates this arrangement for several bytes. For instance, the bytes corresponding to dirty bits 1950a and 1951a have not yet been modified by processors 1910 or 1920. Therefore, they remain set to "0". Conversely, each of the four bytes corresponding to variable X in cache line 1910 has been updated or modified by processor 1910. Therefore, all four dirty bits 1950b-c corresponding to these bytes are set to "1". Since processor 1920 has not modified or updated variable X, the corresponding dirty bits 1951b-c in cache line 1920 remain set to "0". Since each of the four bytes corresponding to variable Y in cache line 1920 has been modified by processor 1920, all four dirty bits 1951f-i corresponding to these bytes are set to "1". Since processor 1901 has not modified Y, the corresponding dirty bits 1950f-i remain set to "0".

[0405] Logically grouping dirty bits together might make the "dirty line" bits 1935 / 1945 redundant. This is because dirty line bits 1935 / 1945 indicate that cache line 1910 / 1920 is dirty if and only if at least one byte is dirty. Despite this redundancy, maintaining dirty line bits 1935 / 1945 may still be desirable. Since they are single bits, dirty line bits 1935 / 1945 can generally be read faster and easier than all the dirty bits 1950 / 1951 together. Furthermore, checking dirty line bits 1935 / 1945 to determine whether the value in cache 1910 / 1920 has been updated does not require any logical operations. Therefore, maintaining dirty line bits 1935 / 1945 allows for efficient evaluation of the data state in cache 1910 / 1920, regardless of any redundancy. Dirty bits 1935 / 1945 can be maintained (i.e. explicitly written) or calculated from dirty bits 1950 / 1951.

[0406] like Figure 14 As shown, each cache line 1910 / 1920 may also include "valid" (or "validity") bits 1937 / 1947. These valid bits 1937 / 1947 correspond to... Figure 12 The valid bits 1705a-n are shown in the exemplary cache structure.

[0407] As in Figure 12As discussed in the context, the valid bit can be used to specify whether data from external memory should be used to flush the associated cache line. For example, setting the valid bit 1937 to "0" indicates that the data in cache line 1910 is invalid and needs to be flushed. Therefore, during the next data read from external memory, processor 1901 will overwrite cache line 1910 with the current data stored in the corresponding cache line in external memory. Setting the valid bit 1937 to "1" indicates that the data in cache line 1910 is valid (i.e., cache line 1910 does not need to be overwritten with data from external memory). In this way, the valid bit 1937 can be used to flush the associated cache line whenever a new process is started or initiated. Note that, as discussed herein, "starting" a process can typically mean starting the execution of the process remotely or locally. Once a process is started, it can be initiated, for example, by copying values ​​to local memory. For example, a process initiation can automatically set all valid bits (e.g., 1937 and 1947) to "0", ensuring that all cache lines are updated with the values ​​stored in external memory as quickly as possible. This process is called "invalidating" the cache data. A process can also invalidate the cache after it has written data to external memory. As discussed in more detail below, when cache lines 1910 / 1920 have been written to external memory or main memory, valid bits 1937 and 1947 can be invalidated (e.g., set to "0") after a write-back. For example, invalidating cache 1910 / 1920 at the end of a process when it is written back allows cache 1910 / 1920 to be updated with new data from external memory (e.g., verified) before the next process begins. Cache 1910 / 1920 can also be invalidated by setting valid bits 1937 and 1947 to invalidate at the initiation of cache 1910 / 1920 and in several other cases.

[0408] Processors 1901 / 1902 can use dirty bits 1950 / 1951 to determine when and how to write to external memory to reduce or eliminate the problem of false sharing. For example, processors 1901 / 1902 can generate a single memory request to write their entire cache line 1950 / 1951 to external memory. When writing to the cache line, processors 1901 / 1902 can use dirty bits 1950 / 1951 to only write those dirty bytes (e.g., in...). Figure 14The example shown has a value of "1". In this example, processor 1901 will only write the new or modified value of X stored in 1915b-c, and will not change any other values ​​in the cache line of external memory. This means that if processor 1902 previously wrote the updated value of Y (i.e., the updated value stored in 1927) to external memory, processor 1901 will not overwrite that updated value of Y. If the writes occur in reverse order (i.e., first processor 1901 uses dirty bits 1950b-c to write the updated value of X, and then processor 1902 uses dirty bits 1951f-i to write the updated value of Y), then the second write will not overwrite the updated value of X. This is because processor 1902 will use dirty bits 1951f-i to write only the new value of Y in 1927 to external memory. It will not change the value of X in external memory because the dirty bit (i.e., dirty bits 1951b-c) corresponding to the value of X in cache line 1920 is set to "0". Therefore, overwriting of the most recently updated data can be avoided regardless of the order in which writes occur.

[0409] As described above, writing cache lines 1910 / 1920 to external memory using dirty bits 1950 / 1951 can be accomplished using standard bus protocols. For example, as described above, a single memory request can be made to write an entire cache line. In this case, the write can utilize I / O coherence protocols, such as the software I / O coherence protocol described in “Maintaining I / O Data Coherence in Embedded Multicore Systems” (TB Berg, Micro, IEEE 29(3): pp. 10-19 (2009)). This standard cache coherence protocol provides a hardware mechanism by which cache 1910 / 1920 requests and relinquishes ownership of shared data. More specifically, “I / O coherence” involves a protocol in which a first processor 1901 (if 1901 is an “I / O coherence device”) can read data from a second processor (e.g., processor 1902, where 1902 is a CPU that provides support for I / O coherence devices). In the I / O coherence protocol, processor 1901 is guaranteed to obtain the latest copy of the shared data from processor 1902. Processor 1901 can also perform writes, enabling processor 1902 to retrieve the latest copy of the shared data. As discussed in more detail below, these protocols can be used in combination with any of the solutions or embodiments described herein.

[0410] According to an embodiment of the invention, each core is configured to output the contents to be written to a cache line and the associated valid bits to external memory 1650 (during one or more cycles). External memory 1650 is capable of processing the valid bits and updating the cache line only with the updated cache line bytes. For example, external memory can be configured to be byte-enabled and capable of updating the cache line only with selected bytes.

[0411] Candidate Card Figure 13B For example, external memory 1650 may receive cache line content 1810 (including modified variable X 1815) from processor 1801 and cache line content 1820 (including modified variable Y 1817) from processor 1802 during one or more cycles (simultaneously and / or continuously), both involving the same line, and may modify variables Y and X accordingly using only the byte-enabled protocol.

[0412] In another exemplary approach, a memory request can be generated for each "dirty byte" (i.e., each byte of cached data corresponding to a dirty bit) or for each group of adjacent dirty bytes. This approach requires a separate write for each dirty byte.

[0413] Optionally, byte enable bits can be used to control which data in cache lines 1950 / 1951 will be written to external memory in a single write operation. Setting a byte enable bit to "1" indicates that the data corresponding to those bits will be written to external memory. Setting a byte enable bit to "0" indicates that the data corresponding to those bits will not be written. Therefore, byte enable bits can be set based on dirty bits 1950 / 1951. More specifically, when the corresponding dirty bit 1950 / 1951 indicates that data has been modified by processor 1901 / 1902, the byte enable bit corresponding to a single memory cache line write can be set to "1". The byte enable bit for all other data in the write operation can be set to "0". Setting the byte enable bit in this way results in only modified or updated data being written to external memory.

[0414] This type of write is supported by the I / O coherence protocols discussed above. More specifically, I / O coherence typically supports writes of fewer than a full cache line by using a byte enable bit in the bus request. In other words, if the processor 1901 is an "I / O coherent device," it automatically uses the byte enable bit as described above.

[0415] The single-write method is relatively efficient, at least because it requires fewer write operations to write multiple updated variables to external memory. For example, in a case where cache line 1910 has two updated variables (each 1 byte in size) (e.g., variables A and B), using the byte enable bit will allow both variables to be written to external memory in a single write operation. This advantage is particularly important when external memory is written in data strings (e.g., DRAM). In this case, if the size of cache line 1910 is equal to the size of the DRAM data string (e.g., 64 bytes), writing A and B will both require issuing only a single 64-byte data string, where the byte enable bit corresponds to the variable and B is set to "1". This write is twice as efficient as the alternative (i.e., using data strings to write each dirty byte of A and B separately). This is because writing A and B separately requires two single-byte data strings. However, even if the on-chip bus protocol supports single-byte data strings, the DRAM memory does not. Thus, two single-byte data strings will be required from the DRAM. For a DRAM with a 64-byte data string size, this would require two 64-byte data strings to write A and B to external memory.

[0416] Software for solving true sharing Figure 11 A diagram illustrating the arrangement between processes according to an example of this disclosure is shown. Figure 11 The arrangement in [the context] can solve the problems of accidental and intentional true sharing mentioned above. As will be described in more detail below, in [the context] Figure 11 One characteristic of the system described in the document is that all processes are encoded so that two concurrently running processes do not access writable (or "mutable") variables.

[0417] Figure 16A and Figure 16B This illustrates a non-limiting example of two processes executed by two processors, where the processes are designed (programmed) not to access the same segment (e.g., the same byte) of the same memory line simultaneously (or even different versions of the contents of the same memory line). It is possible to prevent one process from accessing the same segment of the same memory line for any predetermined period of time. This period of time can be very long (e.g., thousands or even tens of thousands of cycles). It should be noted that the two processes may be unrelated to each other, and one process may not necessarily trigger or control the other.

[0418] The combination of real collision prevention and false collision management provides a robust and consistent memory management scheme.

[0419] In Figure 16A and Figure 16B In the example shown, the two processors 1901 and 1902 run two different processes, A and B, respectively. Figure 16BThe durations of processes A and B are shown in the timeline. Note that although in Figure 16A and... Figure 16B The timeline only shows two processes, A and B, but this is not intended to impose restrictions. In fact, processes A and B can be started sequentially compared to those shown in Figure 16A and B. Figure 16B The process is much more extensive than shown. The timeline begins at "0" and shows six phases (11105-11130). The structure of the cache 1910 / 1920 associated with processors 1901 / 1902 is shown below. Figure 14 As shown in the image.

[0420] As in Figure 16B As indicated, processes A and B run concurrently in the following sense: process A runs for the entire duration of the timeline (0 to 11130), and process B runs only for a portion of the timeline (11110 to 11125). When process A is started at point 0 on processor 901, its first task may be initiated by "[writing input]" (i.e., copying the variables it needs from external memory (not shown) to the local cache 1910 of processor 901). Examples may be included in... Figure 14 Let X and Y be variables represented in the table. Process A can set all valid bits 1937 for each line in cache 1910 to "0", such that the next read from external memory will overwrite cache line 1910. Setting the valid bits 1937 in this way may be advantageous, as each cache line 1910 is assumed to be invalid. New input can then be freely read from external memory, ensuring that cache 1910 will not contain any stale values ​​written by previous processes when the new process executes. After the input is read into cache 1910 and process A executes, process A can perform operations that modify the variables (e.g., X and / or Y) in cache line 1910. When this happens, process A can write the modified values ​​of the variables to local cache 1910, setting the dirty bit 1950 corresponding to the newly written variable to "1".

[0421] 11105-11110 Startup Process B Process A can run on processor 1901, making 1901 a "consumer" processor and processor 1902 a "producer" processor. In this case, process A can initiate process B on processor 1902, as shown at 11110 in Figure 16A. Process B can be, for example, a computational process that takes a relatively long time to complete.

[0422] At the start of process B (11110), the valid bit 1947 in cache 1920 may be invalid, for example, equal to "0" (i.e., indicating that the data in cache 1920 needs to be refreshed with a value from external memory). In this way, new input can be freely read from external memory, ensuring that cache 1920 will not contain any stale values ​​written by previous processes when a new process executes. For example, process B can read variables X and Y ( Figure 8 ).

[0423] Procedure B, 11110-11115, is executed without shared variables. During this period, process B executes. When it does so, it can read additional variables into its cache 1920 and / or modify variables in cache 1920. For example, it can modify variables X and Y. When this happens, it stores the modified variables in its local cache 1920 and sets the corresponding dirty bit 1951 to "1" to indicate the modified data, such as... Figure 14 As shown. When the data is modified, process B can further set the valid bit 1947 to "0", indicating that cache line 1920 is no longer valid.

[0424] During the execution of process B, as shown in Figure 16A, process A can still execute, as long as its execution does not require variables that can be accessed by process B. In this example, if process B accesses variable variables X and Y, then process A will not be allowed to access X and Y until process B terminates at 11125. Furthermore, processor 1901 can also run other processes, assuming those processes also do not access variables accessed by processor B. That is, while process B is executing, other processes running on processor 1901 will not be allowed to access variables X and Y. In this sense, when process B is executing on processor 1902, processor 1901 is still free to run "independent work" (e.g., work that does not depend on variables that might be modified by process B). Restricting processor 1901 to "independent" work prevents the sharing of variable data. If a process running on processor 1901 concurrently with process B running on processor 1902 does not access the same variable data or variables as process B, then as described above... Figure 8 In the context discussed here, the "true sharing" problem may not exist. In short, while process B is executing, no other process can share any mutable data with process B.

[0425] Process B (11115-11125) terminates by sharing all variable variables. The computation of process B is completed at 11115. At this point, process B can initiate a "write-back" or update the external memory process with any changes it has made to variables in the local cache 1920 of processor 1902. A write-back can be performed as described above. Figure 14 The write-back is performed as described in the context (e.g., by setting the byte enable bit using the dirty bit 1951 to write all modified data to external memory in a single write). Write-backs are typically repeated across all cache lines. As shown at 115-11120 in Figure 16A, the process can also be performed by setting all valid bits 1947 to "0" for each cache line (i.e., invalidating each cache line). Invalidation and write-back can be performed simultaneously or separately.

[0426] As shown in Figure 16A, from 11120 to 11125, process B can signal that it has completed execution. Signaling completion by process B allows other processes to access any variable variables used by process B after the write-back. Because process B has performed a write-back, the updated values ​​of the variables used by process B are now stored in external memory. In this example case, process B writes variables X and Y back to external memory, and upon receiving the signal, process A (or any other process running on processor 1901) will be able to access copies of the newly modified X and Y that processor B just wrote to external memory.

[0427] 11130 Process A Read Output After process B has terminated and signaled completion (11120-11125), process A (and any other process running on the system) can access the variables that process B just wrote to external memory. As shown in Figure 16A, process A is free to read the output generated by process B from external memory. Those outputs can include any variables that were written to process B (e.g., variables X and Y in this example).

[0428] Model and I / O consistency Above and in Figure 11The true data sharing model described in the context is supported by an I / O coherence protocol. More specifically, I / O coherence supports shared data only at process "boundaries" (i.e., process start-up 1105-11110 and termination 11115-11125). In fact, I / O coherence is adapted to this type of data sharing because it is typically designed for cases where processor 1901 ("I / O coherent device") has no cache. Because the protocol assumes that there is no cache for processor 1901, processor 1902 is unaware of the state of processor 1901's cache. Therefore, processor 1902 provides the latest copy of the input to process A running on processor 1901 and writes its data to external memory upon termination, as if it were an I / O device without a cache (11115-11120).

[0429] Increased consistency of results As discussed above, software used to solve true sharing ( Figure 11 This essentially prohibits or reduces data sharing during concurrent execution. Therefore, data sharing is reduced or eliminated during execution, resulting in a more consistent order in which shared variables are written to external memory. In fact, under strict or rigorous application of this restrictive sharing, the order in which processes are written to external memory can be considered fixed or immutable, leading to more consistent or even deterministic results.

[0430] This is best illustrated by example. In Figure 11 In the example shown, process B will write / update any variables it modifies to external memory at 11115. That is, by a deliberately imposed constraint, process A will not update any data or variables it shares with process B until process B terminates execution by writing its data to external memory (11115) and signaling completion (11125). In other words, because process A cannot access any variable data being used by process B until process B terminates execution by writing its data to external memory (11115) and signaling completion (11125), process B will always write any mutually shared data before process A writes its data. This means that in the case of... Figure 11 The examples shown illustrate certain embodiments in which any mutually shared data (e.g., variables X and Y) will always First updated by process B, then by process A. As long as processes A and B are deterministic (i.e., do not generate random data), then... Figure 11 The results produced by the system should also be deterministic.

[0431] Conversely, systems that facilitate the sharing of variable data through parallel processes will lead to nondeterministic and sometimes unpredictable updates to the shared data / variables. This is because such systems cannot correct the order in which processes update variables in external memory. An example is a system that uses data locks to prevent consistency problems while allowing parallel processes to share data. A data lock is a variable that a process must check before it can modify the data protected by the lock. When only one process can check the lock at a time, only one process can modify the data at a time. Therefore, implementing locks can reduce consistency problems by preventing simultaneous access / updates of data. However, even if they may not access the lock simultaneously, two processes (e.g., Figure 11 Processes A and B in the system can still access locks and data during parallel execution. In this case, the order in which the two processes write to external memory can be determined by a variety of factors, including the details of the data input to the system. Even the order of the input data (e.g., sorting the input data according to different criteria) may potentially change the order in which the two processes write to external memory. Because some results may depend on the order in which the processes update the data in external memory, the system can have considerable variability in its outcomes or consequences.

[0432] Figure 16C Data locks 8100a-j and data lock requesters 8200a-e are shown according to embodiments of the present invention.

[0433] Assuming a request to lock a data lock can be made by a party belonging to Figure 11 Processor 1604a-n or belonging to Figure 6A The processor cores 604a-d and serial processor 616 generate data lock requesters 8200a-e. Assume there are five processors. Any number of processors / requesters can be provided.

[0434] Data lock 8100a-j can belong to the data lock section 8020 of ITC 8000, but it can be located elsewhere.

[0435] The number of data locks can be 256, but it doesn't have to be. A trade-off can be made between the number of data locks and the functionality they can provide. For example, when using data locks to protect the contents of a histogram bitmap, there could be 256 data locks for every 1024 bars, although any relationship between the number of data locks and bars can be provided.

[0436] A request to lock a data lock includes the identifier of the data lock that should be locked and the locking command. Figure 16C In this context, the identifier is represented as C0.ReqLockID - C4.ReqLockID, and the lock opcode is represented as C0.lock - C4.lock.

[0437] A request to unlock a data lock includes the identifier of the data lock to be unlocked and the unlock opcode. Figure 16C In this context, the identifier is represented as C0.ReqLockID - C4.ReqLockID, while the unlock opcode is represented as C0.release - C4.release.

[0438] Data lock 8100a includes comparator 8102 (for comparing the identifier of data lock 8100a - “Self-ID” with each of C0.ReqLockID - C4.ReqLockID) and logic gates (such as AND gates 8104a-e and AND gates 8105a-e), which form a request filter that does not propagate data lock requests (lock or release) unrelated to data lock 8100a.

[0439] A request to unlock data lock 8100a is sent to AND gates 8105a-e to perform a logical AND with the output of comparator 8102, and the output of AND gates 8105a-e is fed to OR gate 8010 to generate a release signal 8108 indicating acceptance of one or more requests to release data lock 810a.

[0440] The output signals of AND gates 8104a-e, along with the mask bits (mask[0] - mask[5] of mask 8418), are sent to AND gates 8106a-e, which only send requests masked by mask 8418 to the first priority encoder 8110. As will be explained in more detail below, mask 8418 is timed out to provide a dynamic arbitration scheme. The mask can allow the processing of the masked request to lock data lock 8100a.

[0441] The first priority encoder 8110 receives only requests for the masked portion of the locked data lock 8100a, selects up to a single masked portion, and outputs an authorization vector 8410 (including [0] of the bit authorization mask – [4] of the authorization mask) indicating the selected masked portion. It is assumed that once a selection is made, only one bit of the authorization vector 8410 of the mask is set.

[0442] OR gate 8114 applies an OR operation to the bits of the authorization vector 8410 of the mask to determine whether the first priority encoder has selected a request for a single mask.

[0443] While the first priority encoder 8110 arbitrates only between requests for a mask, the second priority encoder 8112 arbitrates between all requests, regardless of the mask.

[0444] The first and second priority encoders 8110 and 8112 can apply any arbitration scheme. For example, the first and second priority encoders can select the request with the lowest index. Any other arbitration scheme may be applicable. The first and second priority encoders 8110 and 8112 can apply the same arbitration scheme or different arbitration schemes.

[0445] The output signal of AND gate 8104a-e is also sent to the second priority encoder 8112. The second priority encoder 8112 receives a request to lock data lock 8100a, selects up to a single request (regardless of the mask), and outputs a mask-ignored authorization vector 8412 indicating the selected mask (including bit authorization_no mask[0]). – Authorization_no mask[4]). Assume that once a selection is made, only one bit of the authorization vector is set to mask-unknown.

[0446] The masked grant vector 8410 and the mask ignorance grant vector 8412 are fed to the first multiplexer 8118, and the selection between these two vectors is determined by a control bit output from the OR gate 8114. If the first priority encoder 8110 selects a request for a single mask, the mask grant vector 8410 is output from the first multiplexer 8118. If the first priority encoder 8110 does not select a request for any mask, the mask ignorance grant vector 8412 is output from the first multiplexer.

[0447] The value of data lock 8100a is stored in D-type trigger 8130 and represented as state (STATE) 8422.

[0448] An AND operation (gate 8116) is applied between state 8422 and the reverse release 8108 to provide a "no one wins" signal 8414 indicating that the data lock is locked and there is no request to unlock the data lock.

[0449] The "No one wins" signal 8414 is fed to the second multiplexer 8120, causing the second multiplexer 8120 to output a reset authorization vector (e.g., 00000) when the data lock is locked and there is no request to unlock it. Otherwise, the second multiplexer 8120 outputs a signal from the first multiplexer 8118 to provide an authorization vector indicating the selected request to lock the data lock 1800a.

[0450] The grant vector 8420 is output to a processor that can (based on the content of the grant vector) notify which processor has successfully locked data lock 1800a.

[0451] The authorization vector 8420 is sent to the OR gate 8124 that outputs the output signal 8125. The output signal 8125 and the "no one wins" signal 8414 are fed to the OR gate 8128, which resets the trigger 8130 only when both the output signal 8125 and the "no one wins" signal 8414 are reset.

[0452] The authorization vector 8420 is also fed to the mask encoder 8121, which modifies the mask 8414 and feeds the updated mask to the buffer 8122. The buffer 8122 can be a FIFO.

[0453] A mask encoder can apply any mask modification scheme. For example, a mask encoder can generate a mask that identifies the selected request, suspend the corresponding selection bits of the mask and all the lower significant bits of the mask (if present), and set all the higher significant bits of the mask.

[0454] This hardware architecture is compact, fast, and easy to access, and allows only a single processor to lock a single data lock per cycle.

[0455] Figure 16D A state machine 8210 for a data lock update request according to an embodiment of the present invention is shown.

[0456] The state machine is executed by each of the data lock requesters 8200a-e.

[0457] State machine 8210 is started from the idle state 8212.

[0458] After idle 8212, the state 8218 can be the state where a lock request (cmd_lock) is sent.

[0459] After idle 8212, it is also possible (if not certain to send a data lock request) to check whether the unlock criteria have been met: (a) whether the data lock requester has generated a data lock unlock command (cmd_unlock), and (b) whether the thread (or process) whose data lock was locked by the data lock requester has finished. The completion of a thread or process can be detected in various ways, such as detecting whether the write queue of the processor allocated to the thread or process is empty (store_but_empty[TID]).

[0460] Exiting idle also involves sending a request to the processor to stop fetching instructions from instruction memory (set itu_WaitFor Lock), preventing the execution of threads that depend on the unlocking of the data lock.

[0461] If the unlock criteria are met, proceed to state 8216; otherwise, proceed to state 8214, which waits until the unlock criteria are met.

[0462] Status 8216 includes sending a request to ITU 8200 to unlock a data lock with an identifier that should be unlocked (e.g., C0.ReqLockID and C0.release).

[0463] State 8216 is followed by state 8212, which is idle. Exiting from state 8216 involves sending a request to the processor to restart fetching instructions from instruction memory (set itu_WaitFor Lock), allowing execution of threads that depend on the unlocking of the data lock.

[0464] After state 8218 comes step 8220, which checks the authorization (of the request for the locked data lock). If the request has been authorized, then state 8220 is followed by the idle phase 8218. Otherwise, state 8220 is followed by state 8222, which waits for the next time slot (allocated to a thread that has been blocked from execution until the locked data lock is authorized), and then state 8218 (or state 8220) follows step 8222.

[0465] The state machine integrates data lock management and bucket scheduling, and provides a compact, fast, and low-profile real estate solution for thread management.

[0466] Increased test reliability exist Figure 11 Increased consistency of results in a system facilitates debugging. In this system, as discussed above, the order of updates to external memory is fixed by constraints that prevent concurrent processes from accessing mutable data. This means that any code that adheres to this constraint, at least in terms of the order in which it updates data to external memory, should be deterministic. Therefore, one way to debug such a program is to test for inconsistent or uncertain results based on, for example, the order or sorting of the input data. If any such input produces inconsistent results, then 1) some processes in the system violate constraints against concurrent processes accessing mutable data, 2) some processes themselves are not deterministic, or 3) both 1) and 2) apply.

[0467] Furthermore, by monitoring process dependencies and data reads / writes to external memory, debugging tools for resolving potential faults can be built relatively easily. Figure 11In the publicly disclosed model, process A initiating process B implies that the processes are interdependent. The restricted sharing mode only allows interdependent processes to share data. Specifically, process A initiating B means that B can read memory written by A (1110). This also means that once process B terminates execution by writing its data to external memory (1125), process A can read memory written by process B (1130). Therefore, a simple debugging tool can be constructed as follows. This tool can: a) store the ID of the last process that wrote to a specific variable, and b) compare that ID with the IDs of processes that have read from the variable since the last write. If the ID comparison indicates that the variable was read by a process that does not depend on the last written data, it indicates that concurrent processes have shared mutable data. Similarly, if the ID comparison indicates that data was last written by a process that does not depend on any process that has read data since the last write, it also indicates that concurrent processes have shared mutable data. These two instances are in... Figure 11 In the context of this discussion, all situations will be considered program errors.

[0468] In systems that do not adhere to the constraint that concurrent processes cannot access mutable data, such tests may not be reliably implemented. This is because such systems are expected to have results that depend at least to some extent on the order of the input data.

[0469] Therefore, based on the foregoing, some examples of this disclosure pertain to an apparatus comprising multiple processors executing multiple processes, wherein multiple caches associated with the multiple processors are provided. The apparatus may include multiple caches, including at least a first cache associated with a first processor. The apparatus may also include a memory accessed by the multiple processors and storing multiple variables, wherein the multiple processors execute at least one of the multiple processes by: initiating a first process of the multiple processes on the first processor by storing a subset of the multiple variables into the first cache; terminating the first process by writing an updated copy of the subset to memory; and restricting access to the subset by multiple processes other than the first process during the execution of the first process. The multiple processes may include a second process, the execution of the first process on the first processor being initiated by a second process executed on the second processor, termination of execution including the first process invalidating the first cache and signaling completion to the second process, and upon receiving the signal, the second process accessing the subset. The apparatus may include an indicator providing indication of at least a first state and a second state, in which the first processor has not written bytes of data to the first cache, and in the second state, the first processor has written bytes of data to the first cache. The indicator may include a single bit. Indicators can be stored in a first cache. Terminating the execution of the first process by writing an updated copy of a subset can include, during a first state, generating a request for a line of the first cache containing bytes of data in the first cache, writing the line to memory such that the bytes of cached data in memory corresponding to the bytes of cached data in the first cache are substantially unchanged, and during a second state, writing the line to memory to overwrite the bytes of data in memory corresponding to the bytes of data in the first cache. Multiple processors can include multiple cores, and multiple cores share multiple caches. I / O coherence protocols enable devices to connect to other devices via an interface.

[0470] Some examples of this disclosure relate to a method for executing multiple processes in a device having multiple processors and multiple caches, the multiple caches including at least a first cache. References Figure 16E Method 8600 includes storing (8602) a plurality of variables in memory accessible by a plurality of processors, initiating (8604) a first process of a plurality of processes on a first processor by storing a subset of the plurality of variables in a first cache, terminating (8606) the first process by writing an updated copy of the subset to memory, and restricting (8608) access to the subset by a plurality of processes other than the first process during the execution of the first process. These processes are designed such that during the execution of the plurality of processes, only up to a single process can access a subset of memory (e.g., a portion of a memory line) at a time.

[0471] The method may include a second process executing (8601) multiple processes on a second processor, step 8604 including initiating a first process by the second process, and step 8606 including terminating the first process by invalidating a first cache and signaling completion to the process, and accessing (8612) the subset through the second process upon receiving the signal. The method may include providing (8614) an indicator that provides indication of at least a first state and a second state, in which the first processor has not written bytes of data in the first cache, and in the second state that the first processor has written bytes of data in the first cache. The indicator may include a single bit. Step 8606, terminating the execution of the first process by writing an updated copy of the subset, may include generating a request during the first state for a line of the first cache containing bytes of data in the first cache, writing the line to external memory such that the bytes of cached data in memory corresponding to the bytes of cached data in the first cache are substantially unchanged, and writing the line to memory during the second state to overwrite the bytes of data in memory corresponding to the bytes of data in the first cache. This method may include sharing multiple caches across multiple cores of multiple processors. This method may include enabling a device to interface with another device via an I / O coherence protocol or any other protocol, such as a byte-enabled support protocol. This method may include managing spurious contention by outputting an indicator with content to memory capable of performing updates based on the indicator.

[0472] Some examples of this disclosure relate to a non-transitory computer-readable storage medium having an instruction set stored thereon for processing software programs. When executed by a device having multiple processors and multiple cache memories, the instructions cause the device to store multiple variables in memory accessible by the multiple processors, initiate a first process among multiple processes on a first processor by storing a subset of the multiple variables into a first cache, the first cache being one of multiple caches in the device, terminate the first process by writing an updated copy of the subset to memory, and restrict access to the subset by multiple processes other than the first process during execution of the first process. The instructions can cause the device to execute a second process among multiple processes on a second processor, initiate the first process by the second process, terminate the first process by invalidating the first cache and signaling completion to the second process, and access the subset through the second process when the signal is received. The instructions can cause the device to store an indicator that provides indication of at least a first state and a second state, in which the first processor has not written bytes of data to the first cache, and in the second state, the first processor has written bytes of data to the first cache. The indicator may include a single bit. The indicator may be stored in the first cache. Terminating the execution of the first process by writing an updated copy of a subset may include, during a first state, generating a request for a line of the first cache containing bytes of data in the first cache, writing the line to memory such that the bytes of cached data in memory corresponding to the bytes of cached data in the first cache are substantially unchanged, and during a second state, writing the line to memory to overwrite the bytes of data in external memory corresponding to the bytes of data in the first cache. These instructions enable a device to share multiple caches across multiple cores of multiple processors. These instructions enable a device to interface with another device via an I / O coherence protocol.

[0473] A multi-core processor device may be provided, which may include multiple processing cores configured to execute software programs using bucket-based threading, one or more data caches, one or more instruction memories, and an inter-thread communication module, which may include an atomic counter section and a data lock section for synchronization among the multiple threads.

[0474] The inter-thread communication module may or may not belong to multiple processing cores, one or more data caches, and one or more instruction memories.

[0475] The data lock section may include multiple data locks, wherein each data lock may include a mask for masking requests to lock the data lock, a mask encoder for changing the mask over time, a first priority encoder for selecting a request to lock the data lock using a selected mask, and a second priority encoder for selecting a request to lock the data lock regardless of the mask.

[0476] The first and second priority encoders can apply the same arbitration scheme.

[0477] The first and second priority encoders can apply different arbitration schemes.

[0478] Multiple processing cores may include data lock requesters; each data lock requester is configured to execute a state machine that controls the sending of requests to lock data locks, sends requests to unlock data locks, and selectively blocks the execution of threads.

[0479] Different data locks are binary variables, and different threads can only be executed if the data lock has a predetermined value.

[0480] The atomic counter section may include a memory module for storing multiple entries of multiple atomic counter values, a discriminator for periodically selecting up to a single request for updating a given atomic counter, and a processor for updating the given atomic counter.

[0481] The number of multiple entries can be less than the number of data locks in the data lock section.

[0482] One approach can be provided (see) Figure 48 Method 6600) may include multiple threads of a software program executed by multiple processing cores using bucket thread processing (6210), wherein execution by multiple threads may include synchronization between the execution of threads by utilizing data locks and atomic counters of an inter-thread communication module (6220).

[0483] The inter-thread communication module may or may not belong to multiple processing cores, one or more data caches, and one or more instruction memories.

[0484] Synchronization between the execution of threads may include managing (6622) multiple data locks, wherein the management of data locks may include masking requests for locking data locks by means of a mask, the mask being changed by a mask encoder over time, a first priority encoder selecting a request for locking data locks by a selected mask, and a second priority encoder selecting a request for locking data locks regardless of the mask.

[0485] This method may include applying the same arbitration scheme to both the first priority encoder and the second priority encoder.

[0486] The method may include different arbitration schemes that can be applied by the first priority encoder and the second priority encoder.

[0487] Multiple processing cores may include data lock requesters; wherein methods may include a state machine executed by each data lock requester (6630) for controlling the sending of requests to lock data locks, sending requests to unlock data locks, and selectively blocking the execution of threads.

[0488] The method may include storing (6640) multiple atomic counter values ​​at multiple entries in a memory module, having a discriminator periodically select up to a single request for updating a given atomic counter, and having the processor update the given atomic counter.

[0489] The number of multiple entries can be less than the number of data locks in the data lock section.

[0490] A non-transitory computer-readable storage medium may be provided, on which an instruction set is stored for multiple threads of a software program to be executed by multiple processing cores using bucket thread processing, wherein the execution of the multiple threads may include synchronization between the execution of the threads by utilizing data locks and atomic counters of an inter-thread communication module.

[0491] Data collection Figure 17 An exemplary vector processor according to an example of this disclosure is shown. Vector processor 2200 may include an array of addressable registers 2202 for storing data. Vector processor 2200 may receive data from an external source at a plurality of input registers 2206a-2206c and store the data in a specific memory location within addressable register 2202. In one example, the input registers may accept command parameters (e.g., opcodes of commands) and their associated operands. Operands may include data or address operands that may reference at least one register of the array. Based on the input command parameters, logic / processing circuitry 2204 may process the data stored in the addressable registers. A complete discussion of an exemplary vector processor is provided in U.S. Patent No. 8,300,058, which is incorporated herein by reference in its entirety.

[0492] Memory banks can be used in conjunction with the aforementioned systems 100 and 2200 to provide requested data. One example of a type of memory read is called a “scalar” read. A scalar read typically reads a single value from a single memory address. Another type of memory read is a single “vector” read, which uses a single address of a vector in memory as a starting point to read multiple vector values. In other words, a vector read will read all the values ​​of vector V (v0, v1, v2, ...) by using vector address “A” to extract the specific value at that address. A typical vector read relies on the proximity of the data of the vector being read in memory. A vector read will be able to load the values ​​of vector V using the following understanding: if the address of the vector is A, then component v1 is located at A+1 in memory, component v2 at A+2 in memory, component v3 at A+3 in memory, and so on. In the eight-byte example discussed above, a single vector read will use a single access to retrieve eight bytes of consecutive data, each of which corresponds to a different component of the vector. The data in a single vector read is most likely stored in a single memory location. However, in some implementations, it may be possible to read vectors into multiple memories.

[0493] Figure 18 This illustrates the alternative schemes for the aforementioned single memory access "single vector" read. Specifically, Figure 18 This illustrates an architecture 1300 that may be able to "collect" data read from multiple memory banks. Collection also refers to vector reads of data in the following sense: in some implementations, it can retrieve vector data. Again, an 8-byte read is chosen as an example for illustration. Figure 18 The implementation of architecture 2300 is shown. However, it should be understood that, within the context of this disclosure, any appropriate number of bytes can be read for an architecture such as architecture 2300.

[0494] like Figure 18 As shown, architecture 2300 can replace a single memory group with eight separate memory groups 2310a-h. Architecture 2300 may also include multiple memory initiators 2330a-h (eight in this example) connected to memory groups 2310a-h via interconnect 2320. Each initiator 2330a-h can forward an address corresponding to requested data to one of the memory groups 2310a-h via interconnect 2330. Interconnect 2320 can route the address to the appropriate group 2310a-h so that group 2310a-h can provide the requested data. Typically, each initiator 2330a-h is capable of routing addresses to access data in each group 2310a-h. However, in some embodiments, initiators 2330a-h may be pre-assigned to a specific group or a subset of groups 2310a-h.

[0495] The interconnect 2320 can be implemented using any suitable architecture, including the use of crossbar switches, switches, arbitration, or other interconnect hardware. The interconnect 2320 can further include multiple instances of these components and various arrangements of these and other components. In some implementations, it may be advantageous for the interconnect 2320 to handle “contention” that may occur when multiple addresses point to the same memory bank 2310a-h. A relatively complex interconnect 2320 that can be used in the context of this disclosure may provide additional advantages regarding the handling of contention and in adapting to increased scalability (e.g., by increasing the number of available memory banks and / or starters). However, a less complex interconnect 2320 design may also offer advantages in terms of lower power consumption, complexity, and / or throughput.

[0496] Accessing each of the eight memory groups 2310a-h in the same cycle via a "collection" memory operation can present advantages over accessing a single memory group, especially via scalar or single-vector memory reads. This potential advantage is best illustrated by example. Each group 2310a-h can have, for example, an access width of one byte per group. In this case, if an operation requires eight bytes of data, each byte stored in a different group, architecture 2300 can conceivably provide all eight required bytes of data in the same cycle. However, doing so requires implementing a scheme to map the addresses of the required bytes to the corresponding groups 2310a-h, with the appropriate addresses provided by the initiator 2310a-h. Many such schemes are possible, including sequentially accessing each group by iterating through only groups 2310a-h.

[0497] In some instances, a single data request for eight bytes of data can be mapped to a portion of a non-contiguous block of data in memory and / or to eight different addresses that are not located close together in memory. As an example, a single request for eight bytes of vector data could include single-byte vector components, each stored in a different group 2310a-h. This can occur during image correction operations such as fisheye correction. In fisheye correction, the data in question (i.e., the data that needs to be corrected) may be located around the periphery of the image. Such data has a relatively high probability of being stored in different locations in memory (e.g., in the same memory group with different addresses or in completely different memory groups). In this case, a single vector read as described above may not be optimized for handling such a request. For example, a single vector read of a single memory group might take eight cycles to read such a dataset and one cycle to read from each of the different addresses.

[0498] Figure 18The architecture 2300 shown, however, can handle such a request in a single cycle. In 2300, each group 2310a-h can provide one byte of data per cycle. This results in a throughput of 8 bytes per cycle, even if the data stored in different groups is not contiguous or close in memory. This type of data acquisition, which combines data from different memory locations in response to a request, is generally considered different from a single vector memory read as a "collection" operation.

[0499] Although this disclosure primarily relates to indicator 2330a-h ( Figure 18 This is an example of a scenario where each initiator 2330a-h requests one byte of memory, but other scenarios are possible. For instance, each initiator 2330a-h may request two bytes of memory. In this case, initiator 2330a-h needs one byte and can use the least significant bit to select the correct byte in the response data. This works even if the response data is returned to several initiators that access different bytes within the response word.

[0500] In some instances, addresses corresponding to other data in a component or a single data request will be mapped to the same group. Since architecture 2300 can only provide one byte per cycle from each group 2310a-h in this example, this condition will result in lower throughput. In short, without a mechanism to handle this specific case, architecture 2300 will require two cycles to read data from two different addresses mapped to the same group. For example, if two of the eight addresses generated by initiators 2330a-h are mapped to the same group, then that group will require two cycles to provide two bytes of data (i.e., one cycle for two bytes of data represented by each of the two addresses in the group). In this case, throughput will be halved to an average of four bytes per cycle (eight bytes in two cycles). Similarly, if three addresses are mapped to the same group, it will take three cycles to retrieve all eight bytes of data. The throughput then decreases to eight bytes / three cycles = 2.67 bytes / cycle. If all addresses are mapped to the same group, there will be no efficiency gain in implementing multiple groups 2310a-h, because it would take 8 cycles to get all eight bytes of data (i.e., one byte throughput per cycle).

[0501] Modified implementation for almost identical address handling As discussed above, collection operations that access two different addresses on the same memory group can lead to degraded throughput. More specifically, different addresses on the same group must be accessed in different cycles, thus reducing the average amount of memory returned per cycle. The situation of accessing two or more different addresses on the same group over two or more cycles is referred to herein as "group contention".

[0502] Problems can arise when two or more addresses input for collection are not strictly identical but point to the same word on the same memory bank. In such cases, the addresses are considered "nearly identical." Unless the collection operation has a mechanism for handling nearly identical addresses, they are typically treated as different addresses on the same bank. As discussed above, this treatment can lead to "bank contention" and a corresponding decrease in throughput.

[0503] Figure 19A An implementation of architecture 2400 is shown, including modified interconnects that can replace interconnect 2320. Figure 18 This is used to add the same address processing to the collection operation. In addition to the various components of the Architecture 2400, Figure 19A Memory groups 2410.0-2410.7 are also shown in the center of the diagram. (As shown...) Figure 19A As shown, there are eight groups 2410.0–2410.7. However, the number 8 is merely exemplary, and it should be understood that, within the context of this disclosure, architecture 2400 can be implemented to accommodate more than eight groups as needed. Architecture 2400 can also accommodate fewer than eight groups, depending on the application.

[0504] Assume each “collect” data read command includes eight addresses for eight bytes to be retrieved. The number of addresses (eight) and the length of the data units (bytes) are merely non-limiting examples. Interconnect 2400 includes a metadata calculator 24301 that generates metadata according to predetermined rules (e.g., indicator ac[][] 2431) such that only a single memory initiator accesses the same row at a time. The metadata calculator 24301 can compute metadata for each “collect” read command. Alternatively, a buffer can be used to store consecutive collect read commands, and the metadata calculator 24301 can compute metadata for one collect read command after another. The computation of metadata may include comparing the addresses of data units (or more precisely, portions of addresses pointing to memory rows) to find nearly identical addresses, marking nearly identical addresses, and then generating metadata according to a predefined scheme.

[0505] like Figure 19AAs shown, architecture 2400 includes eight command queues 2420.0-2420.7. Each command queue may correspond to one of memory groups 2410.1-2410.7. A series of addresses 2430 (A0…A7) are fed to each of queues 2420.0-2420.7. In addition to addresses 2430, architecture 2400 may also use the indicator ac[][]2431, which can be used to help determine which group receives which address and, as discussed in more detail in the next section, determine whether race conditions can be avoided by utilizing nearly identical addresses.

[0506] Each queue 2420.0-2420.7 can receive all eight addresses 2430 (A0…A7), even if any single queue can only use one of addresses 2430. This is because when an address 2430 is provided to command queues 2420.0-2420.7, the group corresponding to any given address may be unknown. Note that in this example, the fact that the number of addresses happens to be equal to the number of memory groups 2420.0-2420.7 (i.e., eight) is merely for illustrative purposes and not intended to be limiting. The number of addresses 2430 does not necessarily have to be equal to the number of groups 2420.0-2420.7. In some implementations of this disclosure, the number of addresses 2430 may be greater than or less than the number of groups 2420.0-2420.7.

[0507] As discussed in more detail in later sections, each command queue 2420.0-2420.7 can determine which address (A0…A7) 2430 is queued (and thus which data is collected from their associated group) by using the indicator ac[][] 2431 and / or “address bits” in address 2430. There are many schemes for using the indicator ac[][] 2431 or address 2430 to determine which address is processed by which group 2410.1-2410.7. The discussion of specific schemes in this disclosure is intended to be merely exemplary. Any suitable scheme is within the context of this disclosure.

[0508] An example scheme for determining address 2430 as a queue is to collect the address for each command queue 2420.1-2420.7, for which ac[i][i] has the value "1", where "i" is the index of queue 2420.1-2420.7 and its associated group 2410.1-2410.7. Alternatively, or as an alternative to this scheme, it is also possible to assign certain values ​​of "address bits" or "group selection bits" to Ai[] 2430. In one convention, address bits 1:3 can be group selection bits, such that if Ai[1:3] == 5, then command queue 2420 with index 5 (i.e., 2420.5) will process Ai. However, it should be understood that these schemes / conventions are merely exemplary, and any other conventions / schemes applicable to this application may be used in the context of this disclosure.

[0509] Although not in Figure 19A The document explicitly shows that the pipeline stage can precede the use of each queue 2420.0-2420.7. For each queue 2420.0-2420.7, the pipeline stage can determine which address 2430 (A0...A7) corresponds to the group 2410.0-2410.7 associated with the queue. Note that the pipeline stage can be a single pipeline stage, or it can itself include several pipeline stages. The pipeline stage can be performed based on "address bits" or "group selection bits," as discussed above.

[0510] Command queues 2420.0-2420.7 can be used to handle "group contention" (i.e., multiple different addresses mapped to groups 2410.0-2410.7 associated with queues 2420.0-2420.7). In some embodiments, queues 2420.0-2420.7 handle contention by ordering the different addresses so that they are processed in different cycles, one address per cycle.

[0511] Since handling command contention in command queues 2420.0-2420.7 can be expensive in terms of throughput, it may be advantageous to avoid placing addresses in command queues 2420.0-2420.7 unless necessary. For example, it may be advantageous to avoid using command queues 2420.0-2420.7 when the addresses in the processor are different but point to data within the same word ("nearly identical" addresses).

[0512] like Figure 19A As shown, the architecture may include a series of multiplexers (“muxes”) 405a-h. Multiplexers 405a-h may receive requested data from groups 2401.0-2401.7. Figure 19AMultiplexers 405a-h are shown that receive data from each group 2401.0-2401.7. While this is typical, it should be understood that this configuration is merely exemplary, and other configurations are also consistent with this disclosure. For example, any of the multiplexers 405a-h may receive data only from a subset of groups 2401.0-2401.7. Multiplexers 405a-h also receive an indicator matrix ac[][] 2431. Multiplexers 405a-h may receive matrix ac[][] 2431 or elements of matrix 2431 via buffer 440, which helps in selecting which data elements to provide. Buffer 440 may also introduce latency, and other functions not explicitly described herein, if needed. Figure 19A As shown, each multiplexer 405a-h can receive different rows of matrix ac[][] 2431. In other configurations (not shown) consistent with this disclosure, each multiplexer 405a-h can receive the entire matrix ac[][] 2431. In the latter case, multiplexer 405a-h can select the portion of matrix ac[][] 2431 to use in order to determine which data to select.

[0513] Multiplexer 405a-h can use elements of matrix ac[][] 2431 to determine which data (i.e., from which group 2410.0-2410.7) should be provided to the byte result register 2401a-h associated with multiplexer 405a-h. Specific methods and conventions for determining which data should be provided to which register 2401a-h can vary, although several examples will be discussed in the following sections. It should be understood that the methods used to determine the dataset from ac[][] 2431 discussed herein are merely exemplary, and any suitable method is consistent with this disclosure.

[0514] Figure 19B It is shown in Figure 19A Flowchart 450 shows an exemplary implementation of the architecture in the example. (See also:) Figure 19B As shown, in step 2451, addresses (A0...A7) 2430 and indicator ac[][] 2431 are provided to each command queue 2420.0-2420.7. At step 2452, command queues 2420.0-2420.7 use indicator ac[][] 2431 to select the appropriate address (A0...A7) 2430, which corresponds to the memory group 405.0-405.7 associated with queues 2420.0-2420.7. At this stage, command queues 2410.0-2420.7 also use indicator ac[][] 2431 to determine whether the requested address is nearly identical to another address in their queue, A0...A7 2420.

[0515] The nearly identical determination can take many forms consistent with this disclosure, as discussed in more detail in the following sections. Continuing with step 2452, if the provided address is nearly identical to another address (once to which data was provided), then in step 2453, queues 2420.0-2420.7 will not forward that address to memory groups 2410.0-2410.7 for retrieval. In step 2453, each group 2410.1-2410.7 receives the address of the data to be retrieved from its corresponding queue 2420.0-2420.7. Furthermore, in step 2453, the indicator matrix ac[][] 2431 (or a portion of the matrix, such as the portion selected by buffer 440) is forwarded to multiplexers 405a-h. In step 2454, each of multiplexers 404a-h receives data from each of groups 2410.1-2410.7. In step 455, multiplexers 404a-h use indicator matrix ac[][] 2431 to determine which data from groups 2410.0-2410.7 is forwarded to the byte result registers 2401a-h associated with the multiplexers. When each of queues 2420.0-2420.7 is empty, flowchart 2450 (and the collection operation) terminates.

[0516] implement Figure 19B The method shown can be accomplished in two operations. First, two or more nearly identical addresses can be identified and separated from other addresses that are not nearly identical and point to the same group. When this is done, the data requested by the nearly identical addresses can be provided using a single read of the memory bank in a single cycle. Second, when the memory bank returns a multi-byte word, the byte corresponding to each of the nearly identical addresses can be returned. The first step will be discussed in more detail in the following sections.

[0517] Distinguishing almost identical addresses One method to distinguish nearly identical addresses is to apply pipeline stages (in addition to or in combination with the pipelines described above) to sort addresses that do not require separate memory access. Such addresses can be, for example, addresses that are nearly identical to other addresses somewhere in command queues 2420.0–2420.7. Sorting can be facilitated by creating indicators (e.g., bits or other indicators) that indicate whether each address 2430 (A0…A7) requires a memory address. Indicators can take many different forms, but one form is a two-dimensional array of bits “ac[][]” 2431.

[0518] The first element of the two-dimensional indicator ac[][] 2431 can be used to indicate whether data needs to be read from a given address. This will be referred to herein as the “access” indicator. For each address A0...A7 in series 2430, the access indicator will be the element in ac[][] 2431 with two indices equal to the address. In other words, the access indicator for A0 is a[0][0], the access indicator for A1 is a[1][1], the access indicator for A2 is a[2][2], and so on. It should be understood that this is merely a convention for illustrative purposes. Other conventions are possible and within the scope of this disclosure. As a shorthand, we generally refer to the access indicator herein as “ac[x][x]”.

[0519] In the exemplary convention, ac[x][x] can be specified such that when ac[x][x] is set to "1", address 2430 associated with ac[x][x] requires a separate memory read. Examples in this configuration where ac[x][x] would be set to "1" would include where ac[x][x] corresponds to address 2430 that does not have nearly identical addresses, or where ac[x][x] corresponds to address 2430 as the lowest index address in a series of nearly identical addresses. If the address associated with it is nearly identical to another address 2430 in queues 2420.0-2420.7 with a lower index, then ac[x][x] can be set to "0". In this case, the address associated with ac[x][x] does not require a separate memory read, but can rely on a memory read for a nearly identical address with a lower index. This convention will be used in the description below. However, it should be understood that this convention is merely illustrative, and any other suitable convention may be adopted (e.g., using "1" or another indicator when address 2430 requires a separate memory read, etc.).

[0520] To implement the above convention, memory reads can be performed at nearly identical addresses by using the lowest index. In other words, if there is a series of addresses 2430 (A0...A7) and addresses A1 and A3 are nearly identical, then the address for A1 is used in the memory read to obtain the data for both A1 and A3. Consistent with the above convention, a[x][x] for A1 is then set to "1" (requiring a separate memory read) and for A3 it is set to "0" (not requiring a separate memory read).

[0521] The indicator ac[][] 2431 preferably includes additional bits specifying the relationship between each address and other addresses in series 2430. This second "relationship" indicator will be referred to herein as "a[x][y]". Note that each address A0...A7 in series 2430 will have 1 a[x][x] bit and 7 a[x][y] bits, each a[x][y] bit corresponding to another address in that series. For Figure 20 The generic address Ax in the code illustrates this convention.

[0522] Following the exemplary convention, the relation indicator ac[y] can be used to indicate whether a data read for an associated address should be routed to another address. For example, if ac[x][y] is set to "1" for another address in series 2430 (A0…A7), then data obtained from a read from address Ax associated with ac[x][1] should be provided to address Ay in series 2430. In that case, since no read is needed from Ay, the access indicator for Ay (a[y][y]) can be set to "0". In other words, ac[x][y] indicates that the data read from Ax should be sent to a higher index, almost identical address.

[0523] Figures 21A-21C Parts of the ac[x][y] 2431 matrix are shown for individual addresses A1, A3, and A4, respectively, in an exemplary case where all three addresses A1, A3, and A4 are nearly identical. Figure 21A As shown, for the a[x][x] indicator of A1, the lowest index, almost identical address a[1][1], will be set to "1", causing data to be read from A1. For the ac[x][x] indicators of A3 and A4 (a[3][3] and a[4][4]), they will both be set to "0" because A3 and A4 are the higher indices of A1, almost identical addresses. This is in... Figure 21B and Figure 21C As shown, Figure 21B and 21C Let ac[x][x] represent 2431 for A3 and A4 respectively.

[0524] In the same example, the relation indicator ac[x][y] for A1 can be set to "1" at positions A3 and A4 so that data read from A1 should also be sent to A3 and A4. This is in Figure 21A It is illustrated schematically. Also, as... Figure 21AAs shown, ac[1][y] is set to "1" at the locations specified for addresses "A3" and "A4" because the data associated with A1 needs to be transferred to satisfy the requests associated with A3 and A4. This is again because, in this example, A3 is a higher-order, nearly identical address to A1. Figure 21A In the example, assume that A3 and A4 are the only nearly identical addresses to A1 in a series of addresses 2430 (A0...A7), and that the remaining values ​​of ac[1][y] all have the value "0". Figure 21B and Figure 21C The corresponding pointers ac[x][y] 2430, a[3][y], and a[4][y] are shown for A3 and A4, respectively. For example... Figure 21B and Figure 21C As shown, the pointers ac[x][y] for A3 and A4 are both "0" because they are both neighbors with almost the same index as A1. Figure 21B and Figure 21C It is also shown that the indicator ac[y] for A3 and A4 are both "0" because the higher index of A1, almost identical neighbors (the data associated with A3 and A4) do not need to be provided to any other address in the series of addresses 2430 (A0...A7).

[0525] Figure 22-24 The entire ac[][] 2431 matrix is ​​shown for the series of addresses 2430 (A0...A7) in three exemplary cases. According to the exemplary conventions above, since the addresses with lower indices are actually accessed, ac[x][y] is set to "0" for x>y. Figure 22-24 In the matrix, each element in the top left part is zero, so the top left part of the matrix is ​​omitted from each of these diagrams.

[0526] In one exemplary case, where none of the addresses in the series of addresses 2430 (A0...A7) are nearly identical to one another, Figure 22 The entire indicator matrix (minus the top left portion) is shown as ac[x][y] 2431. In other words, Figure 22The following case illustrates ac[x][y] 2431, where each address 2430 points to data in memory groups 2310a-2310h that is not in the same word as the data pointed to by any of the other addresses 2430. In that case, all diagonal elements of the indicator matrix ac[x][y] 2431 (i.e., all elements with x = y = indices at the address) are set to "1". This indicates that each address in series 2430 is accessed, and the data corresponding to these addresses will be provided to registers 2401a-h by multiplexers 2905a-h. All off-diagonal elements of ac[x][y] are set to "0" because the data returned from each of the access addresses 2430 is only returned to that specific address, and not to any other address in series 2430. In other words, since none of the addresses 2430 (A0...A7) are nearly identical to any other address, the data read using each address 2430 will only be returned once in response to the initiator that requested data using that specific address. Data for each address 2430 will not be returned in response to any initiator that did not specifically request data from that address. To reflect this, all off-diagonal elements of ac[x][y] 2431 are set to "0".

[0527] Figure 23 The diagram shows ac[x][y]2431 for all addresses 2420 (A1...A7) that are nearly identical to A0. Since A0 is the lowest-order nearly identical address, a[x][x] for A0 is set to "1" (i.e., a[0][0] = 1). Since all other addresses A1...A7 are the highest-order nearly identical addresses to A0, the data requests they represent can be fulfilled by accessing A0 individually. Accordingly, for each of the other addresses A1…A7, the "access" indicator element (ac[x][x]) is set to "0". Instead, the first column (ac[0][y]) (the column indicating the relationship between the data accessed via A0 and other addresses) is set to "1". This indicates that data should be used from the access from A0 to provide data for each of the other addresses A1...A7 in series 2430.

[0528] Figure 24The example shown is ac[x][y] 2431, where each of A0-A3 is nearly identical to addresses A4-A7 respectively. In this case, since A0-A3 is the lowest index address of their nearly identical address pairs, each of A0-A3 has a value "1" in a[x][x]. In other words: a[0][0] = a[1][1] = a[2][2] = a[3][3] = 1. Since A4-A7 is the higher index address that is nearly identical to the lower index address (A0-A3), each of them has a value "0" in its a[x][x] (i.e., ac[4][4] = ac[5][5] = ac[6][6] = ac[7][7] = 0). Since the data read from A0 provides enough data for the data read represented by A4, the relation indicator of A0 relative to A4 (i.e., a[0][4]) is set to "1". Again, this indicates that the data request represented by A4 will be satisfied by a memory read performed on A0, and the appropriate data will be routed to satisfy the A4 data request. Similarly, for their respective nearly identical pairs A5, A6, and A7, the relation indicators for A1, A2, and A3 are each set to "1" (i.e., ac[1][5] = ac[2][6] = ac[3][7] = 1). This indicates that the data reads from A1, A2, and A3 provide sufficient data for the data reads represented by A5, A6, and A7, respectively. Figure 24 As shown, all other elements of ac[x][y] 2431 are set to "0".

[0529] The actual encoding of the above conventions / schemes can be accomplished in various ways consistent with this disclosure. Several exemplary methods for encoding this scheme will now be introduced. However, it should be understood that these encoding methods are merely examples of some general concepts, conventions, and schemes discussed above. It should be understood that the representation of this code is not restrictive, and the concepts, conventions, and schemes disclosed herein are merely exemplary.

[0530] One approach to encoding the above conventions and example cases is to implement the general algorithm expressed below in pseudocode. The general algorithm is used to compute ac[x][y] based on a series of n addresses An, where n is any integer (including but not limited to "8" used in the examples above). Note that the symbol "~=" in the pseudocode below indicates a Boolean expression that returns "1" if its operands are nearly identical, and "0" otherwise. In the formulas below, where the identifiers "x" or "y" are used to denote indices in An or ac[x][y], it should be understood that "x" refers to the column in the ac matrix, and "y" refers to the row, such as... Figure 22-24 As shown.

[0531] For all addresses 2430 An (e.g., in the 8-byte example, n = 1...7): 1. Set ax[n][n] equal to "1" (i.e., to indicate that the data requested by An must be accessed) if and only if the data corresponding to An has not been accessed by lower-indexed addresses (i.e., indices x from n - 1 to 0): a. ac[n][n] = product(!ac[x][n], for x from n - 1 to 0) 2. (Note that in this implementation, ac[0][0] is always 1, indicating that the data corresponding to A0 is always accessed. This is because A0 is the lowest-indexed address and thus cannot be almost the same as another address with a lower index.)

[0532] 2. For all rows y corresponding to An in ac[n][y], if An is almost the same as Ay, set a[n][y] equal to "1" (i.e., an indicator to return the data associated with An to Ay): a. For all y > n: i. ac[n][y] = (ac[n][n]) && (An == Ay) b. (Note that this calculation must be performed in a specific order. Specifically, ac[n][y] must be calculated after a[n][n], and a[n][n] must be calculated after a[x][n] for all values of x < n.)

[0533] According to the above, if the access element (ac[x][x]) for an address is "0", indicating that the element has not been accessed, the data corresponding to that access element will not be provided in response to a data request made using any other address. Thus, in this case, if ac[x][x] = 0, then a[x][y] = 0 for the address.

[0534] Figure 25A The implementation of the above general algorithm is shown in actual code. As described above, Figure 25A the code in corresponds to an exemplary case of eight addresses (A0...A7) 2430 and their corresponding 8x8 indicator matrix ac[][] 2431. Figure 25A The code in is written to comply with the order requirements described above. For example, in the first step, a[0][0] is set to "1" because the data corresponding to address A0 must be accessed. As Figure 25AAs shown, a[x][y] is calculated column-wise in the columns as 2431 (i.e., first for column ac[x=0][y], then for column ac[x=1][y], then for ac[x=2][y], ... and finally for column a[x=7][y]). As discussed above, in Figure 25A The code shown is intended to be exemplary and not restrictive. It should be understood that variations of this code may deviate from the architecture and methods disclosed herein while still achieving the intended implementation. Figure 25A The example shown.

[0535] Figure 25A The code describes setting ac[][] 2431 so that it can be used both to determine which data to retrieve and to return to registers 2401a-h. Specifically, once based on ac[][] 2431 ( Figure 19B Step 2454) returns the read data from group 2310a-h, and the data must be returned to the correct initiator (i.e., to the correct byte result register 2401a-h corresponding to the initiator). Figure 19B (Step 2455). To accomplish this, the column of bit ac[i] can set bit ac[i][j] to 1 if and only if the read data corresponding to Ai must be returned to the initiator j. Figure 25A One possible implementation of the code relies on the fact that for any j, there will exist at most one instance where ac[i][j] is "1". In an exemplary implementation, a simple logical "OR" can be performed among the eight read responses returned by the eight groups, where the read response for group i is logically ANDed with ac[i][j]. In this case, read response i will input an OR expression (and return to registers 2401a-h) unless ac[i][j] == 0. In this case, 0 will input an OR expression.

[0536] Therefore, based on the foregoing, some examples of this disclosure pertain to a device including one or more memory banks, one or more registers, and connectors linking one or more memory banks to one or more registers. The device may also include one or more queues storing a set of addresses for accessing data from one or more memory banks, the set of addresses being selected from a data request based on whether the selected address is substantially identical to other addresses in the data request. The selection may be based on an indicator matrix that may include a two-dimensional matrix with diagonal elements indicating whether an address in the data request is a lowest-index nearest neighbor or has no nearest neighbor. The selection may be based on the diagonal elements to select the set of addresses. The selection may include at least one of addresses that are not substantially identical to any other address in the data request, or addresses that are substantially identical to a set of addresses in the data request and have the lowest index of the address in that set. The selection may include determining whether any address in the request corresponds to the same word in the same memory bank stored in one or more memory banks. The connector may provide data to one or more registers based on the indicator matrix. Providing data to one or more registers based on an indicator matrix may include: determining, via the indicator matrix, one or more addresses in the data request that are not substantially identical to any other address in the data request, or substantially identical to a set of other addresses in the data request and have the lowest index of the addresses in that set; and providing data associated with the determined one or more addresses to one or more registers. The device may include one or more multiplexers, and the determination is performed by one or more multiplexers.

[0537] Some examples of this disclosure (see, for example) Figure 25BFor a method 8700 for processing data, the method includes: determining (8710) metadata (e.g., an indicator matrix) indicating whether an address in a data request is substantially the same as other addresses in the data request; selecting (8714) a set of addresses for accessing data from one or more memory banks based on the metadata; storing (8718) the selected set of addresses in one or more queues; and retrieving (8722) data corresponding to the selected set of addresses from the memory banks based on one or more queues. The indicator matrix may include a two-dimensional matrix with diagonal elements indicating whether an address in the data request is a lowest-index nearest neighbor or has no nearest neighbor, and selection (8714) may be based on the diagonal elements to select the set of addresses. Selection (8714) may include selecting at least one of an address that is not substantially the same as any other address in the data request or an address that is substantially the same as a set of addresses in the data request and has the lowest index of the addresses in that set. Selection (8714) may include determining whether any address in the request corresponds to the same word in the same set of addresses stored in one or more memory banks. The method may include providing (8724) data to one or more registers via a linker based on the indicator matrix. Providing 8724 data to one or more registers based on an indicator matrix may include: determining, via the indicator matrix, one or more addresses in the data request that are not substantially identical to any other address in the data request, or substantially identical to a set of other addresses in the data request and have the lowest index of the addresses in that set, and providing 8728 data associated with the determined one or more addresses to one or more registers. This determination may be performed by one or more multiplexers. According to one embodiment of the invention, each memory bank has a queue, and the method includes assigning addresses to all queues and selecting addresses to be stored by the queues based on metadata.

[0538] Some examples of this disclosure relate to a non-transitory computer-readable storage medium having stored a set of instructions for a software program that, when executed by a computing device, causes the computing device to determine an indicator matrix indicating whether an address in a data request is substantially the same as other addresses in the data request, to select a set of addresses for accessing data from one or more memory banks based on the indicator matrix, to store the selected set of addresses in one or more queues, and to retrieve data corresponding to the selected set of addresses from the memory banks based on one or more queues. The indicator matrix may include a two-dimensional matrix with diagonal elements indicating whether an address in the data request is a lowest-index nearest neighbor or has no nearest neighbor, and the selection may be based on the diagonal elements to select a set of addresses. The selection may include selecting at least one of an address that is not substantially the same as any other address in the data request or an address that is substantially the same as a set of addresses in the data request and has the lowest index of the addresses in that set. The selection may include determining whether any of the addresses in the request corresponds to the same word in the same memory bank stored in one or more memory banks. The instructions may cause the computing device to provide data to one or more registers via a linker based on the indicator matrix. The provision may include determining, via an indicator matrix, one...

Claims

1. An apparatus comprising: Memory; The data processing subsystem includes: --At least one data processing unit, and --At least one address generation unit that generates an address in the memory based on a first set of parameters; A control subsystem provides the first set of parameters and the second set of parameters to the data processing subsystem; and A queue that stores a first set of parameters and a second set of parameters, and provides the second set of parameters to the address generation unit when the data processing unit uses the first set of addresses to process data.

2. The device according to claim 1, wherein: The data processed by the data processing unit includes at least one image window, at least one of the first set of addresses corresponds to the location in the memory where a first portion of the at least one image window is stored, and the address generation unit generates the first set of addresses by iterating over the at least one image window using image parameters, the image parameters including the address in the memory where a second portion of the image window is stored.

3. The device according to claim 2, wherein, The data processing subsystem includes a scalar processor that provides the image parameters to the address generation unit.

4. The device according to claim 1, wherein, The data processing unit includes at least one vector processor, and the data processed by the data processing unit includes vector data.

5. The device according to claim 1, wherein, The data processing subsystem retrieves data from the memory incrementally, and the data processing unit uses an offset to concatenate unaligned vector data in the retrieved data, the offset indicating how the unaligned vector data is unaligned in the memory with respect to the increment.

6. The device according to claim 5, wherein, The address generation unit calculates the offset used by the data processing unit in the concatenation.

7. The device according to claim 6, wherein: The address generation unit generates a first set of addresses by iterating over portions of the at least one image window, and the offset includes an iteration-invariant parameter.

8. A method for processing data, comprising: The control subsystem provides a first set of parameters and a second set of parameters to the data processing subsystem, the data processing subsystem including at least one data processing unit and at least one address generation unit; Store the first set of parameters and the second set of parameters in a queue; The first set of parameters is used to generate a first set of addresses in memory via the address generation unit; When the data processing unit processes data using the first set of addresses, the second set of parameters is provided to the address generation unit via the queue.

9. The method according to claim 8, wherein, The data processed by the data processing unit includes at least one image window, wherein at least one of the first set of addresses corresponds to a location in the memory where a first portion of the at least one image window is stored, and the method includes generating the first set of addresses via the address generation unit by iterating over the at least one image window using image parameters, the image parameters including an address in the memory where a second portion of the image window is stored.

10. The method of claim 9, further comprising providing the image parameters to the address generation unit via a scalar processor of the data processing subsystem.

11. The method according to claim 8, wherein, The data processing includes processing the vector data by at least one vector processor.

12. The method of claim 8, comprising: Data is retrieved from the memory incrementally via the data processing subsystem, and unaligned vector data in the retrieved data is concatenated via the data processing unit using an offset, the offset indicating how the unaligned vector data is unaligned in the memory with respect to the increment.

13. The method of claim 12, further comprising calculating the offset used by the data processing unit in the concatenation via the address generation unit.

14. The method of claim 12, further comprising generating a first set of addresses by iterating over portions of the at least one image window via the address generation unit, wherein the offset includes an iteration-invariant parameter.

15. A non-transitory computer-readable storage medium having stored thereon an instruction set of a software program, the instruction set causing the computing device, when executed by a computing device, to: The control subsystem provides a first set of parameters and a second set of parameters to the data processing subsystem, the data processing subsystem including at least one data processing unit and at least one address generation unit; Store the first set of parameters and the second set of parameters in a queue; The first set of parameters is used to generate a first set of addresses in memory via the address generation unit; as well as When the data processing unit processes data using the first set of addresses, the second set of parameters is provided to the address generation unit via the queue.

16. The non-transitory computer-readable storage medium according to claim 15, wherein: The data processed by the data processing unit includes at least one image window, at least one of the first set of addresses corresponds to a location in the memory where a first portion of the at least one image window is stored, and the instruction set causes the computing device to generate the first set of addresses by the address generation unit through iterating over the at least one image window using image parameters, the image parameters including an address in the memory where a second portion of the image window is stored.

17. The non-transitory computer-readable storage medium according to claim 16, wherein, The data processing subsystem includes a scalar processor that provides the image parameters to the address generation unit.

18. The non-transitory computer-readable storage medium according to claim 15, wherein, The data processing unit includes at least one vector processor, and the data processed by the data processing unit includes vector data.

19. The non-transitory computer-readable storage medium according to claim 15, wherein, The instruction set enables the computing device to: Data is retrieved from the memory incrementally via the data processing subsystem, and unaligned vector data in the retrieved data is concatenated via the data processing unit using an offset, the offset indicating how the unaligned vector data is unaligned in the memory with respect to the increment.

20. The non-transitory computer-readable storage medium according to claim 19, wherein, The instruction set enables the computing device to calculate the offset used by the data processing unit in the cascade via the address generation unit.

21. The non-transitory computer-readable storage medium according to claim 20, wherein: The instruction set causes the computing device to generate a first set of addresses by iterating over portions of the at least one image window via the address generation unit, and the offset includes an iteration-invariant parameter.

Images