Branch prediction method, device and electronic equipment for indirect jump branch instructions

Abstract

The specification provides a branch prediction method, device and electronic equipment of an indirect jump branch instruction, the method comprising: in the case where the indirect jump branch instruction is executed and completed, obtaining instruction information of the indirect jump branch instruction, the instruction information comprising an instruction address and a jump address executed by the indirect jump branch instruction; according to the instruction address, matching in a pre-trained jump address tracking table to obtain target tracking information; obtaining a historical main jump address corresponding to the target tracking information; in the case where the jump address executed by the indirect jump branch instruction is consistent with the historical main jump address, updating the indirect jump branch instruction to a direct jump branch instruction, and taking the historical jump address as a jump address of the updated direct jump branch instruction. The application optimizes the prediction of the indirect jump branch instruction, improves the efficiency of branch prediction, and thus can improve the performance of central processing.

Description

Technical Field

[0001] This application relates to the field of many-core server technology, and in particular to a branch prediction method, apparatus and electronic device for indirect jump branch instructions. Background Technology

[0002] Central Processing Unit Pipeline (CPU Pipeline) technology is a technique that breaks down computer instructions into multiple pipeline stages for execution, allowing the operations of different instruction pipeline stages to overlap, thereby enabling the parallel processing of multiple instructions. CPU pipeline technology can increase the CPU's operating frequency, thus improving CPU performance.

[0003] Within the CPU core, branch prediction is a crucial pipeline stage located at the front end of the CPU pipeline. It analyzes the history of branch instructions (both jump and non-jump) to identify patterns in their execution and predict future branch actions. Branch instructions, which have two or more possible target addresses, have the ability to interrupt the instruction flow. If, upon encountering a branch instruction, the CPU pipeline were to halt until the result of the branch instruction is obtained before continuing execution, numerous pipeline bottlenecks would be created, resulting in idle runs across multiple pipeline stages and performance penalties. Therefore, branch prediction effectively addresses this pipeline bottleneck, preventing performance losses caused by pipeline idle runs and improving instruction execution parallelism and overall processor efficiency.

[0004] However, a successful branch prediction can improve CPU performance, while a wrong prediction can lead to performance loss and wasted power. Therefore, improving the accuracy of branch prediction is key to improving CPU performance.

[0005] One existing approach is to use a filtering mechanism to identify conditional jump instructions that are either highly likely to result in a jump or highly unlikely to result in a jump. Then, the type of the conditional jump instructions with a high probability of result in a jump is updated to the type of a direct branch instruction, or the conditional jump instructions with a high probability of not result in a jump are invalidated. This simplifies the branch prediction process and can improve CPU performance.

[0006] Another existing approach is to use more complex algorithms for branch prediction in order to improve the accuracy of branch prediction. Summary of the Invention

[0007] The inventors discovered that existing technologies for simplifying branch prediction processes only optimize conditional branch instructions. However, besides conditional branch instructions, branch instructions also include indirect branch instructions. Since indirect branch instructions typically have multiple jump target addresses, branch prediction requires access to the Branch Target Buffer (BTB) and the indirect branch predictor. Compared to branch prediction for conditional branch instructions, indirect branch instruction prediction requires longer prediction time and larger capacity. Therefore, if the executing computer program contains many indirect branch instructions, it may put significant pressure on the indirect branch predictor, affecting prediction accuracy. The aforementioned existing technologies do not optimize branch prediction for indirect branch instructions; therefore, their optimization of the branch prediction process is limited, and consequently, their impact on CPU performance improvement is also limited. Furthermore, determining the jump address of the indirect branch predictor through a filtering mechanism has low prediction accuracy, potentially leading to further CPU performance loss and wasted power. Therefore, the filtering mechanism is not suitable for branch prediction of indirect jump branch instructions.

[0008] Regarding existing technologies that improve branch prediction accuracy by increasing algorithm complexity, more complex algorithms mean occupying more chip area and consuming more power, while also affecting CPU cycle time. Therefore, in practice, engineers often need to strike a trade-off between prediction accuracy and algorithm complexity to improve the final performance of the CPU. Consequently, the improvement in branch prediction accuracy offered by this existing technology is limited.

[0009] To address one or more of the aforementioned technical problems or similar issues, this application provides a branch prediction method, apparatus, and electronic device for indirect branch instructions, which optimizes the prediction of indirect branch instructions, improves the efficiency of branch prediction, and thereby enhances the performance of the central processing unit.

[0010] A first aspect of this application provides a branch prediction method for an indirect jump branch instruction. The method includes: when an indirect jump branch instruction is executed, obtaining instruction information of the indirect jump branch instruction, the instruction information including the instruction address of the indirect jump branch instruction and the jump address to which it is executed; matching the indirect jump branch instruction with main jump address tracking information in a pre-trained main jump address tracking table according to the instruction address to obtain target tracking information; obtaining a historical main jump address corresponding to the target tracking information; and when the jump address to which the indirect jump branch instruction is executed is consistent with the historical main jump address corresponding to the target tracking information, updating the indirect jump branch instruction to a direct jump branch instruction, and using the historical main jump address as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction.

[0011] In some embodiments, the primary jump address tracking table includes multiple primary jump address tracking information, each of which includes identification information of historical indirect jump branch instructions, the most recently executed jump address, the number of consecutive executions of the most recently executed jump address, and a valid value indicating the validity of the primary jump address tracking information.

[0012] In some embodiments, matching the indirect jump branch instruction with the main jump address tracking information in a pre-created main jump address tracking table based on the instruction address to obtain target tracking information includes: generating identification information of the indirect jump branch instruction based on the instruction address; matching the identification information of the indirect jump branch instruction with the identification information in the main jump address tracking information in the main jump address tracking table; and determining the main jump address tracking information with matching identification information as the target tracking information of the indirect jump branch instruction.

[0013] In some embodiments, generating the identification information of the indirect jump branch instruction based on the instruction address includes: reading the instruction address of the indirect jump branch instruction; compressing the instruction address to obtain the identification information of the indirect jump branch instruction.

[0014] In some embodiments, obtaining the historical primary jump address corresponding to the target tracking information includes: obtaining the number of consecutive executions of the most recently executed jump address in the target tracking information; determining whether the number of consecutive executions is greater than or equal to a preset threshold for the number of consecutive executions; and if the number of consecutive executions is greater than or equal to the threshold for the number of consecutive executions, determining the most recently executed jump address as the historical primary jump address corresponding to the target tracking information.

[0015] In some embodiments, the method further includes: if the jump address executed by the indirect jump branch instruction is inconsistent with the historical major jump address, not updating the indirect jump branch instruction to a direct jump branch instruction.

[0016] In some embodiments, the method further includes a step of training the main jump address tracking table, wherein the step of training the main jump address tracking table includes: when an indirect jump branch instruction is executed, obtaining the data field information of the indirect jump branch instruction according to a preset data field structure of the main jump address tracking table; generating main jump address tracking information according to the data field information of the indirect jump branch instruction, and storing the generated main jump address tracking information to obtain the main jump address tracking table.

[0017] In some embodiments, the method further includes the step of updating the training of the primary jump address tracking table, wherein the step of updating the training of the primary jump address tracking table includes at least one of the following steps: if there is no primary jump address tracking information in the primary jump address tracking table that matches the indirect jump branch instruction, create primary jump address tracking information corresponding to the indirect jump branch instruction in the primary jump address tracking table; if there is no historical primary jump address corresponding to the target tracking information, update the target tracking information according to the jump address executed by the indirect jump branch instruction; if the jump address executed by the indirect jump branch instruction is inconsistent with the historical primary jump address, update the target tracking information according to the jump address executed by the indirect jump branch instruction.

[0018] A second aspect of this application provides a branch prediction apparatus for an indirect jump branch instruction. The apparatus includes: a first acquisition unit, configured to acquire instruction information of the indirect jump branch instruction when the indirect jump branch instruction is executed, the instruction information including the instruction address of the indirect jump branch instruction and the jump address to which it is executed; a matching unit, configured to match the indirect jump branch instruction with main jump address tracking information in a pre-trained main jump address tracking table according to the instruction address to obtain target tracking information; a second acquisition unit, configured to acquire the historical main jump address corresponding to the target tracking information; and a processing unit, configured to update the indirect jump branch instruction to a direct jump branch instruction when the jump address to which the indirect jump branch instruction is executed is consistent with the historical main jump address corresponding to the target tracking information, and to use the historical main jump address as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction.

[0019] A third aspect of this application provides an electronic device, including: a memory and a processor, wherein the processor and the memory are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to implement the branch prediction method for indirect jump branch instructions as described in the first aspect.

[0020] A fourth aspect of this application provides a computer storage medium storing computer program instructions, which, when executed, implement the steps of the branch prediction method for indirect jump branch instructions as described in the first aspect.

[0021] A fifth aspect of this application provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of the branch prediction method for indirect jump branch instructions as described in the first aspect.

[0022] One of the beneficial effects of the embodiments of the present invention is that: The branch prediction method, apparatus, and electronic device for indirect jump branch instructions provided in this application match the instruction address and jump address of the indirect jump branch instruction in the main jump address tracking table. Under preset conditions, the type of the indirect jump branch instruction is updated to a direct jump branch instruction. In this way, under preset conditions, the indirect jump branch instruction is predicted as a direct jump branch instruction, which improves the efficiency of branch prediction and thus helps to improve the performance of the central processing unit. Furthermore, the main jump target address of the indirect jump branch instruction is determined and verified using the main jump address tracking table. When the indirect jump branch instruction and its jump address match the main jump address tracking table, the historical main jump address that matches the indirect jump branch instruction in the main jump address tracking table is used as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction. This improves the accuracy of branch prediction and can further improve the performance of the central processing unit. Furthermore, this application optimizes the steps for accessing the indirect branch predictor based on existing algorithms, without increasing chip area and power consumption, thus maintaining a balance between the accuracy of branch prediction and the complexity of the algorithm. Moreover, since some indirect branch instructions no longer depend on the indirect branch predictor, the capacity pressure on the indirect branch predictor can be indirectly alleviated, thereby further improving the performance of the central processing unit.

[0023] Embodiments of the present invention are disclosed in detail with reference to the following description and accompanying drawings. It should be understood that the embodiments of the present invention are not limited in scope thereto. Within the spirit and scope of the appended claims, embodiments of the present invention include many changes, modifications, and equivalents.

[0024] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0025] It should be emphasized that the term "including / contains / has" as used herein refers to the presence of a feature, whole or component, but does not exclude the presence or addition of one or more other features, wholes or components. Attached Figure Description

[0026] The above and other objects, features and advantages of embodiments of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 It is a schematic diagram of the internal structure and pipeline of a CPU core; Figure 2 This is a schematic diagram of the branch predictor's operation flow; Figure 3 This is a schematic diagram of a branch prediction method for indirect jump branch instructions according to an embodiment of this application; Figure 4 This is a schematic diagram of an indirect jump branch instruction according to an embodiment of this application; Figure 5 This is a schematic diagram of the main jump address tracking table in an embodiment of this application; Figure 6 This is a schematic diagram illustrating the steps for obtaining target tracking information according to an embodiment of this application; Figure 7 This is a schematic diagram of the steps for training the main jump address tracking table according to an embodiment of this application; Figure 8 This is a flowchart of a branch prediction method for indirect jump branch instructions according to an embodiment of this application; Figure 9 This is a schematic diagram of a branch prediction device for an indirect jump branch instruction according to an embodiment of this application; Figure 10 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of the branch prediction method, apparatus, and electronic device for indirect jump branch instructions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0028] First aspect of the embodiments

[0029] The first aspect of this application provides a branch prediction method for indirect jump branch instructions, which is applied to the branch prediction pipeline stage of the CPU pipeline. Figure 1 This is a schematic diagram of the internal structure and pipeline of a CPU core. For example... Figure 1 As shown, the CPU core contains multiple pipeline stages, including branch prediction, instruction fetch, decoding, instruction dispatch and rename, instruction execution, and instruction retirement. Branch prediction verification is performed after decoding and instruction execution. Each pipeline stage may also contain multiple pipeline stages (i.e., clock cycles) to support high operating frequencies.

[0030] The computer instructions that control the flow of program instructions in the CPU include branch instructions and non-branch instructions. A non-branch instruction has only one target instruction, i.e., the next instruction; while a branch instruction can have two or more possible target addresses. When a computer program runs, the final selection of the target address of the executed branch instruction is dynamically determined by runtime conditions. Branch instructions can be unconditional branches, meaning they always jump to the target address, or conditional branches, meaning they may or may not jump to the target address depending on whether the condition is met. Furthermore, based on how the target address is specified, branch instructions are generally divided into two types: direct branch instructions (also called unconditional direct branch instructions) and indirect branch instructions. The target address of a direct branch instruction is fixed; it is usually explicitly given in the direct branch instruction or calculated using a simple offset. The target address of an indirect branch instruction is dynamically calculated, usually determined by a value in a register or memory.

[0031] The purpose of branch prediction is to predict the direction and target address of a branch instruction before it is explicitly computed. Without branch prediction, the processor must wait for conditional jump instructions to pass through the execution stage before knowing which instruction to jump to, leading to idle time in multiple pipeline stages from the front end to execution, resulting in significant performance loss. Branch prediction can avoid this performance waste to some extent. The branch predictor is located at the front end of the CPU core pipeline. Based on the result of the previous branch prediction, it continuously predicts the start and end addresses of the next instruction and speculatively executes these instructions. Branch prediction is correct in most cases, thus improving the overall performance of the CPU core. When a branch prediction error is found at a later pipeline level (e.g., after an instruction is decoded or executed), the speculatively executed or partially executed instructions are cleaned up, and the pipeline restarts with the correct branch.

[0032] Figure 2 This is a schematic diagram of the branch predictor's operation flow. For example... Figure 2 As shown, the branch target buffer (BTB) is queried using the current instruction address to obtain relevant information about the branch instruction. This information includes, for example, the location, type, and jump address of the branch instruction. In this application, the jump address can also be referred to as the target jump address, target address, jump target, etc., and this application does not impose any restrictions on this. After obtaining the relevant information of the branch instruction, based on the type of branch instruction obtained from the BTB and combined with different prediction structures, the address of the next instruction, i.e., the prediction address, is predicted. Specifically, it is divided into the following cases: For unconditional direct jump branch instructions, the target jump address read from the BTB, i.e., the address in the branch target address cache, is the prediction address, which is the direct jump address of the direct jump branch instruction; For conditional jump branch instructions, the prediction address is provided based on the prediction result of the conditional branch predictor. If the prediction result indicates a jump, the prediction address is the target jump address read from the BTB; if the prediction result indicates no jump, the prediction address is the address of the current branch instruction + 1, i.e., the sequential address; For indirect jump branch instructions, the prediction result of the indirect branch predictor provides its corresponding prediction address, which is the next address of the indirect jump branch instruction or the indirect jump address; For Return instructions, the next address, i.e., the return address, is provided by the return address stack.

[0033] Of the four instruction types mentioned above, only the prediction result for unconditional direct branch instructions is provided solely by the BTB (Browser Targeting Unit). The other instruction types require the BTB to work in conjunction with other units for prediction. For example, for indirect branch instructions, since these instructions often have multiple target addresses, branch prediction requires access to both the BTB and the indirect branch predictor. The purpose of this application is primarily to improve the efficiency and accuracy of CPU branch prediction, increase the parallelism of instruction execution, and enhance the overall CPU performance by optimizing the prediction process for indirect branch instructions, thereby improving CPU performance.

[0034] Figure 3 This is a schematic diagram of a branch prediction method for indirect jump branch instructions according to an embodiment of this application. For example... Figure 3 As shown, the branch prediction method 100 for indirect jump branch instructions in this application embodiment includes: Step 101: If the indirect jump branch instruction is executed, obtain the instruction information of the indirect jump branch instruction, which includes the instruction address of the indirect jump branch instruction and the jump address to which it is executed. Step 102: Based on the instruction address, match the indirect jump branch instruction with the main jump address tracking information in the pre-trained main jump address tracking table to obtain the target tracking information; Step 103: Obtain the historical main redirect addresses corresponding to the target tracking information; Step 104: If the jump address executed by the indirect jump branch instruction is consistent with the historical main jump address corresponding to the target tracking information, update the indirect jump branch instruction to a direct jump branch instruction, and use the historical main jump address as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction.

[0035] Through the above embodiments, for indirect jump branch instructions, the instruction address and jump address of the indirect jump branch instruction are matched in the main jump address tracking table, and the type of the indirect jump branch instruction is updated to a direct jump branch instruction when the preset conditions are met. In this way, when the preset conditions are met, the indirect jump branch instruction is predicted as a direct jump branch instruction, which improves the efficiency of branch prediction and thus helps to improve the performance of the central processing unit. Furthermore, the main jump target address of the indirect jump branch instruction is determined and verified using the main jump address tracking table. When the indirect jump branch instruction and its jump address match the main jump address tracking table, the historical main jump address that matches the indirect jump branch instruction in the main jump address tracking table is used as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction. This improves the accuracy of branch prediction and can further improve the performance of the central processing unit. Furthermore, this application optimizes the steps for accessing the indirect branch predictor based on existing algorithms, without increasing chip area and power consumption, thus maintaining a balance between the accuracy of branch prediction and the complexity of the algorithm. Moreover, since some indirect branch instructions no longer depend on the indirect branch predictor, the capacity pressure on the indirect branch predictor can be indirectly alleviated, thereby further improving the performance of the central processing unit.

[0036] In some embodiments, the indirect jump branch instruction in step 101 is an indirect jump branch instruction that has already been executed.

[0037] Figure 4 This is a schematic diagram of the indirect jump branch instruction in this application. For example... Figure 4 As shown, indirect jump branch instructions include information such as instruction address, branch instruction, execution count, jump address, and the number of jumps corresponding to the jump address.

[0038] In some embodiments, in step 101, the jump address executed by the jump branch instruction refers to the actual jump address when the indirect jump branch instruction is executed, for example, ... Figure 4 Any one of the jump addresses in the table, or, is related to Figure 4 The new jump address is different from the jump address in the previous one.

[0039] In some embodiments, the execution count, jump address, and corresponding jump count of an indirect jump branch instruction are updated after each execution of the indirect jump branch instruction. For example, suppose that after the execution of the indirect jump branch instruction, it is determined whether the actual jump address of the indirect jump branch instruction exists in the jump address in the instruction information of the indirect jump branch instruction. If it exists, the jump count corresponding to the actual jump address in the instruction information is incremented by 1; if it does not exist, the actual jump address is added to the instruction information of the indirect jump branch instruction, and its corresponding jump count is set to 1.

[0040] In step 102, the indirect jump branch instruction is matched with the main jump address tracking information in the pre-trained main jump address tracking table according to the instruction address.

[0041] In some embodiments, the main jump address tracking table is a pre-trained data table used to track the main jump addresses of indirect jump branch instructions. The main jump address tracking table is only one storage format of the tracking information. In addition, the tracking information can be stored in other data formats according to actual needs, and this application does not limit this.

[0042] In some embodiments, the primary jump address tracking table includes multiple primary jump address tracking information, each of which includes identification information, the most recently executed jump address, the number of consecutive executions of the most recently executed jump address, and a valid value indicating the validity of the primary jump address tracking information.

[0043] Figure 5 This is a schematic diagram of the main redirect address tracking table of this application. For example... Figure 5 As shown, the main jump address trace table includes N main jump address trace information. Each main jump address trace information includes four data fields: the identifier of a historical indirect jump branch instruction, the jump address, the counter, and the valid value.

[0044] The value of the identification information (e.g., identification information a) includes 12 bits. The identification information is obtained by compressing the instruction address of the indirect jump branch instruction. The specific method of obtaining the identification information can be found in the above embodiment, and will not be repeated here.

[0045] The jump address is the most recently executed jump address of the indirect jump branch instruction. The value of the jump address (e.g., destination address b) includes 47 bits.

[0046] The counter is, for example, a saturation counter whose value represents the number of consecutive executions of the jump address of the corresponding indirect jump branch instruction that was most recently executed. The number of consecutive executions (e.g., the number c) includes 7 bits.

[0047] The valid value indicates the validity of the major jump address tracing information. It guides the replacement of major jump address tracing information in the major jump address tracing table. The larger the valid value, the higher the value and validity of the major jump address tracing information. The valid value (e.g., valid value d) may include 7 bits.

[0048] In some embodiments, the number of major jump address tracking entries contained in the major jump address tracking table is capped, for example, N entries. During program execution, the number of indirectly jumped branches may exceed this cap of N. After a new indirect jump branch instruction is detected and executed, if the number of major jump address tracking entries already stored in the major jump address tracking table is less than the cap of N, a new major jump address tracking entry corresponding to the new indirect jump branch instruction can be directly created in the major jump address tracking table. However, if the number of major jump address tracking entries already stored in the major jump address tracking table is equal to the cap of N, then the major jump address tracking entry corresponding to the new indirect jump branch instruction needs to replace an existing major jump address tracking entry in the major jump address tracking table. The major jump address tracking entry to be replaced can be selected based on a valid value; for example, the major jump address tracking entry with the lowest valid value can be selected as the major jump address tracking entry to be replaced.

[0049] In some embodiments, the valid value has a preset range. For example, with 7 bits, the range of the valid value is 0000000~1111111. The setting and updating method of the valid value and the training method of the main jump address tracking table will be described in subsequent embodiments.

[0050] In some embodiments, the data fields of the main jump address tracking information in the main jump address tracking table are not limited to the four types: identification information, jump address, counter, and valid value, and can be adjusted according to actual needs. Furthermore, the number of bits in each data field can also be adjusted according to actual needs, and this application does not impose any restrictions on this.

[0051] Figure 6 This is a schematic diagram illustrating the steps for obtaining target tracking information according to an embodiment of this application. For example... Figure 6 As shown, in step 102, based on the instruction address, the indirect jump branch instruction is matched with the main jump address tracking information in the pre-trained main jump address tracking table to obtain the target tracking information, including: Step 1021: Generate the identifier information of the indirect jump branch instruction based on the instruction address; and Step 1022: Match the identification information of the indirect jump branch instruction with the identification information in the main jump address tracing information in the main jump address tracing table, and determine the main jump address tracing information with matching identification information as the target tracing information of the indirect jump branch instruction.

[0052] For example, with Figure 5 For example, in step 1022, the identifier information of the indirect jump branch instruction is compared with... Figure 5The identification information in the main jump address tracing table shown is matched with the identification information in the main jump address tracing information corresponding to each historical indirect jump branch instruction. The main jump address tracing information with matching identification information is determined as the target tracing information of the indirect jump branch instruction.

[0053] In this way, by matching the unique identifier information corresponding to the instruction address of the indirect jump branch instruction, the main jump address tracing information corresponding to the indirect jump branch instruction can be quickly determined, and thus the target tracing information can be quickly determined.

[0054] In some embodiments, step 1021, generating identification information for an indirect jump branch instruction based on the instruction address, includes: Read the instruction address of the indirect jump branch instruction; and The instruction address is compressed to obtain the identification information of the indirect jump branch instruction.

[0055] For example, such as Figure 4 As shown, assuming the instruction address of the indirect jump branch instruction is 0x00586a47, the instruction address is then compressed. The compression methods include, but are not limited to, offset bit compression, short / long branch hierarchical encoding, leaf offset encoding, branch target buffer auxiliary compression, and jump table compression.

[0056] In this way, by compressing the instruction address of indirect jump branch instructions, a shorter compressed address (i.e., identification information) can be used to replace the complete instruction address. Thus, storing the compressed identification information in the instruction information and main jump address tracking table of indirect jump branch instructions, and matching based on the identification information, can save instruction word length and reduce storage costs.

[0057] In some embodiments, step 103, obtaining the historical primary redirect addresses corresponding to the target tracking information, includes: Obtain the number of consecutive executions of the most recently executed jump address from the target tracking information; Determine whether the number of consecutive executions is greater than or equal to a preset threshold for the number of consecutive executions; If the number of consecutive executions is greater than or equal to the threshold for consecutive executions, the jump address of the most recent execution will be determined as the historical primary jump address corresponding to the target tracking information.

[0058] For example, suppose Figure 5The right side displays the target tracing information containing the identifier 'a'. The counter value represents the number of consecutive executions of the most recently executed jump address of the indirect jump branch instruction corresponding to the target tracing information. Assuming the counter value is count 'c', and count 'c' equals a preset consecutive execution count threshold, then the jump address value in this target tracing information, i.e., target address 'b', is determined as the historical major jump address of the indirect jump branch instruction with identifier 'a'.

[0059] In this way, the jump address of the most recent execution when the number of consecutive jumps reaches the preset number of consecutive executions is determined as the historical primary jump address, which improves the accuracy of the determined historical primary jump destination address.

[0060] In some embodiments, if the number of consecutive executions is less than the threshold for the number of consecutive executions, it is determined that there is no historical primary jump address corresponding to the target tracking information. In this case, the corresponding historical primary jump address cannot be obtained.

[0061] In some embodiments, the threshold for the number of consecutive executions is preset, or is custom, or is the value when the counter reaches saturation; this application does not impose any restrictions on this.

[0062] In some embodiments, the branch prediction method for indirect jump branch instructions in this application further includes: determining whether the jump address executed by the indirect jump branch instruction is consistent with the historical major jump address corresponding to the target tracking information; if the jump address executed by the indirect jump branch instruction is consistent with the historical major jump address, executing step 104, updating the indirect jump branch instruction to a direct jump branch instruction, and using the historical major jump address as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction.

[0063] In some embodiments, in step 104, updating the indirect jump branch instruction to a direct jump branch instruction includes, for example, updating the type of the indirect jump branch instruction in the branch target buffer to the type of the direct jump branch instruction.

[0064] In some embodiments, in step 104, the historical major jump address is used as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction. For example, the aforementioned jump address of the indirect jump branch instruction and its updated type (i.e., the type of the direct jump branch instruction) are directly written into the branch predictor (e.g., ...). Figure 2In the prediction structure of the direct jump branch instruction of the branch predictor shown, for example, it is written into the branch target buffer BTB or the branch target address cache, and the update permission of the indirect jump branch instruction in the prediction structure of the indirect jump branch instruction in the branch predictor is disabled, for example, the update permission of the indirect jump branch instruction in the branch target buffer BTB or the indirect jump branch predictor is disabled.

[0065] In some embodiments, the branch prediction information of direct jump branch instructions is updated asynchronously during the instruction commit phase. In this way, the parallel triggering of instruction commit and branch prediction information updates can avoid pipeline blockage of branch prediction.

[0066] In some embodiments, the branch prediction method for indirect jump branch instructions in this application further includes: If the jump address executed by an indirect jump branch instruction is inconsistent with the historical major jump address, the indirect jump branch instruction will not be updated to a direct jump branch instruction.

[0067] In this way, when the main jump address of an indirect branch instruction is inconsistent with the historical main jump address corresponding to the target tracing information, the indirect branch instruction has a high probability of not jumping to the main jump address. In this case, not updating the type of the indirect branch instruction in the branch target buffer to the type of the direct branch instruction can avoid branch prediction errors that could affect the performance of the central processing unit.

[0068] In some embodiments, the branch prediction method for indirect jump branch instructions in this application further includes a step of training a main jump address tracking table, the training including a process for creating the main jump address tracking table, and a process for updating the main jump address tracking table after its creation.

[0069] Figure 7 This is a schematic diagram illustrating the steps of training the main jump address tracking table according to an embodiment of this application. For example... Figure 7 As shown, the steps for training the main jump address tracking table include: Step 105: After the indirect jump branch instruction has been executed, obtain the data field information of the indirect jump branch instruction according to the preset data field structure of the main jump address tracking table. Step 106: Generate main jump address tracing information based on the data field information of the indirect jump branch instruction, and store the generated main jump address tracing information to obtain the main jump address tracing table.

[0070] For example, assuming there is no major jump address tracking information in the major jump address tracking table, upon detecting the completion of the first indirect jump branch instruction, major jump address tracking information 1 corresponding to the completed first indirect jump branch instruction is generated and stored in the major jump address tracking table. Thus, the major jump address tracking table contains the first major jump address tracking information. For example, the instruction address of the completed first indirect jump branch instruction is compressed to obtain the first identifier information. The actual jump address of the first indirect jump branch instruction is used as the first jump address, and the counter corresponding to the first jump address is assigned a value of 0, and the valid value corresponding to the first jump address is assigned the maximum value (e.g., 1111111). The first identifier information, the first jump address, the value of the counter corresponding to the first jump address, and the valid value are stored in the major jump address tracking table according to the data field format of the major jump address tracking table, resulting in major jump address tracking information 1 corresponding to the first indirect jump branch instruction. This allows for the rapid and efficient generation of a primary jump address tracking table.

[0071] In some embodiments, the type of the branch instruction can be obtained from the branch target buffer (BTB), and the type can be used to determine whether the branch instruction is an indirect jump branch instruction.

[0072] In some embodiments, the branch prediction method for indirect jump branch instructions in this application further includes the step of updating the training major jump address tracking table.

[0073] In some embodiments, updating the training primary jump address tracking table includes at least one of the following steps: If there is no main jump address tracking information in the main jump address tracking table that matches the indirect jump branch instruction, create a new main jump address tracking information corresponding to the indirect jump branch instruction in the main jump address tracking table; In the absence of a historical major jump address corresponding to the target tracking information, the target tracking information is updated based on the jump address executed by the indirect jump branch instruction; When the jump address executed by the indirect jump branch instruction is inconsistent with the historical main jump address, the target tracking information is updated according to the jump address executed by the indirect jump branch instruction.

[0074] The following explains each of the above update steps.

[0075] In some embodiments, if there is no main jump address tracking information in the main jump address tracking table that matches the indirect jump branch instruction, the main jump address tracking information corresponding to the indirect jump branch instruction is created in the main jump address tracking table.

[0076] The method of creating new main jump address tracking information corresponding to indirect jump branch instructions in the main jump address tracking table is similar to the method of creating new main jump address tracking information 1 corresponding to the first indirect jump branch instruction in the main jump address tracking table in the above embodiment. For example, the identifier information of the indirect jump branch instruction and the jump address executed by the indirect jump branch instruction are used as the identifier information and jump address in the newly created main jump address tracking information, respectively, and the counter in the newly created main jump address tracking information is assigned a value of 0, and the valid value in the newly created main jump address tracking information is set to the maximum value.

[0077] If there is no major jump address tracking information in the major jump address tracking table, the above process can be understood as creating the major jump address tracking table. If there is at least one major jump address tracking entry in the major jump address tracking table, the above process can be understood as updating the major jump address tracking table.

[0078] In some embodiments, before creating the main jump address tracking information corresponding to the indirect jump branch instruction in the main jump address tracking table, if there is no main jump address tracking information matching the indirect jump branch instruction in the main jump address tracking table, the method further includes: Determine whether the number of major jump address tracking information in the major jump address tracking table has reached the upper limit (e.g., N in the aforementioned embodiment). If not, create a new major jump address tracking information corresponding to the indirect jump branch instruction in the major jump address tracking table. If yes, further determine whether there is a major jump address tracking information with a valid value of 0 in the major jump address tracking table.

[0079] If a major jump address tracer with a valid value of 0 exists in the major jump address tracer table, a major jump address tracer with a valid value of 0 is randomly selected and deleted. Then, a new major jump address tracer corresponding to the indirect jump branch instruction is created in the major jump address tracer table. If there is no valid main jump address tracking information with a value of 0 in the main jump address tracking table, then the valid value in the main jump address tracking information in the main jump address tracking table will be decremented by 1, and the main jump address tracking information corresponding to the newly created indirect jump branch instruction in the main jump address tracking table will be abandoned. That is, the main jump address tracking information corresponding to the newly created indirect jump branch instruction will not be created in the main jump address tracking table.

[0080] In some embodiments, if there is no historical primary jump address corresponding to the target tracking information, the target tracking information is updated according to the jump address executed by the indirect jump branch instruction.

[0081] For example, if the main jump address tracking table contains main jump address tracking information (i.e., target tracking information) that matches the executed indirect jump branch instruction, but there is no historical main jump address corresponding to the target tracking information, then if the jump address in the target tracking information is the same as the jump address executed by the indirect jump branch instruction, the value of the counter in the target tracking information is incremented by 1; if the jump address in the target tracking information is different from the jump address executed by the indirect jump branch instruction, then the jump address in the target tracking information is updated to the jump address executed by the indirect jump branch instruction, the value of the counter in the target tracking information is updated to 0 (i.e., the counter is cleared), and the valid value in the target tracking information is updated to the maximum value.

[0082] In some embodiments, if the jump address executed by the indirect jump branch instruction is inconsistent with the historical main jump address, the target tracking information is updated according to the jump address executed by the indirect jump branch instruction.

[0083] For example, if the main jump address trace table contains main jump address trace information (i.e., target trace information) that matches the executed indirect jump branch instruction, and there is a historical main jump address corresponding to the target trace information, but this historical main jump address is inconsistent with the jump address executed by the indirect jump branch instruction, then the jump address in the target trace information (which is also the historical main jump address) is updated to the jump address executed by the indirect jump branch instruction, the value of the counter in the target trace information is updated to 0 (i.e., the counter is cleared), and the valid value in the target trace information is updated to the maximum value.

[0084] In this way, the main jump address tracking table is updated according to the indirect jump branch instruction. For example, if the main jump address tracking information corresponding to the indirect jump branch instruction does not exist in the main jump address tracking table, the main jump address tracking information corresponding to the indirect jump branch instruction is generated according to the data field structure of the main jump address tracking table and inserted into the main jump address tracking table. If the main jump address tracking information corresponding to the indirect jump branch instruction already exists in the main jump address tracking table, the main jump address tracking information corresponding to the indirect jump branch instruction is updated according to the actual jump address of the indirect jump branch instruction. Therefore, whenever the indirect jump branch instruction is detected to have been executed, the main jump address tracking table is updated in a timely manner, which can improve the accuracy of the determined target tracking information and historical main jump addresses, thereby improving the accuracy of branch prediction and further improving the performance of the central processing unit.

[0085] In some embodiments, the step of updating the primary jump address tracking table is performed, for example, during the branch prediction process of executing indirect jump branch instructions in this application.

[0086] Figure 8 A flowchart of a branch prediction method for indirect jump branch instructions according to an embodiment of this application. (See attached flowchart.) Figure 8 As shown, the flow 200 of the branch prediction method for indirect jump branch instructions in this application embodiment includes: Step 201: If the indirect jump instruction has been executed, obtain the instruction address and jump address of the indirect jump branch instruction; Step 202: Generate the identification information of the indirect jump branch instruction based on the instruction address of the indirect jump branch instruction; Step 203: Based on the identifier information of the indirect jump branch instruction, determine whether there is target tracking information matching the indirect jump branch instruction in the pre-trained main jump address tracking table; if yes, proceed to step 204; if no, proceed to step 207. Step 204: Determine if there is a historical primary jump address corresponding to the target tracking information; if yes, proceed to step 205; otherwise, proceed to step 208. Step 205: Determine whether the jump address executed by the indirect jump branch instruction is consistent with the historical main jump address; if yes, proceed to step 206; if no, proceed to step 209. Step 206: Update the indirect jump branch instruction to a direct jump branch instruction, and use the historical major jump address as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction, and end the process; Step 207: Create the main jump address tracking information corresponding to the indirect jump branch instruction in the main jump address tracking table, and end the process; Step 208: Update the target tracking information according to the jump address executed by the indirect jump branch instruction, and end the process; Step 209: Update the target tracking information according to the jump address executed by the indirect jump branch instruction, and prevent the indirect jump branch instruction from being updated to a direct jump branch instruction, and end the process.

[0087] The implementation of steps 201 to 209 above can be found in the aforementioned related embodiments, and will not be repeated here.

[0088] Through the above embodiments, the branch prediction method for indirect jump branch instructions provided in this application matches the instruction address and jump address of the indirect jump branch instruction in the main jump address tracking table, and updates the type of the indirect jump branch instruction to a direct jump branch instruction when a preset condition is met. In this way, the indirect jump branch instruction is predicted as a direct jump branch instruction when the preset condition is met, which improves the efficiency of branch prediction and thus helps to improve the performance of the central processing unit. Furthermore, the main jump target address of the indirect jump branch instruction is determined and verified using the main jump address tracking table. When the indirect jump branch instruction and its jump address match the main jump address tracking table, the historical main jump address that matches the indirect jump branch instruction in the main jump address tracking table is used as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction. This improves the accuracy of branch prediction and can further improve the performance of the central processing unit. Furthermore, this application optimizes the steps for accessing the indirect branch predictor based on existing algorithms, without increasing chip area and power consumption, thus maintaining a balance between the accuracy of branch prediction and the complexity of the algorithm. Moreover, since some indirect branch instructions no longer depend on the indirect branch predictor, the capacity pressure on the indirect branch predictor can be indirectly alleviated, thereby further improving the performance of the central processing unit.

[0089] Second aspect of the embodiments

[0090] A second aspect of this application provides a branch prediction apparatus for indirect jump branch instructions. Figure 9 This is a schematic diagram of a branch prediction device for indirect jump branch instructions according to an embodiment of this application. Figure 9 As shown, the branch prediction device 300 for the indirect jump branch instruction includes: The first acquisition unit 301 is used to acquire the instruction information of the indirect jump branch instruction when the indirect jump branch instruction has been executed. The instruction information includes the instruction address of the indirect jump branch instruction and the jump address to which it is executed. Matching unit 302 is used to match the indirect jump branch instruction with the main jump address tracking information in the pre-trained main jump address tracking table according to the instruction address to obtain the target tracking information; The second acquisition unit 303 is used to acquire the historical main jump address corresponding to the target tracking information; The processing unit 304 is used to update the indirect jump branch instruction to a direct jump branch instruction when the jump address of the indirect jump branch instruction execution is consistent with the historical main jump address corresponding to the target tracking information, and to use the historical main jump address as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction.

[0091] In some embodiments, the primary jump address tracking table includes multiple primary jump address tracking information. Each primary jump address tracking information includes identification information of historical indirect jump branch instructions, the most recently executed jump address, the number of consecutive executions of the most recently executed jump address, and a valid value indicating the validity of the primary jump address tracking information.

[0092] In some embodiments, the matching unit 302 is further configured to: generate identification information of an indirect jump branch instruction based on the instruction address; match the identification information of the indirect jump branch instruction with the identification information in the main jump address tracking information in the main jump address tracking table; and determine the main jump address tracking information with matching identification information as the target tracking information of the indirect jump branch instruction.

[0093] In some embodiments, the matching unit 302 is further configured to: read the instruction address of the indirect jump branch instruction; compress the instruction address to obtain the identification information of the indirect jump branch instruction.

[0094] In some embodiments, the second acquisition unit 303 is further configured to: acquire the number of consecutive executions of the most recently executed jump address in the target tracking information; determine whether the number of consecutive executions is greater than or equal to a preset threshold for the number of consecutive executions; and if the number of consecutive executions is greater than or equal to the threshold for the number of consecutive executions, determine the most recently executed jump address as the historical main jump address corresponding to the target tracking information.

[0095] In some embodiments, the processing unit 304 is further configured to: not update the indirect jump branch instruction to a direct jump branch instruction if the jump address executed by the indirect jump branch instruction is inconsistent with the historical major jump address.

[0096] In some embodiments, such as Figure 9 As shown, the branch prediction device for indirect jump branch instructions in this application embodiment further includes a main jump address tracking table training unit 305, which is used to create and update the main jump address tracking table.

[0097] In some embodiments, the main jump address tracking table training unit 305 is further configured to train the main jump address tracking table according to the following steps: when an indirect jump branch instruction is executed, the data field information of the indirect jump branch instruction is obtained according to the preset data field structure of the main jump address tracking table; the main jump address tracking information is generated according to the data field information of the indirect jump branch instruction, and the generated main jump address tracking information is stored to obtain the main jump address tracking table.

[0098] In some embodiments, the main jump address tracking table training unit 305 is further configured to update the trained main jump address tracking table according to at least one of the following steps: if there is no main jump address tracking information in the main jump address tracking table that matches the indirect jump branch instruction, create new main jump address tracking information corresponding to the indirect jump branch instruction in the main jump address tracking table; if there is no historical main jump address corresponding to the target tracking information, update the target tracking information according to the jump address executed by the indirect jump branch instruction; if the jump address executed by the indirect jump branch instruction is inconsistent with the historical main jump address, update the target tracking information according to the jump address executed by the indirect jump branch instruction.

[0099] The branch prediction apparatus for indirect jump branch instructions provided in this application can implement the branch prediction method for indirect jump branch instructions described in the embodiments of the first aspect of this application. Since the principle of the branch prediction apparatus for indirect jump branch instructions in solving the problem is similar to that of the branch prediction method for indirect jump branch instructions, the implementation of the branch prediction apparatus for indirect jump branch instructions can refer to the implementation of the branch prediction method for indirect jump branch instructions, and the repeated parts will not be described again.

[0100] Through the above embodiments, the branch prediction device for indirect jump branch instructions provided in this application matches the instruction address and jump address of the indirect jump branch instruction in the main jump address tracking table, and updates the type of the indirect jump branch instruction to a direct jump branch instruction when a preset condition is met. In this way, the indirect jump branch instruction is predicted as a direct jump branch instruction when the preset condition is met, which improves the efficiency of branch prediction and thus helps to improve the performance of the central processing unit. Furthermore, the main jump target address of the indirect jump branch instruction is determined and verified using the main jump address tracking table. When the indirect jump branch instruction and its jump address match the main jump address tracking table, the historical main jump address that matches the indirect jump branch instruction in the main jump address tracking table is used as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction. This improves the accuracy of branch prediction and can further improve the performance of the central processing unit. Furthermore, this application optimizes the steps for accessing the indirect branch predictor based on existing algorithms, without increasing chip area and power consumption, thus maintaining a balance between the accuracy of branch prediction and the complexity of the algorithm. Moreover, since some indirect branch instructions no longer depend on the indirect branch predictor, the capacity pressure on the indirect branch predictor can be indirectly alleviated, thereby further improving the performance of the central processing unit.

[0101] In addition, embodiments of the present invention also provide an electronic device. Figure 10 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Figure 10 As shown, the electronic device may include a processor 401 and a memory 402, wherein the processor 401 and the memory 402 may be connected via a bus or other means. Figure 10 Taking the example of a connection between China and Israel via a bus.

[0102] Processor 401 may be a central processing unit (CPU). Processor 401 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.

[0103] Memory 402, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the branch prediction method for indirect jump branch instructions in the embodiments of this application (e.g., Figure 7The first acquisition unit 301, matching unit 302, second acquisition unit 303, processing unit 304, and main jump address tracking table training unit 305 are shown in the diagram. The processor 401 executes various functional applications and data processing by running non-transitory software programs, instructions, and modules stored in the memory 402, thereby implementing the branch prediction method for indirect jump branch instructions in the above method embodiments.

[0104] The memory 402 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor 401, etc. Furthermore, the memory 402 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 402 may optionally include memory remotely located relative to the processor 401, and these remote memories may be connected to the processor 401 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0105] The one or more modules are stored in the memory 402, and when executed by the processor 401, the branch prediction method of the indirect jump branch instruction described above is executed.

[0106] The specific details of the above-mentioned electronic device can be understood by referring to the relevant descriptions and effects in the method embodiments, and will not be repeated here.

[0107] This specification also provides a computer storage medium storing computer program instructions that, when executed, implement the steps of the branch prediction method for the indirect jump branch instructions described above.

[0108] This specification also provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of the branch prediction method for the indirect jump branch instruction described above.

[0109] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0110] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. The focus of each embodiment is to describe the differences from other embodiments.

[0111] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0112] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0113] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute certain parts of the methods of various embodiments of this application.

[0114] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0115] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0116] It should be noted that the limitations of each step involved in the embodiments of the present invention are not considered as limiting the order of steps without affecting the implementation of the specific solution. The steps listed first can be executed first, or they can be executed later, or they can even be executed simultaneously. As long as the solution can be implemented, they should be considered to fall within the protection scope of the present invention.

[0117] The present invention has been described above with reference to specific embodiments. However, those skilled in the art should understand that these descriptions are exemplary and not intended to limit the scope of protection of the present invention. Those skilled in the art can make various modifications and variations to the present invention based on its spirit and principles, and these modifications and variations are also within the scope of the present invention.

Claims

1. A branch prediction method for indirect jump branch instructions, characterized in that, The method includes: When an indirect jump branch instruction is executed, the instruction information of the indirect jump branch instruction is obtained, and the instruction information includes the instruction address of the indirect jump branch instruction and the jump address to which it is executed; Based on the instruction address, the indirect jump branch instruction is matched with the main jump address tracking information in the pre-trained main jump address tracking table to obtain the target tracking information; Obtain the historical primary redirect addresses corresponding to the target tracking information; If the jump address executed by the indirect jump branch instruction is consistent with the historical main jump address corresponding to the target tracking information, the indirect jump branch instruction is updated to a direct jump branch instruction, and the historical main jump address is used as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction.

2. The method according to claim 1, characterized in that, The primary jump address tracking table includes multiple primary jump address tracking information entries. Each primary jump address tracking information entry includes the identifier information of historical indirect jump branch instructions, the most recently executed jump address, the number of consecutive executions of the most recently executed jump address, and a valid value indicating the validity of the primary jump address tracking information.

3. The method according to claim 2, characterized in that, Based on the instruction address, the indirect jump branch instruction is matched with the main jump address tracking information in a pre-created main jump address tracking table to obtain target tracking information, including: The identification information of the indirect jump branch instruction is generated based on the instruction address; The identification information of the indirect jump branch instruction is matched with the identification information in the main jump address tracking information in the main jump address tracking table, and the main jump address tracking information with matching identification information is determined as the target tracking information of the indirect jump branch instruction.

4. The method according to claim 3, characterized in that, The identification information of the indirect jump branch instruction is generated based on the instruction address, including: Read the instruction address of the indirect jump branch instruction; The instruction address is compressed to obtain the identification information of the indirect jump branch instruction.

5. The method according to claim 2, characterized in that, Obtaining the historical primary redirect addresses corresponding to the target tracking information includes: Obtain the number of consecutive executions of the most recently executed jump address from the target tracking information; Determine whether the number of consecutive executions is greater than or equal to a preset threshold for the number of consecutive executions; If the number of consecutive executions is greater than or equal to the threshold number of consecutive executions, the jump address of the most recent execution is determined as the historical primary jump address corresponding to the target tracking information.

6. The method according to claim 1, characterized in that, The method further includes: If the jump address executed by the indirect jump branch instruction is inconsistent with the historical main jump address, the indirect jump branch instruction will not be updated to a direct jump branch instruction.

7. The method according to claim 1, characterized in that, The method also includes the step of training the primary jump address tracking table. The steps for training the primary jump address tracking table include: When the indirect jump branch instruction is executed, the data field information of the indirect jump branch instruction is obtained according to the preset data field structure of the main jump address tracking table; The main jump address tracking information is generated based on the data field information of the indirect jump branch instruction, and the generated main jump address tracking information is stored to obtain the main jump address tracking table.

8. The method according to claim 7, characterized in that, The method also includes the step of updating the primary jump address tracking table used for training. The step of updating the primary jump address tracking table includes at least one of the following steps: If there is no main jump address tracking information matching the indirect jump branch instruction in the main jump address tracking table, the main jump address tracking information corresponding to the indirect jump branch instruction is created in the main jump address tracking table. If there is no historical major jump address corresponding to the target tracking information, the target tracking information is updated according to the jump address executed by the indirect jump branch instruction; If the jump address executed by the indirect jump branch instruction is inconsistent with the historical main jump address, the target tracking information is updated according to the jump address executed by the indirect jump branch instruction.

9. A branch prediction device for indirect jump branch instructions, characterized in that, The device includes: The first acquisition unit is used to acquire the instruction information of the indirect jump branch instruction when the indirect jump branch instruction is completed, wherein the instruction information includes the instruction address of the indirect jump branch instruction and the jump address to which it is executed; A matching unit is used to match the indirect jump branch instruction with the main jump address tracking information in a pre-trained main jump address tracking table according to the instruction address to obtain target tracking information; The second acquisition unit is used to acquire the historical main jump address corresponding to the target tracking information; The processing unit is configured to update the indirect jump branch instruction to a direct jump branch instruction when the jump address executed by the indirect jump branch instruction is consistent with the historical main jump address corresponding to the target tracking information, and to use the historical main jump address as the jump address of the direct jump branch instruction obtained by updating the indirect jump branch instruction.

10. An electronic device, characterized in that, include: The system includes a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to implement the branch prediction method for indirect jump branch instructions as described in any one of claims 1 to 8.

11. A computer storage medium, characterized in that, The computer storage medium stores computer program instructions, which, when executed, implement the steps of the branch prediction method for indirect jump branch instructions as described in any one of claims 1 to 8.

12. A computer program product, characterized in that, The method comprises a computer program that, when executed by a processor, implements the steps of the branch prediction method for the indirect jump branch instruction as described in any one of claims 1 to 8.

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