Memory access control method, memory access method, device, storage medium and program product

Abstract

Embodiments of the present application provide a memory access control method and a memory access method, device, storage medium and program product. In the embodiments of the present application, for DMA access of a target device, the state of a memory page in physical memory is perceived, when the accessed memory page is swapped into the physical memory, a first path that does not support memory page fault is used for page access, improving the access efficiency; when the accessed memory page is not in the physical memory, the first path that does not support memory page fault is switched to a second path that supports memory page fault, and the access to the page is completed after the page is swapped into the physical memory by triggering the memory page fault mechanism on the second path, so that the DMA access process of the target device can support memory page fault, the memory page of the DMA access can be swapped into or out of the physical memory as needed, improving the utilization rate of the physical memory resources, and at the same time, even if memory page fault occurs after switching from the first path to the second path, the target device will not be down.

Description

Technical Field

[0001] This application relates to the field of cloud computing technology, and in particular to a memory access control method, memory access method, device, storage medium and program product. Background Technology

[0002] With the development of cloud computing technology, some hardware acceleration devices have emerged to help host machines improve cloud computing performance, such as CIPU (Cloud Infrastructure Processing Unit) and NPU (Neural Network Processing Unit), which allow the host machine to offload some functions, such as virtualization and computing tasks, to these hardware acceleration devices.

[0003] These hardware acceleration devices can be viewed as small computer systems, possessing relatively complete computing, network, storage, and peripheral resources. The peripherals access virtual memory via DMA (Direct Memory Access) and use the IOMMU (Input-Output Memory Management Unit) to translate virtual memory addresses into physical memory addresses.

[0004] Because DMA allows peripherals to exchange data directly with memory without CPU (Central Processing Unit) intervention, the IOMMU must maintain a mapping between the virtual memory address accessed by DMA and the physical memory address. This is known as "pinning" the virtual memory address to prevent page faults, especially on hardware-accelerated devices where page faults can directly cause system crashes. However, pinning the virtual memory address accessed by DMA leads to lower utilization of physical memory resources. Summary of the Invention

[0005] This application provides a memory access control method and memory access method, device, storage medium and program product, for realizing DMA access support for memory page faults without causing the target device to crash, thereby improving the utilization of physical memory resources.

[0006] This application provides a memory access control method for controlling a target peripheral device on a target device to access a target page. The target page is any memory page that the target peripheral device needs to access. The method includes: when the target page is swapped out of physical memory, controlling the target peripheral device to switch from a first path to a second path so that the target peripheral device accesses the target page through the second path; when the target page is swapped back into physical memory, controlling the target peripheral device to switch from the second path to the first path so that the target peripheral device accesses the target page through the first path. The first path is a memory access path where the target peripheral device queries the physical address of the target page using a first address translation component that does not support memory page faults to access the target page. The first address translation component is used to perform address translation between the target peripheral device and physical memory. The second path is a memory access path where simulation software, on behalf of the target peripheral device, queries the physical address of the target page using a second address translation component that supports memory page faults to access the target page. The second address translation component is used to perform address translation between the processor and physical memory of the target device.

[0007] This application also provides a memory access method applied to a target peripheral on a target device. The method includes: under the control of a memory management module, when a target page to be accessed by the target peripheral is swapped out of physical memory, switching from a first path to a second path, and accessing the target page through the second path; under the control of the memory management module, when the target page is swapped back into physical memory, switching from the second path to the first path, and accessing the target page through the first path; wherein, the first path is a memory access path in which the target peripheral queries the physical address of the target page to access the target page through a first address translation component that does not support memory page faults, and the first address translation component is used to perform address translation between the target peripheral and physical memory; the second path is a memory access path in which simulation software, on behalf of the target peripheral, queries the physical address of the target page to access the target page through a second address translation component that supports memory page faults; the second address translation component is used to perform address translation between the processor and physical memory of the target device.

[0008] This application embodiment also provides a target device, including: a target peripheral and computing resources, wherein a kernel management module and simulation software are running on the computing resources; wherein the kernel management module is used to execute the steps in the memory access control method; and the target peripheral is used to execute the steps in the memory access method.

[0009] This application embodiment also provides a peripheral device, including: a memory and a processor, wherein the memory is used to store a computer program, and the processor is coupled to the memory and used to execute the computer program to implement the steps in the memory access method.

[0010] This application also provides a computer-readable storage medium that, when executed by a processor, enables the processor to implement the steps in the secure container migration method.

[0011] This application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, performs the steps in the secure container migration method.

[0012] In this embodiment, for DMA access of the target peripheral, a first path that does not support memory page faults and a second path that supports memory page faults are provided. Combined with the ability to detect whether a memory page is in physical memory, flexible switching between the two paths is achieved when accessing a memory page. Specifically, when the accessed memory page is swapped into physical memory, the first path that does not support memory page faults is used to access the page, improving access efficiency. When the accessed memory page is not in physical memory, the system switches from the first path that does not support memory page faults to the second path that supports memory page faults. By triggering a memory page fault mechanism on the second path, the page is swapped back into physical memory, completing the page access. This allows the DMA access process of the target device to support memory page faults, and the memory pages accessed by DMA can be swapped into or out of physical memory as needed, improving the utilization of physical memory resources. Furthermore, even if a memory page fault occurs after switching from the first path to the second path, it will not cause the target device to crash. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0014] Figure 1a This is a schematic diagram of the structure of a target device provided in an embodiment of this application;

[0015] Figure 1b This is a schematic diagram illustrating a memory access control method provided in an embodiment of this application.

[0016] Figure 2a A flowchart illustrating a memory access control method provided as another exemplary embodiment of this application;

[0017] Figure 2bA schematic diagram of a process for switching from a first path to a second path is provided as another exemplary embodiment of this application;

[0018] Figure 2c A timing diagram illustrating a switch from a first path to a second path, provided as another exemplary embodiment of this application;

[0019] Figure 3 A flowchart illustrating a memory access method provided as another exemplary embodiment of this application;

[0020] Figure 4a A schematic diagram of a process for switching from a second path to a first path is provided as another exemplary embodiment of this application;

[0021] Figure 4b A timing diagram illustrating a switch from a second path to a first path, provided as another exemplary embodiment of this application;

[0022] Figure 5 A flowchart illustrating yet another exemplary embodiment of the memory access control method provided in this application;

[0023] Figure 6 A flowchart illustrating a memory access method provided as another exemplary embodiment of this application;

[0024] Figure 7 A schematic diagram of the structure of a peripheral device provided as another exemplary embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that, in the cases involving user information in the embodiments of this application, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse. In addition, the various models involved in this application (including but not limited to language models or large models) comply with relevant laws and standards.

[0027] In this application embodiment, various forms of electronic devices with peripheral devices are referred to as target devices, such as physical machines, host machines, or some hardware acceleration devices. These peripheral devices are the I / O (Input / Output) devices of the target devices. Optionally, they can be interconnected with the target devices via PCI (Peripheral Component Interconnect) bus or PCIE (Peripheral Component Interconnect Express) bus, and are therefore also called PCI devices. These PCI devices can directly access the physical memory of the target devices. To improve the utilization of physical memory, virtual memory technology is used, that is, using external disk space as an extension of physical memory, temporarily storing some data in external disk space, and exchanging data with external disk space when needed. By using virtual memory, a larger virtual memory than the actual physical memory can be generated. There is a mapping relationship between virtual memory and physical memory. Address translation is used to convert virtual memory addresses to physical memory addresses, thereby realizing access to physical memory. Here, virtual memory address is simply called virtual address, physical memory address is simply called physical address, and address translation refers to the process of converting virtual address to physical address. For peripheral devices, the physical memory of hardware-accelerated devices can be accessed through Direct Memory Access (DMA), and address translation is completed through the IOMMU.

[0028] In traditional DMA schemes, the IOMMU must maintain a mapping between the virtual and physical addresses accessed during DMA, essentially pinning the virtual addresses to prevent page faults. This is especially crucial on hardware-accelerated devices, where a page fault can directly cause the target device to crash. However, pinning the virtual memory addresses accessed during DMA leads to low utilization of physical memory resources. Therefore, DMA operations that do not support page faults result in low memory resource utilization. To enable DMA operations to support page faults, one implementation requires the IOMMU to support both ATS (Address Translation Services) and PRI (Page Request Interface) to achieve DMA operation support for page faults. ATS is a hardware capability that caches the virtual-to-physical address mapping in the target device, allowing the target device to perform address translation locally without frequently requesting the IOMMU for address translation, thus reducing the load on the IOMMU. The Page Request Interface (PRI) is an industry-standard PCI bus protocol defined by the PCI-SIG (Peripheral Component Interconnect Special Interest Group) for handling memory page faults.

[0029] However, most physical machines do not support ATS hardware capabilities, especially some small hardware acceleration devices, so the above solutions cannot be implemented on some devices. In addition, although some devices have ATS hardware capabilities and can implement the above solutions, the cost is high and the compatibility is poor.

[0030] In this embodiment, for DMA access of the target peripheral, a first path that does not support memory page faults and a second path that supports memory page faults are provided. Combined with the ability to detect whether a memory page is in physical memory, flexible switching between the two paths is achieved when accessing a memory page. Specifically, when the accessed memory page is swapped into physical memory, the first path that does not support memory page faults is used to access the page, improving access efficiency. When the accessed memory page is not in physical memory, the system switches from the first path that does not support memory page faults to the second path that supports memory page faults. By triggering a memory page fault mechanism on the second path, the page is swapped back into physical memory, completing the page access. This allows the DMA access process of the target device to support memory page faults, and the memory pages accessed by DMA can be swapped into or out of physical memory as needed, improving the utilization of physical memory resources. Furthermore, even if a memory page fault occurs after switching from the first path to the second path, it will not cause the target device to crash.

[0031] Furthermore, in this embodiment, existing hardware acceleration devices that do not support the PRI interface and ATS IOMMU can enable DMA operations to have memory page fault capability through hardware and software collaboration without any additional hardware costs, resulting in low cost and high compatibility. Furthermore, in an optional embodiment of this application, the switching between the first path and the second path involves switching the corresponding address translation page table to ensure data integrity.

[0032] Furthermore, in an optional embodiment of this application, during the switching process between the first path and the second path, the target peripheral performs a drain process on the access requests being processed, in order to wait for any access requests that may exist on the first path or the second path to end, thereby avoiding DMA address translation errors.

[0033] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0034] In this application, the product form of the target device is not limited. For example, the target device can be a host machine, which can be various terminal devices such as computers, mobile phones, and tablets, or server-side devices such as traditional servers, cloud servers, server clusters, or workstations. As another example, the target device can also be a hardware acceleration device that provides acceleration services to the host machine. A hardware acceleration device refers to a hardware device used to accelerate specific types of data processing, allowing the host machine to offload some functions to more efficient, dedicated hardware acceleration devices, thereby accelerating the processing speed of specific types of data. For example, in cloud computing scenarios, by using hardware acceleration devices adapted to specific types of data processing, such as CIPUs (Computer Integrated Processing Units), which are processors used to cloudify and hardware-accelerate computing, storage, and network infrastructure, computing efficiency can be significantly improved. It should be noted that the technical solutions provided in this application are particularly suitable for hardware acceleration devices. Therefore, in the following embodiments, the target device is described as a hardware acceleration device, but this is not the only applicable method.

[0035] For example, Figure 1a This is a schematic diagram of the structure of a target device provided in this embodiment. In this embodiment, the target device 10 includes a software layer and a hardware layer 110. The software layer of the target device 10 can be divided into user mode 18 and kernel mode 19. The kernel mode 19 includes a memory management module 12, which is responsible for the memory management of the target device 10. Memory management includes, but is not limited to, memory resource allocation and reclamation, memory mapping, and virtual memory management. Furthermore, the hardware layer 110 of the target device 10 includes various hardware resources of the target device 10, such as, but not limited to, processors and physical memory 15, etc.

[0036] In this embodiment, the target device 10 has a target peripheral 11. The target peripheral 11 refers to an external device that is interconnected with the processor 17 of the target device 10 using various bus protocols to extend the functionality of the target device 10. For example, it can be, but is not limited to, a PCI bus or a PCIe bus interconnected with the processor of the target device 10. In addition to the PCI or PCIe bus, other buses can also be used for interconnection, such as the CXL (Compute Express Link, a new open interconnect standard) bus, and there is no limitation on this.

[0037] In this embodiment, the type of the target peripheral 11 is not limited. For example, it can be a general peripheral, including but not limited to input / output devices (such as displays and keyboards), network devices (such as network cards and network switches), and external storage devices. As another example, the target peripheral 11 can also be a device that controls the interconnection between general peripherals and the processor, referred to as a peripheral controller. The peripheral controller can be, but is not limited to, an FPGA (Field-Programmable Gate Array). The FPGA communicates with the general peripherals through a specific interface to control them.

[0038] In this embodiment, the target peripheral 11 can access the physical memory 15 of the target device 10 via DMA, allowing the target peripheral 11 to directly exchange data with the physical memory 15 of the target device 10 without the processor of the target device 10 participating in data transfer. In this embodiment, the "DMA access request" initiated by the target peripheral via DMA is simply referred to as an "access request." An access request can be a read request or a write request. A read request refers to reading data from a memory page in physical memory via DMA, while a write request refers to writing data to a memory page in physical memory via DMA. A memory page is the smallest unit for organizing and managing data in physical memory, and its size can be 4KB, 8KB, 2MB, etc., without limitation.

[0039] Before the target peripheral 11 accesses physical memory 15, the upper-layer application 111 requests virtual memory from the memory management module 12. If the target device 10 is implemented as a hardware acceleration device, the upper-layer application 111 can be an application running on the hardware acceleration device; alternatively, it can be an application running on a host machine interconnected with the hardware acceleration device, without limitation. The memory management module 12 responds to the application 111's request, mapping the virtual memory to physical memory 15, and maintaining and managing the address mapping relationship between virtual memory and physical memory 15, establishing an address translation page table (hereinafter referred to as a "page table"). In this embodiment, the address of the virtual memory is called the virtual address, and the address of the physical memory 15 is called the physical address. Through the address mapping relationship between virtual memory and physical memory 15 maintained by the address translation page table, the virtual address can be converted to a physical address, allowing access to memory pages in physical memory 15 based on the converted physical address.

[0040] In this embodiment, the address translation page table is sent to the first address translation component 13 and the second address translation component 14 of the target device 10, such as... Figure 2a As shown, the address translation page table of the first address translation component includes page table entries c1, c2, and cn, where n is greater than 2 and is a natural number; the address translation page table of the second address translation component includes page table entries b1, b2, and bj, where j is greater than 2 and is a natural number. Theoretically, the page table entries stored in the address translation page tables of the first and second address translation components are the same, but for ease of distinction and description, ... Figure 2a Different labels are used for identification.

[0041] In this embodiment, the first address translation component 13 is used to perform address translation between the target peripheral device 11 and the physical memory 15. When the target peripheral device 11 accesses a memory page in the physical memory 15, it provides address translation services to the target peripheral device 11, that is, converting the virtual address of the memory page to be accessed into a corresponding physical address, so that the target peripheral device 11 can access the corresponding memory page based on the physical address. Optionally, the first address translation component 13 may be, but is not limited to, an IOMMU. The second address translation component 14 is used to perform address translation between the processor 17 of the target device 10 and the physical memory 15. When an application running on the processor 17 needs to access a memory page in the physical memory 15, it provides address translation services to the processor 1 (or the application), that is, converting the virtual address of the memory page to be accessed into a corresponding physical address, so that the processor can access the corresponding memory page based on the physical address. Optionally, the second address translation component 14 may be, but is not limited to, an MMU.

[0042] The first address translation component and the second address translation component are used for address translation on different memory access paths of the target peripheral, respectively. The following section combines... Figure 1b This section introduces the different memory access paths for the target peripheral.

[0043] When the target peripheral 11 initiates an access to a memory page in physical memory 15, it carries the virtual address of that memory page in the access request. This access request is sent to the first address translation component 13. Upon receiving the access request, the first address translation component 13 looks up the corresponding page table entry in the address translation page table based on the virtual address in the access request, retrieves the physical address corresponding to the virtual address of the memory page from that page table entry, and returns the physical address to the target peripheral 11. The target peripheral 11 then accesses the memory page in physical memory 15 based on this physical address. For ease of description and distinction, the memory page that the target peripheral 11 is currently accessing is referred to as the target page. The target page can be any memory page that the target peripheral 11 needs to access, for example, any memory page that the target peripheral 11 has the right to access.

[0044] In this embodiment, the target peripheral device 11 queries the physical address of the target page through the first address translation component 13 to access the memory access path of the target page, which is called the first path. The target peripheral device 11 can directly access the physical memory of the target device through the first path without going through the processor, resulting in high memory access efficiency. Therefore, the first path is also called the fast path. Accessing the target page through the first path requires the target page to reside in the physical memory 15 at all times. The first address translation component 13 does not support memory page faults because a memory page fault will cause the target device to malfunction, especially when the target device 10 is implemented as a hardware-accelerated device, where a memory page fault will directly cause the hardware-accelerated device to crash.

[0045] In this embodiment, in a scenario where the target peripheral 11 accesses physical memory 15 using DMA, it is desirable to support memory page faults without causing malfunctions or crashes in the target device, thereby improving the utilization of physical memory resources. The reason why supporting memory page faults can improve the utilization of physical memory resources is as follows: In virtual memory technology, external persistent storage media (e.g., disks) can be used as an extension of physical memory 15. To improve the utilization of physical memory space, a page replacement algorithm can be used to swap some memory pages stored in physical memory 15 to external persistent storage media. When these memory pages (e.g., the target page) need to be accessed, they can be swapped back into physical memory from the external persistent storage media. By combining the use of physical memory 15 and external disk space, virtual memory space exceeding the size of physical memory 15 can be used.

[0046] In this embodiment, it is desirable that in scenarios where the target peripheral 11 accesses physical memory 15 using DMA, the target page can be swapped out of physical memory 15 to persistent storage when the target peripheral does not access the target page, and swapped back into physical memory when the target peripheral needs to access the target page. This allows the target peripheral to successfully access the target page without causing malfunctions or crashes in the target device. To achieve this objective, in this embodiment, for scenarios where the target peripheral 11 accesses physical memory 15 using DMA, in addition to providing a first path that does not support memory page faults, a second path that supports memory page faults is also provided. The second path requires memory access through the processor and has lower memory access efficiency than the first path; therefore, the second path is also called the slow path. By accessing memory pages through the second path, the memory pages accessed by DMA can also be swapped out of physical memory 15 instead of remaining in physical memory 15 indefinitely, thereby improving resource utilization. The second path needs to accommodate both DMA operations and memory page faults. In this embodiment, the second path achieves this by converting DMA memory access operations that do not support memory page faults into processor access operations to physical memory that support memory page faults. This ensures that DMA memory access operations support memory page faults. Furthermore, to convert DMA memory access operations that do not support memory page faults into processor access operations to physical memory that support memory page faults, the second path includes simulation software 16. The second path is a memory access path where the simulation software 16, on behalf of the target peripheral 11, queries the physical address of the target page through a second address translation component 14 (e.g., MMU) that supports memory page faults. The second address translation component itself supports memory page faults; if a memory page fault is triggered, it will swap the target page from external disk space back into physical memory so that the target peripheral can access the target page through the second path.

[0047] The simulation software 16 runs on the processor 17 of the target device and is a software program used to simulate the interaction process between the processor 17 of the target device 10 and the target peripheral 11 based on the target interconnect protocol. The target interconnect protocol refers to the interconnect protocol used between the processor and the target peripheral, such as PCIe or CXL. Access requests to the target peripheral 11 do not support direct address translation via the second address translation component 14. Therefore, the simulation software 16 on the processor 17 interacts with the target peripheral 11 to receive DMA access requests from it. The simulation software 16 and the target peripheral 11 use DMA to send and receive access requests; that is, the target peripheral directly writes the access request into the physical memory space of the simulation software 16, and the simulation software 16 directly reads the access request from its physical memory space. The physical memory space of the simulation software 16 is a portion of the physical memory of the target device; optionally, this physical memory space is small. Then, the simulation software 16, on behalf of the target peripheral 11, queries the physical address of the target page through the second address translation component 14. When the second address translation component 14 triggers a page fault, the target page is swapped back into physical memory, and the target page is accessed according to its physical address. Figure 1a Taking the deployment of simulation software 16 in user space 18 of target device 10 as an example, but not limited to this. There is no limitation on the deployment location of simulation software 16 at the software layer. It can be implemented in user space 18, or it can be implemented in kernel space 19, or it can be distributed and implemented in both user space 18 and kernel space 19.

[0048] In this embodiment, for the scenario where the target peripheral 11 accesses physical memory 15 using DMA, two memory access paths are provided: a first path and a second path. Furthermore, combined with the memory management module's maintenance and management of the target page's existence status in physical memory, the memory management module controls the target peripheral to switch between the first and second paths, ultimately achieving support for memory page fault capabilities in DMA memory access operations and improving the utilization of physical memory resources. Specifically, the memory management module uses a page replacement algorithm to swap in and out of each memory page in physical memory. Therefore, it can determine whether each memory page has been swapped into physical memory. If not, the memory management module can also determine the storage location of that memory page on the external disk space. In other words, the memory management module can sense whether each memory page has been swapped in or out of physical memory. Based on this, upon detecting that the target page has been swapped out of physical memory, the target peripheral is switched from the first path to the second path, allowing it to access the target page via the second path. On the second path, the simulation software, acting on behalf of the target peripheral, queries the physical address of the target page using a second address translation component that supports memory page faults. Since the second address translation component (e.g., MMU) supports memory page faults, if the target page is swapped out of physical memory, a physical address corresponding to the virtual address of the target page cannot be provided, triggering a memory page fault. This causes the target page to be swapped back into physical memory, generating a physical address corresponding to the virtual address of the target page. This physical address is then returned to the simulation software, enabling it to access the target page based on its physical address. In this process, DMA access that does not support memory page faults is converted into a memory page fault access process using the second address translation component (e.g., MMU), enabling the target device's DMA access process to support memory page faults. Upon detecting that the target page has been swapped back into physical memory, the system controls the target peripheral to switch from the second path to the first path, so that the target peripheral can access the target page through the first path. Accessing the target page through the first path is faster and more efficient.

[0049] In this embodiment, for DMA access of the target peripheral, a first path that does not support memory page faults and a second path that supports memory page faults are provided. Combined with the ability to detect whether a memory page is in physical memory, flexible switching between the two paths is achieved when accessing a memory page. Specifically, when the accessed memory page is swapped into physical memory, the first path that does not support memory page faults is used to access the page, improving access efficiency. When the accessed memory page is not in physical memory, the system switches from the first path that does not support memory page faults to the second path that supports memory page faults. By triggering a memory page fault mechanism on the second path, the page is swapped back into physical memory, completing the page access. This allows the DMA access process of the target device to support memory page faults, and the memory pages accessed by DMA can be swapped into or out of physical memory as needed, improving the utilization of physical memory resources. Furthermore, even if a memory page fault occurs after switching from the first path to the second path, it will not cause the target device to crash.

[0050] In this embodiment, the page replacement algorithm used by the memory management module is not limited. For example, it can be, but is not limited to, the Least Recently Used (LRU) algorithm, the First-In-First-Out (FIFO) algorithm, or the hot-cold page replacement algorithm. The FIFO algorithm prioritizes the memory page that entered physical memory earliest. The LRU algorithm assumes that a memory page that has not been accessed in the past period will not be accessed again in the near future. Therefore, it selects the memory page that has not been used in the most recent period for replacement. The hot-cold page replacement algorithm divides memory pages into cold pages and hot pages based on their access frequency. Cold pages are memory pages with low access frequency (e.g., below a first set access rate threshold), and hot pages are memory pages with high access frequency (e.g., above a second set access rate threshold). Cold pages are given priority for replacement during page replacement. The first set access rate threshold is less than or equal to the second set access rate threshold. It should be understood that any algorithm capable of replacing memory pages from physical memory can be used as the page replacement algorithm in this embodiment.

[0051] Optionally, during the process of swapping memory pages out of physical memory using a page replacement algorithm, memory compression technology can be used to compress the memory pages to be swapped out of physical memory and store the compressed memory pages in persistent storage media, thereby improving the utilization of persistent storage media. Correspondingly, when it is necessary to swap the compressed memory pages into physical memory, the compressed memory pages can be decompressed first, and then the decompressed memory pages can be stored in physical memory. Of course, memory compression technology can also be omitted during the swapping out and swapping in process, thus saving the overhead of memory compression.

[0052] Furthermore, in the embodiments of this application, by designing the process of switching from a fast path (i.e., the first path) to a slow path (i.e., the second path) and the process of switching from a slow path (i.e., the second path) to a fast path (i.e., the first path), the timing correctness of the DMA operation is ensured during path switching.

[0053] The following is in conjunction with the appendix Figure 2a The process of switching from the first path to the second path is described.

[0054] Before switching from the first path to the second path, the target peripheral accesses the target page through the first path. For example... Figure 2a As shown in S21, the target peripheral sends an access request to the first address translation component. Figure 2a As shown in S22, the second address translation component receives the access request and queries the physical address of the target page based on the access request. Figure 2a As shown in S23, the first address translation component returns the queried physical address to the target peripheral. Further, as... Figure 2a As shown in S24, the target peripheral accesses the target page based on the physical address of the target page.

[0055] In this scenario, when the target page is swapped out of physical memory, the memory management module controls the target peripheral to switch from the first path to the second path. Optionally, during the process of controlling the target peripheral to switch from the first path to the second path, such as... Figure 2a As shown in S25, the target peripheral is notified to block the issuance of access requests for the target page, that is, to suspend the issuance of DMA access requests for the target page. Optionally, the memory management module maintains a blocking bitmap for the target page. The blocking bitmap is used to control whether the target peripheral blocks access requests for the target page through setting values. In this embodiment, the specific value of the setting value on the blocking bitmap is not limited. The setting value can also be any value, as long as it is globally consistent. The specific value of the setting value is not limited and can be selected according to requirements.

[0056] In this optional embodiment, the blocking bitmap corresponding to the target page is set to a first value, where the first value is an example of the aforementioned set value; optionally, the first value is 1, but not limited thereto. Further, as... Figure 2b As shown in S251, the blocking bitmap set to the first value is sent to the target peripheral to notify the target peripheral to block the issuance of access requests. Upon receiving the notification from the memory management module, the target peripheral blocks access requests to the target page according to the notification. Optionally, the target peripheral receives the blocking bitmap corresponding to the target page sent by the memory management module; if the blocking bitmap is set to the first value, access requests to the target page are blocked.

[0057] like Figure 2c As shown, assuming that access request A1 is sent before the target peripheral blocks access requests to the target page, then if access requests to the target page are blocked by the target peripheral, access requests sent after access request A1 will be blocked until the blocking of access requests to the target page is lifted.

[0058] To avoid errors in A1 access requests, if an access request to the target page is blocked by the target peripheral device, such as... Figure 2a As shown in S26, the target peripheral is notified to drain the incoming access requests and determine whether the draining process is complete. This draining process is performed while waiting for the access requests on the first path to finish, such as waiting for access request A1 to finish. The incoming access requests include read requests and / or write requests initiated against the target page.

[0059] In this embodiment, during the process of draining ongoing access requests and determining that the draining process is complete, such as... Figure 2b As shown in S261, a third value is written to the global empty register of the target peripheral to trigger the target peripheral to empty the pending read and / or write requests. The specific value of the third value is not limited; for example, it can be 1 or 0. It should be noted that the third value is unrelated to the first value, and subsequent second, fourth, and fifth values; "third" is only for distinction and does not imply any order or size limitation.

[0060] For the target peripheral, based on the notification from the memory management module, the processing access requests are emptied. Optionally, during the emptying process of processing access requests, a third value written by the memory management module is read from the global empty register of the target device, and based on the third value, the processing read requests and / or write requests are emptied. Further, after the emptying process for write requests is completed, the target peripheral sends a write operation carrying the third value to the simulation software. The write operation is order-preserving, meaning it is executed in the order it was written. If the simulation software receives a write operation carrying the third value, it can be determined that write requests preceding this write operation have been completed, i.e., the exclusion process for write requests is complete. Therefore, as... Figure 2b As shown in S262, when the memory management module receives a write operation carrying a third value, it can determine that the target peripheral has completed the emptying process for the write request. Figure 2c As shown, the end of the A1 access request indicates that the target peripheral has completed the emptying process for the write request.

[0061] In this embodiment, the method for determining whether the target peripheral has completed the write request emptying process is not limited. For example, the simulation software may be polled to see if it has received a write operation carrying a third value. If the simulation software has received a write operation carrying a third value, it is determined that the target peripheral has completed the write request emptying process. Alternatively, the target peripheral may be determined to have completed the write request emptying process upon receiving a notification message from the simulation software, where the notification message is actively sent by the simulation software after receiving the write operation carrying a third value.

[0062] The process of draining access requests in progress can also include draining read requests. During the draining of read requests, such as... Figure 2b As shown in S263, the read empty register of the target peripheral is read. Figure 2b As shown in S264, if the read result of the read empty register meets the set read empty condition, it is determined that the emptying process of the target peripheral for the read request has been completed. The read empty register is used to store the read request.

[0063] This embodiment does not limit the method for determining whether the target peripheral has completed the emptying process for the read request. For example, the tail pointer position of the read empty register is read, and the head pointer position of the read empty register is continuously read. In this case, the read empty register is an internal circular buffer, with the head and tail pointers pointing to the next read request to be processed and the most recently added read request, respectively. The head pointer position gradually approaches the tail pointer position as the read request is emptyed. When the head pointer position is greater than or equal to the tail pointer position, it is determined that the target peripheral has completed the emptying process for the read request. Based on this, the target peripheral can update the value of the target device's read empty register or the head pointer position according to the emptying process of the read request, so that the memory management module can determine whether the target peripheral has completed the emptying process for the read request based on the reading result of the read empty register.

[0064] For example, to determine whether the target peripheral has completed the emptying process for a read request, one can check if the read empty register is empty. If the read empty register is empty, it indicates that the target peripheral has completed the emptying process for the read request. In this case, the internal buffer of the read empty register does not need to be a circular buffer; a non-circular buffer is also acceptable. Simply clear the read request after processing each read request. When the read empty register is found to be empty, it means that the read request has been completely emptyed.

[0065] Once it is confirmed that the emptying process has been completed, the address translation page tables for the first and second paths are switched so that the address translation page tables for the second path take effect.

[0066] Optionally, during the address translation page table switching process, such as Figure 2a As shown in S27, a second address translation page table is generated for the second path. During the generation process, the virtual address of the target page in the virtual address space of the second path is calculated, and a mapping relationship between the virtual address and the physical address corresponding to the target page is established. This mapping relationship is used as a page table entry in the second address translation page table. In other words, the second address translation page table includes the mapping relationship between the second virtual address and the physical address of the target page in the virtual address space.

[0067] After generating the second address translation page table, the switching of the address translation page table also includes: Figure 2a As shown in S28, the address translation page table of the second address translation component is switched; and, as shown in S28, the address translation page table of the second address translation component is switched. Figure 2a As shown in S29, the address translation page table of the first address translation component is switched.

[0068] The second address translation component contains a first address translation page table. The second address translation component supports both hardware and software access. Hardware access, a new feature in this embodiment, involves simulated software, acting on behalf of the target peripheral, querying the currently active second address translation page table through the second address translation component, which supports memory page faults, to obtain the physical address of the target page. Software access targets application programs. The second address translation component can directly receive access requests from application programs and, based on these requests, query the first address translation page table on the second address translation component to obtain the physical address of the target page. The first address translation page table includes a mapping between the virtual addresses of the target page's virtual address space and the corresponding physical addresses of the target page.

[0069] It's important to note that the virtual addresses of the target page in the first and second address translation page tables are different, but they are both mapped to the same physical address—the physical address of the target page. These different virtual addresses distinguish which path the access request originated from.

[0070] Therefore, it can be seen that the second address translation component will have both a first address translation page table and a second address translation page table. In this embodiment, to make the second address translation page table effective, as follows: Figure 2b As shown in S281, the first address translation page table corresponding to the first path is set to unavailable.

[0071] Furthermore, such as Figure 2bAs shown in S291, the page table entry corresponding to the target page used by the first address translation component is invalidated. The address translation page table on the first address translation component is referred to as the third address translation page table. The third address translation page table includes at least the page table entry corresponding to the target page, and may also include page table entries corresponding to other memory pages. In this case, the page table entry of the target page is invalidated, but the page table entries corresponding to other memory pages can still be used for address translation of the first path. Invalidation of the page table entry corresponding to the target page includes: invalidation of the page table entry of the target page in physical memory and invalidation of the page table entry of the target page in the cache. Optionally, cache invalidation refers to the invalidation of the page table entry of the target page in the TLB (Translation Lookaside Buffer, page table cache). The TLB cache stores page table entries that are highly likely to be accessed.

[0072] Furthermore, after the address translation page table switch from the first path to the second path is completed, such as Figure 2a As shown in S210, the target peripheral is notified to switch from the first path to the second path. Optionally, when notifying the target peripheral to switch from the first path to the second path, the process includes: setting the path bitmap corresponding to the target page to a fourth value; and, as shown in S210. Figure 2b As shown in S2101, the path bitmap after being set to the fourth value is sent to the target peripheral to notify the target peripheral to switch from the first path to the second path. The value of the fourth value is not limited; for example, it can be 1 or 0.

[0073] After notifying the target peripheral to switch from the first path to the second path, such as Figure 2a As shown in S211, the target peripheral is notified to unblock the access request for the target page. Optionally, during this process, the blocking bitmap is set to a second value, which is another example of the settings described above. Optionally, if the first value is 1, the second value can be 0 to distinguish it from the first value, but is not limited to this. Figure 2b As shown in S2111, the blocking bitmap set to the second value is sent to the target peripheral to notify the target peripheral to release the blocking of access requests. For the target peripheral, a notification from the memory management module is received, and according to the notification, the issuance of access requests for the target page is blocked. Optionally, when blocking the issuance of access requests for the target page according to the notification from the memory management module, this includes: receiving the blocking bitmap corresponding to the target page sent by the memory management module; if the value of the blocking bitmap is the second value, the blocking of access requests for the target page is released. Thus, the target peripheral is switched from the first path to the second path.

[0074] like Figure 2cAs shown, when the target peripheral releases the block on the access request to the target page, it signifies that the target peripheral has switched from the first path to the second path. Therefore, an access request can be sent to the target page, such as an A2 access request. In this case, the target page will be accessed through the second path.

[0075] The above-described process of switching from the first path to the second path ensures the correct timing of the DMA during path switching.

[0076] The following describes the process of the target peripheral accessing the target page through the second path.

[0077] Under the control of the memory management module, after switching from the first path to the second path, if an access request for the target peripheral is received, such as... Figure 3 As shown in S31, an access request is sent to the simulation software on the second path. The simulation software, on behalf of the target peripheral, queries the physical address of the target page through the second address translation component. In an optional embodiment, the simulation software corresponds to target memory, which is a portion of the target device's physical memory. When sending an access request to the simulation software on the second path, the process includes: writing the access request to the target memory via a DMA write operation, wherein the access request includes the virtual address of the target page. Further, as... Figure 3 As shown in S32, the simulation software reads the virtual address of the target page from the access request. Further, as... Figure 3 As shown in S33, the simulation software sends the virtual address of the target page to the second address translation component. Upon receiving the virtual address of the target page, the second address translation component, as follows... Figure 3 As shown in S34, based on the second address translation page table, the physical address corresponding to the virtual address of the target page is queried. Since the target page is not in physical memory, ... Figure 3 As shown in S35, a page fault is triggered, and the target page is swapped back into physical memory. When the target page is swapped back into physical memory, as... Figure 3 As shown in S36, the simulation software continues to access the target page in physical memory. Upon completion of the access, as... Figure 3 As shown in S36, the simulation software returns the access result of the target page. Optionally, the simulation software returning the access result of the target page includes: the simulation software writing the access result of the target page into the target memory, so that the target peripheral device can read the access result of the target page from the target memory through a DMA read operation. Accessing the target page through the second path allows for the occurrence of target page faults without causing the target device to crash, thus improving the utilization of physical memory resources.

[0078] In this scenario, when the target page is swapped back into physical memory, the target peripheral can be controlled to switch from the second path to the first path, allowing the target peripheral to access the target page via the first path. Optionally, during the process of controlling the target peripheral to switch from the second path to the first path, such as... Figure 4a As shown in step S41, the target peripheral is notified to block the issuance of access requests for the target page. For an explanation of how to block access requests for the target page, please refer to the foregoing embodiments.

[0079] like Figure 4b As shown, assuming that the A3 access request is sent before the target peripheral blocks the access request to the target page, then if the access request to the target page is blocked by the target peripheral, access requests sent after the A3 access request will be blocked until the blocking of the access request to the target page is lifted.

[0080] Furthermore, the target peripheral is notified to drain the incoming access requests and to determine whether the draining process is complete. For details on how to perform the draining process and how to determine its completion, please refer to the aforementioned embodiments, which will not be repeated here. The draining process here is to wait for the access requests on the second path to finish, such as waiting for the A3 access request to finish.

[0081] Optionally, during the process of notifying the target peripheral to drain the incoming access requests and determining whether the draining process is complete, such as... Figure 4a As shown in S421, the global request register of the target peripheral is queried to obtain the number of access requests currently existing on the second path. Further, as... Figure 4a As shown in S422, determine whether the number of access requests obtained in this query is the same as the number of access requests obtained in the previous query; if the number of access requests obtained in this query is different from the number of access requests obtained in the previous query, then... Figure 4a As shown in S43, the target peripheral is notified to drain the access requests in progress and to determine whether the draining process is complete. Figure 4b As shown, the end of access request A3 indicates that the drain process for write requests on the target peripheral has been completed. If the number of access requests obtained in this query is the same as the number of access requests obtained in the previous query, the drain process and related operations to determine whether the drain process is complete can be omitted, thus saving the resources consumed by the drain process.

[0082] Furthermore, the address translation page tables for the first path and the second path are switched to make the address translation page table corresponding to the first path effective. In an optional embodiment, during the switching of the address translation page tables for the first path and the second path, such as Figure 4a As shown in S44, the page table entry corresponding to the target page used by the first address translation component is restored, and, as shown in S44... Figure 4aAs shown in step S45, the second address translation page table corresponding to the second path is set to unavailable. Similar to the previous embodiment, in this optional embodiment, the second address translation page table refers to the second address translation page table located on the second address translation component. Setting the second address translation page table on the second address translation component to unavailable enables the first address translation page table on the second address translation component to take effect.

[0083] After switching the address translation page tables for the first and second paths, such as Figure 4a As shown in step S46, the target peripheral is notified to switch from the second path to the first path. Optionally, the path bitmap corresponding to the target page is set to the fifth value, and the path bitmap with the fifth value is sent to the target peripheral to notify it to switch from the second path to the first path. The fifth value can be any value, as long as it is distinguishable from the fourth value. For example, if the fourth value is 0, the fifth value can be 1, or the fourth value is 1 and the fifth value is 0, but it is not limited to these. It should be noted that the fourth and fifth values ​​are different, and the fourth and fifth values ​​can be preset values ​​(referred to as preset values).

[0084] After notifying the target peripheral to switch from the second path to the first path, such as Figure 4a As shown in step S47, the target peripheral is notified to unblock the access request to the target page. Optionally, when notifying the target peripheral to unblock the access request to the target page, the process includes: setting the blocking bitmap to a second value, and sending the blocked bitmap with the second value to the target peripheral to notify the target peripheral to unblock the access request. This completes the switch of the target peripheral from the second path to the first path.

[0085] like Figure 4b As shown, when the target peripheral releases the block on the access request to the target page, it signifies that the target peripheral has switched from the second path to the first path. Therefore, an access request can be sent to the target page, such as an A4 access request. In this case, the target page will be accessed through the first path.

[0086] The process of switching from the second path to the first path ensures the correct timing of DMA during path switching. Furthermore, after switching to the first path, accessing the target page through the first path, without going through the processor, provides improved memory page access efficiency.

[0087] Figure 5 This is a flowchart illustrating yet another exemplary embodiment of a memory access control method provided in this application. The method is used to control a target peripheral device on a target device to access a target page, where the target page is any memory page that the target peripheral device needs to access, such as... Figure 5 As shown, the method includes:

[0088] S501: When the target page is swapped out of physical memory, control the target peripheral to switch from the first path to the second path so that the target peripheral can access the target page through the second path;

[0089] S502: When the target page is swapped back into physical memory, control the target peripheral to switch from the second path to the first path, so that the target peripheral can access the target page through the first path; wherein, the first path is the memory access path of the target peripheral by querying the physical address of the target page through a first address translation component that does not support memory page faults, and the first address translation component is used to perform address translation between the target peripheral and physical memory; the second path is the memory access path of the target page by the simulation software on behalf of the target peripheral by querying the physical address of the target page through a second address translation component that supports memory page faults; the second address translation component is used to perform address translation between the processor of the target device and physical memory.

[0090] In an optional embodiment, when controlling the target peripheral to switch from the first path to the second path, the process includes: notifying the target peripheral to block the issuance of access requests for the target page; notifying the target peripheral to perform a drain process on the processing access requests and determining whether the drain process is complete; if the drain process is determined to be complete, switching the address translation page tables for the first path and the second path so that the address translation page table corresponding to the second path becomes effective; notifying the target peripheral to switch from the first path to the second path; and after switching from the first path to the second path, notifying the target peripheral to release the blocking of access requests for the target page.

[0091] In an optional embodiment, when notifying the target peripheral device to block the issuance of an access request, the method includes: setting the blocking bitmap corresponding to the target page to a first value, and sending the blocking bitmap after setting the first value to the target peripheral device to notify the target peripheral device to block the issuance of the access request; correspondingly, notifying the target peripheral device to unblock the access request includes: setting the blocking bitmap to a second value, and sending the blocking bitmap after setting the second value to the target peripheral device to notify the target peripheral device to unblock the access request; wherein the first value and the second value are different.

[0092] In an optional embodiment, the access requests in the process include read requests and / or write requests initiated against the target page. When notifying the target peripheral to perform a flushing process for the access requests in the process and determining whether the flushing process is complete, the process includes: writing a third value into the global flush register of the target peripheral to trigger the target peripheral to perform a flushing process for the read requests and / or write requests in the process, and sending a write operation carrying the third value to the simulation software after completing the flushing process for the write requests in the process; then, if the simulation software determines that it has received a write operation carrying the third value, it determines that the flushing process for the write requests by the target peripheral has been completed; and / or, reading the read flush register of the target peripheral, and if the reading result of the read flush register meets the set read flushing conditions, it determines that the flushing process for the read requests by the target peripheral has been completed, wherein the read flush register is used to store read requests.

[0093] In one optional embodiment, when it is determined that the simulation software has received a write operation carrying the third value, and when it is determined that the target peripheral has completed the emptying process for the write request, the method includes: polling the simulation software to see if it has received a write operation carrying the third value; if it is found that the simulation software has received the write operation carrying the third value, it is determined that the target peripheral has completed the emptying process for the write request; or, when a notification message is received from the simulation software, it is determined that the target peripheral has completed the emptying process for the write request, wherein the notification message is actively sent by the simulation software after receiving the write operation carrying the third value.

[0094] In one optional embodiment, when reading the read empty register of the target peripheral, and if the reading result of the read empty register meets the set read empty condition, it is determined that the emptying process of the target peripheral for the read request has been completed, the method includes: reading the tail pointer position of the read empty register, and continuously reading the head pointer position of the read empty register, wherein the head pointer position gradually approaches the tail pointer position as the read request is emptyed, and if the head pointer position is greater than or equal to the tail pointer position, it is determined that the emptying process of the target peripheral for the read request has been completed; or, reading whether the read empty register is empty, and if the read empty register is found, it is determined that the emptying process of the target peripheral for the read request has been completed.

[0095] In an optional embodiment, when switching address translation page tables for the first path and the second path, the method includes: generating a second address translation page table for the second path, the second address translation page table including the mapping relationship between the second client virtual address and the physical address of the virtual address space to which the target page belongs; setting the first address translation page table corresponding to the first path to be unavailable, the first address translation page table including the mapping relationship between the first client virtual address and the physical address of the virtual address space to which the target page belongs; and setting the page table entry corresponding to the target page used by the first address translation component to be invalid.

[0096] In an optional embodiment, when notifying the target peripheral to switch from the first path to the second path, the method includes: setting the path bitmap corresponding to the target page to a fourth value, and sending the path bitmap after being set to the fourth value to the target peripheral to notify the target peripheral to switch from the first path to the second path; correspondingly, when notifying the target peripheral to switch from the second path to the first path, the method includes: setting the path bitmap corresponding to the target page to a fifth value, and sending the path bitmap after being set to the fifth value to the target peripheral to notify the target peripheral to switch from the second path to the first path; wherein the fourth value and the fifth value are different.

[0097] In an optional embodiment, when controlling the target peripheral to switch from the second path to the first path, the process includes: notifying the target peripheral to block the issuance of access requests for the target page; notifying the target peripheral to perform a drain process on the processing access requests and determining that the drain process is complete; if the drain process is determined to be complete, switching the address translation page tables for the first path and the second path so that the address translation page table corresponding to the first path takes effect; notifying the target peripheral to switch from the second path to the first path; and after switching from the second path to the first path, notifying the target peripheral to release the blocking of access requests for the target page.

[0098] In an optional embodiment, when notifying the target peripheral to drain the access requests in process and determining that the draining process is complete, the process includes: querying the global request register of the target peripheral to obtain the number of access requests currently existing on the second path; if the number of access requests obtained in this query is different from the number of access requests obtained in the previous query, then notifying the target peripheral to drain the access requests in process and determining that the draining process is complete.

[0099] Figure 6 This is a flowchart illustrating a memory access method as provided in another exemplary embodiment of this application. Figure 6 As shown, the method includes:

[0100] S601: Under the control of the memory management module, when the target page that the target peripheral needs to access is swapped out of physical memory, the system switches from the first path to the second path and accesses the target page through the second path.

[0101] S601: Under the control of the memory management module, when the target page is swapped back into physical memory, the system switches from the second path to the first path and accesses the target page through the first path. The first path is where the target peripheral queries the physical address of the target page using a first address translation component that does not support memory page faults to access the target page's memory access path. The first address translation component performs address translation between the target peripheral and physical memory. The second path is where the simulation software, on behalf of the target peripheral, queries the physical address of the target page using a second address translation component that supports memory page faults to access the target page's memory access path. The second address translation component performs address translation between the target device's processor and physical memory.

[0102] In an optional embodiment, under the control of the memory management module, when the target page that the target peripheral needs to access is swapped out of physical memory, the switching from the first path to the second path includes: blocking the issuance of access requests for the target page according to a notification from the memory management module; performing a drain process on the processing access requests according to a notification from the memory management module; invalidating the page table entry corresponding to the target page used by the first address translation component when the drain process is determined to be complete; switching from the first path to the second path according to a notification from the memory management module; and releasing the blocking of access requests for the target page according to a notification from the memory management module after switching from the first path to the second path.

[0103] In an optional embodiment, when blocking the issuance of access requests to the target page according to the notification from the memory management module, the method includes: receiving a blocking bitmap corresponding to the target page sent by the memory management module; if the value of the blocking bitmap is a first value, blocking the issuance of access requests to the target page; correspondingly, when releasing the blocking of access requests to the target page according to the notification from the memory management module, the method includes: receiving a blocking bitmap corresponding to the target page sent by the memory management module; if the value of the blocking bitmap is a second value, releasing the blocking of access requests to the target page; wherein the first value and the second value are different.

[0104] In an optional embodiment, if the access requests in the process include read requests and / or write requests initiated against the target page, then when performing drain processing on the access requests in the process according to the notification from the memory management module, the process includes: reading a third value written by the memory management module from the global drain register of the target device; performing drain processing on the read requests and / or write requests in the process according to the third value; if the drain processing for the write requests is completed, sending a write operation carrying the third value to the simulation software so that the memory management module can determine that the drain processing for the write requests of the target peripheral has been completed; and / or, updating the value or head pointer position of the read drain register of the target device according to the drain processing of the read requests in the process, so that the memory management module can determine whether the drain processing for the read requests of the target peripheral has been completed based on the reading result of the read drain register, wherein the read drain register is used to store read requests.

[0105] In an optional embodiment, when accessing the target page via the second path, the process includes: sending an access request for the target page to the simulation software on the second path, so that the simulation software, on behalf of the target peripheral, queries the physical address of the target page through the second address translation component; when the second address translation component triggers a memory page fault, swapping the target page back into physical memory; and accessing the target page according to its physical address; and receiving the access result of the target page returned by the simulation software.

[0106] In an optional embodiment, the simulation software corresponds to a target memory, which is a portion of the physical memory of the target device. When sending an access request to the simulation software on the second path, the process includes: writing the access request to the target memory via a DMA write operation so that the simulation software can read the access request, where the access request includes the virtual address of the target page; and receiving the access result of the target page returned by the simulation software, which includes: reading the access result of the target page from the target memory via a DMA read operation, where the access result of the target page was written to the target memory by the simulation software.

[0107] In an optional embodiment, when the target page is swapped back into physical memory under the control of the memory management module, the process of switching from the second path to the first path includes: blocking the issuance of access requests for the target page according to a notification from the memory management module; draining the processing access requests according to a notification from the memory management module; after determining that the draining process is complete, making the page table entry corresponding to the target page used by the first address translation component valid; switching from the second path to the first path according to a notification from the memory management module; and after switching from the second path to the first path, releasing the blocking of access requests for the target page according to a notification from the memory management module.

[0108] The detailed implementation methods and beneficial effects of each step in this embodiment have been described in detail in the foregoing embodiments, and will not be elaborated here.

[0109] It should be noted that the execution subject of each step in the method provided in the above embodiments can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 601 to 602 can be device A; or the execution subject of step 601 can be device A, and the execution subject of step 602 can be device B; and so on.

[0110] Furthermore, in some of the processes described in the above embodiments and accompanying drawings, multiple operations appear in a specific order. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or they may be executed in parallel. The operation numbers, such as 601, 602, etc., are merely used to distinguish different operations and do not represent any execution order. Additionally, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first" and "second" in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.

[0111] Figure 7 This is a schematic diagram of the structure of a peripheral device provided as another exemplary embodiment of this application. For example... Figure 7 As shown, the peripheral device can be implemented as the target peripheral in the aforementioned embodiments, specifically including: memory 74 and processor 75.

[0112] Memory 74 is used to store computer programs and can be configured to store various other data to support operation on the target peripheral. Examples of this data include instructions for any application or method used to operate on the target peripheral, contact data, phone book data, messages, pictures, videos, etc.

[0113] The memory 74 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0114] Processor 75, coupled to memory 74, is configured to execute a computer program in memory 74 for: switching from a first path to a second path, and accessing the target page via the second path, under the control of a memory management module, when a target page to be accessed by the target peripheral is swapped out of physical memory; and switching from the second path to the first path, and accessing the target page via the first path, under the control of the memory management module; wherein, the first path is a memory access path in which the target peripheral queries the physical address of the target page to access the target page through a first address translation component that does not support memory page faults, the first address translation component being used to perform address translation between the target peripheral and physical memory; the second path is a memory access path in which emulation software, on behalf of the target peripheral, queries the physical address of the target page to access the target page through a second address translation component that supports memory page faults; the second address translation component being used to perform address translation between the processor and physical memory of the target device.

[0115] In an optional embodiment, when the processor 75 switches from the first path to the second path under the control of the memory management module, and the target page that the target peripheral needs to access is swapped out of physical memory, the processor 75 specifically performs the following actions: blocking the issuance of access requests for the target page according to a notification from the memory management module; performing a drain process on the processing access requests according to a notification from the memory management module; invalidating the page table entry corresponding to the target page used by the first address translation component when the drain process is determined to be complete; switching from the first path to the second path according to a notification from the memory management module; and releasing the blocking of access requests for the target page according to a notification from the memory management module after switching from the first path to the second path.

[0116] In an optional embodiment, when the processor 75 blocks the issuance of access requests for the target page according to the notification from the memory management module, it is specifically configured to: receive a blocking bitmap corresponding to the target page sent by the memory management module; if the value of the blocking bitmap is a first value, block the issuance of access requests for the target page; correspondingly, when the processor 75 releases the blocking of access requests for the target page according to the notification from the memory management module, it includes: receiving a blocking bitmap corresponding to the target page sent by the memory management module; if the value of the blocking bitmap is a second value, release the blocking of access requests for the target page; wherein the first value and the second value are different.

[0117] In an optional embodiment, the access requests in processing include read requests and / or write requests initiated against the target page. The target peripheral includes a global empty register 77 and a read empty register 711. The global empty register 77 is used to trigger the target peripheral to empty the read requests and / or write requests in processing; the read empty register 711 is used to store read requests. When the processor 75 emptys the access requests in processing according to the notification from the memory management module, it is specifically used to: read the data written by the memory management module from the global empty register of the target device. The third value is used to perform emptying processing on the read requests and / or write requests in progress; if the emptying processing for the write requests is completed, a write operation carrying the third value is sent to the simulation software so that the memory management module can determine that the emptying processing for the write requests of the target peripheral has been completed; and / or, based on the emptying processing of the read requests in progress, the value of the read emptying register or the head pointer position of the target device is updated so that the memory management module can determine whether the emptying processing for the read requests of the target peripheral has been completed based on the reading result of the read emptying register.

[0118] In an optional embodiment, when the processor 75 accesses the target page through the second path, it is specifically configured to: send an access request for the target page to the simulation software on the second path, so that the simulation software, on behalf of the target peripheral, queries the physical address of the target page through the second address translation component; when the second address translation component triggers a memory page fault, swap the target page back into physical memory; and access the target page according to the physical address of the target page; and receive the access result of the target page returned by the simulation software.

[0119] In an optional embodiment, the simulation software corresponds to a target memory, which is a portion of the physical memory of the target device. When the processor 75 sends an access request to the simulation software on the second path, it is specifically configured to: write the access request to the target memory through a DMA write operation so that the simulation software can read the access request, wherein the access request includes the virtual address of the target page; and receive the access result of the target page returned by the simulation software, including: reading the access result of the target page from the target memory through a DMA read operation, wherein the access result of the target page was written to the target memory by the simulation software.

[0120] In an optional embodiment, when the processor 75 switches from the second path to the first path under the control of the memory management module after the target page has been swapped back into physical memory, it specifically performs the following: according to a notification from the memory management module, it blocks the issuance of access requests for the target page; according to a notification from the memory management module, it performs a draining process on the processing access requests; when it is determined that the draining process is complete, it sets the page table entry corresponding to the target page used by the first address translation component to valid; according to a notification from the memory management module, it switches from the second path to the first path; and after switching from the second path to the first path, according to a notification from the memory management module, it releases the blocking of access requests for the target page.

[0121] In an optional embodiment, the target peripheral includes a global request register 710, which stores the number of access requests currently existing on the second path. According to the notification from the memory management module, the processing of access requests is cleared, including: responding to a query operation from the memory management module, querying the global request register of the target peripheral to obtain the number of access requests currently existing on the second path, so that if the number of access requests obtained in this query differs from the number obtained in the previous query, the memory management module notifies the target peripheral to clear the processing of access requests and confirms that the clearing process is complete.

[0122] Furthermore, such as Figure 7 As shown, the target peripheral also includes: communication component 76, display, power supply component 78, audio component 79 and other components. Figure 7 The diagram only shows a portion of the components and does not imply that the target peripheral only includes... Figure 7 The components shown. Additionally... Figure 7The components within the dashed box are optional, not mandatory, and their specific requirements depend on the product form of the target peripheral. In this embodiment, the target peripheral can be a terminal device such as a desktop computer, laptop computer, smartphone, or IoT device, or a server-side device such as a conventional server, cloud server, or server array. If the target peripheral in this embodiment is a terminal device such as a desktop computer, laptop computer, or smartphone, it may include... Figure 7 The components within the dashed box; if the target peripheral device in this embodiment is implemented as a server-side device such as a conventional server, cloud server, or server array, it may be omitted. Figure 7 The component within the dashed box.

[0123] Accordingly, embodiments of this application also provide a target device, including: a target peripheral and computing resources, wherein a kernel management module and simulation software run on the computing resources; wherein the kernel management module is used to execute Figure 5 The steps in the method shown; the target peripheral is used for Figure 6 The steps in the method shown involve the kernel management module and the target peripheral working together to enable DMA memory access operations to support memory page fault capability.

[0124] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above method embodiments.

[0125] Accordingly, this application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps in the above method embodiments.

[0126] The aforementioned memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0127] The aforementioned communication components are configured to facilitate wired or wireless communication between the device containing the communication components and other devices. The device containing the communication components can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G / LTE, 5G, or combinations thereof. In one exemplary embodiment, the communication components receive broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication components also include a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra Wide Band (UWB), Bluetooth (BT), and other technologies.

[0128] The aforementioned display includes a screen, which may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen can be implemented as a touchscreen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touches, swipes, and gestures on the Touch Panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation.

[0129] The aforementioned power supply components provide power to various components within the device in which they reside. These power supply components may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to the device in which they reside.

[0130] The aforementioned audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC) configured to receive external audio signals when the device containing the audio component is in an operating mode, such as call mode, recording mode, or voice recognition mode. The received audio signals can be further stored in memory or transmitted via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0131] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) containing computer-usable program code.

[0132] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0133] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0134] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0135] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, CPU), input / output interfaces, network interfaces, and memory.

[0136] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0137] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, Digital Video Disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0138] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0139] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A memory access control method, characterized in that, The method for controlling a target peripheral device on a target device to access a target page, wherein the target page is any memory page that the target peripheral device needs to access, includes: When the target page is swapped out of physical memory, the target peripheral is controlled to switch from the first path to the second path, so that the target peripheral can access the target page through the second path. When the target page is swapped back into physical memory, the target peripheral is controlled to switch from the second path to the first path, so that the target peripheral can access the target page through the first path. The first path is the memory access path where the target peripheral queries the physical address of the target page through a first address translation component that does not support memory page faults in order to access the memory of the target page. The first address translation component is used to perform address translation between the target peripheral and physical memory. The second path is a memory access path in which the simulation software, on behalf of the target peripheral, queries the physical address of the target page through a second address translation component that supports memory page faults; the second address translation component is used to perform address translation between the processor and physical memory of the target device.

2. The method according to claim 1, characterized in that, Controlling the target peripheral device to switch from the first path to the second path includes: The target peripheral device is notified to block the issuance of access requests for the target page; The target peripheral is notified to drain the access requests in progress and to determine whether the draining process is complete. Once the emptying process is confirmed to be complete, the address translation page tables for the first path and the second path are switched so that the address translation page table corresponding to the second path takes effect. The target peripheral device is notified to switch from the first path to the second path; After switching from the first path to the second path, the target peripheral is notified to unblock the access request for the target page.

3. The method according to claim 2, characterized in that, Notification of the blocking access request from the target peripheral device includes: Set the blocking bitmap corresponding to the target page to the first value, and send the blocking bitmap after setting the first value to the target peripheral device to notify the target peripheral device to block the issuance of the access request; Accordingly, the target peripheral is notified to unblock the access request, including: Set the blocking bitmap to the second value, and send the blocked bitmap after setting the second value to the target peripheral device to notify the target peripheral device to release the blocking of the access request; The first value and the second value are different.

4. The method according to claim 2, characterized in that, The access requests in progress include read requests and / or write requests initiated against the target page. The target peripheral is notified to drain the access requests in progress, and the process of draining the requests is determined to be complete, including: Write a third value into the global empty register of the target peripheral to trigger the target peripheral to empty the read and / or write requests in progress, and after completing the emptying of the write requests in progress, send a write operation carrying the third value to the simulation software. If the simulation software receives a write operation carrying the third value, it determines that the target peripheral has completed the emptying process for the write request; and / or, it reads the read emptying register of the target peripheral, and if the reading result of the read emptying register meets the set read emptying conditions, it determines that the target peripheral has completed the emptying process for the read request, wherein the read emptying register is used to store the read request.

5. The method according to claim 4, characterized in that, If the simulation software receives a write operation carrying the third value, it is determined that the target peripheral has completed the emptying process for the write request, including: The simulation software is polled to see if it has received a write operation carrying the third value. When the simulation software is polled to receive a write operation carrying the third value, it is determined that the target peripheral has completed the emptying process for the write request. or, Upon receiving a notification message from the simulation software, it is determined that the target peripheral has completed the emptying process for the write request. The notification message is actively sent by the simulation software after receiving a write operation carrying the third value.

6. The method according to claim 5, characterized in that, Read the read-empty register of the target peripheral. If the read result of the read-empty register meets the set read-empty condition, determine that the emptying process of the target peripheral for the read request has been completed, including: The tail pointer position of the read empty register is read, and the head pointer position of the read empty register is continuously read. The head pointer position gradually approaches the tail pointer position as the read request is emptyed. When the head pointer position is greater than or equal to the tail pointer position, it is determined that the target peripheral has completed the emptying process for the read request. or, Check if the read empty register is empty. If the read empty register is empty, it is determined that the target peripheral has completed the emptying process for the read request.

7. The method according to claim 2, characterized in that, Switching the address translation page table for the first path and the second path includes: A second address translation page table is generated for the second path. The second address translation page table includes the mapping relationship between the second client virtual address and the physical address of the virtual address space to which the target page belongs. Set the first address translation page table corresponding to the first path to unavailable. The first address translation page table includes the mapping relationship between the first client virtual address and the physical address of the virtual address space to which the target page belongs. Invalidate the page table entry corresponding to the target page used by the first address translation component.

8. The method according to claim 2, characterized in that, Notifying the target peripheral to switch from the first path to the second path includes: Set the path bitmap corresponding to the target page to the fourth value, and send the path bitmap after setting to the fourth value to the target peripheral device to notify the target peripheral device to switch from the first path to the second path; Accordingly, notifying the target peripheral to switch from the second path to the first path includes: Set the path bitmap corresponding to the target page to the fifth value, and send the path bitmap after setting to the fifth value to the target peripheral device to notify the target peripheral device to switch from the second path to the first path; The fourth value and the fifth value are different.

9. The method according to any one of claims 1-7, characterized in that, Controlling the target peripheral device to switch from the second path to the first path includes: The target peripheral device is notified to block the issuance of access requests for the target page; The target peripheral is notified to drain the access requests in progress and to determine whether the draining process is complete. Once the emptying process is confirmed to be complete, the address translation page tables for the first path and the second path are switched so that the address translation page table corresponding to the first path takes effect. The target peripheral is notified to switch from the second path to the first path; After switching from the second path to the first path, the target peripheral is notified to unblock the access request for the target page.

10. The method according to claim 9, characterized in that, The target peripheral is notified to drain the incoming access requests and to confirm that the draining process is complete, including: Query the global request register of the target peripheral to obtain the number of access requests currently existing on the second path; If the number of access requests obtained in this query is different from the number of access requests obtained in the previous query, then the target peripheral is notified to drain the access requests in process and confirm that the draining process is complete.

11. A memory access method, characterized in that, The method, applied to a target peripheral on a target device, includes: Under the control of the memory management module, when the target page that the target peripheral needs to access is swapped out of physical memory, the system switches from the first path to the second path and accesses the target page through the second path. Under the control of the memory management module, when the target page is swapped back into physical memory, the system switches from the second path to the first path and accesses the target page through the first path. The first path is the memory access path where the target peripheral queries the physical address of the target page through a first address translation component that does not support memory page faults in order to access the memory of the target page. The first address translation component is used to perform address translation between the target peripheral and physical memory. The second path is a memory access path in which the simulation software, on behalf of the target peripheral, queries the physical address of the target page through a second address translation component that supports memory page faults; the second address translation component is used to perform address translation between the processor and physical memory of the target device.

12. The method according to claim 11, characterized in that, Under the control of the memory management module, when the target page that the target peripheral needs to access is swapped out of physical memory, the system switches from the first path to the second path, including: Based on the notification from the memory management module, the issuance of access requests for the target page is blocked; Based on the notification from the memory management module, the access requests in progress are drained. Once the emptying process is confirmed to be complete, the page table entry corresponding to the target page used by the first address translation component is set to invalid. Based on the notification from the memory management module, switch from the first path to the second path; After switching from the first path to the second path, the blocking of access requests to the target page is lifted according to the notification from the memory management module.

13. The method according to claim 12, characterized in that, Based on the notification from the memory management module, blocking the issuance of access requests for the target page includes: Receive the blocking bitmap corresponding to the target page sent by the memory management module; if the value of the blocking bitmap is the first value, block the issuance of access requests for the target page; Accordingly, based on the notification from the memory management module, the blocking of access requests to the target page is lifted, including: Receive the blocking bitmap corresponding to the target page sent by the memory management module; if the value of the blocking bitmap is the second value, release the blocking of the access request for the target page; The first value and the second value are different.

14. The method according to claim 12, characterized in that, If the access requests in progress include read requests and / or write requests to the target page, then according to the notification from the memory management module, the access requests in progress will be cleared, including: Read the third value written by the memory management module from the global empty register of the target device, and empty the read and / or write requests in progress according to the third value; If the write request purging process is completed, a write operation carrying the third value is sent to the simulation software so that the memory management module can determine that the target peripheral has completed the write request purging process; and / or, based on the purging process of the read request in progress, the value of the target device's read purging register or the head pointer position is updated so that the memory management module can determine whether the target peripheral has completed the read request purging process based on the reading result of the read purging register, wherein the read purging register is used to store read requests.

15. The method according to claim 11, characterized in that, Accessing the target page via the second path includes: Send an access request for the target page to the simulation software on the second path, so that the simulation software can query the physical address of the target page through the second address translation component on behalf of the target peripheral. When the second address translation component triggers a memory page fault, the target page is swapped back into physical memory and the target page is accessed according to the physical address of the target page. Receive the access results of the target page returned by the simulation software.

16. The method according to claim 15, characterized in that, The simulation software corresponds to target memory, which is a portion of the physical memory of the target device. Therefore, an access request is sent to the simulation software on the second path, including: The access request is written to the target memory via a DMA write operation so that the simulation software can read the access request, which includes the virtual address of the target page. Receiving the access result of the target page returned by the simulation software includes: reading the access result of the target page from the target memory through a DMA read operation, wherein the access result of the target page is written to the target memory by the simulation software.

17. The method according to any one of claims 11-16, characterized in that, Under the control of the memory management module, when the target page is swapped back into physical memory, the process switches from the second path to the first path, including: Based on the notification from the memory management module, the issuance of access requests for the target page is blocked; Based on the notification from the memory management module, the access requests in progress are drained. Once the emptying process is confirmed to be complete, the page table entry corresponding to the target page used by the first address translation component is set to valid; Based on the notification from the memory management module, switch from the second path to the first path; After switching from the second path to the first path, the blocking of access requests to the target page is lifted according to the notification from the memory management module.

18. A target device, characterized in that, include: The target peripheral and computing resources, wherein a kernel management module and simulation software are running on the computing resources; wherein the kernel management module is used to execute the steps of the method according to any one of claims 1-10; and the target peripheral is used to execute the steps of the method according to any one of claims 11-17.

19. A peripheral device, characterized in that, include: A memory and a processor, the memory for storing a computer program, the processor coupled to the memory for executing the computer program to implement the steps of the method of any one of claims 11-17.

20. A computer-readable storage medium, characterized in that, When the computer program is executed by a processor, it causes the processor to perform the steps of the method according to any one of claims 1-10 and 11-17.

21. A computer program product, characterized in that, Includes a computer program / instruction that, when executed by a processor, performs the steps of the method according to any one of claims 1-10 and 11-17.

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