Command scheduling module, front-end subsystem, and compute chip

Abstract

The application provides a command scheduling module, a front-end subsystem and a computing chip, and relates to the technical field of circuits.The command scheduling module comprises a storage unit, a command receiving unit and a command processing unit;the command receiving unit is connected with the storage unit;the storage unit at least comprises a first command buffer unit and a second command buffer unit;the reading priority of the first command buffer unit is higher than that of the second command buffer unit;the first command buffer unit is used for buffering control commands;the second command buffer unit is used for buffering low-priority commands;the low-priority commands comprise ordinary task commands;the command receiving unit is used for reading commands from the storage unit and analyzing the commands to obtain analysis results;the command processing unit is connected with the command receiving unit and is used for creating or processing tasks according to the analysis results.The reading priority of the first command buffer unit is higher than that of the second command buffer unit, so that the control commands can be preferentially executed, and invalid task execution is reduced.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more specifically, to a command scheduling module, a front-end subsystem, and a computing chip. Background Technology

[0002] With the development of technology, command scheduling modules have been widely used and have become a research hotspot.

[0003] In related technologies, the command scheduling module of a chip has a command buffer, but the buffer capacity is generally small. If the command buffer is full, no new commands can be stored. During the execution of a task, the chip may encounter configuration errors or other issues. In such cases, continuing to execute the task is meaningless, and the user will want to abort or cancel the corresponding task.

[0004] However, the limited capacity of the command buffer in related technologies means that corresponding abort / cancel commands can only be stored and executed after the command buffer has sufficient space, which can easily lead to invalid task execution. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a command scheduling module, a front-end subsystem, and a computing chip, so as to solve the aforementioned technical problems in the related technologies.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a command scheduling module, including: a storage unit, a command receiving unit, and a command processing unit; The command receiving unit is connected to the storage unit. The storage unit includes at least a first command buffer unit and a second command buffer unit. The first command buffer unit has a higher read priority than the second command buffer unit. The first command buffer unit is used to buffer control commands, and the second command buffer unit is used to buffer low-priority commands, including ordinary task commands. The command receiving unit is used to read commands from the storage unit, parse the commands, and obtain the parsing results; The command processing unit is connected to the command receiving unit and is used to create or process tasks based on the parsing results.

[0007] Optionally, the command scheduling module further includes: an interface unit and an access conversion unit; The command receiving unit is connected to the interface unit, and the interface unit is connected to the storage unit through the access conversion unit; The command receiving unit sends an access instruction to the access conversion unit through the interface unit. The access conversion unit is used to convert the access instruction into an access instruction corresponding to any one of the buffer units and read the corresponding cached command information from any one of the buffer units.

[0008] Optionally, the storage unit further includes: a configuration information storage unit; the configuration information storage unit is used to store the computing configuration information required when executing the computing task, the computing configuration information including the system state entry address and the system state packet address; The command processing unit is used to read the computing configuration information from the configuration information storage area of ​​the storage unit when processing the computing task.

[0009] Optionally, the command scheduling module further includes: a register space unit; The register space unit is connected to the command receiving unit and the command processing unit respectively. The register space unit is used to store the configuration information of the command scheduling module so that the command receiving unit and the command processing unit can obtain the configuration information of the command scheduling module. The register space unit is also used to generate interrupt information based on the task processing status in the command scheduling unit, so that the processor receives the interrupt information.

[0010] Secondly, embodiments of this application also provide a front-end subsystem, including a subsystem on-chip network and a command scheduling module as described in any of the first aspects above; The command scheduling module is connected to the subsystem on-chip network, and the subsystem on-chip network is connected to the bus interface unit, for obtaining the first command packet sequentially through the subsystem on-chip network and the bus interface unit.

[0011] Optionally, the front-end subsystem further includes: a command processor; The command processor is used to obtain a second command packet from the main central processing unit through the subsystem on-chip network and the bus interface unit; The command processor is connected to the command scheduling module and is used to parse the second command packet to obtain a parsed command packet, and send the parsed command packet to the command scheduling module. The parsed command packet has a specified length.

[0012] Optionally, the front-end subsystem further includes: an interrupt receiving unit; The interrupt receiving unit is connected to the command scheduling module and the command processor respectively, and is used to obtain an interrupt signal through the bus interface unit and send the interrupt signal to at least one of the command scheduling module and the command processor so that the command scheduling module and the command processor process the interrupt signal.

[0013] Optionally, the storage unit in the command scheduling module further includes: an interrupt storage unit. The command processor is also used to read message interrupt vectors from the message interrupt vector table area in the interrupt storage unit and generate an interrupt signal to send to the bus interface unit.

[0014] Thirdly, embodiments of this application also provide a computing chip, including: a bus interface unit, a first on-chip network, and a front-end subsystem as described in any of the second aspects above; The front-end subsystem is connected to the bus interface unit through the first chip on-chip network. The command scheduling module in the front-end subsystem obtains command packets from the main central processing unit through the subsystem on-chip network, the first chip on-chip network, and the bus interface unit in the front-end subsystem.

[0015] Optionally, the computing chip further includes: a computing unit; The computing unit executes the computing tasks generated by the command processing unit in the command scheduling module based on SIMT (Single Instruction Multithreading) to obtain computing results. The computing unit is connected to the subsystem on-chip network in the front-end subsystem to send the computing results to the bus interface unit through the subsystem on-chip network.

[0016] The beneficial effects of this application are as follows: This application provides a command scheduling module, including a storage unit, a command receiving unit, and a command processing unit. The command receiving unit is connected to the storage unit, which includes at least a first command buffer unit and a second command buffer unit. The first command buffer unit has a higher read priority than the second command buffer unit. The first command buffer unit is used to buffer control commands, and the second command buffer unit is used to buffer low-priority commands, including ordinary task commands. The command receiving unit reads commands from the storage unit and parses the commands to obtain parsing results. The command processing unit is connected to the command receiving unit and is used to create or process tasks based on the parsing results. By using a first command buffer unit to buffer control commands and a second command buffer unit to buffer ordinary task commands, partitioned storage for different commands is achieved. Even if the storage space of the second command buffer unit is completely occupied, it does not affect the storage of control commands in the first command buffer unit. Moreover, the first command buffer unit has a higher read priority than the second command buffer unit, thus prioritizing the execution of control commands and reducing the occurrence of invalid task execution. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the structure of a command scheduling module provided in an embodiment of this application. Figure 1 ; Figure 2 A schematic diagram of the structure of a command scheduling module provided in an embodiment of this application. Figure 2 ; Figure 3 A schematic diagram of the structure of a command scheduling module provided in an embodiment of this application. Figure 3 ; Figure 4 A schematic diagram of the structure of a front-end subsystem provided in this application embodiment. Figure 1 ; Figure 5 A schematic diagram of the structure of a front-end subsystem provided in this application embodiment. Figure 2 ; Figure 6 A schematic diagram of the structure of a computing chip provided in this application embodiment. Figure 1 ; Figure 7 A schematic diagram of the structure of a computing chip provided in this application embodiment. Figure 2 ; Figure 8 This is a schematic diagram of the structure of a computing chip system provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] The modules, units, command processors, etc. mentioned in this application may include one or more hardware circuits, including but not limited to: application-specific integrated circuits, digital signal processors, field-programmable gate arrays, discrete logic circuits, state machines, and any combination of the aforementioned circuits; these circuits are specifically designed, configured, and interconnected to perform one or more specific functions disclosed in this application.

[0024] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0025] Figure 1 A schematic diagram of the structure of a command scheduling module provided in an embodiment of this application. Figure 1 ,like Figure 1 As shown, the command scheduling module includes a storage unit, a command receiving unit, and a command processing unit. The command receiving unit is connected to the storage unit, which includes at least a first command buffer unit and a second command buffer unit. The first command buffer unit has a higher read priority than the second command buffer unit. The first command buffer unit is used to buffer control commands, and the second command buffer unit is used to buffer low-priority commands, including ordinary task commands. The command receiving unit is used to read commands from the storage unit and parse the commands to obtain the parsing results; the command processing unit is connected to the command receiving unit and is used to create or process tasks based on the parsing results.

[0026] The storage unit can be SRAM (Static Random Access Memory).

[0027] It should be noted that the control commands buffered in the first command buffer unit are high-priority commands, such as urgent control commands, which can be used for operations such as aborting tasks, pausing, resuming, and managing task queues. For example, they may include commands such as task cancellation and clearing the task queue. The second command buffer unit is used to buffer low-priority commands for daily use. In most business operations, ordinary task commands are written to the second command buffer unit. However, in emergency situations, commands can be written to the first command buffer unit to bypass restrictions, for example, quickly canceling the execution of some tasks. In some embodiments, when commands overflow in the second command buffer unit, a portion of the first command buffer unit can be used for buffering, providing a certain degree of redundancy.

[0028] The first command buffer unit is a high-priority buffer, and the second command buffer unit is a low-priority buffer. Both the first and second command buffer units belong to the command buffers within the storage unit.

[0029] For example, during software initialization, the register file of the command scheduling module specifies the priority and size of the first command buffer unit and the second command buffer unit. Assuming the entry address of the first command buffer unit is fixed at 0 and its size is size0, the entry address of the second command buffer unit can be size0.

[0030] In some embodiments, the command buffer is structured as a ring buffer. The data structure resembles a ring, initially with both the read and write pointers pointing to address 0. When a command is written, the write pointer is incremented by 1; when the command receiving unit reads a command, the read pointer is incremented by 1. The read pointer always follows the write pointer. The user side does not need to concern itself with the address organization. If the write pointer does not catch up with the read pointer, it means there is still space in the command buffer to write commands. If the write pointer catches up with the read pointer, it means the command buffer is full.

[0031] In this embodiment, the command receiving unit reads ordinary task commands from the second command buffer unit, parses the ordinary task commands to obtain parsing results, and the command processing unit creates tasks based on the parsing results. The command receiving unit reads control commands from the first command buffer unit, parses the control commands to obtain parsing results, and the command processing unit processes tasks based on the parsing results. Specifically, the command receiving unit reads commands when the command buffer is not empty and sends the parsing results to the command processing unit.

[0032] In some implementations, the command receiving unit may include a command reading module and a command decoder. The command reading module reads commands from either the first or second command buffer unit. It parses the commands according to a preset command format and the actual value to obtain the parsing result. The command reading module can maintain multiple read pointer counters locally, with a default value of 0. When the write pointer of either the first or second command buffer unit is not equal to the read pointer, the command reading module initiates a read request starting at address N×size + read pointer. Each time a command is read, the corresponding command buffer unit increments its corresponding read pointer counter by one, until the read pointer counter equals N×Size - 1 and is then reset to zero. Both the first and second command buffer units can be managed in a first-in, first-out manner and each has its own read and write pointers.

[0033] It is worth noting that the command processing unit can create, abort, launch, and notify task triggering based on the parsing results. Task creation can include data transfer tasks, kernel startup tasks, and synchronization tasks. The command processing unit can also manage task queues.

[0034] In one embodiment of this application, the first command buffer unit and the second command buffer unit can store commands of different lengths depending on their type. In other embodiments, both the first command buffer unit and the second command buffer unit store fixed-length commands, storing different types of commands in fixed bits, thus reducing the complexity of design and parsing.

[0035] In summary, this application provides a command scheduling module, including: a storage unit, a command receiving unit, and a command processing unit. The command receiving unit is connected to the storage unit, which includes at least: a first command buffer unit and a second command buffer unit. The first command buffer unit has a higher read priority than the second command buffer unit. The first command buffer unit is used to buffer control commands, and the second command buffer unit is used to buffer low-priority commands, including ordinary task commands. The command receiving unit reads commands from the storage unit and parses the commands to obtain parsing results. The command processing unit is connected to the command receiving unit and is used to create or process tasks based on the parsing results. By using a first command buffer unit to buffer control commands and a second command buffer unit to buffer ordinary task commands, partitioned storage for different commands is achieved. Even if the storage space of the second command buffer unit is fully occupied, it does not affect the storage of control commands in the first command buffer unit. Moreover, the first command buffer unit has a higher read priority than the second command buffer unit, which allows control commands to be executed first. This enables the "queue-jumping" priority processing of control commands through the first command buffer unit, reducing the occurrence of invalid task execution.

[0036] In this embodiment, the command processing unit can read at least one of a clear queue instruction and a delete task instruction from the first command buffer unit. Based on the clear queue start instruction, it modifies all tasks in the target task queue. Based on the clear queue end instruction, it ends the clearing process and restores the state of the target task queue. The command processing unit can also create waiting tasks in the task queue based on waiting commands. If a waiting task is detected moving to the head of the target task queue, it monitors whether the tasks the waiting task depends on have been completed, obtaining a monitoring result. Based on this monitoring result, it processes the waiting task.

[0037] The clear start instruction is stored in the first command buffer unit, and the clear end instruction is stored in the second command buffer unit. The reading priority of the first command buffer unit is higher than that of the second command buffer unit. In this way, the clear start instruction has a higher priority than the clear end instruction. The higher-priority clear start instruction is given priority in establishing the clear state, and the lower-priority clear end instruction is the last to end the clear state. This ensures that all tasks in between the start and end are accurately captured and terminated.

[0038] In addition, the target task queue can include a task queue list and a task queue buffer. When modifying the task / queue state, only the task queue list needs to be modified. When launching a task, the task state in the task queue list needs to be considered. This ensures that the task is processed according to the latest state when it is launched, thus achieving low-power task / queue state modification and control.

[0039] Optionally, Figure 2 A schematic diagram of the structure of a command scheduling module provided in an embodiment of this application. Figure 2 ,like Figure 2 As shown, the command scheduling module also includes: an interface unit and an access conversion unit; The command receiving unit is connected to the interface unit, and the interface unit is connected to the storage unit through the access conversion unit; The command receiving unit sends an access instruction to the access conversion unit through the interface unit. The access conversion unit is used to convert the access instruction into an access instruction corresponding to any buffer unit in each buffer unit, and read the corresponding cached command information from any buffer unit.

[0040] The interface unit can be an AXI multi-m1s, specifically an AXI (Advanced eXtensible Interface) bridge with multiple masters and one slave. In one embodiment, the master can be an input from the subsystem's on-chip network outside the command scheduling module, and the slave is the one destined for the access translation unit. The subsystem's on-chip network can input commands to the storage unit via the AXI port.

[0041] Additionally, the access conversion unit may include an SRAM controller.

[0042] In this embodiment, the command receiving unit is a command receiving port. The command receiving unit sends an access instruction to the access conversion unit through the interface unit. The access conversion unit converts the access instruction from the interface unit into an access instruction for a single-port storage unit, that is, converts the AXI access into a single-port SRAM access. The storage unit access instruction may include an access instruction from a first command buffer unit or a second command buffer unit. Based on the access instruction from the first command buffer unit or the second command buffer unit, corresponding cached command information is read from the first command buffer unit or the second command buffer unit.

[0043] In summary, the command receiving unit sends access instructions to the access conversion unit through the interface unit. After the access conversion unit converts the access instructions, it controls the reading of corresponding cached command information from multiple buffer units according to priority and order, so that different units can access each other and can read command information in the buffer units in an orderly and efficient manner.

[0044] The interface unit is an AXI with multiple hosts and a single slave. The access conversion unit processes and controls the access commands sent by the interface unit from multiple hosts. In this embodiment, the interface unit can efficiently aggregate access commands from multiple hosts, such as the subsystem's on-chip network, significantly reducing the number of hardware interfaces and interconnection complexity. Moreover, the access path can be simplified by interacting with the access conversion unit through a unified slave port.

[0045] Optionally, such as Figure 2 As shown, the storage unit further includes a configuration information storage unit. This unit stores the computational configuration information required for executing computational tasks. The computational configuration information may include one or more of the following: system-state entry address, system-state packet address, power consumption and frequency control information, and computational unit configuration information. Specifically, the configuration information storage unit can store different computational configuration information based on the specific type of computational task, such as constant computation, tensor computation, sparse matrix computation, and reduction computation.

[0046] The command processing unit is also used to read computing configuration information from the configuration information storage area of ​​the storage unit when processing computing tasks. The command processing unit can read the corresponding computing configuration information according to the command type information to achieve efficient computing.

[0047] In some implementations, the command receiving unit sends an access instruction for computing configuration information to the access conversion unit via the interface unit. The access conversion unit then converts the access instruction for computing configuration information into an access instruction corresponding to the configuration information storage area, and reads the computing configuration information from the configuration information storage area. The interface unit can be an AXI multi-m1s, and the master can contain the access instruction for computing configuration information given by the command receiving unit.

[0048] The configuration information storage unit may include SIMT (Single-Instruction, Multiple-Thread) configuration, which refers to the specific configuration parameter settings under a single-instruction, multiple-thread architecture. For example, the configuration information storage unit may also include SIMD (Single-Instruction, Multiple-Data) configuration, which, based on the specific hardware configuration parameters or structural settings under a single-instruction, multiple-data architecture, sequentially achieves a high degree of adaptation between the computing unit and the computing architecture. The configuration information storage unit can be considered as a computing configuration information storage area.

[0049] It should be noted that the computational configuration information required to execute the computational task can specifically be the configuration content generated for the KernelLaunch Task. The command processing unit reads the computational configuration information from the configuration information storage area of ​​the storage unit when processing the computational task. For example, the computational configuration information stored in the configuration information storage unit is pre-stored, such as in the firmware. After the chip is powered on, it is loaded into the configuration information storage unit, for example, by the MCU (Microcontroller Unit).

[0050] In summary, a configuration information storage unit is also provided in the storage unit to store some or all of the computing configuration information required when performing computing tasks. By partitioning the storage unit and storing specific information in different partitions, the storage space in the storage unit can be fully utilized.

[0051] For example, the partition can be dynamic, and the storage unit includes a shared partition storage unit. The shared partition storage unit can be dynamically configured to belong to either the command buffer unit or the configuration information storage unit based on the current command execution status. When command execution is busy and the first command buffer unit has a high level (e.g., commands occupy more than or equal to 80% of the storage space in the FIFO queue), it belongs to the first command buffer unit. When the first command buffer unit has a low level (e.g., less than 80% of the storage space), it can belong to the configuration information storage unit, loading and storing more computational configuration information for the command processing unit to read quickly.

[0052] Optionally, Figure 3 A schematic diagram of the structure of a command scheduling module provided in an embodiment of this application. Figure 3 ,like Figure 3 As shown, the command scheduling module also includes: register space units; The register space unit is connected to the command receiving unit and the command processing unit respectively. The register space unit is used to store the configuration information of the command scheduling module so that the command receiving unit and the command processing unit can obtain the configuration information of the command scheduling module. The register space unit is also used to generate interrupt information based on the task processing status of the command processing unit, so that the processor can receive the interrupt information.

[0053] The register space unit may include the control and status registers of the command scheduling module, which can be triggered when the command scheduling module executes a task and is responsible for generating an interrupt.

[0054] In some implementations, other units, such as the CPU, can send configuration information to the register space unit. The register space unit can receive and store the configuration information and send it to the command receiving unit and the command processing unit respectively, or the command receiving unit and the command processing unit can actively read it. The configuration information can be command format, field rule definition, etc. The command receiving unit and the command processing unit perform command / task processing according to the configuration information. The register space unit obtains the task processing status from the command processing unit, such as whether the task was successfully launched or successfully completed, and generates stored interrupt information based on the task processing status. Then, it sends the interrupt information to the processor for task feedback, and the processor can obtain the feedback information.

[0055] It should be noted that the processor can be a CPU (Central Processing Unit).

[0056] In summary, setting up an independent register space unit allows for flexible configuration of the command scheduling module's configuration information. Furthermore, the register space unit can be used to determine the task processing status within the command processing unit, achieving efficient feedback on task processing status.

[0057] Figure 4 A schematic diagram of the structure of a front-end subsystem provided in this application embodiment. Figure 1 ,like Figure 4 As shown, the front-end subsystem may include: a subsystem on-chip network connected to the aforementioned command scheduling module; The command scheduling module is connected to the subsystem's on-chip network, which in turn is connected to the bus interface unit. This allows the module to sequentially obtain the first command packet through both the subsystem's on-chip network and the bus interface unit. Alternatively, the first command packet can be a basic command packet.

[0058] In some implementations, the subsystem on-chip network is connected to the bus interface unit via the first chip on-chip network, and the bus interface unit is connected to the main CPU. The command scheduling module obtains the first command packet sequentially through the subsystem on-chip network, the first chip on-chip network, the bus interface unit, and the main CPU. The first command packet is routed and transmitted via the subsystem on-chip network and then processed by the command scheduling module.

[0059] It should be noted that the bus interface unit can be a PCIe (Peripheral Component Interconnect Express) unit, the subsystem on-chip network can be the on-chip network in the front-end subsystem, and the first chip on-chip network can include the on-chip networks connecting all subsystems of the entire chip. Specifically, the first chip on-chip network can be the configure NOC (Configure Network on Chip), responsible for routing configuration management messages between various subsystems / modules within the chip. The subsystem on-chip network can be directly connected to the bus interface unit, or it can be connected to the bus interface unit via the first chip on-chip network.

[0060] In summary, the front-end subsystem provided in this application includes: a subsystem on-chip network and the aforementioned command scheduling module connected together; wherein, the command scheduling module is connected to the subsystem on-chip network, and the subsystem on-chip network is connected to a bus interface unit, used to sequentially obtain a first command packet through the subsystem on-chip network and the bus interface unit. The command scheduling module is used for command parsing and processing. The subsystem on-chip network can support the simultaneous transmission of multiple command packets on different paths, which can improve the concurrent processing capability. Moreover, obtaining the first command packet based on the subsystem on-chip network and the bus interface unit can achieve effective and reliable acquisition of the first command packet.

[0061] Optionally, Figure 5 A schematic diagram of the structure of a front-end subsystem provided in this application embodiment. Figure 2 ,like Figure 5 As shown, the front-end subsystem also includes: a command processor; The command processor is used to obtain second command packets from the main central processing unit via the subsystem on-chip network and bus interface unit; The command processor is connected to the command scheduling module and is used to parse the second command packet to obtain the parsed command packet. The parsed command packet is then sent to the command scheduling module. The parsed command packet has a specified length.

[0062] The command processor can work with the command scheduling module to perform scheduling feedback processing and manage the relevant interrupts of the computing chip scheduling.

[0063] In some embodiments, the command processor sequentially receives / acquires a second command packet sent / generated by the main central processing unit (CPU) through the subsystem on-chip network, the first chip on-chip network, and the bus interface unit. The second command packet may include a custom command packet of a non-preset length or type. The command processor, acting on behalf of the CPU, breaks down the custom command packet into fixed-length basic command packets so that the command scheduling module can process them efficiently. In other words, the command processor handles complex commands and works in conjunction with the command scheduling module to handle basic commands.

[0064] In one embodiment of this application, the second command packet can be a complex command packet. Considering module area, circuit complexity, and processing efficiency, the command scheduling module does not directly process the second command packet. The main central processing unit can send the customized second command packet to the command processor. The command processor parses the second command packet to obtain a parsed command packet, which is a simple instruction packet. The command scheduling module then processes the parsed command packet, preserving a scalability for driver-to-firmware transfer. The main central processing unit sequentially sends the second command packet to the command processor through the bus interface unit, the first chip on-chip network, and the subsystem on-chip network.

[0065] It should be noted that the command processor can also handle some abnormal events, such as command scheduling module failures, memory failures, and computing unit failures. The computing unit will be discussed later.

[0066] Furthermore, the AXI on-chip network's read / write access to the SRAM space is converted into SRAM read / write timing by the access translation unit, with write operations being exclusively used by the on-chip network. However, read operations can be contested by multiple units, such as the command receiving unit and the command processing unit. AXI multi-M1S can employ a Round-Robin strategy ("polling scheduling strategy") to handle read contention among these three units, or it can set the priority of each unit for read contention handling.

[0067] In summary, a command processor is configured to parse complex second command packets, yielding the parsed command packets. The command scheduling module then processes these parsed packets, reducing the complexity and workload on the scheduling module. This also allows the front-end subsystem to handle complex second command packets appropriately. Furthermore, offloading complex command packet parsing from the processor to the front-end subsystem further reduces the processor's processing load.

[0068] Optionally, such as Figure 5 As shown, the front-end subsystem also includes: an interrupt receiving unit; The interrupt receiving unit is connected to the command scheduling module and the command processor respectively. It is used to obtain interrupt signals through the bus interface unit and send interrupt signals to the command scheduling module and the command processor so that the command scheduling module and the command processor can process the interrupt signals.

[0069] In some implementations, the internal data transfer engine of the chip can generate interrupts based on data transfer tasks or access tasks from external chips. After the interrupt signal arrives at the chip, it can be routed to the first chip's on-chip network via the bus. The interrupt receiving unit receives the interrupt signal sequentially through the subsystem's on-chip network, the first chip's on-chip network, and the bus interface unit. The interrupt receiving unit unpacks the packaged interrupt signal to obtain the interrupt signal, and then sends the interrupt signal to the command scheduling module and the command processor respectively, so that the command scheduling module and the command processor can perform interrupt processing based on the interrupt signal.

[0070] In summary, the interrupt receiving unit can efficiently acquire interrupt information through the bus interface unit and send the interrupt signal to the command scheduling module or command processor based on the interrupt signal information and the operating status of each unit. This allows the command scheduling module and command processor to process the interrupt signal accurately and reliably. This achieves the front-end subsystem's reception and processing of interrupt signals. For example, interrupts related to ordinary task synchronization requirements based on external chips can be sent to the command scheduling module, while interrupts related to the cessation of complex instruction packet parsing can be sent to the command processor. Alternatively, interrupt signals can be sent to the command scheduling module when it is working normally, and to the command processor when the command scheduling module malfunctions. This ensures that even if the command scheduling module malfunctions, the front-end subsystem can still perform interrupt processing normally.

[0071] Optionally, such as Figure 2 As shown, the storage unit in the command scheduling module also includes: an interrupt storage unit; The command processor is also used to read message interrupt vectors from the message interrupt vector table area in the interrupt memory unit and generate interrupt signals to send to the bus interface unit.

[0072] The interrupt storage unit can be an MSIx (Message Signaled Interrupts eXtended) vector table area. The message interrupt vectors stored in the message interrupt vector table area of ​​the interrupt storage unit are MSIx vectors.

[0073] In some implementations, when the current subsystem needs to send an interrupt signal to the processor, the command processor can read the MSIx vector from the MSIx vector table area, generate an interrupt signal, and send it to the bus interface unit via the subsystem's on-chip network and the first chip's on-chip network, and then transmit it to the main CPU. The interrupt signal can actively write the status information of the task execution result to the main CPU's memory area via the bus interface unit, transferring some of the main CPU's functions and achieving localized management of the scheduling mechanism.

[0074] It's worth noting that the MSIx vector table area can be pre-stored in the firmware and loaded into the interrupt memory by the MCU after the chip powers on. Specifically, the MSIx vector table area stores the interrupt vector table that triggers PCIe MSIx, which is then queried by the command processor. This fully utilizes the storage space of the command scheduling module to enable the command processor to query the nearest interrupt vector table.

[0075] In one embodiment of this application, the contents stored in the first command buffer unit, the second command buffer unit, the configuration information storage unit, and the interrupt storage unit in the storage unit can be read as needed by the subsystem on-chip network, the command receiving unit, the command processing unit, etc.

[0076] In summary, setting up an interrupt storage unit in the storage unit specifically for storing message interrupt vectors enables fast reading of message interrupt vectors, facilitating the command processor to efficiently generate interrupt signals and transmit them to the bus interface unit.

[0077] Optionally, Figure 6 A schematic diagram of the structure of a computing chip provided in this application embodiment. Figure 1 ,like Figure 6 As shown, the bus interface unit, the first chip-on-chip network, and the aforementioned front-end subsystem; The front-end subsystem is connected to the bus interface unit through the on-chip network of the first chip. The command scheduling module in the front-end subsystem can obtain command packets from the main central processing unit through the on-chip network of the subsystem in the front-end subsystem, the on-chip network of the first chip, and the bus interface unit.

[0078] In this embodiment, all command packets can be routed via the first chip's on-chip network and then processed by the command scheduling module in the front-end subsystem. This facilitates unified scheduling and management of message routing throughout the entire chip via the first chip's on-chip network. Specifically, the first chip's on-chip network can be a configure NOC (Configure Network on Chip), responsible for the configuration management message routing connections of various subsystems / modules within the chip.

[0079] like Figure 6 As shown, the bus interface unit may also include a data transfer engine, which may be an HDMA, and the tasks performed on the HDMA will be converted into a series of configurations, which are transferred from the subsystem on-chip network and the first chip on-chip network.

[0080] In summary, this application provides a front-end subsystem, including: a bus interface unit, a first on-chip network, and the aforementioned front-end subsystem. The front-end subsystem is connected to the bus interface unit via the first on-chip network. The command scheduling module in the front-end subsystem obtains command packets from the main central processing unit through the subsystem's on-chip network and the bus interface unit. By setting the bus interface unit and the first on-chip network on the computing chip, the command processing module in the front-end subsystem can reliably and efficiently obtain / acquire command packets from the main central processing unit.

[0081] Optionally, Figure 7 A schematic diagram of the structure of a computing chip provided in this application embodiment. Figure 2 ,like Figure 7 As shown, the computing chip also includes: a computing unit; The computing unit executes the computing tasks generated by the command processing unit in the SIMT command scheduling module and obtains the computing results. The computing unit is connected to the subsystem on-chip network in the front-end subsystem to send computing results to the bus interface unit via the subsystem on-chip network.

[0082] The computing unit can be based on SIMT Cluster (Single Instruction, Multiple Threads).

[0083] In this embodiment, the contents stored in the first command buffer unit and the second command buffer unit can be divided into two main categories: task packages and control packages. The task packages can create three types of tasks: kernel startup tasks (corresponding to computation tasks), data transfer engine startup tasks (corresponding to data transfer tasks), and waiting tasks. The computation unit executes the computation tasks generated by the command processing unit based on the SIMT command to obtain the computation results.

[0084] It should be noted that the computing unit is connected to the subsystem on-chip network in the front-end subsystem. Tasks applied to the computing unit are translated into a series of configurations, which pass through the subsystem on-chip network to reach the computing unit. For example... Figure 7 As shown, SIMT's interrupt is directly hardwired to the front-end subsystem, and then simultaneously connected to the command scheduling module and the command processor.

[0085] In addition, in this embodiment of the application, the command scheduling module may also include: an interrupt processor, which is used to receive interrupt requests from the HDMA and the computing unit, and cooperate with the command processor to process their completion interrupts. If the interrupt is within the processing range, the interrupt will be cleared directly and the dequeue operation of the task queue will be triggered.

[0086] In summary, in this embodiment, the computing unit is configured to perform computational tasks and transmit computational results externally via a bus interface unit. This achieves the execution of corresponding computational processes for commands sent externally and the feedback of computational results to the outside world.

[0087] like Figure 7 As shown, the computing chip also includes a second on-chip network, which can be a dedicated communication network (Data NoC) for transmitting data. By dividing the on-chip network into a configuration on-chip network and a data on-chip network, efficient isolation and transmission of configuration information and data information can be achieved.

[0088] In practical applications, a GPGPU (General-Purpose computing on Graphics Processing Units) may consist of a front-end subsystem and computing units. The computing chip may include: a GPGPU, a bus interface unit, a first on-chip network, and a second on-chip network.

[0089] Among them, the waiting task and the command-triggered notification issued by the main CPU establish a collaborative mechanism with the first two types of tasks by executing the waiting and executing the notification, which can complete the synchronization between multiple GPGPUs.

[0090] In this embodiment of the application, the computing chip can be a GPU Die (graphics processor die). Figure 8 This is a schematic diagram of the structure of a computing chip system provided in an embodiment of this application, such as... Figure 8 As shown, a computing chip system may include: one GPU Die and multiple IO Dies (input / output dies), with the IO Dies used to store memory chips. The computing chip system can communicate with the CPU or other GPUs via a bus interface unit. Tasks from the CPU or other GPUs are transmitted to the computing chip system through the bus interface unit.

[0091] Both the GPU and the IO die have HDMA modules that handle data transfer. Once the transfer is complete, a level is raised to generate an interrupt as a completion marker.

[0092] It's important to note that if the command scheduling module and CPU communicate directly with the computing unit via the bus interface unit, a significant amount of time is wasted between the main CPU, the bus interface unit, and the computing unit. The computing unit completes its calculations and sends feedback to the bus interface unit before sending the next task. However, by using the command scheduling unit, when the CPU sends multiple kernel tasks (core computing tasks executed on the GPU), the command scheduling unit acts as an intermediary, quickly initiating and switching between tasks, thus improving efficiency.

[0093] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A command scheduling module, characterized in that, include: Storage unit, command receiving unit, and command processing unit; The command receiving unit is connected to the storage unit. The storage unit includes at least a first command buffer unit and a second command buffer unit. The first command buffer unit has a higher read priority than the second command buffer unit. The first command buffer unit is used to buffer control commands, and the second command buffer unit is used to buffer low-priority commands, including ordinary task commands. The command receiving unit is used to read commands from the storage unit, parse the commands, and obtain the parsing results; The command processing unit is connected to the command receiving unit and is used to create or process tasks based on the parsing results.

2. The command scheduling module according to claim 1, characterized in that, The command scheduling module further includes: an interface unit and an access conversion unit; The command receiving unit is connected to the interface unit, and the interface unit is connected to the storage unit through the access conversion unit; The command receiving unit sends an access instruction to the access conversion unit through the interface unit. The access conversion unit is used to convert the access instruction into an access instruction corresponding to any one of the buffer units and read the corresponding cached command information from any one of the buffer units.

3. The command scheduling module according to claim 1, characterized in that, The storage unit further includes: a configuration information storage unit; the configuration information storage unit is used to store the computing configuration information required when executing computing tasks, the computing configuration information including the system state entry address and the system state packet address; The command processing unit is used to read the computing configuration information from the configuration information storage area of ​​the storage unit when processing the computing task.

4. The command scheduling module according to claim 1, characterized in that, The command scheduling module further includes: a register space unit; The register space unit is connected to the command receiving unit and the command processing unit respectively. The register space unit is used to store the configuration information of the command scheduling module so that the command receiving unit and the command processing unit can obtain the configuration information of the command scheduling module. The register space unit is also used to generate interrupt information based on the task execution status of the command scheduling module, so that the processor receives the interrupt information.

5. A front-end terminal system, characterized in that, It includes a subsystem on-chip network and a command scheduling module as described in any one of claims 1-4 above; The command scheduling module is connected to the subsystem on-chip network, and the subsystem on-chip network is connected to the bus interface unit, for obtaining the first command packet sequentially through the subsystem on-chip network and the bus interface unit.

6. The front-end terminal system according to claim 5, characterized in that, The front-end subsystem also includes: a command processor; The command processor is used to obtain a second command packet from the main central processing unit through the subsystem on-chip network and the bus interface unit; The command processor is connected to the command scheduling module and is used to parse the second command packet to obtain a parsed command packet, and send the parsed command packet to the command scheduling module. The parsed command packet has a specified length.

7. The front-end terminal system according to claim 6, characterized in that, The front-end subsystem also includes: an interrupt receiving unit; The interrupt receiving unit is connected to the command scheduling module and the command processor respectively, and is used to obtain an interrupt signal through the bus interface unit and send the interrupt signal to at least one of the command scheduling module and the command processor so that the command scheduling module and the command processor process the interrupt signal.

8. The front-end terminal system according to claim 7, characterized in that, The storage unit in the command scheduling module also includes: an interrupt storage unit; The command processor is also used to read message interrupt vectors from the message interrupt vector table area in the interrupt storage unit and generate an interrupt signal to send to the bus interface unit.

9. A computing chip, characterized in that, include: The bus interface unit, the first chip-on-chip network, and the front-end subsystem as described in any one of claims 5-7; The front-end subsystem is connected to the bus interface unit through the first chip on-chip network. The command scheduling module in the front-end subsystem obtains command packets from the main central processing unit through the subsystem on-chip network, the first chip on-chip network, and the bus interface unit in the front-end subsystem.

10. The computing chip according to claim 9, characterized in that, The computing chip further includes: a computing unit; The computing unit executes the computing tasks generated by the command processing unit in the command scheduling module based on SIMT (Single Instruction Multithreading) to obtain computing results. The computing unit is connected to the subsystem on-chip network in the front-end subsystem to send the computing results to the bus interface unit through the subsystem on-chip network.

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