An integrated system of intelligent photovoltaic optimization and distributed edge computing of optical calculation

Abstract

The application provides a kind of integrated system of intelligent photovoltaic optimization and distributed edge computing of light algorithm.The system integrates photovoltaic optimization chip, intelligent edge computing module and networking module in a single hardware unit through encapsulation integration platform, shares power management layer and heat dissipation substrate, and is provided with special hardware interrupt line between two chips, only allows low-power operator to execute during sampling protection window through sampling time sequence coordination mechanism, postpones high-power operator to restore after sampling window ends, eliminates the interference of power consumption peak on sampling accuracy, and is further provided with bus voltage predictive protection mechanism, outputs voltage prediction sequence covering multiple sampling windows in the future, simultaneously drives preventive power consumption narrowing and protection advance dynamic adjustment, forms the coordinated control closed loop of prediction-narrowing-advance trinity.The application realizes the coordinated optimization of photovoltaic optimization and edge computing in a single hardware unit.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing, and more specifically to an integrated intelligent photovoltaic optimization and distributed edge computing system that combines optical and computational computing. Background Technology

[0002] As the computing power demands of AI inference tasks continue to grow, the deployment scale of edge computing nodes is expanding, leading to increasingly prominent pressures on power supply. Photovoltaic power generation, as an important source of clean energy, is widely used in industrial parks, data centers, and large-scale photovoltaic power plants. Combining photovoltaic power generation with edge computing to achieve coordinated energy and computing power supply has become an important technological path to alleviate these problems.

[0003] In existing technologies, photovoltaic optimization equipment and edge computing equipment are typically deployed separately, connected via independent power interfaces. This results in large system size and high deployment costs, making it difficult to meet the needs of large-scale distributed deployments. Therefore, the industry has proposed a technical solution that integrates photovoltaic optimization modules and edge computing modules into a single hardware unit to reduce system size and deployment costs.

[0004] Regarding the coordinated scheduling of photovoltaic (PV) power output and computing power, CN121277657B discloses a task processing method for PV edge computing nodes. This method aims to match the task processing volume of each PV edge computing node with its current power supply capacity. Based on service latency, service energy consumption, and energy storage models, it constructs processor resource allocation optimization sub-problems and task migration optimization sub-problems. A multi-agent reinforcement learning algorithm is then used to jointly solve these optimization sub-problems, resulting in optimized processor resource allocation and task migration strategies. This scheme achieves matching of PV power output and computing power at the macro-level scheduling of task queues and processor resource allocation. However, its coordination mechanism relies on a multi-agent reinforcement learning algorithm for optimization, resulting in a long response latency. It can only meet the macro-level resource scheduling needs at the task level and cannot satisfy the real-time coordination requirements under the microsecond-level timing constraint of the maximum power point tracking (MPPT) algorithm sampling window. Furthermore, this scheme uses service latency and energy consumption as optimization objectives, failing to incorporate MPT sampling accuracy into the constraints and neglecting the coupling interference caused by the peak power consumption of the tensor processing unit under the shared bus architecture on the MPT sampling accuracy.

[0005] However, in an architecture that integrates the photovoltaic optimization module and the edge computing module into a single hardware unit, the aforementioned macro-level scheduling coordination solution faces a technical problem that has not yet been solved by existing technologies: the photovoltaic optimization chip and the edge computing module share the same DC bus. When the tensor processing unit within the edge computing module performs inference calculations, it generates periodic power consumption peaks, causing a momentary drop in the bus voltage within the sampling window of the maximum power point tracking (MPPT) algorithm. The photovoltaic optimization chip misinterprets this voltage drop as a disturbance response, causing a power point judgment offset, which in turn triggers a vicious cycle of output reduction and further voltage drop, leading to a continuous decline in photovoltaic power generation efficiency. Existing MPT and edge computing scheduling technologies are designed independently for their respective domains and do not consider the coupling interference problem between the two in the shared bus scenario, thus failing to fundamentally eliminate the interference of the tensor processing unit's power consumption peaks on the MPT sampling accuracy. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings by proposing an integrated intelligent photovoltaic optimization and distributed edge computing system that combines optical and computational capabilities.

[0007] The present invention adopts the following technical solution:

[0008] An integrated intelligent photovoltaic optimization and distributed edge computing system is disclosed. This system integrates a photovoltaic optimization chip, an intelligent edge computing module, and a networking module into a single hardware unit through an integrated packaging and testing platform. The three share a power management layer and a heat dissipation substrate. The photovoltaic optimization chip supplies power to the intelligent edge computing module and the networking module through a DC bus.

[0009] The photovoltaic optimization chip includes a closed-loop current sensor, a high-frequency sampling circuit, and a digital signal processing unit. The closed-loop current sensor and the high-frequency sampling circuit synchronously acquire the port voltage and current of the photovoltaic string. The acquired data is sent to the digital signal processing unit, which runs an adaptive maximum power point tracking algorithm to drive the synchronous rectifier bridge to regulate the output voltage of the photovoltaic string to the DC bus voltage.

[0010] A dedicated hardware interrupt line is provided between the photovoltaic optimization chip and the intelligent edge computing module. Before the adaptive maximum power point tracking algorithm enters the sampling phase, the photovoltaic optimization chip sends a sampling protection signal to the intelligent edge computing module through the hardware interrupt line. After the scheduling unit in the intelligent edge computing module responds to the sampling protection signal, it only allows low-power operations to continue to be executed during the sampling protection window, and postpones high-power operations until the sampling window ends. After the photovoltaic optimization chip completes sampling, it sends a sampling release signal through the hardware interrupt line. After the scheduling unit responds to the sampling release signal, it resumes the normal scheduling of high-power operations.

[0011] The system is equipped with a bus voltage predictive protection mechanism. The power sensing register samples the bus voltage value at a fixed sub-cycle and synchronously records the measured irradiance sequence. The system has several historical irradiance template curves pre-set in on-chip storage. During operation, the measured irradiance sequence is matched with each template curve for similarity, and the template with the highest similarity is selected as the reference curve. Based on the trend of the reference curve after the current moment and the deviation correction between the measured sequence and the template, a voltage prediction sequence covering multiple future sampling windows is output. When the predicted voltage corresponding to any sampling window in the voltage prediction sequence is lower than the safe sampling threshold, the scheduling unit performs preventive power consumption narrowing for that sampling window. At the same time, the protection advance of the sampling protection signal is dynamically adjusted according to the irradiance decrease intensity index defined by the difference in predicted voltage between adjacent sampling windows. The dynamically adjusted protection advance is written into the preset register of the sampling clock counter and takes effect in the next sampling cycle, forming a three-in-one coordinated control closed loop of prediction, narrowing and advance.

[0012] Furthermore, during the inference model compilation stage, the compiler marks each operator node in the computation graph with a power consumption flag based on the operator type. Operators involving large-scale parallel floating-point multiplication and addition operations are marked as high-power operations, while operators whose computational load is linearly related to the number of input tensor elements and do not involve large-scale parallel multiplication and addition operations are marked as low-power operations. The power consumption flag is attached to the operator node descriptor in the form of a one-bit flag and loaded into on-chip storage along with the model file.

[0013] During runtime, the scheduling unit simultaneously extracts power consumption flags and maintains a power consumption flag queue that is strictly one-to-one with the task execution queue when loading operator nodes into the task execution queue. When multiple inference tasks are executed concurrently, each task independently maintains its own power consumption flag queue. When the scheduling unit responds to the sampling protection signal, it traverses the head of the power consumption flag queue of all active tasks, performs a suspension operation on the head operators marked as high power consumption, and allows the head operators marked as low power consumption to continue execution until completion.

[0014] Furthermore, the scheduling unit maintains an execution context structure for each active inference task. The execution context structure includes a pointer to the current execution position of the computation graph, the starting address and length of the input tensor of the suspended operator in the on-chip cache.

[0015] The on-chip cache is divided into two parts: a resident area and a protection cache. The resident area is used to store the normal calculation results of model weights and intermediate activation tensors, while the protection cache is dedicated to storing snapshots of input tensors of operators that are suspended during the sampling protection window.

[0016] After the sampling window ends, the scheduling unit resumes execution from the execution position pointer. For operators that have saved input tensors, the input is read from the protection buffer and execution continues. For high-power operators that have not yet started, they are executed sequentially according to the original computation graph order.

[0017] Furthermore, when multiple consecutive sampling protection windows are triggered in a short period of time, if the high-power operator that was suspended during the previous protection window has not yet completed its recovery execution, and a new protection window arrives again, the scheduling unit checks the execution position pointer of the operator. If the operator is still in a suspended state, the original cache entry is directly reused without being written repeatedly.

[0018] The read and write operations of the execution position pointer are implemented through hardware atomic instructions, ensuring the consistency of the pointer state in a multi-threaded scheduling environment.

[0019] Furthermore, the photovoltaic optimization chip has a built-in sampling clock counter, which operates synchronously with the sampling clock of the high-frequency sampling circuit. It automatically resets to zero and starts counting again at the end of each sampling cycle. When the count value reaches a preset protection advance amount, the photovoltaic optimization chip automatically pulls up the hardware interrupt line to trigger the hardware interrupt of the intelligent edge computing module. The protection advance amount is written into the preset register of the sampling clock counter.

[0020] The photovoltaic optimization chip has a built-in sampling timing register. The sampling timing register starts when sampling begins and triggers a sampling completion interrupt when it is full. In response to the sampling completion interrupt, the photovoltaic optimization chip pulls the hardware interrupt line low. The intelligent edge computing module exits the protection state after detecting the falling edge.

[0021] Furthermore, the historical irradiance template curve is determined by collecting historical irradiance data under various typical weather patterns and pre-stored in on-chip storage before the system leaves the factory;

[0022] The similarity matching is achieved by measuring the distance between the measured irradiance sequence and the corresponding interval of each template curve in the current time period, and the template with the smallest distance is selected as the reference curve.

[0023] The deviation correction amount is the difference between the measured irradiance sequence and the selected reference curve at the current time. Based on the deviation correction amount, the predicted value of the reference curve after the current time is shifted and corrected as a whole to obtain the corrected voltage prediction sequence.

[0024] Furthermore, the irradiance decrease intensity index is defined as the predicted voltage difference between the current sampling window and the next sampling window in the voltage prediction sequence;

[0025] When the irradiance decrease intensity index is zero or negative, the protection advance amount is maintained at the calibrated reference value;

[0026] When the irradiance decrease intensity index is positive, the scheduling unit adds an additional advance amount on the basis of the baseline protection advance amount. The additional advance amount is proportional to the irradiance decrease intensity index. The proportionality coefficient is determined in the calibration process by measuring the actual time required for the tensor processing unit to decrease from full load to the target power consumption state under different decrease rate conditions and written into the additional advance amount slope register.

[0027] Furthermore, the safety sampling threshold is determined in the factory calibration process by measuring the steady-state value of the bus voltage under no computational load conditions, subtracting the allowable input voltage deviation of the high-frequency sampling circuit under maximum noise conditions from the steady-state value, and writing it into the threshold register.

[0028] The narrowing range of the preventive power consumption reduction is calculated linearly based on the difference between the predicted voltage and the safety sampling threshold. The linear proportionality coefficient is determined in the calibration process by measuring the slope of the voltage response under different load conditions and written into the slope register.

[0029] Furthermore, the intelligent edge computing module adopts a microkernel architecture, which decomposes the operating system into a process management microkernel and several functional service processes. Each service process runs in an independent virtual address space and communicates with each other only through a formally verified message passing interface.

[0030] The photovoltaic optimization control path and the computing task execution path correspond to independent service processes. The two paths do not share any memory areas. The photovoltaic side control instructions have the highest scheduling priority, ensuring that any anomalies in the computing task cannot spread to the photovoltaic optimization control path.

[0031] Furthermore, the intelligent edge computing module integrates a hardware encryption accelerator on the data path of the tensor processing unit to encrypt the inference intermediate results and user data written to the on-chip cache in real time, and to decrypt the data read from the on-chip cache in real time.

[0032] The key is generated by an on-chip physically unclonable function circuit when the system is powered on. The physically unclonable function circuit uses manufacturing process deviations to generate a unique response value that is bound to the physical characteristics of the chip. After being processed by the key derivation function, it serves as the working key of the hardware encryption accelerator. The key exists only in the key register during power-on and is automatically cleared after power-off. No plaintext copy is left in any non-volatile storage medium.

[0033] The beneficial effects achieved by this invention are:

[0034] This invention addresses the problem of peak power consumption of the tensor processing unit interfering with the maximum power point tracking (MPPT) sampling accuracy due to the shared DC bus between the photovoltaic optimization chip and the intelligent edge computing module. The invention establishes a sampling timing coordination mechanism by setting a dedicated hardware interrupt line between the two chips. During the sampling protection window, the execution of high-power operators is postponed, allowing only low-power operators to continue running. This fundamentally eliminates the interference of peak power consumption of the tensor processing unit on the stability of the bus voltage within the MPPT sampling window, avoids the vicious coupling cycle caused by power point judgment offset, and improves photovoltaic power generation efficiency.

[0035] This invention employs a bus voltage prediction mechanism based on historical irradiance template matching to output a voltage prediction sequence covering multiple future sampling windows, transforming the system's response to bus voltage drops from passive to proactive prevention. Compared to the passive response methods in existing technologies based on instantaneous sample values, this invention can proactively implement preventative power consumption reduction measures based on irradiance variation trends. During periods of continuous irradiance decline, the system enters a stable computing power reduction process ahead of time, avoiding the passive triggering of the sampling protection mechanism due to prediction lag. This further ensures the stability of maximum power point tracking sampling accuracy under complex lighting conditions.

[0036] This invention simultaneously applies the output of the predicted sequence to two control parameters: preventative power consumption narrowing and dynamic adjustment of the protection lead, forming a coordinated control closed loop integrating prediction, narrowing, and lead. Compared to existing designs where power management and sampling timing are independent, this invention deeply couples the two mechanisms through an irradiance decrease intensity index. This allows the protection lead to adaptively extend with the predicted decrease intensity and automatically shrink to a baseline value during the irradiance stabilization phase to reduce interference with the inference task. While ensuring maximum power point tracking sampling accuracy, this maximizes the overall throughput of the inference task, achieving coordinated optimization of photovoltaic optimization and edge computing power within a single hardware unit.

[0037] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the overall structural framework of the present invention;

[0039] Figure 2 This is a schematic diagram of the sampling timing coordination mechanism of the present invention;

[0040] Figure 3 This is a schematic diagram of the power consumption marking and task scheduling mechanism of the present invention;

[0041] Figure 4This is a schematic diagram of the bus voltage predictive protection mechanism of the present invention;

[0042] Figure 5 This is a schematic diagram of the on-chip cache structure and execution location pointer recovery mechanism of the present invention. Detailed Implementation

[0043] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention.

[0044] Example 1.

[0045] This embodiment provides an integrated intelligent photovoltaic optimization and distributed edge computing system that combines optical computing with optical computing. Figure 1 The system integrates a photovoltaic optimization chip, an intelligent edge computing module, and a networking module into a single hardware unit through an integrated packaging and testing platform. The three share a power management layer and a heat dissipation substrate. The photovoltaic optimization chip supplies power to the intelligent edge computing module and the networking module through a DC bus.

[0046] The port voltage and current of the photovoltaic string are synchronously acquired by a closed-loop current sensor and a high-frequency sampling circuit, and then sent to the digital signal processing unit in the photovoltaic optimization chip. The digital signal processing unit runs an adaptive maximum power point tracking algorithm, which is based on the variable step size perturbation observation method. It dynamically adjusts the perturbation step size according to the power change rate within the continuous sampling period, quickly relocks the global maximum power point under local shading conditions, and drives the synchronous rectifier bridge to stabilize the string output to a uniform DC bus voltage.

[0047] Under the aforementioned shared bus architecture, the tensor processing unit in the intelligent edge computing module generates periodic power consumption peaks when performing inference calculations, causing the bus voltage to drop instantaneously within the MPPT sampling window. The photovoltaic optimization chip misjudges the voltage drop as a disturbance response, causing a power point judgment offset, which in turn triggers a vicious cycle of output reduction and further voltage drop.

[0048] To address the aforementioned issues, the system incorporates a dedicated hardware interrupt line between the photovoltaic optimization chip and the intelligent edge computing module. This interrupt line employs a unidirectional push-pull output drive, is active high, and features a filter capacitor to suppress glitches. It operates independently of the data bus and is used to implement a sampling timing coordination mechanism.

[0049] Combination Figure 2 The photovoltaic optimization chip has a built-in sampling clock counter, which operates synchronously with the sampling clock of the high-frequency sampling circuit. It automatically resets to zero and restarts counting at the end of each sampling cycle. When the counter value reaches a preset protection advance, the chip automatically pulls the hardware interrupt line high, triggering a hardware interrupt of the intelligent edge computing module. The protection advance is equal to the maximum response delay required for the intelligent edge computing module to complete the current low-power operator and enter the protection state from receiving the interrupt. This delay is determined through worst-case analysis during the system integration testing phase and written into the preset register of the sampling clock counter. The duration of the sampling window is controlled by the sampling timing register in the photovoltaic optimization chip. The sampling timing register starts at the beginning of sampling and triggers a sampling completion interrupt after it is full. After responding to the interrupt, the chip immediately pulls the hardware interrupt line low. The intelligent edge computing module exits the protection state after detecting the falling edge. Since the start and end times of the hardware interrupt line are actively controlled by the internal timing of the photovoltaic optimization chip, the intelligent edge computing module only passively responds to the edge signal. There is no need for a clock synchronization protocol between the two, eliminating the complexity of cross-chip clock domain alignment.

[0050] Combination Figure 3 During the inference model compilation phase, after completing operator fusion and memory planning, the compiler performs power consumption classification labeling on each operator node in the computation graph.

[0051] All operators involving large-scale parallel floating-point multiplication and addition operations, including matrix multiplication in fully connected layers, sliding window multiplication and addition in convolutional layers, transpose operations, and query key-value product calculations in attention mechanisms, are marked as high-power operations.

[0052] Operators whose computational cost is linearly related to the number of input tensor elements and do not involve large-scale parallel multiplication and addition, including ReLU, Sigmoid, LayerNorm, BatchNorm, MaxPooling, and element-level addition, are all marked as low-power operations.

[0053] The power consumption flag is attached to the operator node descriptor of the computation graph as a one-bit flag and loaded into on-chip storage along with the model file. During runtime, when the scheduling unit loads the operator node from the model file into the task execution queue, it simultaneously extracts the power consumption flag and maintains a power consumption flag queue that is strictly one-to-one with the task execution queue. When multiple inference tasks are executed concurrently, each task independently maintains its own power consumption flag queue. When responding to the sampling protection signal, the scheduling unit traverses the head of the power consumption flag queue of all active tasks, performs a suspension operation on all head operators marked as high power consumption, and allows head operators marked as low power consumption to continue execution until completion, thereby ensuring the integrity of the protection mechanism in concurrent scenarios.

[0054] Combination Figure 5The scheduling unit maintains an execution context structure for each active inference task, which includes a pointer to the current execution position of the computation graph, the starting address and length of the input tensor of the suspended operator in the on-chip cache. The on-chip cache is divided into a resident area and a protection cache. The resident area is used to store the normal calculation results of model weights and intermediate activation tensors. The protection cache is dedicated to storing snapshots of the input tensors of the suspended operators during the sampling protection window. The capacity of the protection cache is determined during the system design phase based on the product of the maximum number of supported concurrent tasks and the size of the input tensor of the maximum high-power operator in a single task, ensuring that in the worst case, the input tensors of the suspended operators of all concurrent tasks can be completely stored in the protection cache without overflow. When multiple consecutive sampling protection windows are triggered in a short period of time, if the previous protection window period Before a suspended high-power operator can resume execution, a new protection window arrives. The scheduling unit checks the execution position pointer of the operator. If the operator is still suspended, the original cache entry is reused directly without rewriting, thus preventing the protection buffer from overflowing due to continuous triggering. The read and write operations of the execution position pointer are implemented through hardware atomic instructions, ensuring the consistency of the pointer state in a multi-threaded scheduling environment. Any modification to the pointer by any thread is immediately visible to other threads, eliminating the risk of execution position disorder caused by race conditions. After the sampling window ends, the scheduling unit resumes execution from the execution position pointer. For operators that have saved input tensors, the input is read from the protection buffer and execution continues. For high-power operators that have not yet started, they are executed sequentially according to the original computation graph order, ensuring that the computation result of the inference task is completely consistent with that before the interruption.

[0055] Combination Figure 4 Based on the sampling timing coordination mechanism, the system further includes a bus voltage predictive protection mechanism.

[0056] The MPPT sampling period is determined by the overflow period of the sampling tick counter. This period is a fixed value and is written into a dedicated period register during system initialization.

[0057] The power sensing register reads the current count value of the period register at the end of each sampling sub-cycle and calculates the remaining time until the next sampling window arrives, using this as a time reference for prediction.

[0058] The power sensing register samples the bus voltage value at a fixed sub-cycle and synchronously records the measured irradiance sequence within the current time period. The system has several pre-set historical irradiance template curves in on-chip storage, each template corresponding to the intraday irradiance variation pattern under a typical weather pattern.

[0059] During operation, the system performs similarity matching between the measured irradiance sequence and each template curve, selects the template with the highest similarity as the reference curve for the current weather model, and predicts the bus voltage trend within several MPPT sampling periods based on the trend of the reference curve after the current moment and the deviation correction between the measured sequence and the template, and outputs a voltage prediction sequence covering multiple future sampling windows.

[0060] The safe sampling threshold is determined in the factory calibration process: the steady-state value of the bus voltage is measured under no calculated load conditions, and the allowable input voltage deviation of the MPPT sampling circuit under maximum noise conditions is subtracted from the steady-state value to obtain the safe sampling threshold, which is then written into the threshold register.

[0061] When the predicted voltage corresponding to any sampling window in the prediction sequence is lower than the safe sampling threshold, the scheduling unit performs preventive power narrowing for that sampling window. The narrowing magnitude is calculated linearly based on the difference between the predicted voltage of the corresponding sampling window and the safe sampling threshold. When the difference is zero, the narrowing magnitude is zero. When the difference reaches the calibrated maximum difference, the tensor processing unit is limited to the lowest power consumption state. The linear scaling factor is determined in the calibration process by measuring the voltage response slope under different load conditions and written into the slope register.

[0062] Based on the preventive power consumption reduction, the system further applies the output of the predicted sequence to the dynamic adjustment of the protection lead in the sampling timing coordination mechanism.

[0063] The system defines the predicted voltage difference between the current sampling window and the next sampling window in the prediction sequence as the irradiance drop intensity index, which reflects the expected drop in bus voltage within a future sampling period.

[0064] The dispatching unit dynamically adjusts the protection lead time based on the irradiance reduction intensity index:

[0065] When the intensity decline index is zero or negative, it indicates that the irradiance prediction is stable or rising, and the protection lead time is maintained at the calibrated baseline value.

[0066] When the descent intensity index is positive, the scheduling unit adds an additional advance amount on the basis of the baseline protection advance amount. The additional advance amount is proportional to the descent intensity index. The proportional coefficient is determined in the calibration process by measuring the actual time required for the tensor processing unit to descend from full load to the target power consumption state under different descent rates and written into the additional advance amount slope register.

[0067] The superimposed protection advance is written into the preset register of the sampling clock counter and takes effect in the next sampling cycle.

[0068] The above dynamic correction causes the triggering time of the hardware interrupt line to be advanced as the predicted decrease intensity increases during the continuous decrease phase of irradiance. This gives the tensor processing unit more time to complete the current low-power operator and enter the protection state, avoiding the situation where high-power operations are not completely suspended within the sampling window due to insufficient unloading time.

[0069] During the irradiance stabilization phase, the protection lead is reduced to the baseline value, decreasing the cumulative duration of the tensor processing unit in the protection state, thereby improving the overall throughput of the inference task.

[0070] Preventive power consumption reduction and dynamic protection advance work together in terms of timing: the power consumption reduction command is issued in advance according to the predicted sequence, and the dynamically extended protection advance causes the hardware interrupt triggering time to be advanced accordingly. The two work together to ensure that the bus voltage is in a convergent and stable state when the sampling window arrives, forming a three-in-one coordinated control closed loop of prediction, reduction and advance.

[0071] The update of the prediction sequence, the issuance of power narrowing instructions, and the writing of protection lead are all completed within one sub-sampling period, ensuring that the above-mentioned coordinated control actions take effect before the corresponding sampling window arrives.

[0072] The aforementioned predictive protection mechanism transforms the system's response to bus voltage dips from passive to proactive prevention, and is deeply coupled with the sampling timing coordination mechanism to jointly ensure the stability of MPPT sampling accuracy under bus voltage fluctuation conditions.

[0073] The intelligent edge computing module adopts a microkernel architecture. The photovoltaic optimization control path and the computing task execution path run in independent service processes. The two paths do not share any memory areas and communicate with each other only through a formally verified message passing interface. The photovoltaic side control instructions have the highest scheduling priority, ensuring that any anomalies in the computing task cannot propagate to the photovoltaic optimization control path.

[0074] The networking module supports multiple network interfaces. After power-on, the node registers with the external computing power scheduling platform, periodically reports the current available computing power and photovoltaic output status, and receives inference task shards from the external platform. The tensor processing unit performs the calculations and returns the results. For user data during task execution, the system integrates a hardware encryption accelerator on the data path of the tensor processing unit. The key is generated by an on-chip physically unclonable function and no plaintext copy is stored in any external storage medium. When the DC bus output continuously exceeds the full-load computing power, the excess power is fed back to the local AC grid via the bidirectional inverter interface.

[0075] Example 2:

[0076] This embodiment provides a hardware implementation method for an integrated intelligent photovoltaic optimization and distributed edge computing system that combines optical computing with optical computing.

[0077] The integrated packaging and testing platform adopts system-level packaging technology, which integrates photovoltaic optimization chips, intelligent edge computing modules and networking modules into a single package using a multi-layer stacking method.

[0078] The photovoltaic optimization chip is placed on the substrate layer of the package, the intelligent edge computing module is interconnected and stacked on the photovoltaic optimization chip through silicon vias, and the networking module is fixed to the side of the package with an RF isolation cavity.

[0079] Inter-chip signal transmission between the three is achieved through a rewiring layer. The rewiring layer also carries the power supply network of the power management layer, distributing the DC bus voltage output by the photovoltaic optimization chip to each power supply domain of the intelligent edge computing module and the networking module.

[0080] The heat dissipation substrate is located at the bottom of the package and contacts the back of the photovoltaic optimization chip and the intelligent edge computing module through a thermally conductive interface material, dissipating the heat generated by both outwards.

[0081] The package only exposes the DC input interface, network interface, and hardware debugging interface to the outside.

[0082] The dedicated hardware interrupt line is implemented inside the package through an independent metal trace in the redistribution layer. This trace maintains sufficient spacing from the trace carrying the data bus signal to avoid crosstalk. The two ends of the trace are connected to the general output pin of the photovoltaic optimization chip and the external interrupt input pin of the intelligent edge computing module, respectively.

[0083] The driving circuit on the photovoltaic optimization chip side adopts a push-pull output structure, which consists of a P-type field-effect transistor and an N-type field-effect transistor connected in series. When the output level is high, the P-type transistor is turned on and the N-type transistor is turned off. When the output level is low, the N-type transistor is turned on and the P-type transistor is turned off. The driving capability meets the capacitive load requirements on the interrupt line.

[0084] A filter capacitor is connected in parallel on the interrupt line. One end of the capacitor is connected to the interrupt line and the other end is grounded. This is used to filter out glitches and interference caused by high-frequency switching operations on the trace.

[0085] The external interrupt input pin on the intelligent edge computing module side is configured in edge-triggered mode. The rising edge triggers the interrupt service routine to enter the protection state, and the falling edge triggers the interrupt service routine to exit the protection state.

[0086] The sampling clock counter consists of a synchronous counter that is from the same source as the sampling clock of the high-frequency sampling circuit. The clock input of the counter is directly connected to the sampling clock output of the high-frequency sampling circuit to ensure that the counting clocks of the two are strictly aligned.

[0087] The counter is equipped with a synchronous clear terminal. At the end of each sampling cycle, the high-frequency sampling circuit outputs a single-cycle pulse to the synchronous clear terminal of the counter to clear the counter and start the next round of counting.

[0088] The current count value of the counter is continuously compared with the stored value in the preset register by a hardware comparator. When the two are equal, the comparator outputs a high level, triggering the internal logic of the photovoltaic optimization chip to pull up the hardware interrupt line.

[0089] The preset register is connected to the debug interface through the internal register configuration bus of the chip. It supports writing the protection advance calibration value during the system integration test phase. The write operation is controlled by the write protection bit and cannot be overwritten during normal operation.

[0090] The sampling timing register consists of an independent decrementing counter. At the start of sampling, the control logic of the photovoltaic optimization chip loads the preset value of the sampling window duration into the counter. The counter decrements at a fixed clock. When it reaches zero, a sampling completion interrupt is triggered. After responding to the interrupt, the control logic pulls the hardware interrupt line low through a push-pull drive circuit.

[0091] The power sensing register consists of a sample-and-hold circuit and an analog-to-digital converter connected in series. The input of the sample-and-hold circuit is connected to the voltage divider detection point of the DC bus to sample and hold the bus voltage at a fixed sub-cycle. The analog-to-digital converter converts the held analog voltage value into a digital value and stores it in the register buffer.

[0092] The register buffer adopts a circular queue structure, and the queue depth corresponds to the length of the historical sampling window required for the difference calculation. Each new sample value is written to the head of the queue and overwrites the oldest sample value.

[0093] The first-order difference calculation unit consists of a subtractor array and a mean calculation circuit. The subtractor array subtracts adjacent sampled values ​​in the circular queue one by one to obtain a difference sequence. The mean calculation circuit sums the difference sequence and then performs a shift operation to obtain the mean, which is output as an estimate of the current voltage drop rate to the predictive control logic.

[0094] The irradiance sampling circuit is set up independently. Its input is connected to the output of the irradiance sensor on the photovoltaic string side. The sampling results are stored in the on-chip irradiance sequence buffer for template matching logic to read.

[0095] The on-chip cache is divided into two parts in the physical address space: a resident area and a protection cache area. A hardware address boundary register is set between the two. The value of the boundary register is written during system initialization and locked by write protection bits to prevent accidental modification during runtime.

[0096] The resident area is used to store model weights and intermediate activation tensors during the inference process. The starting address of the protection buffer is determined by the boundary register and is dedicated to storing snapshots of input tensors of operators that are suspended during the sampling protection window.

[0097] When the scheduling unit writes a tensor snapshot to the protection buffer, it monitors in real time whether the write address exceeds the physical boundary of the protection buffer through a hardware address out-of-bounds detection circuit. Once an out-of-bounds error is detected, an abnormal interrupt is immediately triggered, notifying the scheduling unit to stop the current write operation and report an overflow error, so as to prevent the protection buffer from overflowing and overwriting the resident area data.

[0098] The execution position pointer is stored in a dedicated register inside the scheduling unit. The read and write operations of this register are guaranteed to be atomic through a hardware mutex circuit. During the read and write operation, the mutex circuit generates a wait signal for other access requests until the current operation is completed, thus eliminating race conditions in a multi-threaded environment.

[0099] The hardware encryption accelerator is integrated into the data path of the intelligent edge computing module, located between the data output end of the tensor processing unit and the data input end of the on-chip cache resident area. It encrypts the inference intermediate results and user data written to the resident area in real time, and decrypts the data read from the resident area in real time. The encryption and decryption operations are performed transparently on the data path and do not occupy the computing resources of the tensor processing unit.

[0100] The physically unclonable function circuit consists of several ring oscillator units that generate unique responses by utilizing manufacturing process deviations. When the system is powered on, the physically unclonable function circuit outputs a unique response value that is bound to the physical characteristics of the chip. This response value is processed by the key derivation function and used as the working key of the hardware encryption accelerator. The key exists only in the key register during power-on and is automatically cleared after power-off. No plaintext copy is left in any non-volatile storage medium.

[0101] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of protection of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the scope of protection of the present invention. Furthermore, the elements therein can be updated as technology develops.

Claims

1. A smart photovoltaic optimization and distributed edge computing integrated system, characterized in that, The system integrates a photovoltaic optimization chip, an intelligent edge computing module, and a networking module into a single hardware unit through an integrated packaging and testing platform. The three share a power management layer and a heat dissipation substrate. The photovoltaic optimization chip supplies power to the intelligent edge computing module and the networking module through a DC bus. The photovoltaic optimization chip includes a closed-loop current sensor, a high-frequency sampling circuit, and a digital signal processing unit. The closed-loop current sensor and the high-frequency sampling circuit synchronously acquire the port voltage and current of the photovoltaic string. The acquired data is sent to the digital signal processing unit, which runs an adaptive maximum power point tracking algorithm to drive the synchronous rectifier bridge to regulate the output voltage of the photovoltaic string to the DC bus voltage. A dedicated hardware interrupt line is provided between the photovoltaic optimization chip and the intelligent edge computing module. Before the adaptive maximum power point tracking algorithm enters the sampling phase, the photovoltaic optimization chip sends a sampling protection signal to the intelligent edge computing module through the hardware interrupt line. After the scheduling unit in the intelligent edge computing module responds to the sampling protection signal, it only allows low-power operations to continue to be executed during the sampling protection window, and postpones high-power operations until the sampling window ends. After the photovoltaic optimization chip completes sampling, it sends a sampling release signal through the hardware interrupt line. After the scheduling unit responds to the sampling release signal, it resumes the normal scheduling of high-power operations. The system is equipped with a bus voltage predictive protection mechanism. The power sensing register samples the bus voltage value at a fixed sub-cycle and synchronously records the measured irradiance sequence. The system has several historical irradiance template curves pre-set in on-chip storage. During operation, the measured irradiance sequence is matched with each template curve for similarity, and the template with the highest similarity is selected as the reference curve. Based on the trend of the reference curve after the current moment and the deviation correction between the measured sequence and the template, a voltage prediction sequence covering multiple future sampling windows is output. When the predicted voltage corresponding to any sampling window in the voltage prediction sequence is lower than the safe sampling threshold, the scheduling unit performs preventive power consumption narrowing for that sampling window. At the same time, the protection advance of the sampling protection signal is dynamically adjusted according to the irradiance decrease intensity index defined by the difference in predicted voltage between adjacent sampling windows. The dynamically adjusted protection advance is written into the preset register of the sampling clock counter and takes effect in the next sampling cycle, forming a three-in-one coordinated control closed loop of prediction, narrowing and advance.

2. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 1, characterized in that, During the inference model compilation phase, the compiler marks each operator node in the computation graph with a power consumption flag based on the operator type. Operators involving large-scale parallel floating-point multiplication and addition operations are marked as high-power operations, while operators whose computational load is linearly related to the number of input tensor elements and do not involve large-scale parallel multiplication and addition operations are marked as low-power operations. The power consumption flag is attached to the operator node descriptor in the form of a one-bit flag and loaded into on-chip storage along with the model file. During runtime, the scheduling unit simultaneously extracts power consumption flags and maintains a power consumption flag queue that is strictly one-to-one with the task execution queue when loading operator nodes into the task execution queue. When multiple inference tasks are executed concurrently, each task independently maintains its own power consumption flag queue. When the scheduling unit responds to the sampling protection signal, it traverses the head of the power consumption flag queue of all active tasks, performs a suspension operation on the head operators marked as high power consumption, and allows the head operators marked as low power consumption to continue execution until completion.

3. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 2, characterized in that, The scheduling unit maintains an execution context structure for each active inference task. The execution context structure includes a pointer to the current execution position of the computation graph, the starting address and length of the input tensor of the suspended operator in the on-chip cache. The on-chip cache is divided into two parts: a resident area and a protection cache. The resident area is used to store the normal calculation results of model weights and intermediate activation tensors, while the protection cache is dedicated to storing snapshots of input tensors of operators that are suspended during the sampling protection window. After the sampling window ends, the scheduling unit resumes execution from the execution position pointer. For operators that have saved input tensors, the input is read from the protection buffer and execution continues. For high-power operators that have not yet started, they are executed sequentially according to the original computation graph order.

4. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 3, characterized in that, When multiple consecutive sampling protection windows are triggered in a short period of time, if the high-power operator that was suspended during the previous protection window has not yet completed its recovery execution, and a new protection window arrives again, the scheduling unit checks the execution position pointer of the operator. If the operator is still in a suspended state, the original cache entry is directly reused without being written repeatedly. The read and write operations of the execution position pointer are implemented through hardware atomic instructions, ensuring the consistency of the pointer state in a multi-threaded scheduling environment.

5. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 4, characterized in that, The photovoltaic optimization chip has a built-in sampling clock counter, which runs synchronously with the sampling clock of the high-frequency sampling circuit. It automatically resets to zero and starts counting again at the end of each sampling cycle. When the count value reaches a preset protection advance amount, the photovoltaic optimization chip automatically pulls up the hardware interrupt line to trigger the hardware interrupt of the intelligent edge computing module. The protection advance amount is written into the preset register of the sampling clock counter. The photovoltaic optimization chip has a built-in sampling timing register. The sampling timing register starts when sampling begins and triggers a sampling completion interrupt when it is full. In response to the sampling completion interrupt, the photovoltaic optimization chip pulls the hardware interrupt line low. The intelligent edge computing module exits the protection state after detecting the falling edge.

6. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 5, characterized in that, The historical irradiance template curve is determined by collecting historical irradiance data under various typical weather patterns and pre-stored in on-chip storage before the system leaves the factory. The similarity matching is achieved by measuring the distance between the measured irradiance sequence and the corresponding interval of each template curve in the current time period, and the template with the smallest distance is selected as the reference curve. The deviation correction amount is the difference between the measured irradiance sequence and the selected reference curve at the current time. Based on the deviation correction amount, the predicted value of the reference curve after the current time is shifted and corrected as a whole to obtain the corrected voltage prediction sequence.

7. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 6, characterized in that, The irradiance decrease intensity index is defined as the predicted voltage difference between the current sampling window and the next sampling window in the voltage prediction sequence. When the irradiance decrease intensity index is zero or negative, the protection advance amount is maintained at the calibrated reference value; When the irradiance decrease intensity index is positive, the scheduling unit adds an additional advance amount on the basis of the baseline protection advance amount. The additional advance amount is proportional to the irradiance decrease intensity index. The proportionality coefficient is determined in the calibration process by measuring the actual time required for the tensor processing unit to decrease from full load to the target power consumption state under different decrease rate conditions and written into the additional advance amount slope register.

8. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 7, characterized in that, The safety sampling threshold is determined in the factory calibration process by measuring the steady-state value of the bus voltage under no-calculation load conditions, subtracting the allowable input voltage deviation of the high-frequency sampling circuit under maximum noise conditions from the steady-state value, and writing it into the threshold register. The narrowing range of the preventive power consumption reduction is calculated linearly based on the difference between the predicted voltage and the safety sampling threshold. The linear proportionality coefficient is determined in the calibration process by measuring the slope of the voltage response under different load conditions and written into the slope register.

9. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 8, characterized in that, The intelligent edge computing module adopts a microkernel architecture, which decomposes the operating system into a process management microkernel and several functional service processes. Each service process runs in an independent virtual address space and communicates with each other only through a formally verified message passing interface. The photovoltaic optimization control path and the computing task execution path correspond to independent service processes. The two paths do not share any memory areas. The photovoltaic side control instructions have the highest scheduling priority, ensuring that any anomalies in the computing task cannot spread to the photovoltaic optimization control path.

10. The integrated intelligent photovoltaic optimization and distributed edge computing system as described in claim 9, characterized in that, The intelligent edge computing module integrates a hardware encryption accelerator on the data path of the tensor processing unit to encrypt the inference intermediate results and user data written to the on-chip cache in real time, and to decrypt the data read from the on-chip cache in real time. The key is generated by an on-chip physically unclonable function circuit when the system is powered on. The physically unclonable function circuit uses manufacturing process deviations to generate a unique response value that is bound to the physical characteristics of the chip. After being processed by the key derivation function, it serves as the working key of the hardware encryption accelerator. The key exists only in the key register during power-on and is automatically cleared after power-off. No plaintext copy is left in any non-volatile storage medium.

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