A heterogeneous interface resource comprehensive interaction method and system suitable for a multi-core processor
By integrating heterogeneous interface resources between multi-core processors and FPGAs, the problems of priority arbitration and preemption of high-priority tasks in multi-task concurrency scenarios are solved, achieving deterministic hard real-time transmission and efficient utilization of interface resources.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NARI NANJING CONTROL SYSTEM CO LTD
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies cannot achieve priority arbitration in multi-task concurrent scenarios during data interaction between multi-core processors and FPGAs, cannot achieve priority transmission between different independent cores and FPGAs through the same physical channel, and lack a preemption mechanism for high-priority tasks to low-priority tasks, thus failing to meet the requirements of hard real-time transmission.
By acquiring the metadata of the task data packets, sorting them according to task priority and deadline, abstracting the physical interface into a unified logical resource pool, constructing interface allocation rules for time slots and bandwidth, and introducing hardware-level preemption logic to dynamically adjust bandwidth weights, the real-time transmission of high-priority tasks is ensured.
It achieves microsecond-level latency limits for hard real-time tasks, eliminates the risk of priority inversion, improves the aggregation scheduling of multi-type task data and the utilization rate of interface resources, and meets the real-time requirements of industrial control and power systems.
Smart Images
Figure CN122431883A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of embedded computing architecture, and in particular relates to a method and system for the integrated interaction of heterogeneous interface resources applicable to multi-core processors. Background Technology
[0002] In the field of embedded computing architecture, the collaborative work of multi-core processors and FPGAs has become a key technical solution for realizing complex real-time control systems. With the increasing demands for real-time data processing in applications such as industrial control, power system protection, and intelligent manufacturing, how to achieve efficient and deterministic data interaction between multi-core processors and FPGAs has become a pressing technical problem to be solved in this field.
[0003] In the prior art, there are already technical solutions for implementing network data packet transmission through the cooperation of multi-core processors and FPGAs. For example, CN201811361357 discloses a shared MAC implementation system and method based on a multi-core processor and FPGA. The system includes a multi-core processor end and an FPGA end. The multi-core processor end includes multiple cores, a transceiver data module, and a data arbitration module. The FPGA end includes an FPGA interface configuration register, a MAC module, and a priority arbitration module. Its working principle is as follows: each core of the multi-core processor sends network data packets to the transceiver data module, which processes them and then transmits them to the FPGA end. The FPGA end uses the priority arbitration module to determine the transmission order of network data packets according to the real-time data priority level of the cores, and then sequentially passes the network data packets to the MAC module for transmission.
[0004] However, the aforementioned prior art has the following technical defects:
[0005] 1. Existing technologies only implement priority arbitration transmission of single network data packets, and do not implement priority arbitration between different types of task data when multiple types of task data are aggregated and transmitted, making it difficult to meet the hard real-time transmission requirements of specific task data in multi-task concurrent scenarios.
[0006] 2. Existing technologies only consider priority arbitration transmission when the data to be transmitted is already inside the FPGA, without considering the priority of data transmission between different independent cores of a multi-core processor and the FPGA through the same physical channel.
[0007] 3. Existing technologies only implement a priority-based sequential transmission mechanism, failing to implement a preemptive mechanism for high-priority task data transmission over low-priority task data transmission. This easily leads to priority inversion issues. For example, if low-priority task data is currently being transmitted, and a sudden demand for high-priority task data transmission arises, the high-priority task data transmission can only proceed after the low-priority task data transmission is completed. This cannot meet the hard real-time transmission requirements of high-priority task data, and the waiting time depends on the time required for the low-priority task data transmission to complete. Summary of the Invention
[0008] Purpose of the invention: This invention provides a heterogeneous interface resource integration and interaction method and system applicable to multi-core processors, aiming to solve the problems existing in the prior art, such as the inability to perform priority arbitration transmission of network data packets in multi-task concurrent scenarios, the inability to realize priority transmission of data between different independent cores of multi-core processors and FPGAs through the same physical channel, and the lack of a preemption mechanism for high-priority task data transmission to low-priority task data transmission.
[0009] The present invention also provides a computer device that aims to solve the problems existing in the prior art, such as the inability to achieve efficient priority scheduling and management of heterogeneous interface resources in a multi-core processor environment, the inability to guarantee the real-time and deterministic nature of critical task data in concurrent transmission scenarios, and the lack of a flexible priority preemption mechanism to optimize the overall system throughput performance.
[0010] The present invention also provides a computer-readable storage medium, which aims to solve the problems existing in the prior art, such as the inability to provide executable priority arbitration logic for the integrated interaction of heterogeneous interface resources of multi-core processors, the inability to support priority data transmission programs between multi-core processors and FPGAs based on the same physical channel, and the lack of a data transmission control instruction set for implementing high-priority tasks to preempt low-priority tasks.
[0011] Technical solution: The present invention provides a method for integrating and interacting heterogeneous interface resources applicable to multi-core processors, comprising:
[0012] The task data packets generated by each core processor are obtained, and the metadata of each task data packet is extracted; the metadata includes task priority, service type, data length, and deadline; the service type includes hard real-time task, soft real-time task, and non-real-time task.
[0013] The metadata of each task data packet is input into a global queue and sorted according to task priority as the primary factor and deadline as the secondary factor. The physical interface is abstracted into a unified logical resource pool. The physical interface includes dedicated physical interfaces and non-dedicated physical interfaces.
[0014] The physical interface allocation scheme is initialized based on task priority and physical interface characteristics; interface allocation rules based on time slots and bandwidth are constructed, and the physical interface allocation scheme is adjusted using the interface allocation rules; based on the adjusted allocation scheme, metadata is transmitted sequentially from the global queue to the corresponding physical interface, and the metadata is packaged into data packets and transmitted to the FPGA end through the physical interface; the link load of each physical interface is monitored, and the bandwidth weight of each physical interface is dynamically adjusted.
[0015] If the metadata task priority is the highest priority, and the metadata is allocated to a non-dedicated physical interface according to the adjusted allocation scheme, and the non-dedicated physical interface is currently transmitting a non-highest priority data packet, then the hardware-level preemption logic is triggered to pause the transmission of the non-highest priority data packet, package the highest priority metadata into a data packet and transmit it to the FPGA end, and then resume the transmission of the non-highest priority data packet.
[0016] After receiving the complete transmitted data packet, the FPGA parses and transmits the data packet to the processing line.
[0017] Furthermore, the sorting of metadata by task priority as the primary factor and deadline as the secondary factor includes: first sorting the metadata by task priority, and then sorting metadata with the same priority by deadline.
[0018] Furthermore, the physical interface allocation scheme based on task priority and physical interface characteristics includes: if the physical interface is a dedicated physical interface, then determining the transmission conditions of the dedicated physical interface, including transmitting only the task priority and data length, and initializing the dedicated physical interface to transmit only the metadata corresponding to the task priority and data length; if the physical interface is a non-dedicated physical interface, then initializing the non-dedicated physical interface to transmit metadata of all priorities.
[0019] Furthermore, the interface allocation rules based on time slots and bandwidth include: if the metadata meets the transmission conditions of a dedicated physical interface, the metadata is allocated to the dedicated physical interface; otherwise, the metadata is allocated to a non-dedicated physical interface, and a fixed period of time slots is reserved in the non-dedicated physical interface for hard real-time tasks. When hard real-time services send and receive within the fixed time slots, they do not need to preempt the overall channel and bus resources; a weighted round-robin mechanism is adopted to allocate the remaining bandwidth of the non-dedicated physical interface to soft real-time tasks and non-real-time tasks.
[0020] Furthermore, the dynamic adjustment of the bandwidth weight of each physical interface includes: real-time collection of load indicators of each physical interface, including link utilization, cache queue backlog length, and real-time throughput; weighted summation of each load indicator to obtain a comprehensive load index; if the comprehensive load index of a physical interface exceeds a preset load upper limit, the bandwidth weight of the physical interface is reduced; if the comprehensive load index of a physical interface is lower than a preset load lower limit, the bandwidth weight of the physical interface is increased.
[0021] Furthermore, the hardware-level preemption logic includes: pausing the transmission of non-highest priority data packets via a non-dedicated physical interface and storing unsent data packet fragments in a breakpoint buffer to preserve the transmission context; using the non-dedicated physical interface to package the highest priority metadata into a data packet and transmitting it to the FPGA, where the FPGA parses and transmits it to the corresponding processing line; after the highest priority task is completed, the FPGA sends an execution completion confirmation signal; the non-dedicated physical interface reads the unsent data packet fragments from the breakpoint buffer, adds a resume flag to the header of the data packet, and transmits it to the FPGA; the FPGA identifies the resume flag, receives the unsent data packet fragments, and uses Block RAM for temporary storage, splicing, and verification.
[0022] Furthermore, the step of parsing and transmitting the data packet to the processing line includes: parsing the metadata of the data packet, extracting the task priority, and sending the data packet to the corresponding processing pipeline in order of task priority.
[0023] The present invention provides a heterogeneous interface resource integration and interaction system applicable to multi-core processors, comprising:
[0024] The feature extraction module is used to acquire task data packets generated by each core processor and extract metadata of each task data packet; the metadata includes task priority, service type, data length, and deadline; the service type includes hard real-time task, soft real-time task, and non-real-time task.
[0025] The global virtual queue manager is used to input the metadata of each task data packet into the global queue and sort the metadata in order of task priority as the primary factor and deadline as the secondary factor.
[0026] The resource virtualization unit is used to abstract physical interfaces into a unified logical resource pool; physical interfaces include dedicated physical interfaces and non-dedicated physical interfaces.
[0027] The dynamic allocation strategy unit is used to initialize the allocation scheme of physical interfaces based on task priority and physical interface characteristics; construct interface allocation rules based on time slots and bandwidth, and adjust the allocation scheme of physical interfaces using the interface allocation rules; based on the adjusted allocation scheme, transmit metadata from the global queue to the corresponding physical interface in sequence, and package the metadata into data packets through the physical interface and transmit them to the FPGA end; monitor the link load of each physical interface and dynamically adjust the bandwidth weight of each physical interface.
[0028] The hardware-level preemption control unit is used to trigger hardware-level preemption logic if the metadata task priority is the highest priority, and the metadata is allocated to a non-dedicated physical interface according to the adjusted allocation scheme, and the non-dedicated physical interface is currently transmitting a non-highest priority data packet. This logic pauses the transmission of non-highest priority data packets, packages the highest priority metadata into a data packet and transmits it to the FPGA, and then resumes the transmission of non-highest priority data packets.
[0029] The FPGA receiving / transmitting processing unit is used to parse and transmit the data packet to the processing line after the FPGA receives the complete transmitted data packet.
[0030] The computer device of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above method.
[0031] The present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described method.
[0032] Beneficial effects: Compared with the prior art, the present invention has the following advantages:
[0033] 1. Achieving deterministic hard real-time transmission: This invention introduces time slot reservation and hardware-level preemption mechanisms to ensure that the transmission delay of the highest priority tasks (such as emergency braking commands and fault protection signals) is strictly limited to the microsecond range, and is not affected by the blocking of low-priority large data packets (such as log uploads and image transmissions), thus meeting the stringent requirements of hard real-time in scenarios such as industrial control and power systems.
[0034] 2. Solving the problem of aggregation and scheduling of multi-type task data: This invention breaks through the limitation of traditional solutions that only arbitrate single network data packets. It simultaneously processes multiple heterogeneous data such as control flow, data flow, and video flow, and performs cross-type priority arbitration in a unified global queue to achieve optimal resource allocation in multi-core and multi-task scenarios.
[0035] 3. Eliminate priority inversion: This invention implements dynamic preemption through hardware logic, allowing high-priority tasks to interrupt low-priority tasks at any time, fundamentally eliminating the risk of uncontrollable delay caused by priority inversion.
[0036] 4. Improve the utilization rate of heterogeneous interface resources: This invention pools various physical interface resources such as SPI, PCIe, and GMAC and dynamically allocates bandwidth, avoiding situations where a single interface is congested while other interfaces are idle. The system can adaptively adjust the load of each link according to real-time traffic characteristics, improving overall throughput and the comprehensive utilization rate of interface resources. Attached Figure Description
[0037] Figure 1 This is a flowchart of the method of the present invention.
[0038] Figure 2 This is a schematic diagram of the system of the present invention.
[0039] Figure 3 This is a schematic diagram of the heterogeneous interface resource aggregation and scheduling module in this invention.
[0040] Figure 4 This is a schematic diagram of the FPGA-side receiving / transmitting processing unit in this invention.
[0041] Figure 5 This is a schematic diagram of an embodiment. Detailed Implementation
[0042] like Figure 1 As shown, the heterogeneous interface resource integration and interaction method applicable to multi-core processors described in this invention includes:
[0043] Multi-core processors run an operating system (OS) or a real-time environment (BM) without an operating system. Each independent core generates different types of task data, such as control instructions, sensor data, and video streams, and tags them with metadata tags including task priority, service type, and deadline timestamp to form task data packets.
[0044] Obtain the task data packets generated by each core processor and extract the metadata of each task data packet, including task priority (Level0-LevelN, with Level0 having the highest priority), business type (hard real-time task, soft real-time task, non-real-time task), data length, deadline, etc.
[0045] The metadata of each task data packet is input into a global queue and sorted according to task priority as the primary factor and deadline as the secondary factor. Physical interfaces are abstracted into a unified logical resource pool, including dedicated physical interfaces and non-dedicated physical interfaces. Both types of physical interfaces are standardized logically modeled and uniformly encapsulated into consistent, schedulable logical interface resources, which are then centrally managed by the logical resource pool. The global queue is a virtualized waiting queue. For newly added metadata, it is first sorted according to task priority, and metadata with the same priority is then sorted according to deadline.
[0046] The physical interface allocation scheme is initialized based on task priority and physical interface characteristics: If the physical interface is a dedicated physical interface, the transmission conditions of the dedicated physical interface are determined, including transmitting only the task priority and data length, and the dedicated physical interface is initialized to transmit only the metadata corresponding to the task priority and data length; if the physical interface is a non-dedicated physical interface, the non-dedicated physical interface is initialized to transmit metadata of all priorities.
[0047] Construct interface allocation rules based on time slots and bandwidth: If the metadata meets the transmission conditions of a dedicated channel, then the metadata is allocated to the dedicated channel; otherwise, the metadata is allocated to a non-dedicated physical interface, and a fixed period of time slots is reserved for hard real-time tasks in the non-dedicated physical interface. When hard real-time services send and receive within the fixed time slots, they do not need to preempt the overall channel and bus resources, thus ensuring latency determinism from the time dimension; in the non-dedicated physical interface, a weighted round-robin mechanism is used to allocate the remaining bandwidth for soft real-time tasks and non-real-time tasks.
[0048] The physical interface allocation scheme is adjusted using the interface allocation rules; based on the adjusted allocation scheme, metadata is transmitted sequentially from the global queue to the corresponding physical interface, and the metadata is packaged into a data packet and transmitted to the FPGA end through the physical interface.
[0049] The system calculates the link load of each physical interface in real time and dynamically adjusts the bandwidth weight of each physical interface. Specifically, the system collects load indicators such as link utilization, buffer queue backlog length, and real-time throughput of each physical interface in real time, and performs a weighted summation of these load indicators to obtain a comprehensive load index. If the comprehensive load index of a physical interface exceeds the preset load limit, indicating that the physical interface is overloaded and experiencing congestion, the bandwidth weight of the physical interface is reduced to limit the continuous injection of new traffic. If the comprehensive load index of a physical interface is below the preset load lower limit, indicating that the physical interface is underloaded and has surplus resources, the bandwidth weight of the physical interface is increased to guide the adaptive diversion and migration of service traffic. By dynamically optimizing and adjusting the bandwidth scheduling weight of each interface, under the premise that the upper limit of physical interface bandwidth is fixed, the system achieves multi-interface load balancing, avoids single-link overload and congestion problems, and improves the overall transmission resource utilization.
[0050] If the metadata task priority is the highest priority, and the metadata is allocated to a non-dedicated physical interface according to the adjusted allocation scheme, and the non-dedicated physical interface is currently transmitting a non-highest priority data packet, then hardware-level preemption logic is triggered: an interrupt signal or pause signal is immediately generated and sent to the controller of the physical interface allocated the highest priority; the current non-highest priority data packet is truncated or marked as recoverable at the boundary; the transmission status of the non-highest priority data packet is suspended, and the unsent data packet fragments are stored in the breakpoint buffer, saving the context; then the highest priority metadata is packaged into a data packet and transmitted to the FPGA, which parses it and transmits it to the corresponding processing line; after the highest priority data packet is transmitted, the FPGA sends an execution completion confirmation signal; the transmission of the suspended non-highest priority data packet is resumed, the non-dedicated physical interface reads the unsent data packet fragments from the breakpoint buffer, adds a resume flag to the data packet header, and transmits it to the FPGA; the FPGA recognizes the resume flag, receives the unsent data packet fragments, and uses Block RAM for temporary storage, splicing, and verification. Through hardware-level preemption logic, the priority inversion problem is completely avoided without re-establishing a connection.
[0051] After receiving the data stream, the FPGA parses the metadata header of the data packets, extracts the task priority, and sends the data packets to the corresponding processing pipelines in order of task priority. For data packets that have been preempted and fragmented, the FPGA's internal cache is used to reassemble them to ensure the integrity of the data received by the upper-layer logic, and the data is then sent to the corresponding processing line according to priority.
[0052] Example 2
[0053] like Figure 2 As shown in Embodiment 1, the heterogeneous interface resource integration and interaction system applicable to multi-core processors according to the present invention includes:
[0054] On the multi-core processor side, it is used to run the operating system (OS) or the real-time environment (BM) without an operating system. Each independent kernel generates different types of task data, such as control instructions, sensor data, video streams, etc., and adds metadata tags including task priority, business type, and deadline timestamp to form task data packets.
[0055] The heterogeneous interface resource aggregation and scheduling module is deployed in the driver layer or dedicated coprocessor between the multi-core processor and the FPGA, such as... Figure 3 As shown, it includes a feature extraction module, a global virtual queue manager, a resource virtualization unit, a dynamic allocation strategy unit, and a hardware-level preemption control unit, etc.
[0056] The feature extraction module is used to obtain the task data packets generated by each core processor and extract the metadata of each task data packet, including task priority (Level0-LevelN, with Level0 having the highest priority), business type (hard real-time task, soft real-time task, non-real-time task), data length, deadline, etc.
[0057] The global virtual queue manager is used to input the metadata of each task data packet into the global queue and sort the metadata in order of task priority as the primary factor and deadline as the secondary factor. The global queue is a virtualized waiting queue. For newly added metadata, it is first sorted by task priority, and metadata with the same priority is then sorted by deadline.
[0058] The resource virtualization unit is used to abstract physical interfaces into a unified logical resource pool. The physical interfaces include dedicated physical interfaces and non-dedicated physical interfaces. The two types of physical interfaces are standardized logically modeled, uniformly encapsulated into logical interface resources with consistent specifications and unified scheduling, and incorporated into the logical resource pool for centralized management.
[0059] The dynamic allocation strategy unit is used to initialize the allocation scheme of physical interfaces based on task priority and physical interface characteristics: if the physical interface is a dedicated physical interface, the transmission conditions of the dedicated physical interface are determined, including only transmitting task priority and data length, and the dedicated physical interface is initialized to transmit only the metadata corresponding to the task priority and data length; if the physical interface is a non-dedicated physical interface, the non-dedicated physical interface is initialized to transmit metadata of all priorities.
[0060] Construct interface allocation rules based on time slots and bandwidth: If the metadata meets the transmission conditions of a dedicated channel, then the metadata is allocated to the dedicated channel; otherwise, the metadata is allocated to a non-dedicated physical interface, and a fixed period of time slots is reserved for hard real-time tasks in the non-dedicated physical interface. When hard real-time services send and receive within the fixed time slots, they do not need to preempt the overall channel and bus resources, thus ensuring latency determinism from the time dimension; in the non-dedicated physical interface, a weighted round-robin mechanism is used to allocate the remaining bandwidth for soft real-time tasks and non-real-time tasks.
[0061] The physical interface allocation scheme is adjusted using the interface allocation rules; based on the adjusted allocation scheme, metadata is transmitted sequentially from the global queue to the corresponding physical interface, and the metadata is packaged into a data packet and transmitted to the FPGA end through the physical interface.
[0062] The system calculates the link load of each physical interface in real time and dynamically adjusts the bandwidth weight of each physical interface. Specifically, the system collects load indicators such as link utilization, buffer queue backlog length, and real-time throughput of each physical interface in real time, and performs a weighted summation of these load indicators to obtain a comprehensive load index. If the comprehensive load index of a physical interface exceeds the preset load limit, indicating that the physical interface is overloaded and experiencing congestion, the bandwidth weight of the physical interface is reduced to limit the continuous injection of new traffic. If the comprehensive load index of a physical interface is below the preset load lower limit, indicating that the physical interface is underloaded and has surplus resources, the bandwidth weight of the physical interface is increased to guide the adaptive diversion and migration of service traffic. By dynamically optimizing and adjusting the bandwidth scheduling weight of each interface, under the premise that the upper limit of physical interface bandwidth is fixed, the system achieves multi-interface load balancing, avoids single-link overload and congestion problems, and improves the overall transmission resource utilization.
[0063] The hardware-level preemption control unit is used to trigger hardware-level preemption logic if the metadata task priority is the highest priority, and the metadata is allocated to a non-dedicated physical interface according to the adjusted allocation scheme, and the non-dedicated physical interface is currently transmitting a non-highest priority data packet. The logic is as follows: An interrupt signal or pause signal is immediately generated and sent to the controller of the highest priority physical interface; the current non-highest priority data packet is truncated at the boundary or marked as recoverable; the transmission status of the non-highest priority data packet is suspended, and the unsent data packet fragments are stored in the breakpoint buffer, saving the context; subsequently, the highest priority metadata is packaged into a data packet and transmitted to the FPGA, where it is parsed and transmitted to the corresponding processing line; after the highest priority data packet transmission is complete, the FPGA sends an execution completion confirmation signal; the transmission of the suspended non-highest priority data packet is resumed, the non-dedicated physical interface reads the unsent data packet fragments from the breakpoint buffer, adds a resume flag to the data packet header, and transmits it to the FPGA; the FPGA recognizes the resume flag, receives the unsent data packet fragments, and uses a block... RAM is used for temporary storage, splicing, and verification. Hardware-level preemption logic eliminates the need to re-establish connections, thus completely avoiding priority inversion issues.
[0064] The physical transmission link layer supports the parallel operation of various heterogeneous physical interfaces (including but not limited to SPI, PCIe, GMAC, etc.). Through the abstraction of the heterogeneous interface resource aggregation and scheduling module, these physical interfaces are no longer isolated, but are integrated into a logical and continuous bandwidth and time slot resource pool. It receives instructions from the heterogeneous interface resource aggregation and scheduling module and dynamically divides and allocates the physical link resources (time slices and bandwidth) to different data streams.
[0065] The FPGA-side receive / transmit processing unit is used to parse the metadata header and transmit the data packets to the processing line after the FPGA receives the data stream. For preempted and fragmented data packets, they are reassembled using the FPGA's internal high-speed cache to ensure the integrity of the data received by the upper-layer logic, and the data is sent to the corresponding processing line according to priority, such as... Figure 4 As shown.
[0066] Regarding the above-described technical solution in this embodiment, the process of applying the technical solution to a smart grid relay protection device and the technical effects of the technical solution will be described in detail below.
[0067] The multi-core processor of the smart grid relay protection device adopts a quad-core ARM Cortex-A72 processor and runs a real-time Linux system. Among them, Core0 is responsible for non-real-time data processing and runs a real-time Linux system; Core1 is responsible for human-machine interface and high-speed waveform recording data storage and runs a real-time Linux system; Core2 is responsible for protection algorithm calculation (hard real-time task) and runs a real-time environment without an operating system; Core3 is a heterogeneous interface resource aggregation and scheduling module.
[0068] The FPGA chip is responsible for high-speed sampling data acquisition, waveform data transmission, and trip signal output;
[0069] The heterogeneous interface uses both PCIe Gen2x1 and SPI interfaces; PCIe Gen2x1 is used to transmit sampled data and large-capacity waveform data (high bandwidth, medium latency); SPI is used to transmit trip commands and status words (low bandwidth, extremely low latency).
[0070] The driver for multi-core processors defines a unified data structure, struct TaskData, which tags all business data to be transmitted with metadata to form a task data packet. The specific definition is as follows:
[0071] The data structure fields include type (TRIP / LOG) (business type), timestamp, and payload; the timestamp is used to determine the deadline, and the data payload is used to determine the data length and mark whether the data is short packet data. Short packet data will be given priority to use the low latency channel when it is available.
[0072] Based on the requirements of power relay protection services, the classification rules for service data are as follows:
[0073] Trip command (TRIP): Priority 0 (highest priority), is the core command for emergency handling of power system faults;
[0074] Waveform recording data (LOG): Priority 3 (lowest priority), which is a large volume of non-real-time data such as device operation logs and fault waveform recordings.
[0075] The interface allocation rules based on time slots and bandwidth are determined as follows:
[0076] The PCIe interface allocates 90% of its bandwidth to data with priority 1 to priority 3, and reserves 10% of its bandwidth specifically for burst transmission of trip commands with priority 0.
[0077] The SPI interface is a low-latency dedicated channel used only for short packet data transmission with priority 0 and priority 1 (such as trip commands and status words).
[0078] The heterogeneous interface resource aggregation and scheduling module is activated to complete the pre-allocation of link resources, reserve dedicated resources for hard real-time tasks, and avoid low-priority data occupying critical links.
[0079] Scenario 1: Transmitting only waveform data
[0080] Core1 generates a large amount of waveform data. After marking the data generated by Core1 using the unified data structure struct TaskData, the data is formed into a task data packet and sent to the heterogeneous interface resource aggregation and scheduling module.
[0081] The heterogeneous interface resource aggregation and scheduling module receives the task data packets sent by Core1, extracts the metadata of the task data packets, including task priority (Priority3), business type (LOG), waveform data length, and waveform data deadline; adds the metadata to the global queue, and dynamically sorts the tasks in the global queue according to the order of task priority as the primary factor and deadline as the secondary factor.
[0082] The heterogeneous interface resource aggregation and scheduling module adjusts the allocation scheme of physical interfaces according to task priority and service type using the interface allocation rules; based on the adjusted allocation scheme, it transmits metadata from the global queue to the corresponding physical interface in sequence, and packages the waveform data into PCIe standard data packets through the physical interface;
[0083] PCIe standard data packets are continuously sent to the FPGA via the PCIe interface. At this time, the PCIe link utilization rate is about 90%, and the SPI interface is in a low-load standby state.
[0084] After receiving the PCIe standard data packet, the FPGA parses the PCIe standard data packet, routes it to the DDR memory for storage, and completes normal data interaction.
[0085] like Figure 5 As shown, Scenario 2: Hard real-time burst preemption of transmission (triggered by fault trip command)
[0086] Based on the transmission of waveform data in Scenario 1, Core2 detects power grid faults through protection algorithms and generates trip commands; after marking the data generated by Core2 through the unified data structure struct TaskData, it forms the Core2 task data packet and sends it to the heterogeneous interface resource aggregation and scheduling module.
[0087] The heterogeneous interface resource aggregation and scheduling module receives the task data packets sent by Core2, extracts the metadata of the task data packets of each core processor, including: task priority (Priority0), service type (TRIP), trip instruction data length, and trip instruction deadline; adds the metadata to the global queue, and dynamically sorts the tasks in the global queue according to the order of task priority as the primary factor and deadline as the secondary factor.
[0088] The heterogeneous interface resource aggregation and scheduling module detects that Priority0 data has been enqueued. The module then determines whether the data is a short packet based on its payload attributes.
[0089] If it is a short packet, it is sent directly to the FPGA via the SPI interface with extremely low latency;
[0090] If the packet is not short, an ABORT_TX hardware interrupt signal is immediately sent to the PCIe controller to trigger the preemption logic. After the current TLP (Transaction Layer Packet) transmission is completed, the PCIe controller immediately pauses the transmission of waveform data (Priority3), stores the unsent data packet fragments in the breakpoint buffer, and saves the current transmission context. The heterogeneous interface resource aggregation and scheduling module sends the trip instruction to the FPGA end through the high-priority queue of PCIe to ensure microsecond-level instruction transmission.
[0091] After the FPGA parsing unit identifies the Priority0 trip command, it bypasses all FIFO buffers through the routing matrix and directly routes the command to the trip control register to execute the hardware trip action, completing the emergency fault handling. The FPGA sends a confirmation signal to the heterogeneous interface resource aggregation and scheduling module to confirm the completion of the trip command execution. The scheduling module determines that the high-priority task transmission has ended. The heterogeneous interface resource aggregation and scheduling module reads the unsent waveform recording data segments from the breakpoint buffer, adds a continuation flag to the header of the data packet, and clarifies the data splicing attribute. The heterogeneous interface resource aggregation and scheduling module controls the PCIe interface to resume data transmission and sends the waveform recording data segments with the continuation flag to the FPGA. The FPGA reassembly unit identifies the continuation flag, uses the internal Block RAM to temporarily store, splice, and verify the truncated waveform recording data, and writes it to the DDR memory after verification to ensure data integrity.
Claims
1. A method for integrating and interacting heterogeneous interface resources applicable to multi-core processors, characterized in that, include: The task data packets generated by each core processor are obtained, and the metadata of each task data packet is extracted; the metadata includes task priority, service type, data length, and deadline; the service type includes hard real-time task, soft real-time task, and non-real-time task. The metadata of each task data packet is input into a global queue and sorted according to task priority as the primary factor and deadline as the secondary factor. The physical interface is abstracted into a unified logical resource pool. The physical interface includes dedicated physical interfaces and non-dedicated physical interfaces. The physical interface allocation scheme is initialized based on task priority and physical interface characteristics; interface allocation rules based on time slots and bandwidth are constructed, and the physical interface allocation scheme is adjusted using the interface allocation rules; based on the adjusted allocation scheme, metadata is transmitted sequentially from the global queue to the corresponding physical interface, and the metadata is packaged into data packets and transmitted to the FPGA end through the physical interface; Monitor the link load of each physical interface and dynamically adjust the bandwidth weight of each physical interface; If the metadata task priority is the highest priority, and the metadata is allocated to a non-dedicated physical interface according to the adjusted allocation scheme, and the non-dedicated physical interface is currently transmitting a non-highest priority data packet, then the hardware-level preemption logic is triggered to pause the transmission of the non-highest priority data packet, package the highest priority metadata into a data packet and transmit it to the FPGA end, and then resume the transmission of the non-highest priority data packet. After receiving the complete transmitted data packet, the FPGA parses and transmits the data packet to the processing line.
2. The heterogeneous interface resource integration and interaction method applicable to multi-core processors according to claim 1, characterized in that, The sorting of metadata by task priority as the primary factor and deadline as the secondary factor includes: first sorting the metadata by task priority, and then sorting metadata with the same priority by deadline.
3. The heterogeneous interface resource integration and interaction method applicable to multi-core processors according to claim 1, characterized in that, The physical interface allocation scheme based on task priority and physical interface characteristics includes: if the physical interface is a dedicated physical interface, then determining the transmission conditions of the dedicated physical interface, including transmitting only the task priority and data length, and initializing the dedicated physical interface to transmit only the metadata corresponding to the task priority and data length; if the physical interface is a non-dedicated physical interface, then initializing the non-dedicated physical interface to transmit metadata of all priorities.
4. The heterogeneous interface resource integration and interaction method applicable to multi-core processors according to claim 3, characterized in that, The interface allocation rules based on time slots and bandwidth include: if the metadata meets the transmission conditions of a dedicated physical interface, the metadata is allocated to the dedicated physical interface; otherwise, the metadata is allocated to a non-dedicated physical interface, and a fixed period of time slots is reserved in the non-dedicated physical interface for hard real-time tasks. When hard real-time services send and receive within the fixed time slots, they do not need to preempt the overall channel and bus resources; a weighted round-robin mechanism is adopted to allocate the remaining bandwidth of the non-dedicated physical interface to soft real-time tasks and non-real-time tasks.
5. The heterogeneous interface resource integration and interaction method applicable to multi-core processors according to claim 1, characterized in that, The dynamic adjustment of bandwidth weights for each physical interface includes: real-time collection of load metrics for each physical interface, including link utilization, cache queue backlog length, and real-time throughput; weighted summation of each load metric to obtain a comprehensive load index; if the comprehensive load index of a physical interface exceeds a preset load limit, the bandwidth weight of the physical interface is reduced; if the comprehensive load index of a physical interface is lower than a preset load limit, the bandwidth weight of the physical interface is increased.
6. The heterogeneous interface resource integration and interaction method applicable to multi-core processors according to claim 1, characterized in that, The hardware-level preemption logic includes: pausing the transmission of non-highest priority data packets via a non-dedicated physical interface and storing unsent data packet fragments in a breakpoint buffer to preserve the transmission context; using the non-dedicated physical interface to package the highest priority metadata into a data packet and transmitting it to the FPGA, where the FPGA parses and transmits it to the corresponding processing line; after the highest priority task is completed, the FPGA sends a completion confirmation signal; the non-dedicated physical interface reads the unsent data packet fragments from the breakpoint buffer, adds a resume flag to the data packet header, and transmits it to the FPGA; the FPGA recognizes the resume flag, receives the unsent data packet fragments, and uses Block RAM for temporary storage, splicing, and verification.
7. The heterogeneous interface resource integration and interaction method applicable to multi-core processors according to claim 1, characterized in that, The step of parsing and transmitting the data packet to the processing line includes: parsing the metadata of the data packet, extracting the task priority, and sending the data packet to the corresponding processing pipeline in order of task priority.
8. A heterogeneous interface resource integration and interaction system applicable to multi-core processors, characterized in that, include: The feature extraction module is used to acquire task data packets generated by each core processor and extract metadata of each task data packet; the metadata includes task priority, service type, data length, and deadline; the service type includes hard real-time task, soft real-time task, and non-real-time task. The global virtual queue manager is used to input the metadata of each task data packet into the global queue and sort the metadata in order of task priority as the primary factor and deadline as the secondary factor. The resource virtualization unit is used to abstract physical interfaces into a unified logical resource pool; physical interfaces include dedicated physical interfaces and non-dedicated physical interfaces. The dynamic allocation strategy unit is used to initialize the allocation scheme of physical interfaces based on task priority and physical interface characteristics; construct interface allocation rules based on time slots and bandwidth, and adjust the allocation scheme of physical interfaces using the interface allocation rules; based on the adjusted allocation scheme, transmit metadata from the global queue to the corresponding physical interface in sequence, and package the metadata into data packets through the physical interface and transmit them to the FPGA end; Monitor the link load of each physical interface and dynamically adjust the bandwidth weight of each physical interface; The hardware-level preemption control unit is used to trigger hardware-level preemption logic if the metadata task priority is the highest priority, and the metadata is allocated to a non-dedicated physical interface according to the adjusted allocation scheme, and the non-dedicated physical interface is currently transmitting a non-highest priority data packet. This logic pauses the transmission of non-highest priority data packets, packages the highest priority metadata into a data packet and transmits it to the FPGA, and then resumes the transmission of non-highest priority data packets. The FPGA receiving / transmitting processing unit is used to parse and transmit the data packet to the processing line after the FPGA receives the complete transmitted data packet.
9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.