Adaptive spatiotemporal computing architecture, method and topological core system based on topological phase transition

Abstract

The application discloses a kind of based on topological phase transition's adaptive space-time computing architecture, method and topological core system.The application engineering "topological phase transition" in complex system into a kind of hardware resource management strategy, the problem that existing computing architecture cannot provide the instantaneous computing capacity of equivalent computing performance beyond hardware fixed limit for local burst task because hardware space-time benchmark is invariable is solved.The application monitors the interaction intensity of system and environment in real time, when the intensity reaches critical threshold, a part of computing unit is dynamically physically fenced off in a general hardware platform, so that it forms independent computing domain, and by dynamically reconfiguring hardware clock generator and memory management unit, the special hardware space-time benchmark that is accurately matched with the emergency task is generated.The application provides underlying architecture solution for the field of extreme requirement for real-time, such as autonomous driving, industrial control, financial transaction, quantum computing measurement and control, aerospace, etc.

Description

Technical Field

[0001] This invention relates to the field of computer architecture and real-time control system technology, specifically to an adaptive spatiotemporal computing device, method, and topology kernel system based on topological phase transition. Background Technology

[0002] In current computing systems, once the computing units have completed hardware initialization or functional configuration, the spatiotemporal reference of the core hardware upon which their operation depends is immutable. Specifically:

[0003] The immutability of the time base: Each computing unit operates on a fixed minimum time step determined by its master frequency. Even with dynamic frequency adjustment technology, its adjustment range is limited to a few preset levels, making it impossible to achieve instantaneous adjustments that are continuously or arbitrarily proportional to the urgency of the task.

[0004] The immutability of the address space baseline: Each computing unit has a fixed address space determined by its address bus width and page table mapping. The granularity and range of this space are preset, and it is impossible to temporarily reconstruct a completely isolated and finer-grained dedicated address space at runtime for a sudden emergency task.

[0005] This "spatiotemporal baseline rigidification" architecture is efficient when handling stable, predictable computational loads. However, when the system encounters sudden, high-intensity interaction demands—for example, an autonomous vehicle suddenly encountering a pedestrian crossing the road on a highway, or an industrial robot experiencing abnormal workpiece slippage during high-speed operation—this immutability leads to a fundamental dilemma:

[0006] Limited Emergency Response: The performance ceiling of computing cores allocated for emergency tasks is locked by their immutable time base. Even if the core responds immediately, it can only operate at a preset fixed rate and cannot gain a shorter response latency by instantly "upsampling". Current technology cannot allow a computing core with a fixed clock speed to temporarily obtain computing performance equivalent to increasing the base clock speed in a very short time.

[0007] Physical isolation is costly: Hardware isolation achieved through technologies such as virtualization or trusted execution environments, like Intel VT-x and ARM TrustZone, still relies on a shared, immutable master clock and memory controller. While they achieve isolation at the access control level, they fail to achieve independence at the performance and time base levels. Malicious or anomalous tasks within one partition can still impact the real-time performance of another partition by exhausting shared bus bandwidth or cache.

[0008] Fault tolerance lag: Existing fault isolation mechanisms (such as watchdog timers and heartbeat detection) recover after a fault occurs by performing a coarse-grained system reset or task migration, resulting in uncontrollable recovery delays. Current technologies cannot complete the logical reconstruction and self-healing of faulty units within the same nanosecond instant of a fault occurrence.

[0009] Therefore, this invention proposes a fundamental change: allowing the system to dynamically and locally isolate a computing domain with an independent and instantaneously optimizable proprietary hardware spatiotemporal reference at the hardware level, specifically to deal with sudden crises or instantaneous operation scenarios, forming an adaptive, non-uniform "spatiotemporal computing architecture". Summary of the Invention

[0010] The purpose of this invention is to address the limitation of existing computing architectures, due to the immutability of the hardware spatiotemporal reference of their computing units. This limitation prevents them from providing equivalent computing performance exceeding fixed hardware limits and decoupled from the main system for localized, extreme tasks while ensuring global system stability. The core idea of ​​this invention is to engineer the concept of "topological phase transition" from complex systems science into a novel hardware resource management strategy. When the system detects a surge in "interaction intensity," instead of scheduling tasks within a fixed hardware spatiotemporal space, a "topological phase transition" is triggered. This isolates an independent computing domain at the hardware level and generates a dedicated, optimized hardware spatiotemporal reference for this domain, precisely matched to the needs of urgent tasks, by dynamically reconfiguring the hardware clock generator (PLL) and memory management unit (MMU). The spatiotemporal reference refers to the collective time and spatial addressing references upon which the computing system depends, including clock signals and memory address mappings.

[0011] In a first aspect, the present invention provides an adaptive spatiotemporal computing device based on topological phase transition, comprising:

[0012] Hardware resource layer: contains multiple independently configurable computing units (such as FPGA logic blocks, NPU cores, etc.).

[0013] Topology phase change controller: A hardware or hardware-software hybrid monitoring and decision-making unit that continuously calculates an indicator reflecting the intensity of interaction between the system and its environment (such as interaction risk entropy, data flow mutation rate, etc.). This interaction intensity indicator is used to quantify the complexity and urgency of data interaction between the computing device and its operating environment, as well as the computational complexity and priority of tasks to be executed. When this indicator exceeds a critical threshold related to the physical limits of the system hardware, it issues a "phase change trigger command".

[0014] Resource Management Unit: In response to the "phase change trigger command", it performs the following core operations:

[0015] Physical fence isolation, achieved through on-chip network routing reconfiguration or bus arbitration, physically isolates a portion of the computing units (the second set of computing units) from the rest (the first set of computing units) in the hardware resource layer, forming an independent computing domain. Specifically, for FPGA platforms, physical fence isolation is implemented by reconfiguring the on-chip network routing table: all input / output ports of the logic blocks corresponding to the second set of computing units are routed only to dedicated sensor and actuator interfaces, severing their connection to the global bus and the main CPU. For NPU platforms, physical fence isolation is implemented through a hardware partitioning mechanism: a portion of the NPU's computing cores is divided into independent hardware partitions, each with its own clock domain, memory controller, and DMA channel, completely isolated from other partitions.

[0016] The system switches between states, maintaining the first set of computing units in a "first operating state" based on a global spatiotemporal reference to sustain basic system operation. It also switches the second set of computing units to a "second operating state."

[0017] A dedicated time-space reference is generated. In the second operating state, the second set of computing units abandons its dependence on the global synchronization clock and unified memory mapping. Its local clock is dynamically reconfigured by a programmable PLL integrated within the computing unit: the resource management unit sends a new frequency configuration word to the PLL, which completes the frequency switching within 100ns and outputs a local clock signal matching the task requirements. The global clock is only used as a reference clock for the PLL and does not directly participate in the operation of the computing unit. Simultaneously, a dedicated local addressing space (i.e., a dedicated intrinsic space) with a more optimized addressing mode is generated specifically for this urgent task.

[0018] Independent computation execution: The second set of computing units, based on the proprietary hardware spatiotemporal reference, performs computations related to high-intensity interactive tasks that trigger phase transitions in a physically isolated manner.

[0019] Time and space are decoupled, and physical fence isolation ensures that the first and second operating states are decoupled in terms of time synchronization and spatial addressing. The two computing domains exchange data only through a dedicated asynchronous FIFO buffer. There is no shared clock signal or memory address space, so timing errors or memory errors in one computing domain cannot propagate to the other computing domain.

[0020] Specifically, the definition of equivalent computing performance: The "equivalent computing performance exceeding the fixed hardware limits" mentioned in this invention refers to significantly increasing the effective computational load per unit global time by generating a dedicated, higher-density spatiotemporal reference for urgent tasks, thereby achieving the same effect as increasing the base clock speed of the hardware, rather than breaking the physical switching speed limit of transistors. For example, a computing core with a base clock speed of 1GHz, through dynamic reconfiguration to generate a local 10GHz clock, can complete 10^7 operations in 1ms global time, equivalent to a 10-fold increase in computing performance based on the base clock speed. Current commercial FPGA platforms support a maximum local clock frequency of 10GHz, with a theoretical upper limit of 100GHz.

[0021] Specifically, the time overhead of physical fence isolation is as follows: for FPGA platforms, the completion time for on-chip network route reconfiguration is less than 1μs; for NPU platforms, the completion time for hardware partition switching is less than 500ns. This time overhead is far less than the millisecond-level latency of software task scheduling and will not affect the real-time response of emergency tasks. Physical fence isolation refers to isolating a portion of computing units from the rest of the system physically through hardware-level route reconfiguration or bus arbitration, forming an independent computing domain and achieving complete decoupling of time and space.

[0022] A preferred embodiment: The device further includes a self-consistency monitor for continuously monitoring the self-consistency index of the independent computation domain in the second operating state. The self-consistency index is used to quantify the temporal consistency deviation between the data input time, the computation completion time, and the result output time, and its calculation formula is: in, This represents the actual delay from data input to result output for the second set of computing units. The self-consistency index is a preset expected delay; its value ranges from [0,1], with a value closer to 1 indicating better timing consistency. When the index deviates from the threshold, the operating parameters are dynamically adjusted to maintain a steady state; if the deviation continues and cannot be recovered, it is forcibly rolled back to the first operating state and the isolation is lifted. When the self-consistency index is higher than the preset optimal threshold, it indicates that the current local clock frequency exceeds the actual requirement, and the local clock frequency is dynamically reduced to reduce system energy consumption.

[0023] Another preferred implementation: For high-priority urgent tasks, the internal time step (the period of the local clock) has a monotonically decreasing function relationship with the interaction intensity index, that is, the more urgent the task, the higher the local clock frequency of the system and the faster the response.

[0024] Another preferred implementation: The second set of computing units can be further divided into multiple sub-computing domains, each with an independent internal spatiotemporal reference, corresponding to tasks of different priorities; different sub-computing domains communicate with each other through asynchronous message queues.

[0025] Secondly, the present invention provides an adaptive spatiotemporal computation method based on topological phase transition, applied to a hardware platform containing multiple independently configurable computing units, comprising the following steps:

[0026] S1: Initialization step, configuring all computing units of the hardware platform to run in the first running state, in which all computing units run based on a global spatiotemporal reference.

[0027] S2: Monitoring step, real-time acquisition of an interaction intensity index, the interaction intensity index is used to quantify the complexity and urgency of data interaction between the hardware platform and its operating environment, as well as the computational complexity and priority of the task to be executed.

[0028] S3: Phase transition step, when the interaction intensity index reaches a preset critical threshold, perform the following operations:

[0029] The hardware platform is physically fenced off from at least the first set of computing units and the second set of computing units to form an independent computing domain;

[0030] The first set of computing units is controlled to maintain the first operating state;

[0031] The second set of computing units is controlled to switch to a second operating state. In the second operating state, the second set of computing units generates an internal spatiotemporal reference through dynamic reconstruction.

[0032] S4: Execution step: In the second running state, control the second set of computing units to perform calculations related to the high-interaction intensity task that triggers the phase transition based on the internal spatiotemporal reference;

[0033] The time and space scales of the internal spatiotemporal reference are dynamically determined based on the real-time requirements of the high-interaction-intensity task and the hardware performance of the second set of computing units.

[0034] The physical fence isolation decouples the first set of computing units from the second set of computing units in terms of time synchronization and spatial addressing. The two computing domains exchange data only through a dedicated asynchronous buffer, and there is no shared clock signal or memory address space.

[0035] In a preferred embodiment, the method further includes:

[0036] S5: Steady-state maintenance step, continuously monitoring a self-consistency index, the self-consistency index being used to quantify the temporal consistency deviation of the second computing unit set in the second operating state, the data input time, the calculation completion time and the result output time; when the self-consistency index deviates from a preset self-consistency threshold, dynamically adjusting at least one operating parameter of the second computing unit set to maintain the self-consistency index within the range limited by the self-consistency threshold.

[0037] S6: Rollback step: When it is detected that the self-consistency index continuously deviates from the self-consistency threshold for more than a preset time and cannot be restored by adjusting the operating parameters, the second computing unit set is forcibly rolled back from the second operating state to the first operating state, and the physical fence isolation between it and the first computing unit set is released.

[0038] Thirdly, the present invention provides a topology core system, which includes:

[0039] A general-purpose processor for running the operating system and performing non-real-time tasks;

[0040] A reconfigurable computing hardware comprising multiple independently configurable computing units for performing computationally intensive or hard real-time tasks;

[0041] A topology phase change controller, coupled to the general-purpose processor and the reconfigurable computing hardware, is configured to: acquire an interaction intensity index in real time, the interaction intensity index being used to quantify the complexity and urgency of data interaction between the topology core system and its operating environment, as well as the computational complexity and priority of the task to be executed; and generate a phase change trigger instruction when the interaction intensity index reaches a preset critical threshold.

[0042] A resource management unit, coupled to the topology phase change controller and the reconfigurable computing hardware, is configured to, in response to the phase change trigger command,: physically fence off at least a first part of the computing units in the reconfigurable computing hardware to a second part of the computing units, forming an independent computing domain; control the first part of the computing units to maintain a first operating state, in which the first part of the computing units operates based on a global spatiotemporal reference; control the second part of the computing units to switch to a second operating state, in which the second part of the computing units generates an internal spatiotemporal reference through dynamic reconfiguration, and performs calculations related to the high-interaction-intensity task that triggers the phase change based on the internal spatiotemporal reference; wherein, the time scale and spatial scale of the internal spatiotemporal reference are dynamically determined according to the real-time requirements of the high-interaction-intensity task and the hardware performance of the second part of the computing units; the physical fence isolation decouples the first part of the computing units and the second part of the computing units in terms of time synchronization and spatial addressing, and the two computing domains exchange data only through a dedicated asynchronous buffer, without sharing clock signals and memory address spaces.

[0043] The resource management unit integrates hardware virtualization management functions, enabling dynamic allocation and isolation of computing resources. The reconfigurable computing hardware includes a field-programmable gate array (FPGA) or a reconfigurable neural network processor. Physical fence isolation is achieved through on-chip network routing reconfiguration or a bus arbitration mechanism. The local clock in the internal spatiotemporal reference is generated by a programmable phase-locked loop (PLL) integrated within the reconfigurable computing hardware. The resource management unit sends a frequency configuration word to the PLL, which completes frequency switching within 100ns, outputting a local clock signal matching the task requirements.

[0044] Fourthly, the present invention provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the adaptive spatiotemporal calculation method described in any of the preceding claims.

[0045] This application is a hardware-level performance enhancement extension of the invention patents filed by the applicant on the same day, namely "Method, System and Storage Medium for Endogenous Spatiotemporal Generation of Dynamic Interactive System", "Method, System and Storage Medium for Environmental Perception Based on Dynamic Interactive Topological Field", and "Method, System and Medium for Dynamic Interactive Cognition and Motion Control Based on Topological Field", with significantly different technical features.

[0046] The "topology core" architecture proposed in this invention has the following advantages compared to existing technologies:

[0047] (1) Equivalent computational performance exceeding hardware limitations: This technology enables the system to break through its underlying hardware spatiotemporal reference. By dynamically reconfiguring a dedicated, higher-frequency local clock for a single urgent task, it achieves, for the first time, computational performance equivalent to increasing the underlying clock frequency for a specific task by increasing the effective computation per unit global time, without increasing the underlying hardware clock frequency. Under the test conditions of this embodiment, the equivalent computational performance of urgent tasks on the same hardware platform is improved by more than 10 times.

[0048] (2) Strict physical-level security isolation: The "physical fence isolation + dynamic reconfiguration of dedicated time and space reference" implemented in this technology ensures that the two operating states are not only isolated in terms of data access, but also decoupled in terms of time perception and spatial cognition. The two computing domains exchange data only through a dedicated asynchronous FIFO buffer, and there is no shared clock signal or memory address space. Compared with x86 virtualization technology, the isolation strength is greatly improved, which can resist most known side-channel attacks and timing attacks.

[0049] (3) Nanosecond-level hardware logic self-healing: Local faults are treated as "topological defects". Fault tolerance is achieved through hardware-level "self-consistency monitoring" and "instant logic reconfiguration". The fault recovery time is shortened from millisecond / microsecond-level software detection and reset to nanosecond-level hardware logic self-healing. The measured fault recovery time is less than 100ns, which is more than 1000 times faster than existing technologies.

[0050] (4) Extreme optimization of computing resources and energy efficiency: No need to "prepare for battle" for peak performance. The computing resources operate at low power consumption under normal conditions, and only "burst" to form a high-performance "spacetime bubble" when encountering a crisis. The resources are recycled after the task is completed, realizing the maximum utilization of energy and computing power. The system can dynamically adjust the local clock frequency and the number of computing units according to the real-time requirements of the task and the current energy consumption level, so as to minimize energy consumption while ensuring the task completion time.

[0051] (5) Significantly reduces the real-time synchronization overhead of large-scale distributed systems: In multi-sensor or cluster computing scenarios, the system does not require all nodes to reach consensus at the same time. It allows local nodes to independently solve the most pressing problems using their own "local time" and finally exchange only conclusive information, thereby significantly reducing the real-time synchronization overhead of large-scale distributed systems. Attached Figure Description

[0052] Figure 1 : Schematic diagram of an adaptive spatiotemporal computing architecture based on topological phase transition;

[0053] Figure 2 : Diagram of state transition and spatiotemporal generation process from the first running state to the second running state;

[0054] Figure 3 : Schematic diagram of multi-level nested spacetime bubble. Detailed Implementation

[0055] All numerical values ​​in this invention are merely examples to facilitate understanding of the invention. Actual parameters depend on the system hardware platform, application scenario, and control cycle, and do not constitute a limitation on the scope of protection of this invention.

[0056] Example 1: Application in high-level autonomous driving platforms

[0057] This embodiment is based on a heterogeneous, centralized autonomous driving computing platform, which includes a multi-core CPU, a high-performance NPU, and a large FPGA.

[0058] System input parameters:

[0059] Hardware platform: NVIDIA Drive Orin (8-core CPU + 200TOPS NPU + FPGA accelerator card)

[0060] Global base clock speed: 1GHz, global control cycle: 100ms

[0061] Global map resolution: 1m

[0062] Interaction risk entropy threshold: =0.8

[0063] Self-consistency threshold: =0.9

[0064] Expected delay in emergency obstacle avoidance calculation:

[0065] Step 1: Initialization

[0066] The first computing unit set consists of an 8-core CPU running the Linux operating system and global path planning.

[0067] The second computing unit set consists of all NPU cores and 80% of FPGA logic resources, which are in a low-power sleep state.

[0068] Global time-space baseline: 1GHz global clock + unified 4GB memory mapping.

[0069] Step 2: Monitoring and Triggering

[0070] Sensor input: The forward-facing lidar detected a metal obstacle with dimensions of 0.5m × 0.5m at a distance of 50m ahead at time t=0.

[0071] Collision prediction probability calculation: in , , Calculated

[0072] Interactive risk entropy calculation:

[0073] Triggering condition judgment: The topology phase change controller issues a phase change trigger command at t=0.1ms.

[0074] Step 3: Phase transition and generation of dedicated time-space reference

[0075] Physical fence isolation: The resource management unit completes on-chip network rerouting at t=0.5μs, isolating all NPU cores and 80% of FPGA logic blocks into independent computing domains.

[0076] Local clock generation: The frequency configuration word is sent to the PLL, and the PLL completes the frequency switching at t=0.6μs to generate a local 10GHz clock (period 100ns).

[0077] Dedicated address space generation: Reconfigure the MMU to generate a local high-precision map space centered on the vehicle, with a resolution of 0.1m and an address range of 0x00000000-0x000FFFFF.

[0078] State transition completion time: t=1.0μs, the second computing unit set enters the second running state.

[0079] Step 4: Maintaining Steady State and Emergency Obstacle Avoidance

[0080] Emergency obstacle avoidance calculation: The NPU executes the model predictive control algorithm based on a 10GHz local clock, and the actual time to complete one trajectory planning operation is:

[0081] Calculation of self-consistency index:

[0082] Control command output: A steering command of 15 degrees is sent to the actuator at t=1.8ms.

[0083] Equivalent computational performance improvement:

[0084] Step 5: Regression

[0085] At time t=3.0s, the obstacle was successfully avoided, and the interaction risk entropy decreased to H=0.12;

[0086] At t=3.001s, the resource management unit removes the physical fence isolation, and the NPU and FPGA restore global clock synchronization, returning to a low-power state.

[0087] The system's final output result:

[0088] Total response time: 1.8ms (the average response time of existing technology is 150ms, which is 83 times faster).

[0089] Minimum safe distance: 2.8m (current technology averages 15m);

[0090] Peak computing power utilization: 98% (compared to an average of 30% for existing technologies).

[0091] Example 2: Application in multi-level nested spacetime bubbles

[0092] This embodiment demonstrates the simultaneous generation of three nested spatiotemporal bubbles in an extremely complex urban autonomous driving scenario.

[0093] System input parameters:

[0094] Hardware platform: Xilinx Versal ACAP (ARM A72 + AI Engine + FPGA)

[0095] Global control cycle: 100ms

[0096] Total computing resources: 100 AI Engine cores.

[0097] The allocation and parameters of spacetime bubble resources are detailed in Table 1:

[0098] Table 1. Resource Allocation and Parameters of Multilayer Spacetime Bubbles

[0099] 1 (highest) Collision detection 10GHz 10μs 10 2 Emergency Obstacle Avoidance 1GHz 1ms 60 3 (lowest) Local path planning 100MHz 10ms 30

[0100] Priority scheduling mechanism:

[0101] High-priority spacetime bubbles can preempt the computing resources of low-priority spacetime bubbles;

[0102] When collision detection cavitation detects an emergency danger, it can immediately preempt all 100 AI Engine cores;

[0103] Different spacetime bubbles communicate with each other via an asynchronous FIFO queue with a depth of 1024, with a communication delay of less than 100ns.

[0104] Example 3: Application in high-speed industrial robot-human collaboration

[0105] This embodiment uses a high-speed collaborative robot as the platform. During normal operation, the robot's main controller performs trajectory planning at 10ms intervals. When it enters an operating space shared with a human worker, the system proactively triggers a fenced-off FPGA computing domain to enter a second operating state. This computing domain generates a 100-microsecond local clock and continuously runs a pure "safety boundary calculation" task based on the dynamic models of the robot and the human. This isolated "safety spacetime bubble" is decoupled from the main controller. Once its calculation predicts any possibility of accidental contact, it will, within microseconds, independently of the main system, directly issue compliance or stop commands to the actuators to ensure the safety of the human worker.

[0106] Test results: When a worker enters the workspace, the system triggers a topological phase transition within 500 ns; generates a local safety clock with a period of 100 μs, improving the safety boundary calculation frequency by 100 times; the accuracy of the predicted collision time is ±1 ms; the emergency stop response time is 200 μs (the average of the existing technology is 10 ms, which is 50 times better); and the efficiency of human-machine collaboration is improved by 40%.

[0107] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A topological phase transition based adaptive spatiotemporal computing device, comprising: include: A hardware resource layer, containing multiple independently configurable computing units; A topology phase change controller, coupled to the hardware resource layer, is configured to: acquire an interaction intensity index in real time, the interaction intensity index being used to quantify the complexity and urgency of data interaction between the computing device and its operating environment, as well as the computational complexity and priority of the tasks to be executed; and generate a phase change trigger command when the interaction intensity index reaches a preset critical threshold. A resource management unit, coupled to the topology phase change controller and the hardware resource layer, is configured to, in response to the phase change trigger command, perform the following operations: physically fence off at least a first set of computing units and a second set of computing units in the hardware resource layer to form an independent computing domain; control the first set of computing units to maintain a first operating state, in which the first set of computing units... A set of computing units operates based on a global spatiotemporal reference. A second set of computing units is controlled to switch to a second operating state. In this second operating state, the second set of computing units dynamically reconstructs an internal spatiotemporal reference and performs calculations related to high-interaction-intensity tasks that trigger phase transitions based on this internal spatiotemporal reference. The time and spatial scales of the internal spatiotemporal reference are dynamically determined based on the real-time requirements of the high-interaction-intensity tasks and the hardware performance of the second set of computing units. Physical fence isolation decouples the first and second sets of computing units in terms of time synchronization and spatial addressing. The two computing domains exchange data only through a dedicated asynchronous buffer, without sharing clock signals or memory address spaces.

2. The topology phase change based adaptive spatiotemporal computing device of claim 1, wherein, The global spatiotemporal reference includes a global synchronization clock and a unified memory-mapped address space; the internal spatiotemporal reference includes a local clock generated by a reconfigured hardware clock generator, independent of the global synchronization clock, and a dedicated address space generated by a reconfigured memory management unit, independent of the unified memory-mapped address space.

3. The topology phase change based adaptive spatiotemporal computing device of claim 2, wherein, The frequency of the local clock is dynamically adjusted according to task requirements, and may be higher or lower than the frequency of the global synchronization clock; the data granularity of the dedicated address space is dynamically adjusted according to task requirements, and may be smaller or larger than the data granularity of the unified memory-mapped address space.

4. The adaptive spatiotemporal computing device based on topological phase transition according to any one of claims 1 to 3, characterized in that, The topology phase change controller is further configured to: continuously monitor a self-consistency index, which is used to quantify the timing consistency deviation of the second computing unit set at the data input time, the calculation completion time, and the result output time in the second operating state; when the self-consistency index deviates from a preset self-consistency threshold, dynamically adjust at least one operating parameter of the second computing unit set to restore the self-consistency index to the range defined by the self-consistency threshold, thereby maintaining the stability of the second operating state; when the self-consistency index is higher than a preset optimal threshold, dynamically reduce the frequency of the local clock to reduce system energy consumption.

5. The adaptive spatiotemporal computing device based on topological phase transition according to claim 4, characterized in that, The formula for calculating the self-consistency index is as follows: in, This represents the actual delay from data input to result output for the second set of computing units. The preset expected delay; the self-consistency index ranges from [0,1], and the closer the value is to 1, the better the timing consistency.

6. The adaptive spatiotemporal computing device based on topological phase transition according to claim 4, characterized in that, The resource management unit is further configured to: when the topology phase change controller detects that the self-consistency index continuously deviates from the self-consistency threshold for more than a preset time and cannot be restored by adjusting the operating parameters, forcibly revert the second computing unit set from the second operating state to the first operating state and remove its physical fence isolation from the first computing unit set; the typical value of the preset time is 1ms.

7. The adaptive spatiotemporal computing device based on topological phase transition according to claim 1, characterized in that, The second set of computing units generates an internal spatiotemporal reference through dynamic reconstruction, including: generating an internal time step that matches the response time requirements of the high-interaction-intensity task, wherein the internal time step may be smaller or larger than the time step of the global spatiotemporal reference; and generating an internal addressing space that matches the state space granularity of the high-interaction-intensity task, wherein the granularity of the internal addressing space may be smaller or larger than the addressing space granularity of the global spatiotemporal reference.

8. The adaptive spatiotemporal computing device based on topological phase transition according to claim 7, characterized in that, For high-priority urgent tasks, the internal time step has a monotonically decreasing relationship with the interaction intensity index, that is, the higher the interaction intensity index, the shorter the internal time step.

9. The adaptive spatiotemporal computing device based on topological phase transition according to claim 1, characterized in that, The second set of computing units can be further divided into multiple sub-computing domains. Each sub-computing domain has an independent internal spatiotemporal reference and corresponds to tasks of different priorities. Different sub-computing domains communicate with each other through asynchronous message queues.

10. The adaptive spatiotemporal computing device based on topological phase transition according to claim 1, characterized in that, The computing unit includes at least one of a reconfigurable logic block, a neural network processor, a graphics processor, and a digital signal processor.

11. The adaptive spatiotemporal computing device based on topological phase transition according to claim 1, characterized in that, The first set of computing units is used to maintain the operating system, non-real-time task scheduling, and basic communication functions of the device; the second set of computing units is used to perform calculations related to high-interaction-intensity tasks that trigger phase transitions within the independent computing domain formed by the physical fence isolation.

12. The adaptive spatiotemporal computing device based on topological phase transition according to claim 1, characterized in that, The physical fence isolation is completed in less than 1 μs, and the internal spatiotemporal reference is generated in less than 100 ns.

13. An adaptive spatiotemporal computation method based on topological phase transition, applied to a hardware platform containing multiple independently configurable computing units, characterized in that, Includes the following steps: S1: Initialization step, configuring all computing units of the hardware platform to run in the first running state, in which all computing units run based on a global spatiotemporal reference; S2: Monitoring step, real-time acquisition of an interaction intensity index, the interaction intensity index is used to quantify the complexity and urgency of data interaction between the hardware platform and its operating environment, as well as the computational complexity and priority of the task to be executed; S3: Phase transition step, when the interaction intensity index reaches a preset critical threshold, perform the following operations: physically isolate at least the first set of computing units and the second set of computing units of the hardware platform to form an independent computing domain; control the first set of computing units to maintain the first operating state; control the second set of computing units to switch to a second operating state, in which the second set of computing units generates an internal spatiotemporal reference through dynamic reconstruction; S4: Execution step: In the second operating state, control the second computing unit set to perform calculations related to the high-interaction-intensity task that triggers the phase transition, based on the internal spatiotemporal reference; wherein, the time scale and spatial scale of the internal spatiotemporal reference are dynamically determined according to the real-time requirements of the high-interaction-intensity task and the hardware performance of the second computing unit set; the physical fence isolation decouples the first computing unit set and the second computing unit set in terms of time synchronization and spatial addressing, and the two computing domains exchange data only through a dedicated asynchronous buffer, without sharing clock signals and memory address spaces.

14. The adaptive spatiotemporal computation method based on topological phase transition according to claim 13, characterized in that, Also includes: S5: Steady-state maintenance step, continuously monitoring a self-consistency index, the self-consistency index being used to quantify the temporal consistency deviation of the second computing unit set in the second operating state, the data input time, the calculation completion time and the result output time; when the self-consistency index deviates from a preset self-consistency threshold, dynamically adjusting at least one operating parameter of the second computing unit set to maintain the self-consistency index within the range limited by the self-consistency threshold; S6 The rollback step involves forcibly rolling back the second computing unit set from the second operating state to the first operating state when it is detected that the self-consistency index continuously deviates from the self-consistency threshold for more than a preset time and cannot be restored by adjusting the operating parameters, and removing the physical fence isolation between the second computing unit set and the first computing unit set.

15. A topological core system, characterized in that, include: A general-purpose processor for running the operating system and performing non-real-time tasks; and a reconfigurable computing hardware comprising multiple independently configurable computing units for performing computationally intensive or hard real-time tasks. A topology phase change controller, coupled to the general-purpose processor and the reconfigurable computing hardware, is configured to: acquire an interaction intensity index in real time, the interaction intensity index being used to quantify the complexity and urgency of data interaction between the topology core system and its operating environment, as well as the computational complexity and priority of the tasks to be executed; and generate a phase change trigger instruction when the interaction intensity index reaches a preset critical threshold; a resource management unit, coupled to the topology phase change controller and the reconfigurable computing hardware, is configured to, in response to the phase change trigger instruction,: physically fence off at least a first part of the computing units in the reconfigurable computing hardware to a second part of the computing units, forming an independent computing domain; and control the first part of the computing units to maintain a first operating state, in which state... The first part of the computing unit operates based on a global spatiotemporal reference. The second part of the computing unit is controlled to switch to a second operating state. In the second operating state, the second part of the computing unit generates an internal spatiotemporal reference through dynamic reconstruction and performs calculations related to high-interaction-intensity tasks that trigger phase transitions based on the internal spatiotemporal reference. The time scale and spatial scale of the internal spatiotemporal reference are dynamically determined according to the real-time requirements of the high-interaction-intensity tasks and the hardware performance of the second part of the computing unit. The physical fence isolation decouples the first part of the computing unit from the second part of the computing unit in terms of time synchronization and spatial addressing. The two computing domains exchange data only through a dedicated asynchronous buffer and do not share clock signals and memory address spaces.

16. The topological core system according to claim 15, characterized in that, The reconfigurable computing hardware includes a field-programmable gate array or a reconfigurable neural network processor; the physical fence isolation is achieved through on-chip network routing reconfiguration or a bus arbitration mechanism; the local clock in the internal spatiotemporal reference is generated by a programmable phase-locked loop integrated within the reconfigurable computing hardware, the resource management unit sends a frequency configuration word to the programmable phase-locked loop, the programmable phase-locked loop completes frequency switching within 100ns, and outputs a local clock signal that matches the task requirements.

17. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 13 to 14.

Images