A server startup fault detection method, device, equipment and storage medium
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INSPUR (SHANDONG) COMPUTER TECH CO LTD
- Filing Date
- 2026-04-29
- Publication Date
- 2026-07-21
Smart Images
Figure CN122431932A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of servers, and in particular to a method, apparatus, device, and storage medium for detecting server startup failures. Background Technology
[0002] In large-scale data center operations and critical business continuity scenarios, the efficiency of fault diagnosis and recovery during the server startup phase directly determines operational costs and the extent of business loss. Therefore, fault detection during the server startup phase is crucial. Currently, the server startup process primarily relies on the collaborative capabilities of the Basic Input / Output System (PIS) and the controller. However, due to the lack of a startup result interaction mechanism between the IPS and the controller, the controller cannot accurately identify the server's startup status, easily misjudging fault scenarios and resulting in insufficient targeted operational responses. Furthermore, when startup failure occurs, the root cause cannot be located, and direct restarting may damage the site environment, leading to the loss of critical fault information and increasing the difficulty of subsequent troubleshooting.
[0003] Therefore, current server startup failure detection technologies suffer from problems such as lack of interactive verification, ambiguous distinction between failure types, and insufficient preservation of failure data, which cannot meet the needs of modern data centers for startup reliability and intelligent operation and maintenance. Summary of the Invention
[0004] In view of this, the purpose of the present invention is to provide a server startup failure detection method, apparatus, device and storage medium, which solves the problems of lack of interactive verification, ambiguous distinction of failure types and insufficient preservation of failure data in the existing server startup failure detection technology.
[0005] To address the aforementioned technical problems, this invention provides a server startup failure detection method, comprising: If the controller does not detect a system startup success confirmation signal from the basic input / output system within the first preset time, the server is determined to be in a startup failure state, and the flash memory status is verified by the controller. If the flash memory is in normal condition, the cause of the server's startup failure is determined to be a system crash. The controller reads the complete flash memory image and register information and analyzes and locates the root cause of the failure. If the flash memory status is abnormal, the cause of the server's startup failure is determined to be a flash memory malfunction. The controller reads the register information and analyzes it to locate the root cause of the failure.
[0006] On the one hand, if the controller does not detect a system startup success confirmation signal from the basic input / output system within a first preset time, then the server is determined to be in a startup failure state. Before the controller verifies the flash memory status, the process also includes: When the server is powered on, it performs a power-on self-test through the basic input / output system. If the power-on self-test passes, it enters the system boot process. After the boot process is completed, a timer is started to obtain the time. The power-on self-test includes hardware initialization and fault diagnosis. When the timing reaches the second preset time, the system starts successfully and a confirmation signal is output to the controller through the basic input / output system. The second preset time is shorter than the first preset time.
[0007] On the one hand, the controller reads the complete flash memory image and register information, and analyzes and locates the root cause of the fault, including: Based on the complete flash memory image restoration boot process, determine whether the firmware has a fault; Based on the register information, locate the central processing unit execution node at the time of startup failure and determine whether a software or hardware failure has occurred.
[0008] On the one hand, the controller reads register information and analyzes it to locate the root cause of the fault, including: The register information is read by the controller; the register information includes register values. The register values are compared with the register baseline values when the server starts normally to identify abnormal register values that deviate from the register baseline values, and the abnormal addresses corresponding to the abnormal register values are determined. By referring to the architecture manual of the central processing unit, the abnormal register value is decoded, and the fault characteristics corresponding to the abnormal register value are analyzed. The abnormal address is mapped to a preset stage of the power-on self-test, and combined with the fault characteristics, the specific stage at which the server startup failure occurred and the corresponding execution instruction are located.
[0009] On the one hand, it also includes: If the controller detects a system startup success confirmation signal output by the basic input / output system within the first preset time, then the server is determined to be in a normal startup state, a startup log is recorded, and the startup log is stored locally on the controller. The startup log includes at least a real-time timestamp, startup time, basic input / output system version, the time of receiving the system startup success confirmation signal, and startup self-test data.
[0010] On the one hand, if the controller detects a system startup success confirmation signal output by the basic input / output system within the first preset time period, then the server is determined to be in a normal startup state, including: The controller monitors the status of the input / output interface pins in real time. If the status of the input / output interface pins is detected to be high within the first preset time, the server is determined to be in a normal startup state. The input / output interface pin is the pin between the controller and the basic input / output system, and the input / output interface pin is defined as the system startup successful confirmation signal terminal.
[0011] On the one hand, the controller verifies the flash memory status, including: The controller acquires control of the serial peripheral interface of the flash memory, and reads the flash memory identification code of the flash memory using the serial peripheral interface protocol; the flash memory identification code includes the manufacturer identification code and the device identification code. The manufacturer identification code is compared with a preset list of standard manufacturer identification codes, and the device identification code is compared with a preset list of standard device identification codes. If any of the preset conditions are met, the flash memory status is abnormal; the preset conditions are: manufacturer identification code comparison failure, inability to read manufacturer identification code, device identification code comparison failure, and inability to read device identification code. If the manufacturer identification code and the device identification code match, the flash memory status register and data check value are checked. If the check passes, the flash memory status is determined to be normal; if the check fails, the flash memory status is determined to be abnormal.
[0012] The present invention also provides a server startup failure detection device, comprising: The fault detection module is used to determine that the server is in a startup fault state if the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time, and to verify the flash memory status through the controller. The first positioning module is used to determine that the cause of the server's startup failure is a system crash if the flash memory status is normal. It reads the complete flash memory image and register information through the controller and analyzes and locates the root cause of the failure. The second positioning module is used to determine that the cause of the server's startup failure is a flash memory malfunction if the flash memory status is abnormal. It reads register information through the controller and analyzes it to locate the root cause of the failure.
[0013] The present invention also provides a server startup failure detection device, comprising: Memory, used to store computer programs; A processor is used to implement the server startup failure detection method described above when executing the computer program.
[0014] The present invention also provides a computer-readable storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the server startup fault detection method described above.
[0015] The present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the server startup fault detection method described above.
[0016] As can be seen from the above technical solution, this invention determines that the server is in a startup failure state if the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time, and verifies the flash memory status through the controller; if the flash memory status is normal, the cause of the server startup failure is determined to be a system crash, and the controller reads the complete flash memory image and register information for analysis and location of the root cause of the failure; if the flash memory status is abnormal, the cause of the server startup failure is determined to be a flash memory malfunction, and the controller reads register information for analysis and location of the root cause of the failure. The beneficial effects of this invention are: through the startup status verification and fault classification processing mechanism of the controller and the basic input / output system working together, the controller can accurately distinguish the startup failure type, providing a basis for targeted fault repair and reducing invalid restarts; and different information collection logic and fault root cause location are executed according to the startup failure type. By collecting the complete flash memory image and register information, the server fault state is maintained to avoid environmental damage, and the data can be exported through a remote operation and maintenance platform, which can quickly locate the root cause of the failure; improving operation and maintenance efficiency, replacing manual on-site troubleshooting, adapting to large-scale data center scenarios, shortening fault repair time, and reducing business interruption losses.
[0017] In addition, the present invention also provides a server startup failure detection device, equipment and storage medium, which also have the above-mentioned beneficial effects. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0019] Figure 1 A flowchart of a server startup failure detection method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a server startup failure detection device provided in an embodiment of the present invention; Figure 3This is a schematic diagram of a server startup failure detection device provided in an embodiment of the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] In large-scale data center operations and critical business continuity scenarios, the efficiency of fault diagnosis and recovery during the server boot-up phase directly determines operational costs and the extent of business loss. Boot failure, a high-frequency fault type, often leads to a cascading impact due to delayed troubleshooting. Currently, the server boot process primarily relies on the BIOS (Basic Input / Output System) to complete POST (Power-On Self Test, used to check if hardware is functioning correctly) and boot loading. While the controller possesses hardware monitoring and remote management capabilities, the interaction between the BIOS and controller is largely limited to basic status reading, resulting in significant technical shortcomings in collaborative boot failure diagnosis. Furthermore, when boot failure occurs, traditional solutions often employ blind restart strategies, which fail to pinpoint the root cause and may damage the downtime environment, leading to the loss of critical fault information and increasing the difficulty of subsequent troubleshooting. Moreover, when restarting is ineffective, manual on-site troubleshooting relies on external devices to read BIOS logs and hardware status, resulting in long troubleshooting cycles, low efficiency, high operational costs, and difficulty in widespread application in large-scale data center scenarios.
[0022] It is evident that current server startup failure detection technologies suffer from problems such as lack of interactive verification, ambiguous distinction between failure types, susceptibility to damage in downtime environments, and insufficient preservation of failure data, failing to meet the demands of modern data centers for startup reliability and intelligent operation and maintenance.
[0023] To address the aforementioned problems, this invention proposes a server startup failure detection method, for details of which can be found in the following reference. Figure 1 , Figure 1 A flowchart illustrating a server startup failure detection method provided in an embodiment of the present invention. The method may include: S101: If the controller does not detect a system startup success confirmation signal from the basic input / output system within the first preset time, the server is determined to be in a startup failure state, and the flash memory status is verified by the controller.
[0024] This embodiment does not limit the controller. For example, it can be a general-purpose controller or a controller specific to a server. For example, it can be a BMC (Baseboard Management Controller). A BMC is a controller specifically designed for monitoring and managing servers. Its main functions include: 1) Device information management: Recording detailed server information, such as model, manufacturer, production date, and production and technical information for each component, chassis and motherboard information, etc. It also records its own information, such as the server hostname, IP (Internet Protocol) address, and BMC firmware version. 2) Server status monitoring and management: Real-time monitoring of the health status of various key server components (such as CPU (Central Processing Unit), memory, hard drive, fans, and chassis, etc.) including temperature and voltage. Based on the data from temperature acquisition points, the BMC adjusts fan speeds to ensure the server does not overheat and controls overall power consumption within a reasonable range. If any component of the server malfunctions, the BMC will promptly report the relevant information to the upper-level network administrator using various industry-standard protocols (such as SNMP (Simple Network Management Protocol), SMTP (Simple Mail Transfer Protocol), and Redfish (Redfish Scalable Platforms Management API)). 3) Remote server control and management: Allows administrators to remotely perform operations such as powering on / off, restarting, maintenance, firmware updates, and system installation. 4) Maintenance management: Includes log management, user management, BIOS management, and alarm management to ensure stable server operation. It should be noted that Flash memory, as the storage medium for BIOS firmware, will directly cause boot interruption if damaged, while system crashes may be caused by hardware malfunctions such as CPU or memory failures or firmware logic errors; the repair strategies for these two are completely different. Therefore, this method requires the controller to perform a preliminary verification of the Flash hardware status when determining a server boot failure.
[0025] This embodiment does not specifically limit the interaction method between the BIOS and the controller. For example, it could be through GPIO (General Purpose Input Output) state changes or log reception. Furthermore, in this embodiment, the controller monitors the state of the input / output interface pins in real time. If a high-level signal is detected on the input / output interface pin within a first preset time, the server is determined to be in a normal startup state. That is, this embodiment reserves a dedicated GPIO pin between the BIOS chip and the controller, defined as a "system startup success confirmation signal," named "GPIO_OS_Ready." The BIOS is the signal outputter, and the controller is the signal receiver. A high level (3.3V) is agreed to be a valid confirmation signal. For example, after the server boots up and the BIOS completes its power-on self-test, a preset time is delayed before the GPIO_OS_Ready signal on the GPIO pin is pulled high.
[0026] Furthermore, the aforementioned verification of the flash memory status via the controller can specifically include: the controller acquiring control of the flash memory's Serial Peripheral Interface (SPI), enabling the controller to read the flash memory's identification code using the SPI protocol; wherein the flash memory identification code can specifically include a vendor identification code and a device identification code (Device ID); comparing the vendor identification code (Vendor ID) with a preset standard list of vendor identification codes, and comparing the device identification code with a preset standard list of device identification codes; if any of the preset conditions are met, the flash memory status is abnormal; the preset conditions are vendor identification code comparison failure, inability to read the vendor identification code, device identification code comparison failure, and inability to read the device identification code; if both the vendor identification code and the device identification code match, then the flash memory status register and data check value are verified; if the verification passes, the flash memory status is determined to be normal; if the verification fails, the flash memory status is determined to be abnormal. This embodiment acquires SPI control through the controller, reads and verifies the vendor ID, device ID, status register, and key data verification values, realizing multi-level accurate verification of Flash from chip legality and model compatibility to data integrity. It can quickly, reliably, and multi-dimensionally determine the status of Flash chips, avoid fault location deviations caused by misjudgment of a single verification point, and improve the stability and accuracy of fault determination.
[0027] Furthermore, if the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time, the server is determined to be in a startup failure state. Before the controller verifies the flash memory status, the process may further include: after the server is powered on, a power-on self-test is performed through the basic input / output system. If the power-on self-test passes, the system boot process begins. After the boot process is completed, a timer is started to obtain the timeout period. The power-on self-test includes hardware initialization and fault diagnosis. When the timeout period reaches a second preset time, a system startup success confirmation signal is output to the controller through the basic input / output system. The second preset time is less than the first preset time.
[0028] This embodiment does not specifically limit the first and second preset times. For example, the second preset time can be 10 minutes, and the first preset time can be 15 minutes. The meaning of the second preset time is: the preset time (such as 10 minutes) after BIOS POST ensures that the server OS (Operating System) boots up, i.e., the server boots successfully; while the first preset time provides a timeout period for the second preset time. This embodiment considers that if other signals are added to determine the boot status, additional hardware GPIO checks would be required. Therefore, this embodiment directly determines the boot status through time, which is more convenient and easier to operate than adding other signals.
[0029] S102: If the flash memory is in normal condition, the cause of the server startup failure is determined to be a system crash. The controller reads the complete flash memory image and register information and analyzes and locates the root cause of the failure.
[0030] If the flash memory is in normal condition, it can be determined that the boot failure is not caused by the flash hardware. Therefore, the boot failure can be further pinpointed to a system crash (referring to a BIOS execution phase freeze / runaway). The controller can read register information through the CPU's debug interface and simultaneously read the complete flash image via the SPI protocol, packaging these two types of data and naming them "boot failure data." Furthermore, the packaged boot failure data can be stored in a dedicated flash partition within the controller, and alarm information (including fault type, number of failures, and data storage path) can be pushed to a remote maintenance platform via the IPMI (Intelligent Platform Management Interface) protocol. For flash damage scenarios, an additional alarm level of "Flash needs priority replacement" is marked. The controller can then maintain the server state until maintenance personnel intervene remotely or on-site, preventing repeated boots from disrupting the crashed environment.
[0031] It's important to note that register information contains detailed CPU data; specifically, it refers to CPU register information, which can be analyzed for instruction addresses, status flags, stack pointers, etc. Collecting register information is crucial for confirming the normality of CPU data and further diagnosing whether a crash was caused by the CPU, and identifying which CPU data triggered the system crash. In other words, it allows for further pinpointing the instruction and stage at which the system crashed based on the CPU's execution context.
[0032] It's important to note that the complete Flash image contains the BIOS operating status, log information to be transmitted to the controller (operation log), its own recorded OS data, the BIOS image, power-on self-test (POST) records, etc., making it a "full log library" of the boot process. Collecting the complete Flash image is to determine whether the BIOS is operating normally, whether there is more detailed fault data in the logs to be transmitted to the controller, and whether OS operating data is recorded. Furthermore, the complete BIOS image can be burned to other servers of the same model, facilitating problem reproduction and further identifying the root cause of the fault.
[0033] Furthermore, the above-mentioned method of reading the complete flash memory image and register information through the controller and analyzing and locating the root cause of the fault can specifically include: reconstructing the boot process based on the complete flash memory image to determine whether the firmware has a fault; and locating the central processing unit execution node at the time of boot failure based on the register information to determine whether a software or hardware fault has occurred.
[0034] It should be noted that the entire boot process can be restored using a complete flash memory image to fill the gaps in the boot phase where there are no system logs. This fully reconstructs every step from power-on to failure, further identifying firmware faults such as firmware code issues or image integrity problems. Register information can further determine if there are hardware or software faults related to instruction execution, bus access, or hardware initialization. However, relying on a single type of data has limitations; therefore, a comprehensive analysis combining the complete flash memory image and register information is necessary.
[0035] Examples: Example 1: If the RIP (Routing Information Protocol) in the register information points to the memory initialization instruction, and the POST record of the complete flash image shows 0x13 (memory detection failed), then it can be confirmed that the problem is a memory hardware failure, not a BIOS logic problem; Example 2: If the register information shows that the instruction executes normally, but the runtime log of the complete flash image shows that the integrity check failed, then it can be confirmed that the BIOS firmware is corrupted, not that the CPU is executing abnormally; Example 3: If the register information shows that the PCIe (Peripheral Component Interconnect Express) instruction execution timed out, and the runtime log of the complete flash image shows that a certain network card enumeration failed, then it can be determined that the network card hardware failure is causing the startup to freeze.
[0036] Furthermore, the above-mentioned process of restoring the boot process from the complete flash memory image to determine whether the firmware has a fault may specifically include: Step 11: Use the Basic Input / Output System (PIOS) parsing tool to split the complete flash memory image and extract the PIOS image, runtime logs, and power-on self-test (POST) records.
[0037] Specifically, the parsing tools can be: Aptio (BIOS / UEFI firmware development and parsing tool), BIOSEditor (BIOS editing and parsing tool), or the open-source tool UEFITool (UEFI firmware parsing and editing tool).
[0038] Step 12: Perform an integrity check on the basic input / output system image and determine whether the firmware has been tampered with or damaged.
[0039] Specifically, the firmware integrity is verified by checking the BIOS Image (e.g., comparing the MD5 (Message-Digest Algorithm 5) / SHA256 (Secure Hash Algorithm 256) against the official version) to check for tampering / damage. If the BIOS Image integrity verification fails, it means that the firmware is damaged / flashing failed, and the official firmware needs to be re-flashed.
[0040] Step 13: Perform in-depth analysis on the extracted operation logs and power-on self-test records. Based on the error codes, timestamps, device identification codes, and power-on codes in the operation logs, locate the self-test failure items and fault types.
[0041] Specifically, filter logs from the runtime logs for the period of startup failure (e.g., "Memory Test Failed" or "PCIe Device No Response"). Pay close attention to the "error code, timestamp, and device ID" in the runtime logs. For example, "Device 0000:01:00.0 Enumeration Timeout" in the log indicates a device enumeration timeout in PCIe slot 1. Records of "temperature exceeding limits" or "voltage abnormality" in the runtime logs can trace the startup failure as being due to hardware overheating or unstable power supply. Peripheral enumeration failure records can pinpoint the faulty peripheral (e.g., RAID (Redundant Array of Independent Disks) card, network card). The key to the POST (Power-On Self-Test) log is the POST code (e.g., 0x13 corresponds to memory testing, 0x26 corresponds to graphics card initialization). Refer to the POST code table to locate the failed POST items and their types. For example, if the POST log stops at 0x55, it indicates a hard drive initialization failure; if the POST loop is at 0x15, it indicates a memory test failure. If the POST record shows "CMOS Checksum Error", it means that the BIOS configuration parameters are lost and the CMOS (Complementary Metal-Oxide-Semiconductor) needs to be reset.
[0042] Step 14: Decompile the basic input / output system image to extract relevant firmware modules, check the startup script and resource allocation logic, and verify whether there are any logical errors or configuration conflicts.
[0043] Specifically, decompile the BIOS image (e.g., extract the PE32 module using UEFITool) and check the startup scripts (e.g., DSC (Platform Description File) and FDF (Flash Description File) for logical errors or configuration conflicts (e.g., peripheral enumeration order errors or resource allocation conflicts).
[0044] S103: If the flash memory status is abnormal, the cause of the server's startup failure is determined to be a flash memory malfunction. The controller reads the register information and analyzes it to locate the root cause of the failure.
[0045] When the flash memory status is abnormal, the boot failure can be directly identified as a flash memory malfunction, because the image is no longer reliable and therefore there is no need to read the image. It is only necessary to read the register information to confirm whether the CPU hangs while accessing the flash memory, further determining the root cause of the boot failure.
[0046] Furthermore, the aforementioned process of reading register information from the controller and analyzing it to pinpoint the root cause of the fault can specifically include: Step 21: Read register information through the controller; register information includes register values.
[0047] Specifically, register information serves as a "temporary data warehouse" during CPU runtime. Register values during a fault can precisely pinpoint the instruction execution node where the process is stalled or malfunctioning. This embodiment does not limit the types of registers. To improve efficiency, key registers (general-purpose registers, program counter, stack pointer, status register, and debug register) can be analyzed in detail.
[0048] Step 22: Compare the register values with the register baseline values when the server starts normally, identify abnormal register values that deviate from the register baseline values, and determine the abnormal addresses corresponding to the abnormal register values.
[0049] For example, the RIP register stores the address of the currently executing instruction. If this address points to a certain code segment in the BIOS startup phase (such as memory initialization or peripheral enumeration), it indicates that the fault is stuck at the instruction execution stage. If the carry or overflow flag bit of the EFLAGS (ExtendedFlags Register) is abnormal, it indicates that the instruction execution has failed.
[0050] Step 23: Refer to the architecture manual of the central processing unit to decode the abnormal register value and analyze the fault characteristics corresponding to the abnormal register value.
[0051] Referring to the corresponding CPU architecture manual (such as the CPU documentation for x86 / c86 / ARM), the meaning of the decoded register values is as follows: 1) If the debug register has a value, it means that the CPU has triggered a hardware breakpoint, and the startup process corresponding to the breakpoint can be located; 2) If the stack pointer points to an illegal memory address, it means that there is a stack overflow / memory addressing error during the startup process.
[0052] Step 24: Map the abnormal address to the preset stage of the power-on self-test, and combine the fault characteristics to locate the specific stage at which the server startup failure occurred and the corresponding execution instruction.
[0053] Specifically, the abnormal address is mapped to the BIOS boot stage (i.e., the key nodes of the power-on self-test: CPU initialization - memory detection - peripheral enumeration - firmware loading), and combined with the fault characteristics obtained from the above analysis, it is determined "which stage and which instruction" the fault occurred in.
[0054] As can be seen, analyzing register information can accurately pinpoint the startup dead point: replacing the fuzzy location of traditional log troubleshooting, it directly locks the location of the CPU executing abnormal instructions (such as memory initialization failure, PCIe device enumeration timeout); it can also distinguish between hardware / software faults: a) if the register value shows that the instruction execution is stuck at the memory read / write stage, and the memory address is valid, it is likely a memory hardware fault; b) if the instruction address points to the BIOS code segment and the verification is abnormal, it is likely a BIOS firmware logic error; 3) shorten the fault troubleshooting cycle: from hour-level troubleshooting by replacing hardware one by one to minute-level root cause location.
[0055] Furthermore, after determining that the server is in a startup failure state, the method further includes: performing a restart operation on the server through the controller; if the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time threshold, the controller records the number of startup failures; when the cumulative number of failures reaches a preset threshold, automatic restart is stopped. This embodiment can directly locate the cause of startup failure and the root cause of the fault after detecting a startup failure, or it can attempt to restart again. When the number of startup failures reaches a certain value, the cause of startup failure and the root cause of the fault can be located.
[0056] Furthermore, it can also include: if the controller detects a system startup success confirmation signal output by the Basic Input / Output System (BIOS) within a first preset time period, then the server is determined to be in a normal startup state, a startup log is recorded, and the startup log is stored locally on the controller. The startup log may include at least a real-time timestamp, startup time, BIOS version, the time the system startup success confirmation signal was received, and startup self-test data. This startup log can be stored locally on the controller without triggering any other operations.
[0057] The server startup failure detection method provided in this embodiment of the invention is as follows: S101: If the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time, the server is determined to be in a startup failure state, and the flash memory status is verified by the controller; S102: If the flash memory status is normal, the cause of the server startup failure is determined to be a system crash, and the controller reads the complete flash memory image and register information, and analyzes and locates the root cause of the failure; S103: If the flash memory status is abnormal, the cause of the server startup failure is determined to be a flash memory abnormality, and the controller reads the register information, and analyzes and locates the root cause of the failure. This method achieves accurate identification, environmental preservation, and efficient recovery of startup failures through a startup status verification and fault classification processing mechanism that coordinates the controller and the basic input / output system, reducing operation and maintenance costs and business losses; and executes different information collection logic and fault root cause location according to the startup failure type. By collecting the complete flash memory image and register information, the server failure state is maintained to avoid environmental damage, and the data can be exported through a remote operation and maintenance platform, which can quickly locate the root cause of the failure; improves operation and maintenance efficiency, replaces manual on-site troubleshooting, adapts to large-scale data center scenarios, shortens fault repair time, and reduces business interruption losses. Furthermore, by determining whether a GPIO acknowledgment signal has been received based on the time dimension, the controller can effectively distinguish the on state and avoid misjudgment during operation and maintenance.
[0058] The server startup failure detection device provided in the embodiments of the present invention will be described below. The server startup failure detection device described below can be referred to in correspondence with the server startup failure detection method described above.
[0059] Please refer to the details. Figure 2 , Figure 2 A schematic diagram of a server startup failure detection device provided in an embodiment of the present invention may include: The fault detection module 100 is used to determine that the server is in a startup fault state if the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time, and to verify the flash memory status through the controller. The first positioning module 200 is used to determine that the cause of the server's startup failure is a system crash if the flash memory status is normal, and to read the complete flash memory image and register information through the controller and analyze and locate the root cause of the failure. The second positioning module 300 is used to determine that the cause of the server's startup failure is a flash memory malfunction if the flash memory status is abnormal. It then reads register information through the controller and analyzes it to locate the root cause of the failure.
[0060] Furthermore, based on the above embodiments, the server startup fault detection device may further include: The timing module is used to perform a power-on self-test through the basic input / output system after the server is powered on. If the power-on self-test passes, the system boot process is entered. After the boot process is completed, the timing starts to obtain the timing time. The power-on self-test includes hardware initialization and fault diagnosis. The output module is used to output a system startup success confirmation signal to the controller through the basic input / output system when the timing time reaches the second preset time. The second preset time is shorter than the first preset time.
[0061] Furthermore, based on the above embodiments, the first positioning module 200 may include: The first positioning unit is used to determine whether there is a firmware fault based on the complete flash memory image restoration boot process. The second positioning unit is used to locate the central processing unit execution node when the startup fails based on the register information, and to determine whether a software or hardware failure has occurred.
[0062] Furthermore, based on the above embodiments, the second positioning module 300 may include: The first reading unit is used to read the register information through the controller; the register information includes register values. The first comparison unit is used to compare the register value with the register reference value when the server starts normally, identify abnormal register values that deviate from the register reference value, and determine the abnormal address corresponding to the abnormal register value. The parsing unit is used to decode the abnormal register value by referring to the architecture manual of the central processing unit and to parse out the fault characteristics corresponding to the abnormal register value. The third positioning unit is used to map the abnormal address to a preset stage of the power-on self-test, and, in conjunction with the fault characteristics, locate the specific stage at which the server startup failure occurred and the corresponding execution instruction.
[0063] Furthermore, based on the above embodiments, the server startup fault detection device may further include: The normal module is used to determine that the server is in a normal startup state if the controller detects a system startup success confirmation signal output by the basic input / output system within the first preset time, records the startup log, and stores the startup log in the controller's local storage; the startup log includes at least a real-time timestamp, startup time, basic input / output system version, the time of receiving the system startup success confirmation signal, and startup self-test data.
[0064] Furthermore, based on the above embodiments, the normal module may include: The determination unit is used to monitor the status of the input / output interface pins in real time through the controller. If the status of the input / output interface pins is detected to be a high-level signal within the first preset time, the server is determined to be in a normal startup state. The input / output interface pin is the pin between the controller and the basic input / output system, and the input / output interface pin is defined as the system startup successful confirmation signal terminal.
[0065] Furthermore, based on any of the above embodiments, the fault detection module 100 may include: The second reading unit is used by the controller to obtain control of the serial peripheral interface of the flash memory, so as to read the flash memory identification code of the flash memory through the serial peripheral interface protocol by the controller; the flash memory identification code includes the manufacturer identification code and the device identification code; The second comparison unit is used to compare the manufacturer identification code with a preset list of standard manufacturer identification codes, and to compare the device identification code with a preset list of standard device identification codes. The flash memory anomaly determination unit is used to determine that the flash memory is in an abnormal state if any of the preset conditions are met; the preset conditions are manufacturer identification code comparison failure, inability to read manufacturer identification code, device identification code comparison failure, and inability to read device identification code. The verification unit is used to verify the flash memory status register and data verification value if the manufacturer identification code and the device identification code are consistent. If the verification passes, the flash memory status is determined to be normal; if the verification fails, the flash memory status is determined to be abnormal.
[0066] It should be noted that the order of the modules and units in the aforementioned server startup fault detection device can be changed without affecting the logic.
[0067] The server startup fault detection device provided in this embodiment of the invention uses a fault detection module 100 to determine that the server is in a startup fault state if the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time, and verifies the flash memory status through the controller; a first positioning module 200 is used to determine that the cause of the server startup fault is system crash if the flash memory status is normal, and reads the complete flash memory image and register information through the controller to analyze and locate the root cause of the fault; a second positioning module 300 is used to determine that the cause of the server startup fault is flash memory abnormality if the flash memory status is abnormal, and reads register information through the controller to analyze and locate the root cause of the fault. This device employs a startup status verification and fault classification processing mechanism that coordinates the controller with the basic input / output system. This enables the controller to accurately distinguish startup fault types, providing a basis for targeted fault repair and reducing unnecessary restarts. Furthermore, it executes different information acquisition logic and fault root cause location based on the startup fault type. By acquiring complete flash memory images and register information, it maintains the server's fault state to prevent environmental damage. The data can be exported through a remote operation and maintenance platform, enabling rapid fault root cause location. This improves operation and maintenance efficiency, replaces manual on-site troubleshooting, adapts to large-scale data center scenarios, shortens fault repair time, and reduces business interruption losses.
[0068] Figure 3 This is a schematic diagram of a server startup failure detection device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the server startup fault detection device may include: Memory 60 is used to store computer programs; The processor 61 is used to execute computer programs to implement the steps of the server startup fault detection method as described in the above embodiments.
[0069] The server startup failure detection device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.
[0070] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.
[0071] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the server startup failure detection method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, relevant data in the server startup failure detection method.
[0072] In some embodiments, the server startup fault detection device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.
[0073] Those skilled in the art will understand that Figure 3 The structure shown does not constitute a limitation on the server startup failure detection device and may include more or fewer components than shown.
[0074] It is understood that if the server startup fault detection method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.
[0075] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the server startup fault detection method described above.
[0076] The following describes a computer program product provided by an embodiment of this application. The computer program product described below can be referred to in conjunction with other embodiments described herein.
[0077] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed server startup failure detection method.
[0078] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0079] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0080] Finally, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0081] The above provides a detailed description of a server startup failure detection method, apparatus, device, and storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A method for detecting server startup failures, characterized in that, include: If the controller does not detect a system startup success confirmation signal from the basic input / output system within the first preset time, the server is determined to be in a startup failure state, and the flash memory status is verified by the controller. If the flash memory is in normal condition, the cause of the server's startup failure is determined to be a system crash. The controller reads the complete flash memory image and register information and analyzes and locates the root cause of the failure. If the flash memory status is abnormal, the cause of the server's startup failure is determined to be a flash memory malfunction. The controller reads the register information and analyzes it to locate the root cause of the failure.
2. The server startup failure detection method according to claim 1, characterized in that, If the controller does not detect a system startup success confirmation signal from the basic input / output system within a first preset time period, the server is determined to be in a startup failure state. Before the controller verifies the flash memory status, the process further includes: When the server is powered on, it performs a power-on self-test through the basic input / output system. If the power-on self-test passes, it enters the system boot process. After the boot process is completed, a timer is started to obtain the time. The power-on self-test includes hardware initialization and fault diagnosis. When the timing reaches the second preset time, the system starts successfully and a confirmation signal is output to the controller through the basic input / output system. The second preset time is shorter than the first preset time.
3. The server startup failure detection method according to claim 1, characterized in that, The controller reads the complete flash memory image and register information, and analyzes and locates the root cause of the fault, including: Based on the complete flash memory image restoration boot process, determine whether the firmware has a fault; Based on the register information, locate the central processing unit execution node at the time of startup failure and determine whether a software or hardware failure has occurred.
4. The server startup failure detection method according to claim 1, characterized in that, The controller reads register information and analyzes it to locate the root cause of the fault, including: The register information is read by the controller; the register information includes register values. The register values are compared with the register baseline values when the server starts normally to identify abnormal register values that deviate from the register baseline values, and the abnormal addresses corresponding to the abnormal register values are determined. By referring to the architecture manual of the central processing unit, the abnormal register value is decoded, and the fault characteristics corresponding to the abnormal register value are analyzed. The abnormal address is mapped to a preset stage of the power-on self-test, and combined with the fault characteristics, the specific stage at which the server startup failure occurred and the corresponding execution instruction are located.
5. The server startup failure detection method according to claim 1, characterized in that, Also includes: If the controller detects a system startup success confirmation signal output by the basic input / output system within the first preset time, then the server is determined to be in a normal startup state, a startup log is recorded, and the startup log is stored locally on the controller. The startup log includes at least a real-time timestamp, startup time, basic input / output system version, the time of receiving the system startup success confirmation signal, and startup self-test data.
6. The server startup failure detection method according to claim 5, characterized in that, If, within the first preset time period, the controller detects a system startup success confirmation signal output by the basic input / output system, then the server is determined to be in a normal startup state, including: The controller monitors the status of the input / output interface pins in real time. If the status of the input / output interface pins is detected to be high within the first preset time, the server is determined to be in a normal startup state. The input / output interface pin is the pin between the controller and the basic input / output system, and the input / output interface pin is defined as the system startup successful confirmation signal terminal.
7. The server startup failure detection method according to any one of claims 1 to 6, characterized in that, The controller verifies the flash memory status, including: The controller acquires control of the serial peripheral interface of the flash memory, and reads the flash memory identification code of the flash memory using the serial peripheral interface protocol; the flash memory identification code includes the manufacturer identification code and the device identification code. The manufacturer identification code is compared with a preset list of standard manufacturer identification codes, and the device identification code is compared with a preset list of standard device identification codes. If any of the preset conditions are met, the flash memory status is abnormal; the preset conditions are: manufacturer identification code comparison failure, inability to read manufacturer identification code, device identification code comparison failure, and inability to read device identification code. If the manufacturer identification code and the device identification code match, the flash memory status register and data check value are checked. If the check passes, the flash memory status is determined to be normal; if the check fails, the flash memory status is determined to be abnormal.
8. A server startup failure detection device, characterized in that, include: The fault detection module is used to determine that the server is in a startup fault state if the controller does not detect a system startup success confirmation signal output by the basic input / output system within a first preset time, and to verify the flash memory status through the controller. The first positioning module is used to determine that the cause of the server's startup failure is a system crash if the flash memory status is normal. It reads the complete flash memory image and register information through the controller and analyzes and locates the root cause of the failure. The second positioning module is used to determine that the cause of the server's startup failure is a flash memory malfunction if the flash memory status is abnormal. It reads register information through the controller and analyzes it to locate the root cause of the failure.
9. A server startup failure detection device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the server startup failure detection method as described in any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the server startup fault detection method as described in any one of claims 1 to 7.