Address processing method and processor

Abstract

The present disclosure provides an address processing method and a processor, the method comprising: using a memory management unit, in a case where an address deletion request for a target physical address is received, determining, according to first running state information in a first running state register, a running storage unit in which the target physical address is stored from a first level storage unit of a multi-level storage unit, and forwarding the address deletion request to the running storage unit; the first level storage unit is a level with the largest storage capacity in the multi-level storage unit; using the memory management unit, in a case where address deletion completion information returned by the running storage unit is received, returning first deletion completion information to a sender of the address deletion request, wherein the address deletion completion information is sent after the running storage unit deletes the cached target physical address. According to the embodiments of the present disclosure, the address deletion efficiency can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an address processing method and a processor. Background Technology

[0002] With the continuous development of computer technology, computers store the addresses required for performing computational tasks in the storage system and instruct the storage system to delete the addresses when they are no longer needed.

[0003] The storage system of the relevant technology includes multiple storage units. When a storage unit fails, the storage system cannot determine whether the failed storage unit has completed address deletion, which causes the deletion operation of the storage system to stop, thereby reducing the address deletion efficiency. Summary of the Invention

[0004] This disclosure provides an address processing method and a processor.

[0005] In a first aspect, this disclosure provides an address processing method applied to a processor, the processor including a memory management unit and a multi-level storage unit, the memory management unit including a first running status register, the method including: using the memory management unit, upon receiving an address deletion request for a target physical address, determining, based on first running status information in the first running status register, the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit, and forwarding the address deletion request to the running storage unit; the first-level storage unit is the level with the largest storage capacity among the multi-level storage units; using the memory management unit, upon receiving address deletion completion information returned by the running storage unit, returning first deletion completion information to the sender of the address deletion request, wherein the address deletion completion information is sent by the running storage unit after deleting the cached target physical address.

[0006] Secondly, this disclosure provides a processor, which includes a memory management unit and a multi-level storage unit, wherein the memory management unit includes a first running status register.

[0007] The memory management unit is configured to: upon receiving an address deletion request for a target physical address, determine the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit based on the first running status information in the first running status register, and forward the address deletion request to the running storage unit; the first-level storage unit is the level with the largest storage capacity among the multi-level storage units, and upon receiving address deletion completion information returned by the running storage unit, return first deletion completion information to the sender of the address deletion request, wherein the address deletion completion information is sent by the running storage unit after deleting the cached target physical address.

[0008] The target storage unit in the multi-level storage unit is configured to: upon receiving an address deletion request for a target physical address, delete the cached target physical address; determine the running storage unit storing the target physical address from the next-level storage unit based on the second running status information in the second running status register; and forward the address deletion request to the running storage unit. Here, the target storage unit is a storage unit in the multi-level storage unit that has a next-level storage unit, and the second running status register is a register configured in the target storage unit. Using the target storage unit, upon receiving address deletion completion information returned by the running storage unit, return second deletion completion information to the sender of the address deletion request.

[0009] The address processing method provided in this embodiment is applied to the memory management unit of a processor. When the first-level storage unit obtains the target physical address, it records the first-level storage unit as a fault-free running storage unit. Upon receiving an address deletion request for the target physical address, the memory management unit forwards the address deletion request to the fault-free running storage unit. Since the running storage unit is fault-free, it can respond to the received address deletion request by deleting the locally cached target physical address and sending address deletion completion information to the memory management unit. When the memory management unit receives the address deletion completion information returned by the running storage unit, it determines that the address deletion is complete and can return first deletion completion information to the sender of the address deletion request. This avoids the problem of deletion operation stalling due to storage unit failure and improves address deletion efficiency.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a flowchart of an address processing method provided in an embodiment of the present disclosure.

[0013] Figure 2 This is a schematic diagram illustrating the deletion of a PTE in an address processing method provided in an embodiment of this disclosure.

[0014] Figure 3 This is a schematic diagram of the processor structure in an address processing method provided in an embodiment of the present disclosure.

[0015] Figure 4 This is a schematic diagram illustrating the application of an address processing method provided in an embodiment of this disclosure.

[0016] Figure 5 A block diagram of a processor provided in an embodiment of this disclosure. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0018] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0019] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, they specify the presence of features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0021] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0022] The address processing method according to embodiments of this disclosure can be executed by an electronic device such as a terminal device or a server. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The method can be implemented by a processor calling computer-readable program instructions stored in memory. Alternatively, the method can be executed by a server.

[0023] The technical terms used in the embodiments of this disclosure are explained below.

[0024] TLB (Translation Lookaside Buffer): This is a high-speed cache inside the GPU used to cache recently used PTEs.

[0025] PTE (Page Table Entry): is a page table entry, specifically a row in the page table. Each row in the page table records a mapping relationship from VA to PA.

[0026] VA (Virtual Address): refers to a virtual address.

[0027] PA (Physical Address): refers to the physical address.

[0028] MMU (Memory Management Unit) refers to the memory management unit; the MMU is a hardware module in the GPU (or CPU) specifically responsible for translating virtual addresses (VA) into physical addresses (PA). The task of the MMU is to accurately translate the "virtual address" accessed by the program into a "physical address" that the hardware can process.

[0029] Invalid_Req: Invalid request, used to invalidate outdated PTEs.

[0030] Invalid_Done: Invalid completion instruction.

[0031] Scheduler: This is the scheduler, the GPU's task scheduling module, used to manage task distribution, synchronization, and lifecycle management, and to prepare the environment required for tasks.

[0032] SM (Streaming Multiprocessor): refers to a streaming multiprocessor; the SM is the basic computing unit in a GPU that actually performs calculations, and a GPU usually contains dozens to hundreds of SMs.

[0033] LSU (Load / Store Unit): This is a hardware unit inside SM that is responsible for read and write operations. The LSU can read data from memory into the registers in the LSU, or write data from the registers in the LSU back to memory.

[0034] translate_req(Translation Request): This is an address translation request, the purpose of which is to translate a virtual address (VA) into its corresponding physical address (PA).

[0035] translate_resp (Translation Response): This refers to the response returned by the MMU (or TLB) after completing the address translation, which includes the translation result. The translation result includes, but is not limited to, the corresponding physical address (PA), access permission bits (whether it is readable / write / execute), and whether it is a translation hit / miss.

[0036] With the continuous development of computer technology, computers store the data required for performing computational tasks in a storage system and instruct the storage system to delete the data when it is no longer needed. Related storage systems include multiple storage units. When a storage unit fails, the storage system cannot determine whether the failed storage unit has completed data deletion, causing the deletion operation to stall.

[0037] In the GPU architecture of related technologies, the TLB and MMU are essential modules. The MMU (Memory Management Unit) performs address translation, which makes program execution more convenient and safer by providing each program with an independent, contiguous "virtual address space." Programs use virtual addresses during runtime. That is, the virtual address (VA) is the logical address used by the program. The corresponding physical address (PA) is the actual hardware address of the data in real memory. The MMU is responsible for automatically and quickly "translating" the virtual address issued by the program into the real physical address when the program accesses memory. To achieve this mapping, the MMU maintains a page table that records the correspondence between virtual and physical addresses. The MMU queries the page table when performing address translation. To accelerate this process, the MMU also integrates a high-speed cache called the TLB, which stores recently used address mappings (i.e., virtual addresses and their corresponding physical addresses), thereby significantly improving translation efficiency.

[0038] During address deletion, if a downstream TLB becomes unusable due to manufacturing defects, the upstream MMU will be unable to collect all Invalid_Done signals, ultimately causing the GPU to freeze. To address this issue, two solutions are possible: The first is to introduce a timeout mechanism. The user sets a maximum waiting time. If this time is exceeded, the MMU considers a downstream fault to exist and sends an Invalid_Done signal directly to the GPU without waiting for downstream signals. The second solution is to add a register to the MMU to mark which downstream TLB_L1 is faulty, eliminating the need to wait for its Invalid_Done signal. Simultaneously, a register is added to TLB_L1 to mark which downstream TLB_L0 is faulty, eliminating the need to wait for its Invalid_Done signal.

[0039] However, the aforementioned timeout mechanisms or register marking techniques all rely on software configuration, which is not only time-consuming but also fails to balance performance and correctness. Timeout mechanisms face a dilemma: the waiting time cannot be too large or too small. If the time is set too small, downstream normal TLBs cannot invalidate outdated PTEs in time, causing the GPU to start working prematurely and use incorrect PTEs, compromising program correctness. Conversely, if the time is set too large, it leads to slow GPU startup times, impacting user experience. Register marking techniques require software to distinguish between normal and corrupted TLBs, and adjusting the TLB hierarchy requires the software, architecture, and design teams to realign, impacting project timelines.

[0040] Based on this, this disclosure provides an address processing method and a processor, as detailed in the explanations in the following embodiments.

[0041] Figure 1 A flowchart illustrating an address processing method provided in an embodiment of this disclosure. (Refer to...) Figure 1 The method is applied to a processor including a memory management unit and a multi-level storage unit. The memory management unit includes a first running status register. The method includes steps S11 to S12.

[0042] Step S11: Using the memory management unit, upon receiving an address deletion request for the target physical address, the running storage unit storing the target physical address is determined from the first-level storage unit of the multi-level storage unit according to the first running status information in the first running status register, and the address deletion request is forwarded to the running storage unit; the first-level storage unit is the level with the largest storage capacity in the multi-level storage unit.

[0043] The target physical address can be understood as the address cached in a multi-level storage unit, and the target physical address can be the physical address corresponding to the virtual address.

[0044] A multi-level storage unit can be composed of multiple storage units at different levels, and the address storage capacity and / or address read / write speed of the storage units at different levels can be different. The first-level storage unit is the one with the largest storage capacity in the multi-level storage unit; correspondingly, the last-level storage unit is the one with the smallest storage capacity in the multi-level storage unit; for example, this multi-level storage unit can be a multi-level TLB. The first-level storage unit can be a TLB that directly exchanges with the MMU, and the last-level storage unit can be a TLB that directly interacts with the LSU.

[0045] Address deletion requests can be understood as deletion requests targeting a physical address. Taking TLB and MMU as examples, MMU is responsible for converting VA to PA, while TLB caches the conversion result (i.e., the target physical address). When PTE (Page Table Entry, representing the mapping relationship between VA and PA) is updated, the GPU needs to invalidate outdated PTEs (i.e., target physical addresses) in TLB and MMU. Figure 2 This is a schematic diagram illustrating the deletion of a PTE in an address processing method provided in this embodiment of the present disclosure. Figure 2As can be seen, the GPU scheduler sends an Invalid_Req signal (i.e., an invalidation request) to the MMU. Upon receiving the signal, the MMU first invalidates outdated PTEs in its internal cache, and then broadcasts the Invalid_Req signal to downstream TLB0_L1 and / or TLB1_L1 (e.g., the first-level memory unit). Upon receiving the signal, TLB0_L1 and / or TLB1_L1 first invalidate outdated PTEs in their internal cache, and then broadcast the Invalid_Req signal to downstream TLB0_L0_0, TLB0_L0_1, TLB1_L0_0, and / or TLB1_L0_1 (i.e., the last-level memory unit). Upon receiving the signal, TLBs such as TLB0_L0_0 first invalidate their internal outdated PTEs, and then send an Invalid_Done signal (i.e., invalidation complete) to upstream TLB0_L1 and / or TLB1_L1. After TLB0_L1 and / or TLB1_L1 collect the downstream Invalid_Done signal, they send an Invalid_Done signal to the upstream MMU. After the MMU collects the downstream Invalid_Done signal, it sends an Invalid_Done signal to the GPU scheduler. Upon receiving the Invalid_Done signal, the GPU can use the MMU normally.

[0046] A running storage unit can be understood as a storage unit that is operating normally in a multi-level storage unit, that is, a storage unit without faults in a multi-level storage unit. For example, the storage unit can be a TLB, register, or cache, and the running storage unit can be a TLB, register, or cache without faults. In some embodiments, the target storage unit can record the first-level storage unit as a running storage unit when the first-level storage unit requests to obtain the target physical address.

[0047] The first running status register can be understood as a register used to store first running status information, which can be information used to represent running and non-running storage units in the first-level storage unit.

[0048] The processor in this disclosure can be configured according to the actual application scenario. For example, the processor can be a GPU or a CPU; or, the processor can be a GPU core or a CPU core.

[0049] In some embodiments, upon receiving an address deletion request for a target physical address, before determining the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit based on the first running status information in the first running status register, the method further includes: using a memory management unit, upon receiving a first address acquisition request sent by the first storage unit, determining the target physical address corresponding to the first address acquisition request, sending the target physical address to the first storage unit, and recording the first storage unit as a running storage unit, wherein the first storage unit is any one of at least one first-level storage unit.

[0050] Specifically, the memory management unit of this disclosure can receive a first address retrieval request sent by the first storage unit, determine a first virtual address from the address retrieval request, query the target physical address corresponding to the first virtual address from the page table or the cache of the memory management unit, and send the target physical address to the first storage unit. Simultaneously, the memory management unit will also mark the first storage unit as a running storage unit to facilitate subsequent address deletion and improve address deletion efficiency.

[0051] In some embodiments, the next-level storage unit is the last-level storage unit in a multi-level storage unit, and the last-level storage unit is connected to the task processing unit; the second address acquisition request is sent by the last-level storage unit to the target storage unit when it receives the task address acquisition request sent by the task processing unit and has not cached the target physical address; the task address acquisition request is sent by the task processing unit during the target task.

[0052] The target task can be understood as a task that needs to be executed by the task processing unit. Examples include computational tasks and data processing tasks. The task processing unit can be understood as a unit capable of processing the target task; for example, it could be a processing circuit or computing unit within a processor. The target task can be a task assigned to the task processing unit by the processor's scheduler.

[0053] A task address retrieval request can be understood as an address retrieval request sent by the task processing unit to the last-level storage unit. The aforementioned address retrieval request is a request sent between multiple levels of storage units.

[0054] Taking the application of the address processing method provided in this disclosure in an MMU scenario as an example, this address processing method will be explained. Figure 3 This is a schematic diagram of the processor structure in an address processing method provided in an embodiment of the present disclosure, based on... Figure 3As can be seen, a GPU core typically includes a Scheduler, several SMs (Solution Modules), and a MMU (Memory Management Unit). Each SM has its own independent LSU and corresponding TLB0_L0_0, TLB0_L0_1, TLB1_L0_0, and TLB1_L0_1 (the last level of memory). Multiple TLBs such as TLB0_L0_0 and TLB0_L0_1 share a single TLB0_L1 (the target memory unit), and multiple TLBs such as TLB0_L1 and TLB1_L1 share a single MMU (the target memory unit). The Scheduler is responsible for issuing tasks (target tasks) to the SMs and preparing the necessary environment for the tasks. The SMs are responsible for executing the tasks issued by the Scheduler, with memory access initiated by the LSUs. Taking the address translation operation between TLB0_L0_0, TLB0_L1, and MMU as an example, memory access requires the PA (Parent Address), but the LSU (Local Subsystem Unit) can only calculate the VA (Version Address). Therefore, the LSU sends a translation request to TLB0_L0_0 using the VA. When a missing value occurs in TLB0_L0_0, the translation request is sent to TLB0_L1 and the MMU level by level. After the MMU translates the VA into the PA (i.e., the target physical address), it returns the PA to the LSU along the TLB0_L1 and TLB0_L0_0 paths. Finally, the LSU can use the PA to access memory. At the same time, both TLB0_L1 and TLB0_L0_0 cache the translation result from VA to PA, thereby speeding up the next translation request.

[0055] As can be seen from the above embodiments, this disclosure effectively improves the translation efficiency from virtual address (VA) to physical address (PA) by constructing a multi-level address translation cache structure (e.g., TLB0_L0_0, TLB0_L1, MMU) in the GPU core, thereby optimizing GPU memory access performance.

[0056] In some embodiments, the first running status information includes a first running status flag bit; recording the first storage unit as a running storage unit includes: using a memory management unit, determining the first running status flag bit corresponding to the first storage unit from the first running status register according to the unit identifier of the first storage unit, and adjusting the first running status flag bit to a first value, wherein the first value is used to indicate that the first storage unit is a running storage unit.

[0057] The first running status flag can be understood as a binary bit used to indicate whether the first storage unit is a running storage unit. The first running status flag includes a first value or a second value. The first value is used to indicate that the first storage unit is a running storage unit; the second value is used to indicate that the first storage unit is not a running storage unit.

[0058] Specifically, the memory management unit in this disclosure can determine the first running status flag bit corresponding to the first storage unit from the first running status register according to the unit identifier of the first storage unit, wherein one flag bit in the first running status register is used to record the running status of a first-level storage unit; and adjust the value in the first running status flag bit to a first value.

[0059] Following the previous example, this disclosure can add a register R_Translate_Received (i.e., the first running status register) to the MMU; wherein, the bits in R_Translate_Received correspond one-to-one with the number of the next level TLB (i.e., the first level storage unit).

[0060] The bits in R_Translate_Received are used to indicate whether a Translate_Req sent by a downstream TLB (i.e., the first-level TLB) has been received; for example... Figure 3 The downstream TLBs of the MMU are TLB0_L1 and TLB1_L1; correspondingly, the R_Translate_Received bit of the MMU is used to indicate whether the Translate_Req of TLB0_L1 or TLB1_L1 has been received; where 0 (i.e., the second value) indicates that it has not been received, and 1 (i.e., the first value) indicates that it has been received.

[0061] As can be seen from the above embodiments, this disclosure can quickly determine which memory units are not faulty and are in use by using the first running status flag, thereby improving the efficiency of subsequent address deletion. By recording the downstream TLB access status, it is not necessary to wait for the Invalid_Done signal of the damaged TLB during the subsequent address deletion process, thus solving the problem of GPU freezing.

[0062] In some embodiments, there are multiple first-level storage units; before determining the target physical address corresponding to the first address acquisition request when receiving a first address acquisition request sent by a first storage unit, the method further includes: using a memory management unit to determine the first running status flag bits corresponding to multiple first-level storage units from a first running status register, and adjusting each first running status flag bit to a second value, wherein a second value is used to indicate that a first-level storage unit is a non-running storage unit.

[0063] Following the previous example, when the processor is powered on, this disclosure resets each bit of R_Translate_Received to 0. Subsequently, for each translation request (i.e., address acquisition request) received from a downstream TLB, the corresponding bit is set to 1. Alternatively, after completing the address deletion operation, this disclosure can reset each bit of R_Translate_Received to 0 for subsequent recording of fault-free TLBs in the new round, thereby facilitating accurate recording and differentiation between running and non-running memory units.

[0064] Step S12: Using the memory management unit, upon receiving the address deletion completion information returned by the running storage unit, the first deletion completion information is returned to the sender of the address deletion request. The address deletion completion information is sent by the running storage unit after deleting the cached target physical address.

[0065] The address deletion completion information can be understood as information indicating that the running storage unit has completed the address deletion. This address deletion completion information can be a deletion completion notification, deletion completion request, or deletion completion signal for the target physical address. For example, the address deletion completion information is the Invalid_Done signal.

[0066] The first deletion completion information can be understood as information indicating that the address deletion has been completed in multiple levels of storage units. The first deletion completion information can be a deletion completion notification, deletion completion request, or deletion completion signal for the target physical address. For example, the first deletion completion information is the Invalid_Done signal.

[0067] The sender of an address deletion request can be understood as the unit or module that sends the address deletion request to the memory management unit or the target storage unit. For example, for the target storage unit, the sender can be the storage unit above the target storage unit; for the memory management module, the sender can be the scheduler in the processor.

[0068] In some embodiments, forwarding the address deletion request to the running storage unit in this disclosure can be done by broadcasting the address deletion request to the next-level storage unit of the target storage unit, wherein the next-level storage unit includes the running storage unit. That is, this disclosure can forward the address deletion request to the running storage unit via broadcast.

[0069] In some embodiments, determining the running storage unit storing the target physical address from the first-level storage unit of a multi-level storage unit based on the first running status information in the first running status register, and forwarding the address deletion request to the running storage unit, includes: using a memory management unit to determine a first deletion status identifier of the first-level storage unit based on the first running status information, determining the running storage unit from the first-level storage unit based on the first deletion status identifier, and forwarding the address deletion request to the running storage unit; wherein the first deletion status identifier is stored in the address deletion register of the memory management unit, the first running status information is used to record running and non-running storage units in the first-level storage unit, and the first deletion status identifier is used to indicate whether the first-level storage unit has completed address deletion.

[0070] The address deletion register can be understood as a register used to record whether the address deletion of the first-level storage unit has been completed through the first deletion status flag.

[0071] The first deletion status flag can be understood as an identifier indicating whether the first-level storage unit has completed address deletion. This first deletion status flag includes a third value and a fourth value. The third value indicates that the running storage unit has not completed address deletion. The fourth value indicates the running storage unit. Alternatively, the fourth value can also be used to indicate that the non-running storage unit has completed address deletion. By pre-recording faulty or unacquired target physical addresses storage units as having "completed address deletion," the problem of MMU deadlock can be avoided.

[0072] Specifically, determining the first deletion status identifier of the first-level storage unit based on the first operating status information includes: using the first operating status information as the first deletion status identifier of the first-level storage unit. For example, copying the first operating status information into the address deletion register as the first deletion status identifier.

[0073] Using the previous example, a register R_Invalid_Pend (i.e., address deletion register) is added to the MMU. When the processor powers on, all bits in R_Invalid_Pend are reset to 0. When an Invalid_Req is received from the upstream, the bits in R_Invalid_Pend are used as bits in R_Translate_Received, that is, R_Invalid_Pend is set to R_Translate_Received.

[0074] For R_Invalid_Pend in the MMU, the bits of this register are used to record whether the current downstream TLB0_L1 or TLB1_L1 of the MMU is processing Invalid_Req. Here, 1 (i.e., the third value) indicates that Invalid_Req has not yet been completed, and 0 (i.e., the fourth value) indicates that it has been completed.

[0075] The TLB (i.e., the running memory unit) with a bit set to 1 in R_Invalid_Pend is identified as the TLB that needs to be deleted from the address, and then an R_Invalid_Pend (i.e., address deletion request) is sent to it.

[0076] As can be seen from the above embodiments, this disclosure can determine the deletion status identifier of the first-level storage unit based on the running status identifier, accurately identify the running storage unit from the first-level storage unit based on the deletion status identifier, and send address deletion requests only to these running storage units, avoiding full refresh, improving processing efficiency, and saving processing resources.

[0077] In some embodiments, the first deletion status is identified by a first deletion flag bit; upon receiving address deletion completion information returned by the running storage unit, returning the first deletion completion information to the sender of the address deletion request includes: using the memory management unit, upon receiving address deletion completion information returned by the running storage unit, determining the first deletion flag bit corresponding to the running storage unit from the address deletion register of the memory management unit; adjusting the first deletion flag bit corresponding to the running storage unit from an initial third value to a fourth value; and returning the first deletion completion information to the sender of the address deletion request when it is determined that all first deletion flag bits are the fourth value; wherein, a first deletion flag bit includes a third value or a fourth value, the third value is used to indicate that address deletion is not completed, the fourth value is used to indicate that address deletion is completed, and the first deletion flag bit corresponding to a non-running storage unit is set to the fourth value.

[0078] Specifically, when the memory management unit receives the address deletion completion information returned by the running memory unit, it can determine the flag bit (i.e. the first deletion flag bit) corresponding to the running memory unit from the address deletion register. Here, a flag bit includes a third value or a fourth value. The third value is used to indicate that the address deletion of the corresponding memory unit has not been completed, and the fourth value is used to indicate that the address deletion of the corresponding memory unit has been completed. Then, the initial third value in the flag bit corresponding to the running memory unit is adjusted to the fourth value.

[0079] Using the previous example, the bits in the MMU's R_Invalid_Pend are used to indicate that the downstream TLB is processing Invalid; 1 indicates that Invalid_Req has not yet been completed, and 0 indicates that it has been completed.

[0080] Upon power-up, the bit of R_Invalid_Pend is reset to 0. When an Invalid_Req is received from upstream, R_Invalid_Pend is set to R_Translate_Received.

[0081] Then, when the MMU or TLB0_L1 receives the Invalid_Done signal (i.e., address deletion completion information) sent by the downstream TLB, it sets the corresponding bit of R_Invalid_Pend to 0. When all bits in R_Invalid_Pend are 0, it is determined that the completed data is invalid, and the Invalid_Done signal (i.e., the first deletion completion information) is sent to the upstream scheduler.

[0082] As can be seen from the above embodiments, this disclosure allows the MMU to automatically identify a damaged TLB without software intervention, avoiding waiting for the Invalid_Done signal of that TLB, and ultimately resolving the potential deadlock problem.

[0083] In some embodiments, the sender includes a scheduler corresponding to the processor; the method further includes: using a memory management unit to receive an address deletion request sent by the scheduler, wherein the address deletion request is sent by the scheduler when the target task corresponding to the target physical address has been completed, and the target task has been allocated to the task processing unit for execution by the scheduler; returning first deletion completion information to the sender of the address deletion request, including: sending the first deletion completion information to the scheduler.

[0084] Following the previous example, based on Figure 3 It is known that after a task is completed, the outdated translation results (i.e., the target physical address) of the TLB and MMU need to be cleared before the Scheduler can continue to send new tasks to the SMs. The specific clearing method is as follows: After all SMs have completed their tasks, the Scheduler sends an Invalid_Req signal to the MMU. Upon receiving this signal, the MMU invalidates (i.e., deletes) its internal outdated PTEs and broadcasts the Invalid_Req to the downstream TLB0_L1. Upon receiving this signal, TLB0_L1 invalidates its internal outdated PTEs and broadcasts the Invalid_Req to the downstream TLB0_L0_0 and TLB0_L0_1. Upon receiving this signal, TLB0_L0_0 and TLB0_L0_1 invalidate their internal outdated PTEs and then pass the Invalid_Done signal to the upstream TLB0_L1. After collecting all the Invalid_Done signals, TLB0_L1 sends the Invalid_Done signal to the upstream MMU. After collecting all the Invalid_Done signals, the MMU sends the Invalid_Done signal to the Scheduler. The Scheduler can only send a new task to the SM after receiving Invalid_Done, thus ensuring that all outdated virtual address to physical address mappings (PTEs) are completely cleared before the task switch, and thus safely start the next task.

[0085] In some embodiments, for a target storage cell in a multi-level storage cell, the method further includes steps one and two.

[0086] Step 1: Using the target storage unit, upon receiving an address deletion request for the target physical address, delete the cached target physical address. Based on the second running status information in the second running status register, determine the running storage unit storing the target physical address from the next-level storage unit and forward the address deletion request to the running storage unit. Here, the target storage unit is a storage unit with a next-level storage unit in a multi-level storage unit, and the second running status register is a register configured in the target storage unit.

[0087] Address deletion requests can be understood as deletion requests targeting a physical address; taking the TLB as an example, the MMU is responsible for converting VA to PA, and the TLB caches the conversion result (i.e., the target physical address). When the PTE (Page Table Entry, representing the mapping relationship between VA and PA) is updated, the GPU needs to invalidate outdated PTEs (i.e., target physical addresses) in the TLB. Figure 2 It can be seen that the GPU sends an Invalid_Req signal (i.e., an invalidation request) to the MMU. After receiving the signal, the MMU broadcasts the Invalid_Req signal (i.e., an address deletion request) to the downstream TLB0_L1 and / or TLB1_L1 (i.e., the target memory unit). Upon receiving the signal, TLB0_L1 and / or TLB1_L1 first invalidates the outdated PTE in their internal cache, and then broadcasts the Invalid_Req signal to the downstream TLB0_L0_0, TLB0_L0_1, TLB1_L0_0, and / or TLB1_L0_1. After receiving the signal, TLBs such as TLB0_L0_0 first invalidate their internal outdated PTE, and then send an Invalid_Done signal (i.e., invalidation complete) to the upstream TLB0_L1 and / or TLB1_L1. After collecting the downstream Invalid_Done signals, TLB0_L1 and / or TLB1_L1 send an Invalid_Done signal to the upstream MMU.

[0088] In some embodiments, deleting a cached target physical address includes: determining an identifier (such as name, number, etc.) of the target physical address from the address deletion request; determining the target physical address (e.g., an outdated PTE) from the cached physical addresses based on the identifier; and deleting the target physical address. The target physical address to be deleted may be all or part of the cached physical addresses.

[0089] In some embodiments, before deleting the cached target physical address upon receiving an address deletion request for the target physical address, the method further includes: using the target storage unit, upon receiving a second address retrieval request sent by the second storage unit, determining the target physical address corresponding to the second address retrieval request, sending the target physical address to the second storage unit, and recording the second storage unit as a running storage unit, wherein the second storage unit is any one of at least one next-level storage unit.

[0090] Specifically, the target storage unit of this disclosure can receive an address retrieval request sent by the second storage unit and determine a first virtual address from the address retrieval request; determine the target physical address from the cached physical address by using the first virtual address, and send the target physical address to the second storage unit. Simultaneously, the target storage unit will also mark the second storage unit as a running storage unit, facilitating subsequent address deletion and improving address deletion efficiency.

[0091] In some embodiments, the second operating status information includes a second operating status flag bit; recording the second storage unit as an operating storage unit includes: using the target storage unit, determining the second operating status flag bit corresponding to the second storage unit from the second operating status register according to the unit identifier of the second storage unit, and adjusting the second operating status flag bit to a first value, wherein the first value is used to indicate that the second storage unit is an operating storage unit.

[0092] The second running status register can be understood as a register used to record whether the second storage unit is a running storage unit through the second running status flag bit.

[0093] The second running status flag can be understood as a binary bit used to indicate whether the second storage unit is a running storage unit. The second running status flag includes a first value and a second value. The first value is used to indicate that the second storage unit is a running storage unit; the second value is used to indicate that the second storage unit is not a running storage unit.

[0094] Following the previous example, this disclosure can add a register R_Translate_Received to each of the non-lowest-level TLBs, such as TLB0_L1; where the bits in R_Translate_Received correspond one-to-one with the number of the next-level TLBs. Figure 3The TLB0_L1 in the code includes two downstream TLBs, TLB0_L0_0 and TLB0_L0_1. In this case, R_Translate_Received has two bits, each corresponding to one of the two downstream TLBs. These bits in R_Translate_Received indicate whether a Translate_Req sent by the downstream TLB (i.e., the next-layer TLB) has been received; for example, Figure 3 The downstream TLBs of TLB1_L1 are TLB1_L0_0 and TLB1_L0_1; correspondingly, the bits of R_Translate_Received are used to indicate whether Translate_Req of TLB1_L0_0 or TLB1_L0_1 has been received; where 0 (i.e., the second value) indicates that it has not been received, and 1 (i.e., the first value) indicates that it has been received.

[0095] As can be seen from the above embodiments, this disclosure can quickly determine which memory units are in use by using the second running status flag, thereby improving the efficiency of subsequent address deletion. By recording the downstream TLB access status, it is not necessary to wait for the Invalid_Done signal of a corrupted TLB during the subsequent address deletion process, thus solving the problem of GPU freezing.

[0096] In some embodiments, there are multiple next-level storage units; before determining the target physical address corresponding to the second address acquisition request when receiving the second address acquisition request sent by the second storage unit, the method further includes: using the target storage unit to determine the second running status flag bits corresponding to multiple next-level storage units from the second running status register, and adjusting each second running status flag bit to a second value, wherein a second value is used to indicate that a next-level storage unit is a non-running storage unit.

[0097] Following the previous example, when the processor is powered on, this disclosure resets each bit of R_Translate_Received to 0. Subsequently, for each translation request received from downstream, the corresponding bit is set to 1. Alternatively, after completing the address deletion operation, this disclosure can reset each bit of R_Translate_Received to 0 for recording fault-free TLBs in the next round, thereby facilitating accurate recording and differentiation between running and non-running memory units.

[0098] Step 2: Using the target storage unit, upon receiving the address deletion completion information returned by the running storage unit, return a second deletion completion information to the sender of the address deletion request.

[0099] The address deletion completion information can be understood as information indicating that the running storage unit has completed address deletion, and the second deletion completion information can be understood as information indicating that the next level storage unit of the target storage unit has completed address deletion. The second deletion completion information can be a deletion completion notification, deletion completion request, or deletion completion signal for the target physical address, such as the Invalid_Done signal.

[0100] The sender of an address deletion request can be understood as the unit or module that sends the address deletion request to the target storage unit. For example, the sender could be the storage unit at the next higher level than the target storage unit.

[0101] In some embodiments, determining the running storage unit storing the target physical address from the next-level storage unit based on the second running status information in the second running status register, and forwarding the address deletion request to the running storage unit, includes: using the target storage unit, determining the second deletion status identifier of the next-level storage unit based on the second running status information, determining the running storage unit from the next-level storage unit based on the second deletion status identifier, and forwarding the address deletion request to the running storage unit; wherein the second deletion status identifier is stored in the address deletion register of the target storage unit, the second running status information is used to record running storage units and non-running storage units in the next-level storage unit, and the second deletion status identifier is used to indicate whether the next-level storage unit has completed address deletion.

[0102] The address deletion register of the target memory cell can be understood as a register set in the target memory cell to record whether the address deletion of the second memory cell has been completed through the second deletion status flag.

[0103] The second deletion status identifier can be understood as information used to indicate whether the second storage unit has completed address deletion. This deletion status identifier includes a third value and a fourth value. The third value is used to indicate that the running storage unit has not completed address deletion, and the fourth value is used to indicate that the running storage unit or the non-running storage unit has completed address deletion.

[0104] Specifically, determining the second deletion status identifier of the next-level storage unit based on the second operating status information includes: using the second operating status flag bit of the next-level storage unit as the second deletion status identifier of the next-level storage unit.

[0105] Using the previous example, a register R_Invalid_Pend is added to TLB0_L1. When the processor powers on, all bits in R_Invalid_Pend are reset to 0. When an Invalid_Req is received from the upstream, the bits in R_Invalid_Pend are used as bits of R_Translate_Received, that is, R_Invalid_Pend is set to R_Translate_Received.

[0106] For R_Invalid_Pend in TLB0_L1, the bits of this register are used to record the TLB downstream of TLB0_L1 that is currently processing Invalid_Req. Here, 1 (i.e., the third value) indicates that Invalid_Req has not yet been completed, and 0 (i.e., the fourth value) indicates that it has been completed.

[0107] The TLB (i.e., the running memory unit) with a bit set to 1 in R_Translate_Received is identified as the TLB that needs to be deleted from the address, and then an R_Invalid_Pend (i.e., address deletion request) is sent to it.

[0108] As can be seen from the above embodiments, this disclosure can determine the second deletion status identifier of the next-level storage unit based on the second running status flag bit, accurately determine the running storage unit from the next-level storage unit based on the second deletion status identifier, and send address deletion requests only to these running storage units, avoiding full refresh, improving processing efficiency, and saving processing resources.

[0109] In some embodiments, the second deletion status is identified by a second deletion flag bit; upon receiving address deletion completion information returned by the running storage unit, returning the second deletion completion information to the sender of the address deletion request includes: using the target storage unit, upon receiving address deletion completion information returned by the running storage unit, determining the second deletion flag bit corresponding to the running storage unit from the address deletion register of the target storage unit; adjusting the second deletion flag bit corresponding to the running storage unit from an initial third value to a fourth value; and returning the second deletion completion information to the sender of the address deletion request when it is determined that all second deletion flag bits are the fourth value; wherein, a second deletion flag bit includes a third value or a fourth value, the third value is used to indicate that address deletion is not completed, the fourth value is used to indicate that address deletion is completed, and the second deletion flag bit corresponding to a non-running storage unit is set to the fourth value.

[0110] Specifically, when the target storage unit receives the address deletion completion information returned by the running storage unit, it determines the flag bit corresponding to the running storage unit from the address deletion register. One flag bit includes a third value or a fourth value. The third value is used to indicate that the address deletion is not completed, and the fourth value is used to indicate that the address deletion is completed. Then, the initial third value in the flag bit corresponding to the running storage unit (i.e. the second deletion flag bit) is adjusted to the fourth value.

[0111] Using the previous example, the bits in R_Invalid_Pend of TLB0_L1 are used to indicate that the downstream TLB is processing Invalid, 1 indicates that Invalid_Req has not yet been completed, and 0 indicates that it has been completed.

[0112] Upon power-up, the bit of R_Invalid_Pend is reset to 0. When an Invalid_Req is received from upstream, R_Invalid_Pend is set to R_Translate_Received.

[0113] Then, when TLB0_L1 receives the Invalid_Done signal (i.e., address deletion completion information) sent by the downstream TLB, it sets the corresponding bit of R_Invalid_Pend to 0. When all bits in R_Invalid_Pend are 0, it determines that the completed data is invalid and sends the Invalid_Done signal (i.e., the second deletion completion information) upstream.

[0114] As can be seen from the above embodiments, this disclosure enables the TLB to automatically identify a damaged TLB without software intervention, thus avoiding waiting for the Invalid_Done signal from the downstream TLB and ultimately resolving potential deadlock issues.

[0115] In some embodiments, obtaining the target physical address corresponding to the first address acquisition request or the second address acquisition request includes: obtaining a first virtual address carried in the first address acquisition request or the second address acquisition request; determining a second virtual address that is the same as the first virtual address from the virtual addresses in the address mapping table; and determining the physical address corresponding to the second virtual address as the target physical address corresponding to the first address acquisition request or the second address acquisition request.

[0116] The address retrieval request can be understood as a request to obtain a physical address, such as an address translation request, used to translate a virtual address into a physical address. The address mapping table can be understood as a table recording the mapping relationship between virtual addresses and physical addresses; this address mapping table can be a PTE (Physical Address Translation Table).

[0117] As can be seen from the above embodiments, this disclosure completes the lookup from virtual address to physical address by querying a pre-maintained address mapping table, ensuring the correct data access path, and realizing the fast and accurate conversion of the virtual address in the request into the corresponding physical address, thereby supporting the upper-layer system or unit to efficiently access the underlying physical storage resources.

[0118] The address processing method provided in this embodiment is applied to the memory management unit of a processor. When the first-level storage unit obtains the target physical address, it records the first-level storage unit as a fault-free running storage unit. Upon receiving an address deletion request for the target physical address, the memory management unit forwards the address deletion request to the fault-free running storage unit. Since the running storage unit is fault-free, it can respond to the received address deletion request by deleting the locally cached target physical address and sending address deletion completion information to the memory management unit. When the memory management unit receives the address deletion completion information returned by the running storage unit, it determines that the address deletion is complete and can return first deletion completion information to the sender of the address deletion request. This avoids the problem of deletion operation stalling due to storage unit failure and improves address deletion efficiency.

[0119] Taking the application of the address processing method provided in this disclosure in an MMU scenario as an example, this address processing method will be explained. Figure 4 This is a schematic diagram illustrating the application of an address processing method provided in an embodiment of this disclosure, based on... Figure 4 As can be seen, the address processing method provided in this disclosure includes two parts: an address translation process and an address invalidation process. The address translation process refers to processing the address translation request sent by the LSU; the address invalidation process refers to clearing outdated address translation results.

[0120] The specific execution steps of the address translation process include steps 41 to 43.

[0121] Step 41: R_Translate_Received=0.

[0122] Specifically, the GPU_CORE typically includes a Scheduler, several SMs, and an MMU. Each SM has its own independent LSU and a corresponding TLB for each LSU; for example, TLB0_L0_0 and TLB0_L0_1 (underlying TLBs) share a TLB0_L1, and multiple TLBs such as TLB0_L1 and TLB1_L1 share a single MMU.

[0123] In this disclosure, a register R_Translate_Received is added to both the MMU and TLB0_L1 and TLB1_L1; the bits in R_Translate_Received correspond one-to-one with the number of the next layer TLB.

[0124] The bits in R_Translate_Received are used to indicate whether the Translate_Req sent by the downstream TLB has been received, where 0 indicates that it has not been received and 1 indicates that it has been received.

[0125] Upon power-up, each bit of R_Translate_Received can be reset to 0, and when a Translate_Req is received from the downstream TLB, the bit position is set to 1.

[0126] Step 42: Has a Translate_Req been received? If yes, proceed to step 43; otherwise, continue waiting.

[0127] Specifically, the Scheduler is responsible for sending tasks to the SM and preparing the necessary environment for the tasks. The SM is responsible for executing the tasks sent by the Scheduler, with memory access initiated by the LSU. Memory access requires the PA, but the LSU can only compute VA. Therefore, the LSU uses the VA to send translation requests to the TLB. When a TLB is missing, translation requests are sent up the chain to the next higher-level TLB and MMU.

[0128] Therefore, the MMU and the upstream TLB need to determine whether they have received the Translate_Req sent by the downstream TLB.

[0129] Step 43: Update R_Translate_Received.

[0130] Specifically, whenever a translation request is received from a downstream TLB, the corresponding bit of the TLB is determined from R_Translate_Received based on the TLB identifier (i.e., Translate_Req_ID) and set to 1.

[0131] The above operation refers to Figure 4 The value is "R_Translate_Received[Translate_Req_ID]=1".

[0132] Based on the above steps, this disclosure uses R_Translate_Received to record which downstream TLB has sent a Translate_Req to the upstream. If the downstream TLB is faulty, it will never send a Translate_Req to the upstream, and therefore the upstream does not need to wait for its Invalid_Done during the subsequent address invalidation process. If the downstream TLB is good, but it has not yet sent a Translate_Req to the upstream (i.e., the downstream TLB does not have a valid PTE), then the upstream also does not need to wait for its Invalid_Done.

[0133] The specific execution steps of the address invalidation process include steps 44 to 410.

[0134] Step 44: R_Invalid_Pend=0.

[0135] Specifically, a register R_Invalid_Pend is added to both the MMU and the TLB with downstream TLBs. When the processor powers on, the bits in R_Invalid_Pend are all reset to 0.

[0136] The bits in R_Invalid_Pend are used to indicate that the downstream TLB is processing Invalid; 1 indicates that Invalid_Req has not yet been completed, and 0 indicates that it has been completed.

[0137] Step 45: Has an Invalid_Req been received? If yes, proceed to step 46; otherwise, continue waiting.

[0138] Step 46: Start the Invalid PTE locally and broadcast Invald_Req downstream.

[0139] Specifically, invalidate outdated PTEs in the internal cache and broadcast an Invalid_Req signal to the downstream TLB.

[0140] Furthermore, this disclosure can also set R_Invalid_Pend to R_Translate_Received (that is, R_Invalid_Pend=R_Translate_Received) when receiving an Invalid_Req from the upstream, so as to facilitate subsequent determination of whether the completed data is invalid.

[0141] In some embodiments, after broadcasting Invald_Req downstream, one can continue to wait to receive the Invalid_Req signal sent upstream.

[0142] Step 47: Did you receive Invalid_Done? If yes, proceed to step 48; otherwise, continue waiting.

[0143] Step 48: Update R_Invalid_Pend.

[0144] Specifically, whenever an Invalid_Done is received from a downstream TLB, the corresponding bit of the TLB is determined from R_Invalid_Pend based on the TLB identifier (i.e., lnvalid_Done_ID) and the bit is set to 0.

[0145] The above operation refers to Figure 4 "R_Invalid_Pend[lnvalid_Done_ID]=0" in .

[0146] Step 49: Determine if R_Invalid_Pend == 0. If yes, proceed to step 410; otherwise, return to step 47 and wait to receive the Invalid_Done signal.

[0147] Specifically, this disclosure determines that the completed data is invalid when all bits in R_Invalid_Pend are 0.

[0148] Step 410: Return Invalid_Done upstream.

[0149] If the completed data is determined to be invalid, this disclosure returns Invalid_Done to the upstream; and returns to step 45 to continue waiting to receive the Invalid_Req signal.

[0150] Based on the above steps, the address processing method in this disclosure proposes a hardware-adaptive TLB detection technology. The upstream module records the translation requests of the downstream module to determine the damage of the downstream module. If no translation request is received from the downstream module, the upstream module will not wait for the Invalid_Done signal of the downstream module, and no software configuration of any registers is required.

[0151] For example, by using R_Invalid_Pend to record which downstream TLB returned the Invalid_Done signal, the combination of R_Invalid_Pend and R_Translate_Received can avoid waiting for the Invalid_Done signal from a corrupted TLB.

[0152] In other words, the address processing method in this disclosure proposes an adaptive MMU deadlock prevention technique. By recording downstream TLB access information, it solves the GPU freezing problem without waiting for the Invalid_Done signal of a corrupted TLB. This solution is simple to implement, requiring only hardware modifications. Compared to timeout mechanisms, it avoids performance degradation caused by excessive timeouts. Compared to register marking techniques, it requires no software modifications.

[0153] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0154] In addition, this disclosure also provides a processor that can be used to implement any of the address processing methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the relevant section of the method and will not be repeated here.

[0155] Figure 5 A block diagram of a processor provided in an embodiment of this disclosure.

[0156] Reference Figure 5 This disclosure provides a processor, which includes a memory management unit 501 and a multi-level storage unit 502. The memory management unit 501 includes a first running status register.

[0157] The memory management unit 501 is configured to: upon receiving an address deletion request for a target physical address, determine the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit 502 based on the first running status information in the first running status register, and forward the address deletion request to the running storage unit; the first-level storage unit is the level with the largest storage capacity in the multi-level storage unit 502, and upon receiving address deletion completion information returned by the running storage unit, return first deletion completion information to the sender of the address deletion request, wherein the address deletion completion information is sent by the running storage unit after deleting the cached target physical address.

[0158] The target storage unit in the multi-level storage unit 502 is configured to: upon receiving an address deletion request for a target physical address, delete the cached target physical address; determine the running storage unit storing the target physical address from the next-level storage unit based on the second running status information in the second running status register; and forward the address deletion request to the running storage unit. Here, the target storage unit is a storage unit in the multi-level storage unit 502 that has a next-level storage unit, the second running status register is a register configured in the target storage unit, and, using the target storage unit, upon receiving address deletion completion information returned by the running storage unit, return second deletion completion information to the sender of the address deletion request.

[0159] In some embodiments, the memory management unit 501 is further configured to: upon receiving a first address acquisition request sent by a first storage unit, determine the target physical address corresponding to the first address acquisition request, send the target physical address to the first storage unit, and record the first storage unit as a running storage unit, wherein the first storage unit is any one of at least one first-level storage unit.

[0160] In some embodiments, the first running status information includes a first running status flag bit; the memory management unit 501 is further configured to: determine the first running status flag bit corresponding to the first storage unit from the first running status register according to the unit identifier of the first storage unit, and adjust the first running status flag bit to a first value, wherein the first value is used to indicate that the first storage unit is a running storage unit.

[0161] In some embodiments, there are multiple first-level storage units; the memory management unit 501 is further configured to: determine the first running status flag bits corresponding to the multiple first-level storage units from the first running status register, and adjust each first running status flag bit to a second value, wherein a second value is used to indicate that a first-level storage unit is a non-running storage unit.

[0162] In some embodiments, the memory management unit 501 is further configured to: determine a first deletion status identifier of a first-level storage unit based on first running status information, determine a running storage unit from the first-level storage unit based on the first deletion status identifier, and forward an address deletion request to the running storage unit; wherein the first deletion status identifier is stored in the address deletion register of the memory management unit 501, the first running status information is used to record running and non-running storage units in the first-level storage unit, and the first deletion status identifier is used to indicate whether the first-level storage unit has completed address deletion.

[0163] In some embodiments, the first deletion status is identified as a first deletion flag bit; the memory management unit 501 is further configured to: upon receiving address deletion completion information returned by the running storage unit, determine the first deletion flag bit corresponding to the running storage unit from the address deletion register of the memory management unit 501; adjust the first deletion flag bit corresponding to the running storage unit from an initial third value to a fourth value; and, if it is determined that all first deletion flag bits are the fourth value, return the first deletion completion information to the sender of the address deletion request; wherein, a first deletion flag bit includes a third value or a fourth value, the third value is used to indicate that the address deletion is not completed, the fourth value is used to indicate that the address deletion is completed, and the first deletion flag bit corresponding to a non-running storage unit is set to the fourth value.

[0164] In some embodiments, the target storage unit is further configured to: upon receiving a second address acquisition request sent by the second storage unit, determine the target physical address corresponding to the second address acquisition request, send the target physical address to the second storage unit, and record the second storage unit as a running storage unit, wherein the second storage unit is any one of at least one next-level storage unit.

[0165] In some embodiments, the second running status information includes a second running status flag bit; the target storage unit is further configured to: determine the second running status flag bit corresponding to the second storage unit from the second running status register according to the unit identifier of the second storage unit, and adjust the second running status flag bit to a first value, wherein the first value is used to indicate that the second storage unit is a running storage unit.

[0166] In some embodiments, there are multiple next-level storage units; the target storage unit is further configured to: determine the second running status flag bits corresponding to the multiple next-level storage units from the second running status register, and adjust each second running status flag bit to a second value, wherein a second value is used to indicate that a next-level storage unit is a non-running storage unit.

[0167] In some embodiments, the target storage unit is further configured to: determine a second deletion status identifier of the next-level storage unit based on the second operating status information, determine a running storage unit from the next-level storage unit based on the second deletion status identifier, and forward the address deletion request to the running storage unit; wherein the second deletion status identifier is stored in the address deletion register of the target storage unit, the second operating status information is used to record running and non-running storage units in the next-level storage unit, and the second deletion status identifier is used to indicate whether the next-level storage unit has completed address deletion.

[0168] In some embodiments, the second deletion status is identified as a second deletion flag bit; the target storage unit is further configured to: upon receiving address deletion completion information returned by the running storage unit, determine the second deletion flag bit corresponding to the running storage unit from the address deletion register of the target storage unit; adjust the second deletion flag bit corresponding to the running storage unit from an initial third value to a fourth value; and, if it is determined that all second deletion flag bits are the fourth value, return the second deletion completion information to the sender of the address deletion request; wherein, a second deletion flag bit includes a third value or a fourth value, the third value is used to indicate that the address deletion is not completed, the fourth value is used to indicate that the address deletion is completed, and the second deletion flag bit corresponding to a non-running storage unit is set to the fourth value.

[0169] In some embodiments, the sender includes a scheduler corresponding to the processor; the memory management unit 501 is further configured to: receive an address deletion request sent by the scheduler, wherein the address deletion request is sent by the scheduler when the target task corresponding to the target physical address has been completed, and the target task has been assigned to the task processing unit for execution by the scheduler; and send first deletion completion information to the scheduler.

[0170] In some embodiments, the next-level storage unit is the last-level storage unit in the multi-level storage unit 502, and the last-level storage unit is connected to the task processing unit; the second address acquisition request is sent by the last-level storage unit to the target storage unit when it receives the task address acquisition request sent by the task processing unit and has not cached the target physical address; the task address acquisition request is sent by the task processing unit during the target task.

[0171] The memory management unit 501 in the processor provided in this embodiment can record the first-level storage unit as a fault-free running storage unit when the first-level storage unit obtains the target physical address, and forward the address deletion request to the fault-free running storage unit when it receives an address deletion request for the target physical address. Since the running storage unit is fault-free, it can respond to the received address deletion request, delete the target physical address cached locally, and send address deletion completion information to the memory management unit 501. When the memory management unit 501 receives the address deletion completion information returned by the running storage unit, it determines that the address deletion is complete and can return the first deletion completion information to the sender of the address deletion request, thus avoiding the problem of deletion operation stalling due to storage unit failure and improving address deletion efficiency.

[0172] The target storage unit in the multi-level storage unit 502 of this processor, when obtaining the target physical address from the target physical address in the next-level storage unit, records the next-level storage unit as a running storage unit that has not experienced a fault. Upon receiving an address deletion request for the target physical address, it first deletes the target physical address cached in the target storage unit, and then forwards the address deletion request to the running storage unit that has not experienced a fault. Since the running storage unit is fault-free, it can respond to the received address deletion request, delete the locally cached address, and send address deletion completion information to the target storage unit. When the target storage unit receives the address deletion completion information returned by the running storage unit, it determines that the address deletion is complete and can return a second deletion completion information to the sender of the address deletion request. This avoids the problem of deletion operation stalling due to storage unit failure and improves address deletion efficiency.

[0173] The above is an illustrative scheme of a processor according to this embodiment. It should be noted that the technical solution of this processor and the technical solution of the address processing method described above belong to the same concept. For details not described in detail in the technical solution of the processor, please refer to the description of the technical solution of the address processing method described above.

[0174] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0175] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. An address processing method, characterized in that, Applied to a processor, the processor including a memory management unit and a multi-level storage unit, the memory management unit including a first running status register, the method includes: Using the memory management unit, upon receiving an address deletion request for a target physical address, the unit determines the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit based on the first running status information in the first running status register, and forwards the address deletion request to the running storage unit; the first-level storage unit is the level with the largest storage capacity among the multi-level storage units. Using the memory management unit, upon receiving address deletion completion information returned by the running storage unit, a first deletion completion information is returned to the sender of the address deletion request, wherein the address deletion completion information is sent by the running storage unit after deleting the cached target physical address.

2. The method according to claim 1, characterized in that, The method further includes: Using the target storage unit, upon receiving an address deletion request for the target physical address, the cached target physical address is deleted. Based on the second running status information in the second running status register, the running storage unit storing the target physical address is determined from the next-level storage unit, and the address deletion request is forwarded to the running storage unit. The target storage unit is a storage unit in the multi-level storage unit that has the next-level storage unit, and the second running status register is a register configured in the target storage unit. Using the target storage unit, upon receiving the address deletion completion information returned by the running storage unit, a second deletion completion information is returned to the sender of the address deletion request.

3. The method according to claim 1 or 2, characterized in that, Before determining the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit based on the first running status information in the first running status register upon receiving an address deletion request for the target physical address, the method further includes: Using the memory management unit, upon receiving a first address acquisition request sent by the first storage unit, the target physical address corresponding to the first address acquisition request is determined, the target physical address is sent to the first storage unit, and the first storage unit is recorded as the running storage unit, wherein the first storage unit is any one of at least one first-level storage unit.

4. The method according to claim 3, characterized in that, The first operating status information includes a first operating status flag bit; The step of recording the first storage unit as the running storage unit includes: Using the memory management unit, based on the unit identifier of the first storage unit, the first running status flag bit corresponding to the first storage unit is determined from the first running status register, and the first running status flag bit is adjusted to a first value, wherein the first value is used to indicate that the first storage unit is a running storage unit.

5. The method according to claim 4, characterized in that, The first-level storage unit consists of multiple units; Before determining the target physical address corresponding to the first address acquisition request upon receiving the first address acquisition request sent by the first storage unit, the method further includes: Using the memory management unit, the first running status flag bits corresponding to multiple first-level storage units are determined from the first running status register, and each first running status flag bit is adjusted to a second value, wherein a second value is used to indicate that a first-level storage unit is a non-running storage unit.

6. The method according to claim 1 or 2, characterized in that, The step of determining the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit based on the first running status information in the first running status register, and forwarding the address deletion request to the running storage unit, includes: Using the memory management unit, a first deletion status identifier of the first-level storage unit is determined based on the first running status information. Based on the first deletion status identifier, the running storage unit is determined from the first-level storage unit, and the address deletion request is forwarded to the running storage unit. The first deletion status identifier is stored in the address deletion register of the memory management unit, the first running status information is used to record the running and non-running storage units in the first-level storage unit, and the first deletion status identifier is used to indicate whether the first-level storage unit has completed address deletion.

7. The method according to claim 6, characterized in that, The first deletion status identifier is a first deletion flag bit; the step of returning the first deletion completion information to the sender of the address deletion request upon receiving the address deletion completion information returned by the running storage unit includes: Using the memory management unit, upon receiving address deletion completion information returned by the running storage unit, the first deletion flag corresponding to the running storage unit is determined from the address deletion register of the memory management unit; the first deletion flag corresponding to the running storage unit is adjusted from an initial third value to a fourth value; and if it is determined that the first deletion flag is the fourth value, the first deletion completion information is returned to the sender of the address deletion request. Wherein, one of the first deletion flag bits includes a third value or a fourth value, the third value is used to indicate that the address deletion is not completed, and the fourth value is used to indicate that the address deletion is completed, and the first deletion flag bit corresponding to the non-running storage unit is set to the fourth value.

8. The method according to claim 2, characterized in that, Before deleting the cached target physical address upon receiving an address deletion request for the target physical address, the method further includes: Using the target storage unit, upon receiving a second address acquisition request sent by the second storage unit, the target physical address corresponding to the second address acquisition request is determined, the target physical address is sent to the second storage unit, and the second storage unit is recorded as the running storage unit, wherein the second storage unit is any one of at least one of the next-level storage units.

9. The method according to claim 8, characterized in that, The second operating status information includes a second operating status flag bit; The step of recording the second storage unit as the running storage unit includes: Using the target storage unit, based on the unit identifier of the second storage unit, the second running status flag bit corresponding to the second storage unit is determined from the second running status register, and the second running status flag bit is adjusted to a first value, wherein the first value is used to indicate that the second storage unit is a running storage unit.

10. The method according to claim 9, characterized in that, There are multiple next-level storage units; Before determining the target physical address corresponding to the second address acquisition request upon receiving the second address acquisition request sent by the second storage unit, the method further includes: Using the target storage unit, the second running status flag bits corresponding to multiple next-level storage units are determined from the second running status register, and each second running status flag bit is adjusted to a second value, wherein a second value is used to indicate that a next-level storage unit is a non-running storage unit.

11. The method according to claim 2 or 8, characterized in that, The step of determining the running storage unit storing the target physical address from the next-level storage unit based on the second running status information in the second running status register, and forwarding the address deletion request to the running storage unit, includes: Using the target storage unit, the second deletion status identifier of the next-level storage unit is determined according to the second running status information. The running storage unit is then determined from the next-level storage unit according to the second deletion status identifier, and the address deletion request is forwarded to the running storage unit. The second deletion status identifier is stored in the address deletion register of the target storage unit, the second running status information is used to record the running storage units and non-running storage units in the next level storage unit, and the second deletion status identifier is used to indicate whether the address deletion of the next level storage unit has been completed.

12. The method according to claim 11, characterized in that, The second deletion status identifier is the second deletion flag bit; the step of returning the second deletion completion information to the sender of the address deletion request upon receiving the address deletion completion information returned by the running storage unit includes: Using the target storage unit, upon receiving address deletion completion information returned by the running storage unit, the second deletion flag corresponding to the running storage unit is determined from the address deletion register of the target storage unit; the second deletion flag corresponding to the running storage unit is adjusted from the initial third value to the fourth value; if it is determined that the second deletion flag is always the fourth value, the second deletion completion information is returned to the sender of the address deletion request. Wherein, one of the second deletion flag bits includes a third value or a fourth value, the third value is used to indicate that the address deletion is not completed, and the fourth value is used to indicate that the address deletion is completed, and the second deletion flag bit corresponding to the non-running storage unit is set to the fourth value.

13. The method according to claim 1 or 2, characterized in that, The sender includes a scheduler corresponding to the processor; the method further includes: The memory management unit receives an address deletion request sent by the scheduler, wherein the address deletion request is sent by the scheduler after the target task corresponding to the target physical address has been completed, and the target task is assigned to the task processing unit for execution by the scheduler. The process of returning first deletion completion information to the sender of the address deletion request includes: The first deletion completion information is sent to the scheduler.

14. The method according to claim 8, characterized in that, The next-level storage unit is the last level storage unit in the multi-level storage unit, and the last level storage unit is connected to the task processing unit. The second address acquisition request is sent by the last-level storage unit to the target storage unit when it receives the task address acquisition request sent by the task processing unit and has not cached the target physical address; The task address acquisition request is sent by the task processing unit during the target task process.

15. A processor, characterized in that, The processor includes a memory management unit and a multi-level storage unit, and the memory management unit includes a first running status register; The memory management unit is configured to: upon receiving an address deletion request for a target physical address, determine, based on the first running status information in the first running status register, the running storage unit storing the target physical address from the first-level storage unit of the multi-level storage unit, and forward the address deletion request to the running storage unit; the first-level storage unit is the level with the largest storage capacity among the multi-level storage units, and upon receiving address deletion completion information returned by the running storage unit, return first deletion completion information to the sender of the address deletion request, wherein the address deletion completion information is sent by the running storage unit after deleting the cached target physical address; The target storage unit in the multi-level storage unit is configured to: upon receiving an address deletion request for the target physical address, delete the cached target physical address; determine the running storage unit storing the target physical address from the next-level storage unit based on the second running status information in the second running status register; and forward the address deletion request to the running storage unit. The target storage unit is a storage unit in the multi-level storage unit that has the next-level storage unit; the second running status register is a register configured in the target storage unit; and, upon receiving address deletion completion information returned by the running storage unit, return second deletion completion information to the sender of the address deletion request using the target storage unit.

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