Parity check error location method, apparatus, device, medium and product

Abstract

The application discloses a parity check error positioning method and device, equipment, medium and product, and relates to the technical field of signal processing. The method comprises the following steps: performing parity check on a to-be-tested data frame; the to-be-tested data frame comprises N-bit to-be-tested data and 1-bit parity check data, wherein N is a positive integer; if parity check error occurs in the to-be-tested data frame, performing bitwise XOR on the N-bit to-be-tested data according to the binary coordinates of the N-bit to-be-tested data to obtain the binary coordinates of error data in the to-be-tested data frame, so that the parity check error data of single bits can be positioned, accurate positioning information is provided for error data correction, and the reliability and fault tolerance of data transmission can be further improved.

Description

[0001] This application is a divisional application of patent application number 202610056290.4 (the original application was filed on January 16, 2026, and the invention was entitled "Parity Check Error Location Method, Apparatus, Circuit, Device, Medium and Product"). Technical Field

[0002] This invention relates to the field of signal processing technology, and in particular to a method, apparatus, device, medium, and product for locating parity check errors. Background Technology

[0003] In digital communication and data storage systems, ensuring the integrity of information transmission and storage is crucial. Parity checking, as one of the fundamental error detection techniques, is widely used in various communication protocols and computer memory systems. Its core objective is to identify single-bit errors that may occur during data transmission or storage.

[0004] The basic principle of parity checking is to add an extra parity bit to the original data bit sequence, ensuring that the number of "1"s in the entire sequence (including data bits and parity bit) satisfies a predetermined parity (odd or even). During data reading, the system recalculates the number of "1"s in the read data byte and compares it with the parity indicated by the pre-stored parity bit. If the two do not match, it is determined that a single-bit error occurred in the byte during storage or transmission.

[0005] Traditional parity checking methods have a significant limitation: while they can detect single-bit errors, they cannot pinpoint the exact bit location where the error occurred. Due to this lack of error localization capability, systems typically cannot directly correct data after detecting a parity error and must instead handle it by requesting retransmission, triggering a system interrupt, or issuing an error message. Summary of the Invention

[0006] This invention provides a method, apparatus, device, medium, and product for locating parity error, in order to solve the problem that traditional parity methods cannot locate single-bit errors.

[0007] In a first aspect, embodiments of the present invention provide a parity check error location method, comprising: Parity check is performed on the data frame to be tested; the data frame to be tested contains N bits of data to be tested and 1 bit of parity check data, where N is a positive integer. If a single-bit flip error occurs in the data frame under test, the binary coordinates of the erroneous data in the data frame under test are obtained by bitwise XORing the N bits of the data under test according to their binary coordinates.

[0008] Secondly, embodiments of the present invention provide a parity check error location device, comprising: The parity check module is used to perform parity check on the data frame to be tested; the data frame to be tested contains N bits of data to be tested and 1 bit of parity check data, where N is a positive integer; The error data location module is used to obtain the binary coordinates of the erroneous data in the test data frame by bitwise XORing the N bits of the test data according to the binary coordinates of the N bits of the test data if a single bit flip error occurs in the test data frame.

[0009] Thirdly, embodiments of the present invention provide an electronic device, the electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the parity error location method according to any embodiment of the present invention.

[0010] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer instructions, which are used to cause a processor to execute the parity error location method described in any embodiment of the present invention.

[0011] Fifthly, embodiments of the present invention provide a computer program product including a computer program, which, when executed by a processor, implements the parity error location method described in any embodiment of the present invention.

[0012] The technical solution of this invention involves parity checking of the data frame under test. The data frame under test contains N bits of data to be tested and 1 bit of parity check data, where N is a positive integer. If a parity check error occurs in the data frame under test, the binary coordinates of the N bits of data to be tested are XORed bit by bit to obtain the binary coordinates of the erroneous data in the data frame under test. This enables the location of single-bit parity check errors, solving the problem that traditional parity check methods cannot locate single-bit errors. It provides accurate location information for the correction of erroneous data and has the beneficial effect of further improving the reliability and fault tolerance of data transmission.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart of a parity check error localization method provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a parity check error location device provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of a parity check error location circuit provided in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of a parity check circuit provided in Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of a load switch provided in Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of an error location sub-circuit provided in Embodiment 3 of the present invention; Figure 7 This is a circuit diagram of a decoder module provided in Embodiment 3 of the present invention; Figure 8 This is a circuit diagram of a single error control chip provided in Embodiment 3 of the present invention; Figure 9 A circuit diagram of a single error data correction chip provided in Embodiment 3 of the present invention; Figure 10 A schematic diagram of the structure of an electronic device for implementing the parity check error location method of this invention. Detailed Implementation

[0016] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0018] Example 1 Figure 1 This is a flowchart of a parity check error location method provided in Embodiment 1 of the present invention. This embodiment is applicable to parity checking of data frames and location of single-bit error data. The method can be executed by a parity check error location device, which can be implemented in hardware and / or software, for example, as a parity check error location circuit. This parity check error location device can be configured in an electronic device. Figure 1 As shown, the method includes: S110. Perform parity check on the data frame to be tested; the data frame to be tested contains N bits of data to be tested and 1 bit of parity check data, where N is a positive integer.

[0019] In this context, the data frame to be tested can be understood as the data frame that requires parity checking. In this embodiment, 1 bit of parity check data can be located at the beginning or end of the data frame to be tested.

[0020] In this embodiment, parity checking includes odd parity or even parity. Odd parity is achieved by adding an extra parity bit to ensure that the number of "1"s in the entire data block is odd. Even parity is achieved by adding an extra parity bit to ensure that the number of "1"s in the entire data block is even.

[0021] For example, the encoding rule for parity checking is as follows: ; For data bits, For check bits, This indicates a bitwise XOR operation. At the sending end, the number of "1"s in the original data is counted, and the parity bit value is determined based on the agreed-upon parity type (odd or even). The original data and the parity bit are then sent together to the receiving end.

[0022] However, data transmission may be affected by interference (such as voltage fluctuations, cosmic rays, and channel noise), causing a "0" to unexpectedly become a "1" or a "1" to become a "0," i.e., a single-bit flip error occurs. After receiving the transmitted data, the receiving end recalculates the total number of "1s" in all bits and compares this total with the agreed-upon parity check type: For odd parity, if the total number is odd, the tested data frame has not experienced a single-bit flip error; if the total number is even, the tested data frame is considered to have experienced a single-bit flip error. For even parity, if the total number is even, the tested data frame has not experienced a single-bit flip error; if the total number is odd, the tested data frame is considered to have experienced a single-bit flip error.

[0023] In this embodiment, the received signal can be sampled and filtered to obtain the signal under test. The signal under test is then parsed to obtain one or more frames of data to be tested. Each data frame contains N bits of data to be tested and 1 bit of parity check data. Parity check is performed on each frame of data to be tested to detect whether the signal under test has been transmitted accurately.

[0024] S120. If a single-bit flip error occurs in the data frame to be tested, the binary coordinates of the erroneous data in the data frame to be tested are obtained by bitwise XORing the N bits of the data to be tested according to the binary coordinates of the N bits of the data to be tested.

[0025] In this context, erroneous data can be considered as data in the data frame under test that has undergone a single-bit flip. In this embodiment, if a single-bit flip error occurs in the data frame under test, the location of the erroneous data in the N bits of the data under test is further determined, thereby achieving the localization of the erroneous data.

[0026] In this embodiment, to facilitate the location of erroneous data, binary coordinates can be assigned to the N bits of data to be tested in the test data frame according to their arrangement order. The number of bits for the binary coordinates can be determined based on the number of bits (i.e., N) of the data to be tested. For example, for 16-bit data, the number of bits for the binary coordinates can be 4, that is, the binary coordinates corresponding to the 0~16 bits of the data to be tested are 0000~1111; for 8-bit data, the number of bits for the binary coordinates can be 3, that is, the binary coordinates corresponding to the 0~16 bits of the data to be tested are 000~111.

[0027] In this embodiment, by performing a bitwise XOR operation on the N-bit data to be tested based on the binary coordinates of the N-bit data to be tested, the XOR result can be obtained. The XOR result can be determined as the binary coordinates of the erroneous data in the data frame to be tested, thereby realizing the location of the erroneous data.

[0028] In this embodiment, obtaining the binary coordinates of erroneous data in the test data frame by bitwise XORing the N bits of test data according to their binary coordinates includes: for each bit's binary coordinate, bitwise XORing the test data whose binary coordinate value is 1 to obtain the binary coordinates of erroneous data in the test data frame; or, for N bits of test data, bitwise XORing the binary coordinates corresponding to the test data with a value of 1 to obtain the binary coordinates of erroneous data in the test data frame.

[0029] The technical solution of this invention involves parity checking of the data frame under test. The data frame under test contains N bits of data to be tested and 1 bit of parity check data, where N is a positive integer. If a parity check error occurs in the data frame under test, the binary coordinates of the N bits of data to be tested are XORed bit by bit to obtain the binary coordinates of the erroneous data in the data frame under test. This enables the location of single-bit parity check error data, providing accurate location information for the correction of error data, which is beneficial to further improve the reliability and fault tolerance of data transmission.

[0030] As an optional embodiment of this example, S120, if a single-bit flip error occurs in the data frame to be tested, the binary coordinates of the erroneous data in the data frame to be tested are obtained by bitwise XORing the N bits of the data to be tested according to their binary coordinates, including: A1. If a single-bit flip error occurs in the data frame under test, the M-bit binary coordinates corresponding to the N-bit data under test are determined according to the arrangement order of the N-bit data under test in the data frame under test.

[0031] For example, consider the 16-bit (N=16) test data 0101111000110101 in the test data frame. The data contains nine "1"s (an odd number). For odd parity, if the parity bit P=1, it is considered that a single-bit flip error has occurred in the test data frame; for even parity, if the parity bit P=0, it is considered that a single-bit flip error has occurred in the test data frame.

[0032] Four bits (M=4) of binary coordinates 0000~1111 can be assigned. The 4-bit binary coordinates corresponding to the 16 bits of data to be tested are shown in Table 1.

[0033] Table 1 A2. For each bit of binary coordinate, perform a bitwise XOR operation on the test data whose binary coordinate value is 1.

[0034] In this embodiment, according to Table 1, the binary coordinates of the first bit (least significant bit) with a value of 1 include: 0001, 0011, 0101, 0111, 1001, 1011, 1101, 1111, and the corresponding test data are: D1(1), D3(1), D5(1), D7(0), D9(0), D11(1), D13(1), D15(1). The test data with a first bit value of 1 are XORed bitwise to obtain Y0 = D1⊕D3⊕D5⊕D7⊕D9⊕D11⊕D13⊕D15 = 1⊕1⊕1⊕0⊕0⊕1⊕1⊕1 = 0; where ⊕ represents the XOR logical operator.

[0035] Similarly, the binary coordinates with the value of 1 in the second bit include: 0010, 0011, 0110, 0111, 1010, 1011, 1110, 1111. The corresponding test data are: D2 (0), D3 (1), D6 (1), D7 (0), D10 (1), D11 (1), D14 (0), D15 (1). The test data with the value of 1 in the second bit are XORed to obtain Y1=D2⊕D3⊕D6⊕D7⊕D10⊕D11⊕D14⊕D15=0⊕1⊕1⊕0⊕1⊕1⊕0⊕1=1.

[0036] The binary coordinates of the 3rd bit with a value of 1 include: 0100, 0101, 0110, 0111, 1100, 1101, 1110, 1111. The corresponding test data are: D4 (1), D5 (1), D6 (1), D7 (0), D12 (0), D13 (1), D14 (0), D15 (1). The test data with a value of 1 in the 3rd bit are XORed to obtain Y2=D4⊕D5⊕D6⊕D7⊕D12⊕D13⊕D14⊕D15=1⊕1⊕1⊕0⊕0⊕1⊕0⊕1=1.

[0037] The binary coordinates of the 4th bit (most significant bit) being 1 include: 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111. The corresponding test data are: D8 (0), D9 (0), D10 (1), D11 (1), D12 (0), D13 (1), D14 (0), D15 (1). The test data with the 4th bit being 1 are XORed to obtain Y3=D8⊕D9⊕D10⊕D11⊕D12⊕D13⊕D14⊕D15=0⊕0⊕1⊕1⊕0⊕1⊕0⊕1=0.

[0038] Therefore, the XOR result of the 4-bit binary coordinate is 0110.

[0039] A3. Determine the binary coordinates of the erroneous data in the data frame to be tested based on the XOR results corresponding to the M-bit binary coordinates.

[0040] In this embodiment, the binary coordinates formed by the XOR results of the M-bit binary coordinates are determined as the binary coordinates of the erroneous data in the data frame under test. Continuing with the above example, the XOR result of the 4-bit binary coordinates is 0110. Therefore, the binary coordinates of the erroneous data in the data frame under test can be determined as 0110, and the corresponding erroneous data is D6=1.

[0041] As another optional embodiment of this example, if a single-bit flip error occurs in the data frame under test, the binary coordinates of the erroneous data in the data frame under test are obtained by bitwise XORing the N bits of the data under test according to their binary coordinates, including: B1. If a single-bit flip error occurs in the data frame under test, the M-bit binary coordinates corresponding to the N-bit data under test are determined according to the arrangement order of the N-bit data under test in the data frame under test.

[0042] In this embodiment, taking the 16-bit (N=16) test data 0101111000110101 in the test data frame as an example, 4 bits (M=4) of binary coordinates 0000~1111 can be assigned. The 4-bit binary coordinates corresponding to the 16-bit test data are shown in Table 1 above.

[0043] B2. For N bits of test data, perform a bitwise XOR operation on the binary coordinates corresponding to the test data with a value of 1 to obtain the binary coordinates of the erroneous data in the test data frame.

[0044] In this embodiment, taking the 16-bit (i.e., N=16) test data 0101111000110101 in the test data frame as an example, according to Table 1, the test data with a value of 1 includes: D3, D4, D5, D6, D10, D11, D13, D15, and the corresponding binary coordinates are 0011, 0100, 0101, 0110, 1010, 1011, 1101, 1111. By XORing the first bit of the binary coordinates, we get Y=0001⊕0011⊕0101⊕0100⊕0110⊕1010⊕1011⊕1101⊕1111=0110. Among them, Y0=1⊕1⊕1⊕0⊕0⊕0⊕1⊕1⊕1=0, Y1=0⊕1⊕0⊕0⊕1⊕1⊕1⊕0⊕1=1, Y2=0⊕0⊕1⊕1⊕1⊕0⊕0⊕1⊕1=1, Y3=0⊕0⊕0⊕0⊕0⊕1⊕1⊕1⊕1=0.

[0045] The XOR result of the 4-bit binary coordinates is 0110. Therefore, it can be determined that the binary coordinates of the erroneous data in the data frame under test are 0110, and the corresponding erroneous data is D6=1.

[0046] B3. Determine the binary coordinates of the erroneous data in the data frame to be tested based on the XOR results corresponding to the M-bit binary coordinates.

[0047] In this embodiment, the XOR result of the 4-bit binary coordinates is 0110. Therefore, the binary coordinates of the erroneous data in the data frame to be tested can be determined to be 0110, and the corresponding erroneous data is D6=1.

[0048] This embodiment can locate single-bit error data in parity checking through simple coordinate allocation and XOR operation, providing accurate location information for error data correction.

[0049] As an optional embodiment of this example, after obtaining the binary location coordinates of the erroneous data, the method further includes: The binary coordinates of the erroneous data are used to determine the corresponding data in the test frame as erroneous data. The erroneous data in the test frame is then corrected to obtain a corrected data frame.

[0050] In this embodiment, since the erroneous data is caused by a single bit flip, the binary coordinates of the erroneous data are identified as the data to be tested corresponding to the data to be tested in the data frame to be tested. The erroneous data in the data frame to be tested is then subjected to a single bit flip (flipped from "0" to "1" or from "1" to "0") to correct the erroneous data and obtain the corrected data frame.

[0051] It should be understood that while the parity check method provided in this embodiment has the ability to locate and correct single-bit errors, when used alone, it can only detect errors in other odd-numbered bits, but cannot locate or correct them; it cannot detect, locate, or correct errors in even-numbered bits either. This is due to the inherent principle of parity check itself. To address this issue, in actual data verification processes, the parity check method provided in this embodiment can be combined with other data verification methods, such as cyclic redundancy check, Hamming codes, and hash functions, to verify the integrity and correctness of the data. Traditional parity checking methods lack error localization capabilities. When a parity error is detected, the system typically cannot directly correct the data and can only handle it by requesting retransmission, triggering a system interrupt, or reporting an error. This can lead to performance degradation or service interruption in many applications with high requirements for data real-time performance and continuity. The parity checking method provided in this embodiment not only has the ability to locate single-bit errors but can also correct errors through simple single-bit flipping. Therefore, if a single-bit flipping error occurs during data frame transmission, it can be directly corrected, further improving the reliability and fault tolerance of data transmission.

[0052] Example 2 Figure 2 This is a schematic diagram of a parity check error location device provided in Embodiment 2 of the present invention. Figure 2 As shown, the device includes: a parity check module 210 and an error data location module 220; Parity check module 210 is used to perform parity check on the data frame to be tested; the data frame to be tested contains N bits of data to be tested and 1 bit of parity check data, where N is a positive integer; The error data location module 220 is used to obtain the binary coordinates of the erroneous data in the test data frame by bitwise XORing the N bits of the test data according to the binary coordinates of the N bits of the test data if a single bit flip error occurs in the test data frame.

[0053] This invention provides a parity check error location device, which performs parity check on a data frame under test. The data frame under test contains N bits of data to be tested and 1 bit of parity check data. If a parity check error occurs in the data frame under test, the binary coordinates of the N bits of data to be tested are XORed bit by bit according to the binary coordinates of the N bits of data to be tested to obtain the binary coordinates of the erroneous data in the data frame under test. This device can locate single-bit parity check error data and provide accurate location information for the correction of error data.

[0054] Optionally, the error data location module 220 includes: The first coordinate allocation unit is used to determine the M-bit binary coordinates corresponding to the N-bit data under test according to the arrangement order of the N-bit data under test in the data frame under test if a single-bit flip error occurs in the data frame under test. The first XOR unit is used to perform a bitwise XOR operation on the test data whose binary coordinate value is 1 for each bit's binary coordinate. An error location unit is used to determine the binary coordinates of erroneous data in the data frame to be tested based on the XOR results corresponding to the M-bit binary coordinates.

[0055] Optionally, the device further includes: The error data correction module is used to, after obtaining the binary position coordinates of the error data, determine the corresponding data in the test frame as the error data, correct the error data in the test frame, and obtain the corrected data frame.

[0056] Optionally, the error data location module 220 includes: The first coordinate allocation unit is used to determine the M-bit binary coordinates corresponding to the N-bit data under test according to the arrangement order of the N-bit data under test in the data frame under test if a single-bit flip error occurs in the data frame under test. The second error location unit is used to perform a bitwise XOR operation on the binary coordinates corresponding to the N-bit test data with a value of 1 to obtain the binary coordinates of the erroneous data in the test data frame.

[0057] The parity error location device provided in the embodiments of the present invention can execute the parity error location method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0058] Example 3 Figure 3 This is a schematic diagram of a parity check error location circuit provided in Embodiment 3 of the present invention. This embodiment can be applied to provide a circuit that can implement the parity check error location method provided in the above embodiments. This circuit can be integrated into a chip via chip packaging. Figure 3 As shown, the parity check error location circuit includes: parity check sub-circuit 31, load switch circuit module 32, and error location sub-circuit 33; The parity check sub-circuit 31 includes: a first preset number of parity check chips 311 connected in series; the input of the parity check chip 311 is N bits of data to be tested contained in the data frame to be tested, where N is a positive integer; the output of the parity check chip 311 outputs the parity check result. The load switch circuit module 32 includes a first inverter 321 and a load switch 322; the input terminal of the first inverter 321 is connected to the output terminal of the parity check chip 311, the output terminal of the first inverter 321 is connected to the first input terminal of the load switch 322, and the first output terminal of the load switch 322 is connected to the power supply terminal of the error location sub-circuit 33; the error location sub-circuit 33 includes: XOR gate modules 331 corresponding to the M-bit binary coordinates of the N-bit test data; each XOR gate module 331 includes a second preset number of XOR gate chips 3311 connected in series; the input of each XOR gate module 331 is the test data with a value of 1 at the corresponding bit's binary coordinate, and the output of the XOR gate module 321 is the binary coordinate of the error data at the corresponding bit.

[0059] In this embodiment, the parity check sub-circuit 31 is used to perform parity check on the N-bit test data to determine whether a single-bit flip error has occurred in the N-bit test data. If a single-bit flip error occurs, the error location sub-circuit 33 is activated through the load switch circuit module 32 to locate the erroneous data in the N-bit test data.

[0060] The parity check sub-circuit 31 includes a first preset number of parity check chips 311 connected in series. The first preset number can be determined based on the number of bits (N) of the data to be tested and the number of input bits of the parity check chips 311. For example, if each parity check chip 311 has 9 input bits, then parity check of 16 bits of data to be tested requires at least two parity check chips cascaded together.

[0061] For example, taking the 74HC280 parity check chip and 16 bits (i.e., N=16) of the data to be tested in the data frame as an example, Figure 4 This is a schematic diagram of a parity check circuit provided in Embodiment 3 of the present invention. Figure 4 As shown, the parity check sub-circuit 31 includes two parity check chips 74HC280 connected in series. The parity check sub-circuit 31 can be designed as an odd parity check sub-circuit or an even parity check sub-circuit according to a pre-agreed parity check mechanism. In the odd parity check sub-circuit, the input data of U1 74HC280 is the first 8 bits of the test data D0~D7 and 1 bit of check data P, and the output data is EVEN1; the input data of U2 74HC280 is the last 8 bits of the test data D8~D15 and EVEN1, and the output data is EVEN2; the parity check result ERROR = EVEN2. ERROR = 1: indicates that the odd parity check result is normal (an odd number of 1s for odd parity check), and no error data location and correction is performed; ERROR = 0: indicates that the odd parity check result is a single bit flip (an even number of 1s for odd parity check), and error data location and correction are initiated.

[0062] In the even parity sub-circuit, the input data of U1 74HC280 consists of the first 8 bits of the test data D0~D7 and 1 bit of parity data P, and the output data is ODD1; the input data of U2 74HC280 consists of the last 8 bits of the test data D8~D15 and ODD1, and the output data is ODD2; the parity check result ERROR = ODD2. ERROR = 1: indicates that the even parity check result is normal (an even number of 1s for even parity check), and no error data location and correction is performed; ERROR = 0: indicates that the even parity check result is a single bit flip (an odd number of 1s for even parity check), and error data location and correction are initiated.

[0063] In this embodiment, the load switch circuit module 32 includes a first inverter 321 and a load switch 322. The input terminal of the first inverter 321 is connected to the output terminal of the parity check chip 311, and is used to invert the parity check result output by the parity check chip 311. The output terminal of the first inverter 321 is connected to the first input terminal of the load switch 322, and the first output terminal of the load switch 322 is connected to the power supply terminal (VCC) 33 of the error location sub-circuit. When the parity check result shows a single bit flip, i.e., ERROR=0, it becomes... after being inverted by the first inverter 321... (High level) Turns on load switch 322, providing power to the power supply terminal 33 of the error location sub-circuit through load switch 322. When the parity check result is normal, i.e., ERROR=1, the result is inverted by the first inverter 321 and becomes... (Low level) cannot turn on the load switch 322, and therefore will not turn on the parity check circuit.

[0064] For example, taking the four-channel load switch chip FPF2700 as an example, Figure 5 This is a schematic diagram of a load switch provided in Embodiment 3 of the present invention. Figure 5As shown, in this embodiment, the error location sub-circuit 33 includes: M XOR gate modules 331, each XOR gate module 331 corresponding to one bit of the binary coordinate. Each XOR gate module 331 includes a second preset number of XOR gate chips 3311 connected in series. The second preset number can be determined according to the number of bits of the data to be tested (i.e., N) and the number of XOR gates contained in the XOR gate chips. For example, the binary coordinates corresponding to 16 bits of data to be tested are 4 bits, and the binary coordinates of each bit are 1 or 0, that is, there are 8 data to be tested with each bit having a binary coordinate of 1, that is, there are 8 data to be tested with each bit participating in the XOR gate operation. If each XOR gate chip 3311 can include 4 XOR gates (each XOR gate can perform XOR operation on two data to be tested), then at least 2 XOR gate chips need to be cascaded. The input of each XOR gate module 331 is the data to be tested with a binary coordinate value of 1 for the corresponding bit, and the output of the XOR gate module 331 is the binary coordinate of the error data in the corresponding bit.

[0065] For example, continuing with the above embodiments, and taking the XOR gate chip 74HC86 as an example, Figure 6 This is a schematic diagram of an error location sub-circuit provided in Embodiment 3 of the present invention. Figure 6 As shown, the binary coordinates of the 16-bit test data are 4 bits, therefore four XOR gate modules 331 are required. For each bit's binary coordinate, performing a bitwise XOR operation on the eight test data bits with a binary coordinate of 1 requires at least three rounds of XOR operations. For example, the first round of XOR operations for Y0=D1⊕D3⊕D5⊕D7⊕D9⊕D11⊕D13⊕D15 includes: D1⊕D3=T1_0, D5⊕D7=T1_1, D9⊕D11=T1_2, D13⊕D15=T1_3, requiring four XOR gates; the second round of XOR operations includes: T1_0⊕T1_1=T2_0, T1_2⊕T1_3=T2_1, requiring two XOR gates; the third round of XOR operations includes: T2_0⊕T2_1=Y1, requiring one XOR gate. It is evident that performing a bitwise XOR operation on 8 test data requires at least 7 XOR gates, and each XOR gate chip 74HC86 can provide 4 XOR gates. Therefore, each XOR gate module requires at least two XOR gate chips 74HC86 connected in series.

[0066] It should be understood that, Figure 6The diagram shows the circuit diagram of an XOR gate module 331 that performs a bitwise XOR operation on the binary coordinates corresponding to the data under test when the value of the first bit is 1. The input data for the circuit diagrams of XOR gate modules 331 for other bits differs, but the implementation principle is exactly the same. Furthermore, the implementation principles of the parity check sub-circuit 31 and the error location sub-circuit 33 for data frames with other bit counts are also completely identical. The number of parity check chips 311, XOR gate modules 331, and XOR gate chips 3311 can be determined as needed; this will not be elaborated further in this embodiment of the invention.

[0067] As an optional embodiment of this example, the parity check error location circuit further includes: a data correction sub-circuit; the data correction sub-circuit includes a decoder module 34, an error control circuit module 35, and an error data correction circuit module 36; Specifically, the second input terminal of the load switch 322 is connected to the output terminal of the first inverter 321, and the second output terminal of the load switch 322 is connected to the power supply of the decoder module 34; the third input terminal of the load switch 32 is connected to the output terminal of the first inverter 321, and the third output terminal of the load switch 322 is connected to the power supply of the error control circuit module 35; the fourth input terminal of the load switch 322 is connected to the output terminal of the first inverter 321, and the fourth output terminal of the load switch 322 is connected to the power supply of the error data correction circuit module 36. The decoder module 34 includes a decoder 341 and a second inverter 342; the input of the decoder module is the M-bit binary coordinates output by the error location sub-circuit, and the output of the decoder module is N-bit decoded data; the decoded data selected by the binary coordinates in the N-bit decoded data is at a first level, and the decoded data not selected by the binary coordinates is at a second level; the input of the second inverter 342 is the N-bit decoded data, and the output of the second inverter 342 is the inverted data of the N-bit decoded data; The error control circuit module 35 includes: a third preset number of error control chips 351 connected in parallel; each error control chip 351 inputs at least one set of first input data, each set of first input data including 1 bit of inverted data from the N bits of inverted data output by the second inverter 342 and the parity check result output by the parity check sub-circuit 31; each error control chip 351 outputs a toggle control signal corresponding to the bit; The error data correction circuit module 36 includes: a fourth preset number of error data correction chips 361 connected in parallel; each error data correction chip 361 inputs at least one set of second input data, each set of second input data including 1 bit of test data from the N bits of test data and the corresponding bit flipping control signal output by the error control chip 351; each error data correction chip 361 outputs correction data corresponding to the test data.

[0068] In this embodiment, the decoder module 34 is used to determine the bit position of the erroneous data in the N-bit test data based on the binary coordinates of the M bits corresponding to the erroneous data. The error control circuit module 35 is used to generate a flip control signal based on the bit position of the erroneous data when the parity check result indicates a single-bit flip error. The error data correction circuit module 36 is used to flip the corresponding bit of the test data according to the flip control signal, thereby correcting the erroneous data.

[0069] In this embodiment, when the parity check result output by the parity check sub-circuit 31 indicates a single-bit flip (ERROR=0), power is supplied to the power supply terminals (VCC) of the decoder 341 and the second inverter 342 in the decoder module 34 via the first inverter 321 and the load switch 322. The decoder module 34 includes a decoder 341 and a second inverter 342. For N bits of test data corresponding to M bits of binary coordinates, the decoder 341 needs to provide at least M address bits (i.e., M inputs) and N lines (i.e., N outputs). The input error location sub-circuit 33 of the decoder 341 outputs the M-bit binary coordinate Y, and the output of the decoder module is N-bit decoded data. The output logic is active low. The selected output pin D[k] goes low (L, 0) (i.e., the first level), while all other unselected outputs remain high (H, 1) (i.e., the second level). k is 0~15, indicating that the k-th bit of the data to be tested is selected. The N-bit decoded data output is inverted by the second inverter 342. The selected output pin D[k] goes high, while all other unselected outputs remain low, inverting the data. .

[0070] For example, continuing with the above embodiments, and taking the 74HC154 decoder as an example, Figure 7 This is a circuit diagram of a decoder module provided in Embodiment 3 of the present invention. Figure 7As shown, the binary coordinates of the 16-bit test data are represented by 4 bits. The 4-bit inputs A0-A3 of the decoder 74HC154 can represent 16 addresses (0000 to 1111), corresponding to the selected outputs Y0 to Y15. This allows the 4-bit binary coordinates of the input error data to be used to output the bit position of the error data within the N-bit test data. For example, if the binary coordinate of the error data is 0110, the output pin of Y6 goes low, corresponding to the error data D6. The second inverter 342 then turns the output pin of Y6 high, activating the error control circuit module and correcting the error data D6.

[0071] In this embodiment, when the parity check result output by the parity check sub-circuit 31 indicates a single-bit flip (ERROR=0), power is supplied to the power supply terminals (VCC) of each error control chip 351 in the error control circuit module 35 via the first inverter 321 and the load switch 322. The error control circuit module 35 includes a third preset number of error control chips 351 connected in parallel. This third preset number can be determined based on the number of bits (N) of the data to be tested and the input bits of the error control chip 351. For example, if the error control chip 351 uses XOR gates to implement bit flipping, and each error control chip 351 can provide 4 XOR gates, then the error control circuit module for 16 bits of data to be tested requires at least 4 error control chips 351, with one error control chip 351 corresponding to every 4 bits of the erroneous data.

[0072] For example, taking the error control chip 74HC08 as an example, Figure 8 This is a circuit diagram of a single error control chip provided in Embodiment 3 of the present invention. The inputs and outputs of the other three error control chips are different, but their circuit implementation principles and layouts are completely identical, and will not be described again in this embodiment. Figure 8 As shown, the error control chip 351 receives four sets of first input data; each set of first input data includes 1 bit of inverted data SELECT[k] from the N-bit inverted data output by the second inverter 342 in the decoder module 34 and the parity check result ERROR output by the parity check sub-circuit 31; each error control chip 351 outputs a corresponding bit flipping control signal FLIP[k], with the logical relationship being FLIP[k] = ERROR ⊕ SELECT[k]. When ERROR = 1 (no single-bit error): all test data are correct data SELECT[k] = 0, thus FLIP[k] = 0, and all test data remain unchanged. When ERROR = 0 (a single-bit error exists): correct test data SELECT[k] = 0, FLIP[k] = 0, and erroneous data SELECT[k] = 1, FLIP[k] = 1.

[0073] In this embodiment, when the parity check result output by the parity check sub-circuit 31 indicates a single-bit flip, i.e., ERROR=0, power is supplied to the power supply terminal (VCC) of each error data correction chip 361 in the error data correction circuit module 36 via the first inverter 321 and the load switch 322. The error data correction circuit module 36 includes a fourth preset number of error data correction chips 361 connected in parallel. The fourth preset number can be determined based on the number of bits (N) of the data to be tested and the input bits of the error data correction chip 361. For example, if the error data correction chip 361 uses XOR gates to implement bit flipping, and each error data correction chip 361 can provide 4 XOR gates, then the error control circuit module for 16 bits of data to be tested requires at least 4 error data correction chips 361, that is, one error data correction chip 361 for every 4 bits in the erroneous data.

[0074] For example, the 74HC86 error data correction chip is used as an example. Figure 9 This embodiment of the invention provides a circuit diagram of a single error data correction chip. The other three error data correction chips have different inputs and outputs, but their circuit implementation principles and layouts are completely identical; therefore, they will not be described again in this embodiment. Figure 9 As shown, each error data correction chip 361 inputs at least one set of second input data, each set of second input data including 1 bit of test data D[k] from the N bits of test data and the corresponding bit toggle control signal FLIP[k] output by the error control chip 351; each error data correction chip 361 outputs the correction data CRECECTED_D corresponding to the bit of test data D[k]. The logical relationship is CRECECTED_D=D[k]⊕FLIP[k]; where, for the erroneous data D[k] corresponding to FLIP[k]=1, This enables data flipping (flipping from "0" to "1" or from "1" to "0"); for the correct data D[k] corresponding to FLIP[k]=0: D[k]⊕0 = D[k], keeping the data unchanged, thus enabling the correction of single-bit erroneous data in N-bit test data.

[0075] Example 4 Figure 10A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0076] like Figure 10 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0077] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0078] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the parity check error localization method.

[0079] In some embodiments, the parity error location method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the parity error location method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the parity error location method by any other suitable means (e.g., by means of firmware).

[0080] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0081] In some embodiments, the parity error localization method may be implemented as a computer program, which is implicitly included in a computer program product. When executed by a processor, the computer program implements the parity error localization method of the present invention. The computer program product can be understood as a software product that primarily implements its solution through a computer program. The computer program used to implement the method of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer program causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer program may be executed entirely on a machine, partially on a machine, partially on a remote machine as a standalone software package, or entirely on a remote machine or server.

[0082] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0083] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0084] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., error data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0085] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0086] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0087] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A parity check error localization method, characterized in that, include: Perform parity checking on the data frame to be tested; The data frame to be tested contains N bits of data to be tested and 1 bit of parity check data; If a single-bit flip error occurs in the data frame under test, the binary coordinates of the erroneous data in the data frame under test are obtained by bitwise XORing the N bits of the data under test according to their binary coordinates.

2. The method according to claim 1, characterized in that, After obtaining the binary location coordinates of the erroneous data, the following is also included: The binary coordinates of the erroneous data are used to determine the corresponding data in the test frame as erroneous data. The erroneous data in the test frame is then corrected to obtain a corrected data frame.

3. The method according to claim 1, characterized in that, If a single-bit flip error occurs in the data frame under test, the binary coordinates of the erroneous data in the data frame under test are obtained by bitwise XORing the N bits of the data under test according to their binary coordinates, including: If a single-bit flip error occurs in the data frame under test, the M-bit binary coordinates corresponding to the N-bit data under test are determined according to the arrangement order of the N-bit data under test in the data frame under test. For N bits of test data, the binary coordinates corresponding to the test data with a value of 1 are XORed bitwise to obtain the binary coordinates of the erroneous data in the test data frame.

4. A parity check error location device, characterized in that, include: The parity check module is used to perform parity checks on the data frame to be tested. The data frame to be tested contains N bits of data to be tested and 1 bit of parity check data; The error data location module is used to obtain the binary coordinates of the erroneous data in the test data frame by bitwise XORing the N bits of the test data according to the binary coordinates of the N bits of the test data if a single bit flip error occurs in the test data frame.

5. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to perform the parity error location method according to any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the parity error location method according to any one of claims 1-3.

7. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the parity error location method according to any one of claims 1-3.

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