A device installation detection system and method

Abstract

The application discloses a device installation detection system and method, and relates to the technical field of computers, which comprises the following steps: reading device insertion method characteristic values from a modular bill of materials to determine an expected installation state sequence by a processor; outputting installation state signals reflecting whether a target pluggable device or a placeholder device is installed in the device slot by a detection circuit arranged in the device slot; determining an actual installation state sequence according to the signals by a control circuit; comparing the actual installation state sequence with the expected installation state sequence expected by a user by the processor; and directly outputting detection result information according to the comparison result. In the production process, whether the device is installed to the correct position can be confirmed at the assembly stage in real time and intuitively, the technical problem of low operation and maintenance efficiency caused by disassembly and adjustment after discovering abnormalities by relying on later testing is solved, the production efficiency is improved, the risk of physical damage is reduced, accurate data basis is provided for subsequent operation and maintenance, and the operation and maintenance efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a device installation and testing system and method. Background Technology

[0002] In the field of modern server manufacturing and maintenance, with the increasing variety of CPU (Central Processing Unit) platforms and models, there are significant differences in the memory channel architecture and recommended insertion methods for different platforms, making memory installation rules increasingly complex. In the current production process, it is difficult for operators to intuitively confirm whether the memory is installed in the correct position. They often rely on later testing to find abnormalities and then disassemble and adjust the machine, which affects production efficiency and increases the risk of physical damage, resulting in low maintenance efficiency. Summary of the Invention

[0003] This application provides a device installation testing system and method to at least solve the technical problem of low operation and maintenance efficiency caused by relying on disassembly and adjustment after discovering anomalies in the later stage of testing.

[0004] This application provides an equipment installation testing system, comprising: The processor is configured to determine the expected installation state sequence of multiple equipment slots corresponding to the initial configuration based on the equipment interpolation characteristic values ​​in the modular bill of materials of the initial configuration. The detection circuit located in the equipment slot is configured to output an installation status signal for the equipment slot, the installation status signal being used to indicate whether the equipment installed in the equipment slot is a target pluggable device or a placeholder device. The control circuit is configured to determine the actual installation state sequence of the multiple equipment slots corresponding to the initial configuration based on the installation state signals output by the multiple detection circuits. The processor is further configured to compare the expected installation state sequence with the actual installation state sequence bit by bit, and generate and output detection result information based on the comparison results.

[0005] This application also provides a method for testing equipment installation, including: Obtain a modular bill of materials for the initial configuration, the modular bill of materials including device interpolation characteristic values ​​corresponding to the processor, the device interpolation characteristic values ​​being used to indicate the expected installation state sequence of multiple device slots under the initial configuration; The actual installation status sequence of multiple equipment slots under the initial configuration is determined by the installation status signal output by the detection circuit located on the equipment slot; the installation status signal is used to indicate whether the equipment installed in the equipment slot is a target pluggable device or a placeholder device. The expected installation state sequence is compared with the actual installation state sequence bit by bit, and the detection result information is generated and output based on the comparison results.

[0006] This application utilizes a modular bill of materials (BOM) to read equipment insertion characteristic values ​​to determine the expected installation state sequence. A detection circuit located in the equipment slot outputs an installation status signal indicating that the slot contains a target pluggable or placeholder device. The control circuit then determines the actual installation state sequence based on these signals. The processor compares the actual installation state sequence with the user-expected sequence and directly outputs the detection result information. This allows for immediate and intuitive confirmation of correct equipment installation during the assembly stage, eliminating the cumbersome process of relying on later testing to identify anomalies and then disassembling and adjusting the equipment. This improves production efficiency and reduces the risk of physical damage, while also providing a precise data foundation for subsequent maintenance and improving maintenance efficiency. Attached Figure Description

[0007] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the structure of an equipment installation and testing system provided in an embodiment of this application; Figure 2 This is a schematic diagram of a detection circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of a control circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another control circuit provided in an embodiment of this application; Figure 5 This is a flowchart illustrating the steps of a device installation and testing method provided in an embodiment of this application. Detailed Implementation

[0009] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0010] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0011] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] Please refer to Figure 1 This application provides a device installation detection system, including: The processor is configured to determine the expected installation state sequence of multiple equipment slots corresponding to the initial configuration based on the equipment interpolation characteristic values ​​in the modular bill of materials of the initial configuration. The detection circuit located in the equipment slot is configured to output an installation status signal for the equipment slot. The installation status signal is used to indicate whether the equipment installed in the equipment slot is a target pluggable device or a placeholder device. The control circuit is configured to determine the actual installation state sequence of multiple equipment slots corresponding to the initial configuration based on the installation state signals output by multiple detection circuits. The processor is also configured to compare the expected installation state sequence with the actual installation state sequence bit by bit, and generate and output detection result information based on the comparison results.

[0013] In this embodiment, the processor determines the expected installation sequence of multiple device slots under the initial configuration based on the device insertion characteristic values ​​in the modular bill of materials. The device insertion characteristic value is a hexadecimal number converted from a 16-bit binary number. Each bit of the binary number corresponds to a device slot; 1 indicates that the slot requires the installation of a target pluggable device, and 0 indicates that no installation is required. Storing this characteristic value in hexadecimal format is more compact than directly storing a binary string. A 16-bit binary sequence can be fully expressed using only 4 hexadecimal characters, thus reducing the data footprint of the modular bill of materials, production task sheets, and the controller's internal memory. Furthermore, hexadecimal representation facilitates manual reading and input by production management and maintenance personnel when verifying configurations. Compared to a long string of binary numbers, hexadecimal characters are shorter, less prone to errors, and more easily compatible with common mask representations in hardware registers. They can be recognized and processed by the underlying control logic without additional conversion, thereby improving the overall system operating efficiency. Taking a dual-socket server as an example, each processor manages 16 memory slots. If the interposer characteristic value is 0x0200, after conversion to binary, only the 9th bit is 1, indicating that only the 9th slot needs to be installed with memory.

[0014] A detection circuit is installed in each device slot, outputting an installation status signal for that slot. This signal indicates whether the device installed in the slot is a target pluggable device or a placeholder device. A placeholder device is a filler component that resembles a target pluggable device in appearance but lacks electrical functionality, such as a memory dummy, used to maintain unobstructed airflow in slots where no actual device is installed. In actual production, each slot either houses actual memory or a memory dummy, and the detection circuit distinguishes between the two using the state of a mechanical switch.

[0015] The control circuit is connected to multiple detection circuits, receives installation status signals output by each detection circuit, and determines the actual installation status sequence of multiple device slots under the initial configuration based on these signals. For example, if slots 1, 3, 5, 7, 9, 11, 13, and 15 out of 16 slots are equipped with physical memory, and the rest are equipped with DUMMYs, then the binary sequence output by the detection circuit will be 1010101010101010. The control circuit uses this sequence as the actual installation status sequence.

[0016] The processor obtains the actual installation state sequence from the control circuit and compares it bit by bit with the previously determined expected installation state sequence. For example, if the expected sequence is 1010101010101010 and the actual sequence is 1010101001010101, the processor will find that the 11th and 13th bits are inconsistent. Based on the comparison result, the processor generates and outputs detection result information. This detection result information indicates whether the installation is correct and, if an installation error occurs, specifically which slots are incorrect. Using this embodiment, during the production process, operators do not need to rely on later testing or consulting paper labels; they can immediately determine whether the memory installation is accurate at the assembly station, thereby avoiding rework and reducing the risk of physical damage.

[0017] In one exemplary embodiment, the processor is further configured to: Obtain the pre-defined processor type characteristics, processor quantity characteristics, first characteristics of pluggable device parameters, second characteristics of pluggable device parameters, and device insertion characteristics corresponding to each processor from the modular bill of materials; Obtain the configuration condition table and the interpolation mapping table. The configuration condition table represents the correspondence between processor type, number of processors, first characteristic of pluggable device parameters, second characteristic of pluggable device parameters, and number of allowed pluggable devices. The interpolation mapping table represents the correspondence between number of processors, number of pluggable devices, and interpolation characteristic value of the corresponding device for each processor. Based on the processor type characteristics, processor quantity characteristics, first characteristic of pluggable device parameters, second characteristic of pluggable device parameters, and number of pluggable devices in the initial configuration, the insertion mapping table is consulted to obtain the device insertion characteristic value corresponding to the processor in the initial configuration. Use the equipment interpolation characteristic value as the equipment interpolation characteristic value in the modular bill of materials.

[0018] In this embodiment, the processor first acquires several pre-set characteristics from the modular bill of materials, including processor type characteristics, processor quantity characteristics, first pluggable device parameter characteristics, and second pluggable device parameter characteristics. The processor type characteristic can be G1 or S1, the processor quantity characteristic can be 1 or 2, the first pluggable device parameter characteristic can be 16G, 32G, 64G, 96G, or 128G, and the second characteristic can be 4800HZ, 5600HZ, or 6400HZ. The modular bill of materials also pre-sets device insertion characteristics for each processor, but their specific values ​​are not yet filled in.

[0019] The processor also retrieves a constraint table and an interpolation mapping table. The constraint table describes the number of pluggable devices allowed to be installed under specific processor types, processor counts, first pluggable device parameter characteristics, and second pluggable device parameter characteristics. For example, when an S1 processor is selected and the count is 1, a 32GB 6400MHz memory module can only support 1, 4, or 8 modules, but not 12 or 16 modules; while a 64GB 6400MHz memory module can support 1, 4, 8, 12, or 16 modules. For a G1 processor with a count of 1, 16GB, 24GB, 32GB, and 48GB 6400MHz memory modules only support 1, 4, or 8 modules. The interpolation mapping table outputs the device interpolation characteristic value for each processor based on the number of processors and the number of pluggable devices. For example, when the number of processors is 1 and the number of memory is 1, the interpolation mapping table gives the memory interpolation characteristic value as 0x0200; when the number of processors is 2 and the number of memory is 12, the corresponding interpolation characteristic values ​​are 0xAA55 and 0x2244 respectively, depending on the processor installation order.

[0020] The processor, based on the processor type, number of processors, first characteristic of pluggable device parameters, second characteristic of pluggable device parameters, and the actual number of pluggable devices to be installed in the initial configuration, first queries the configuration constraint table for compliance verification. If the configuration is not within the allowed range, for example, selecting 12 x 32GB 6400Hz memory modules under a single S1 processor, the configuration constraint table will reject the configuration. As an alternative implementation, the processor can instruct the user to select according to the configuration constraint table. For example, when selecting 32GB 6400Hz memory under a single S1 processor, it will not prompt for 12 modules, but only indicate that it is an option. Next, the processor queries the interpolation mapping table to obtain the device interpolation characteristic value corresponding to each processor in the current configuration. For example, if the initial configuration is 2 G1 processors and 24 x 64GB 6400Hz memory modules, then each processor is allocated 12 memory modules. The interpolation characteristic value for processor 0 is 0xFFFF, and the interpolation characteristic value for processor 1 is 0xAA55. The processor saves these values ​​as equipment interposability characteristic values ​​in the modular bill of materials for subsequent production and inspection. In this embodiment, unique memory interposability information can be automatically derived from the order selection stage without manual intervention.

[0021] In one exemplary embodiment, the detection circuit includes a first detection switch and a second detection switch connected in series, and the occupant device includes a protrusion that cooperates with the second detection switch, wherein: The first detection switch is located below the latch in the equipment slot. When the latch is open, the first detection switch is off, and when the latch is closed, the first detection switch is closed. The second detection switch is installed in the equipment slot along the equipment installation direction. When the target device in the equipment slot is pluggable, the second detection switch is closed; when the device in the equipment slot is occupied, the second detection switch is open.

[0022] In this embodiment, each equipment slot is equipped with two spring switches connected in series, namely a first detection switch and a second detection switch, as shown in the figure. Figure 2 As shown. Simultaneously, the spacer used has a special protruding structure, the position of which matches the second detection switch. The first detection switch is installed below the latch in the equipment slot. When the latch is in the open state, the contacts of the first detection switch are separated, and the switch is off; when the operator installs the equipment in place and presses the latch to close it, the latch will press against the contacts of the first detection switch, causing the switch to close.

[0023] The second detection switch is fixed in a position inside the slot along the device's installation direction. Normally, this switch is in the pop-up position, meaning it is closed. When the target pluggable device is installed in the slot, the second detection switch remains in the pop-up closed position because the actual device has no additional protrusion. When a placeholder device is installed in the slot, the protrusion on the placeholder device will press down on the second detection switch as the device is inserted, causing the switch to open.

[0024] The first and second detection switches are connected in series to form a detection branch. The on / off logic of this branch is as follows: the branch is only conductive when the latch is closed and the second detection switch is not pressed closed (i.e., a real pluggable device is installed in the slot and the latch is engaged), at which point the detection circuit outputs a high level. If a placeholder device is installed in the slot, the second detection switch is open, the branch is not conductive, and the output is low. If the latch is not closed, the first detection switch is open, the branch is not conductive, and the output is low. In this way, the detection circuit can not only distinguish between real devices and placeholder devices, but also detect whether the latch is properly locked, avoiding poor contact problems caused by an open latch.

[0025] In one exemplary embodiment, the control circuit includes: Multiple first shift registers are used. The serial output pin of the (i+1)th first shift register is connected to the serial input pin of the ith first shift register. The multiple parallel input pins of the first shift registers are connected to the outputs of multiple detection circuits, where i is a positive integer. The controller is connected to the serial output pin of the first shift register and is configured to determine the actual installation state sequence of multiple device slots in the initial configuration based on the signal output by the serial output pin of the first shift register.

[0026] The control circuit includes multiple first shift registers and a controller. The first shift registers utilize chips with parallel input and serial output capabilities. Each first shift register has multiple parallel input pins, which are connected to the outputs of multiple detection circuits. Taking a single processor supporting 16 memory slots as an example, refer to... Figure 3 As shown, the outputs of the detection circuits in slots 1 to 8 are connected to pins D0 to D7 of the first first shift register, and the outputs of the detection circuits in slots 9 to 16 are connected to pins D0 to D7 of the second first shift register. These first shift registers are connected in a cascaded manner. Specifically, the serial output pin Q7 of the (i+1)th first shift register is connected to the serial input pin SER of the ith first shift register, where i is a positive integer. For example, the Q7 pin of the second first shift register is connected to the SER pin of the first first shift register. Through this cascading, the serial outputs of all the first shift registers ultimately converge to the serial output pin Q7 of the first first shift register.

[0027] The controller's input pins are connected to the serial output pin of the first shift register. The controller provides a unified clock and load signal to all first shift registers, causing each first shift register to simultaneously latch the level state on its parallel input pins and then continuously output serial data. Specifically, the controller pulls the SH / LD pin low, causing both first shift registers to simultaneously latch the installation status signals of 16 slots; then it pulls the SH / LD pin high and continuously provides 16 CLK clock signals, reading the level output from the Q7 pin of the first first shift register on each rising edge of the clock. In this way, the controller sequentially obtains the binary bits from slot 1 to slot 16, forming a 16-bit actual installation status sequence, for example, 1010101010101010. This cascaded shift register method requires only a small number of the controller's input / output pins to read the status of a large number of device slots, reducing wiring complexity and hardware cost.

[0028] In one exemplary embodiment, the controller is further configured to generate a machine-readable identifier based on an actual installation state sequence; The display is configured to show machine-readable identifiers; The scanning device is configured to scan machine-readable identifiers and decode them to obtain the decoded sequence. The processor is specifically configured to compare the expected installation state sequence with the decoded sequence bit by bit. If the decoded sequence and the expected installation state sequence are different, an alarm message is generated. The alarm message includes the identifier of the device slot where the installation is abnormal.

[0029] In this embodiment, the controller also has the function of generating machine-readable labels. Based on the determined actual installation state sequence, the controller generates a corresponding machine-readable label image data according to a preset barcode encoding rule. For example, if the actual installation state sequence is 1010101010101010, the controller encodes this sequence into a corresponding barcode pattern. This barcode can be a common format such as Code 128 or QR code. The system also includes a display, which can be an E-paper electronic paper display module, installed on the top cover of the server equipment. The E-paper display has the characteristic of maintaining display even when power is off, making it suitable for use in production line workstations. The display is connected to the controller's display output interface, receiving and displaying the machine-readable label image data sent by the controller.

[0030] Operators use scanning devices, such as handheld barcode scanners, to scan the machine-readable markings on the display. The scanner decodes the image, obtaining a decoded sequence. For example, after reading the barcode, the scanner outputs 1010101010101010, which matches the original actual installation sequence. The scanning device uploads the decoded sequence to the Manufacturing Execution System (MES) via wired or wireless means.

[0031] The processor is configured to compare the expected installation state sequence bit by bit with the decoded sequence obtained from the scan. The processor can obtain the expected installation state sequence from the production task order carried in the MES system. For example, if the order is configured with 2 G1 processors and 24 64GB 6400Hz memory modules, the expected installation state sequences are 1111111111111111 and 1010101001010101. If the decoded sequence is exactly the same as the expected sequence, the installation is considered correct, and the system can output an installation success message. If they are inconsistent, for example, the decoded sequence is 1010101001010101 while the expected sequence is 1111111111111111, the processor generates an alarm message. This alarm message clearly includes the identifier of the equipment slot with the installation error, for example, indicating that slots 2, 4, 6, 8, 10, 12, 14, and 16 are incorrectly installed. Operators can quickly locate and correct the incorrect installation based on the alarm message. In this way, the production line can verify the correctness of the installation by automatically scanning and comparing barcodes, instead of relying on manual visual inspection.

[0032] In an exemplary embodiment, the control circuit is further configured to store a limiting condition table and an interpolation mapping table, receive a target configuration after adjusting the initial configuration, determine the device interpolation characteristic value corresponding to the processor in the target configuration according to the limiting condition table and the interpolation mapping table, determine a target installation state sequence of multiple device slots based on the device interpolation characteristic value, compare the target installation state sequence and the actual installation state sequence bit by bit to obtain the difference results of multiple device slots, and generate a prompt signal based on the difference results; the difference results include one of a pluggable device to be installed, a pluggable device to be removed, and a pluggable device to be maintained.

[0033] In this embodiment, the control circuit also has the capability to handle modification and expansion tasks. The control circuit stores a limiting condition table and an interpolation mapping table, which can be stored in internal non-volatile memory. The contents of these tables are the same as described above. For example, the limiting condition table records the restriction relationship that 32G 6400HZ memory under a single S1 processor only supports 1, 4, or 8 memory modules, etc., and the interpolation mapping table records the interpolation characteristic values ​​corresponding to different memory quantities, such as 0x0200, 0xAA55, 0x2244, etc.

[0034] When a server configuration needs to be changed during operation, such as adding or removing the number of pluggable devices or replacing devices with different specifications, the operations and maintenance personnel will enter a target configuration. This target configuration includes the desired processor type, number of processors, parameters for the pluggable devices, and the total number of devices to be installed. For example, if the initial configuration is 2 G1 processors and 16 x 16GB 6400MHz memory modules, the target configuration could be changed to 2 G1 processors and 8 x 16GB 6400MHz memory modules.

[0035] After receiving the target configuration, the control circuit first checks its compliance against the configuration limitation table. For example, for a single G1 processor with 16GB of 6400MHz memory, the configuration limitation table allows installations of 1, 4, or 8 memory modules. A target configuration with 4 modules per processor is compliant, as is a configuration with 8 modules. If the target configuration is non-compliant, such as selecting 12 modules, the control circuit returns a configuration error message. After successful verification, the control circuit further determines the device interpolation characteristic value corresponding to each processor under the target configuration based on the interpolation mapping table, and calculates the target installation state sequence for multiple device slots. For example, when the target configuration is 8 memory modules, with 4 modules allocated to each processor, the interpolation characteristic value obtained from the table is 0x0020 or a similar value, which, after conversion to binary, indicates that memory modules need to be installed in slots 3, 7, 10, and 14.

[0036] The control circuit has also acquired the current actual installation state sequence, for example, the actual sequence is 1010101001010101 when there are initially 16 memory modules. Then, the control circuit compares the target installation state sequence with the actual installation state sequence bit by bit. For example, if the actual sequence is 1010101001010101 and the target sequence is 0010001001000100, after bit-by-bit comparison, the first bit (actually 1, target 0) is considered to be removed, the third bit (actually 0, target 1) is considered to be installed, and so on. The comparison results generate a difference result for each slot, categorized into three types: pluggable device to be installed, pluggable device to be removed, and pluggable device to be maintained. The control circuit generates a prompt signal based on these difference results. This embodiment eliminates the need for maintenance personnel to consult manuals or memorize complex insertion rules; the system can automatically calculate the locations of devices to be added or removed.

[0037] In one exemplary embodiment, it further includes: Indicator lights are installed corresponding to the equipment slots; The control circuit is specifically configured such that when the difference result of the equipment slot is a pluggable device to be installed, the indicator light corresponding to the equipment slot is lit in the first mode; when the difference result of the equipment slot is a pluggable device to be removed, the indicator light corresponding to the equipment slot is lit in the second mode; and when the difference result of the equipment slot is to maintain a pluggable device, the indicator light corresponding to the equipment slot is turned off.

[0038] In this embodiment, the system also includes indicator lights, with one indicator light corresponding to each device slot. These indicator lights can be surface-mount LEDs, installed below each memory slot. A control circuit is connected to these indicator lights and can independently control the lighting and extinguishing of each indicator light, as well as control the color or flashing mode of the indicator light. The control circuit performs corresponding indicator light control operations based on the obtained difference results for each device slot. When the difference result for a device slot indicates that a pluggable device is to be installed, the control circuit controls the indicator light corresponding to that slot to light up in a first mode; when the difference result for a device slot indicates that a pluggable device is to be removed, the control circuit controls the indicator light corresponding to that slot to light up in a second mode; when the difference result for a device slot indicates that a pluggable device is to be maintained, the control circuit controls the indicator light corresponding to that slot to turn off.

[0039] Taking a server with two G1 processors, each managing 16 memory slots, as an example, the slots are numbered from 1 to 16, with C3D0 memory slot numbered 1 and C7D0 memory slot numbered 16. The initial configuration is 16 x 16GB 6400MHz memory modules, installed in slots 1, 3, 5, 7, 10, 12, 14, and 16 of processor 0 and the same numbered slots of processor 1. If it is necessary to reduce the configuration to 8 x 16GB 6400MHz memory modules, according to the memory installation method, the 8 memory modules should be installed in slots 3, 7, 10, and 14 of processor 0 and slots 3, 7, 10, and 14 of processor 1. Taking processor 0 as an example, the control circuit receives the current machine memory installation status sequence as 1010101001010101, and the target installation status sequence as 0010001001000100. After comparing each bit, the differences are as follows: Bit 1 (current 1, target 0) is to be removed; Bit 3 (current 0, target 1) is to be installed; Bit 5 (current 1, target 0) is to be removed; Bit 7 (current 0, target 1) is to be installed; Bit 10 (current 0, target 1) is to be installed; Bit 12 (current 1, target 0) is to be removed; Bit 14 (current 0, target 1) is to be installed; Bit 16 (current 1, target 0) is to be removed. The control circuit controls the indicator lights accordingly: slots 3, 7, 10, and 14 (to be installed) light up green; slots 1, 5, 12, and 16 (to be removed) light up yellow; the remaining slots are off. The color sequence of the indicator lights, from slot 1 to 16, is yellow, off, green, off, yellow, off, green, off, off, green, off, yellow, off, green, off, yellow.

[0040] If expanding from 8 memory modules to 16 memory modules, the current actual installation state sequence is 0010001001000100, and the target installation state sequence is 1010101001010101. The difference is as follows: slots 1, 5, 12, and 16 are to be installed; there are no slots to be removed; the rest remain unchanged. The control circuit controls the slots to be installed to light up green, while the others remain off. The color sequence is green, off, green, off, green, off, green, off, off, green, off, green, off, green, off, green, off, green.

[0041] If the system needs to be upgraded to two S1 processors and twelve 64GB 5600MHz memory modules, the installation position on processor 0 is the same as before, according to the memory insertion method. Therefore, there are no slots to be installed or removed, and all indicator lights are off. The current actual installation status sequence of processor 1 is 1010101001010101, and the target installation status sequence is 1000100000010001. The difference is as follows: slots to be removed are 3, 7, 12, and 16, and slots to be installed are 2, 6, 9, and 13. The control circuit controls the slots to be removed to light up yellow, and the slots to be installed to light up green. The color sequence according to the slot order is green, off, yellow, off, green, off, yellow, off, off, yellow, off, green, off, yellow, off, green. With this intuitive indicator light guidance, maintenance personnel do not need to consult any manuals or stickers; they can accurately complete the memory installation or removal operation directly based on the light colors, improving the efficiency of the upgrade and expansion and avoiding misoperation.

[0042] In one exemplary embodiment, the control circuit includes: The memory is configured to store the actual installation state sequence, the configuration condition table, and the interpolation mapping table. The controller is configured to receive the target configuration after the initial configuration is adjusted, determine the device interpolation characteristic value corresponding to the processor in the target configuration according to the limiting condition table and the interpolation mapping table, determine the target installation state sequence of multiple device slots based on the device interpolation characteristic value, compare the target installation state sequence and the actual installation state sequence bit by bit to obtain the difference result of multiple device slots, and generate and output a serial color control signal based on the difference result. Multiple second shift registers are used. The serial input pin of the first second shift register receives the serial color control signal output by the controller. The serial output pin of the j-th second shift register is connected to the serial input pin of the (j+1)-th second shift register. The parallel output pins of the second shift registers are connected to the indicator lights of the corresponding device slots to drive the indicator lights to light up the specified colors according to the difference results. j is a positive integer.

[0043] In this embodiment, the control circuit specifically comprises a memory, a controller, and multiple second shift registers. The memory stores the actual installation state sequence, a matching condition table, and an interpolation mapping table. The actual installation state sequence can be obtained by the aforementioned detection circuit and the first shift register and then stored in the memory for subsequent comparison. The contents of the matching condition table and the interpolation mapping table are the same as described above, for example, recording the allowed number of G1 and S1 processors under different memory specifications and the corresponding interpolation characteristic values ​​such as 0x0200, 0xAA55, 0x2244, 0xFFFF, etc.

[0044] The controller receives the target configuration input from maintenance personnel and reads the configuration limitation table and interpolation mapping table from memory. It then performs compliance checks and calculates the target installation state sequence. For example, if the target configuration is a reduction from 16 memory modules to 8 16GB 6400MHz memory modules, the controller first verifies the configuration's compliance, then looks up the interpolation mapping table to obtain the target interpolation characteristic value, resulting in the target installation state sequence 0010001001000100. The controller then compares the target installation state sequence with the actual installation state sequence 1010101001010101 read from memory, bit by bit, to obtain the difference results for each slot.

[0045] Then, the controller generates a serial color control signal based on the difference results. This signal consists of three independent binary serial data channels, corresponding to the red, green, and blue components, respectively. In the scenario of reducing the number of slots to 8, the controller outputs signal 1 (red) as 1000100000010001, signal 2 (green) as 1010101001010101, and signal 3 (blue) as 000000000000000000. In the scenario of expanding from 8 to 16 slots, the controller outputs signal 1 as 00000000000000000, signal 2 as 1010101001010101, and signal 3 as 0000000000000000. In this case, only the green signal is valid, and the corresponding slot to be installed will light up green. When reconfigured with two S1 processors and twelve 64GB 5600Hz memory modules, the installation location of processor 0 is the same, and its output signal 1 is 1000100000010001, signal 2 is 1010101001010101, and signal 3 is 00000000000000000; the output signal 1 of processor 1 is 001000100100100, signal 2 is 1010101001010101, and signal 3 is 00000000000000000.

[0046] The system also includes multiple secondary shift registers, which utilize chips with serial input and parallel output capabilities, such as shift registers. (See reference...) Figure 4These second shift registers are connected in a cascaded manner. The serial input pin DS of the first second shift register receives the serial color control signal output by the controller. The serial output pin Q7S of the first second shift register is connected to the serial input pin DS of the second second shift register, and so on. The serial output pin of the j-th second shift register is connected to the serial input pin of the (j+1)-th second shift register, where j is a positive integer. The parallel output pins Q0 to Q7 of each second shift register are connected to the control terminals of the indicator lights in the corresponding device slots. After the controller sends the color data for all slots, it controls all second shift registers to simultaneously update the parallel output pins to the new level state, thereby driving the indicator lights to light up the specified colors according to the difference results. For example, in a downsizing scenario, a specific combination of signals 1 and 2 causes the red and green lights in the slot to be removed to light up simultaneously, displaying yellow, while the green light in the slot to be installed is the only one lit up, displaying green. This cascaded shift register scheme allows the controller to control a large number of indicator lights with only a few signal lines, reducing hardware costs and wiring complexity, while ensuring that all indicator lights can be updated synchronously, avoiding display confusion.

[0047] In one exemplary embodiment, the indicator light includes at least a first color pin, a second color pin, and a third color pin; Multiple second shift registers include three cascaded sets of second shift registers, wherein: The parallel output pins of the first group of second shift registers are respectively connected to the first color pins of the indicator lights of multiple device slots; The parallel output pins of the second shift register in the second group are respectively connected to the second color pins of the indicator lights in multiple device slots; The parallel output pins of the third group of second shift registers are respectively connected to the third color pins of the indicator lights of multiple device slots; The serial color control signal output by the controller includes a first color signal, a second color signal, and a third color signal. The first color signal is input to the serial input pin of the first group of second shift registers, the second color signal is input to the serial input pin of the second group of second shift registers, and the third color signal is input to the serial input pin of the third group of second shift registers.

[0048] In this embodiment, the indicator lights are multi-color LEDs, specifically LEDs that include at least a first color pin, a second color pin, and a third color pin, such as an RGB tri-color LED. One such multi-color LED is installed below each device slot. The second shift registers are organized into three independent cascaded structures. The parallel output pins of the first cascaded second shift registers are connected to the first color pins of all the multi-color LEDs in the device slots, for example, the red pin R. The parallel output pins of the second cascaded second shift registers are connected to the second color pins of all the multi-color LEDs in the device slots, for example, the green pin G. The parallel output pins of the third cascaded second shift registers are connected to the third color pins of all the multi-color LEDs in the device slots, for example, the blue pin B.

[0049] The serial color control signal output by the controller is not a single serial data stream, but rather comprises three independent serial signals, referred to as the first color signal, the second color signal, and the third color signal. The first color signal is input to the serial input pin DS of the first group of second shift registers, the second color signal is input to the serial input pin DS of the second group of second shift registers, and the third color signal is input to the serial input pin DS of the third group of second shift registers. Each group of shift registers operates independently, converting its serial input into a parallel output.

[0050] For example, when the indicator light in the k-th slot needs to display yellow, yellow is a mixture of red and green. The controller sends the k-th bit as a high-level red component to the first set of shift registers, the k-th bit as a high-level green component to the second set of shift registers, and the k-th bit as a low-level blue component to the third set of shift registers. The three colors mix to produce yellow. In a scenario of expanding from 8 memory modules to 16 memory modules, the slot to be installed lights up green. At this time, the controller outputs signal 2 (green signal) as 1010101001010101, while signals 1 and 3 are all 0, causing the corresponding slot to display green. In a scenario of downsizing, the slot to be removed lights up yellow. At this time, the controller outputs signal 1 (red signal) as 1000100000010001, signal 2 (green signal) as 1010101001010101, and signal 3 (blue signal) as all 0, causing the corresponding slot to light up with both red and green simultaneously, displaying yellow.

[0051] With three separate control groups, the system can generate up to eight different colors, thus distinguishing more types of operation instructions. For example, green indicates installation, yellow indicates removal, red indicates an error, and blue indicates caution. This embodiment enhances the richness and intuitiveness of the instruction information, enabling maintenance personnel to understand operational requirements more quickly.

[0052] In summary, this application, based on modular BOM design and board and system logic updates, enables the verification of memory insertion during machine assembly, reducing the time wasted on error analysis and machine rework due to incorrect memory insertion during production testing. It also facilitates subsequent maintenance, expansion, or memory model changes. Maintenance personnel no longer need to consult machine configurations or maintenance stickers to identify memory installation locations; they can simply input expansion or change information and install memory based on the LED lights and their colors on the machine.

[0053] Please refer to Figure 5 This application also provides a device installation testing method, including: S101: Obtain the modular bill of materials for the initial configuration. The modular bill of materials includes the device interpolation characteristic value corresponding to the processor. The device interpolation characteristic value is used to indicate the expected installation state sequence of multiple device slots under the initial configuration. S102: The actual installation status sequence of multiple equipment slots under the initial configuration is determined by the installation status signal output by the detection circuit located on the equipment slot; the installation status signal is used to indicate whether the equipment installed in the equipment slot is a target pluggable device or a placeholder device; S103: Compare the expected installation state sequence with the actual installation state sequence bit by bit, and generate and output the detection result information based on the comparison results.

[0054] First, obtain the modular bill of materials (BOM) for the initial configuration. This BOM contains device insertion characteristics for the processor, such as 0x0200, 0xAA55, 0x2244, or 0xFFFF. These characteristics are derived from 16-bit binary numbers, with each bit corresponding to a device slot. A 1 indicates that the slot should be used to install the target pluggable device, and a 0 indicates that it should not be used. From the device insertion characteristics, the expected installation sequence of multiple device slots under the initial configuration can be deduced. For example, the characteristic value 0xAA55, converted to binary 10101010010101, indicates that slots 1, 3, 5, 7, 10, 12, 14, and 16 need to install memory, while the remaining slots do not require installation.

[0055] Then, a detection circuit located on each device slot outputs an installation status signal. This detection circuit distinguishes between a target pluggable device and a placeholder device installed in the current slot. Taking a memory slot as an example, the detection circuit uses two spring switches connected in series. One switch is located below the latch, closing when the latch is closed; the other switch is located on the side of the slot, closing when the actual memory module has no protrusion and opening when the memory module has a protrusion. When the actual memory module is installed and the latch is closed, the circuit is on and outputs a high level; when the memory module is installed, the circuit is open and outputs a low level. Based on the installation status signals output by multiple detection circuits, arranged in slot order, the actual installation status sequence of multiple device slots under the initial configuration is obtained. For example, if the actual memory modules are installed in slots 1, 3, 5, 7, 9, 11, 13, and 15 out of 16 slots, the actual sequence is 1010101010101010.

[0056] The expected installation state sequence is compared bit by bit with the actual installation state sequence. During the comparison, the binary values ​​of the two are checked for consistency for each slot. For example, if the expected sequence is 1010101001010101 and the actual sequence is 1010101010101010, then there will be differences at positions such as bit 9 (expected 0, actual 1), bit 11 (expected 0, actual 1), bit 12 (expected 1, actual 0), bit 13 (expected 0, actual 1), and bit 14 (expected 1, actual 0). Detection result information is generated and output based on the comparison results. If all bits are the same, the detection result information indicates that the installation is correct; if there are different bits, the detection result information can indicate which specific slots have errors, such as slots 9, 11, and 13 having extra memory installed, or slots 12 and 14 having missing memory. This embodiment can be executed immediately at the memory assembly station on the production line. Operators can know whether the installation is correct without waiting for subsequent testing, thus correcting it in time. This avoids the cumbersome process of disassembling the entire machine after testing, reduces the risk of physical damage, and improves production efficiency.

[0057] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-chip (SoC), a complex programmable logic device (CPLD), a microcontroller unit (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, systems-on-chips, or combinations thereof. The device may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, protocol stack, database management system, operating system, cross-platform runtime environment, virtual machine, or a combination thereof. The aforementioned computer program (also referred to as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0058] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0059] The above provides a detailed description of the equipment installation and testing system and method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A device installation and testing system, characterized in that, include: The processor is configured to determine the expected installation state sequence of multiple equipment slots corresponding to the initial configuration based on the equipment interpolation characteristic values ​​in the modular bill of materials of the initial configuration. The detection circuit located in the equipment slot is configured to output an installation status signal for the equipment slot, the installation status signal being used to indicate whether the equipment installed in the equipment slot is a target pluggable device or a placeholder device. The control circuit is configured to determine the actual installation state sequence of the multiple equipment slots corresponding to the initial configuration based on the installation state signals output by the multiple detection circuits. The processor is further configured to compare the expected installation state sequence with the actual installation state sequence bit by bit, and generate and output detection result information based on the comparison results.

2. The equipment installation testing system according to claim 1, characterized in that, The processor is also configured to: Obtain the pre-defined processor type characteristics, processor quantity characteristics, first characteristics of pluggable device parameters, second characteristics of pluggable device parameters, and device insertion characteristics corresponding to each processor from the modular bill of materials; Obtain a configuration constraint table and an interpolation mapping table. The configuration constraint table represents the correspondence between the processor type, the number of processors, the first characteristic of the pluggable device parameter, the second characteristic of the pluggable device parameter, and the allowed number of pluggable devices. The interpolation mapping table represents the correspondence between the number of processors, the number of pluggable devices, and the device interpolation characteristic value corresponding to the processor. Based on the processor type characteristics, processor quantity characteristics, first characteristic of pluggable device parameters, second characteristic of pluggable device parameters, and number of pluggable devices in the initial configuration, the insertion mapping table is queried to obtain the device insertion characteristic value corresponding to the processor in the initial configuration; The device interpolation characteristic value is used as the device interpolation characteristic value in the modular bill of materials.

3. The equipment installation detection system according to claim 1, characterized in that, The detection circuit includes a first detection switch and a second detection switch connected in series, and the occupant device includes a protrusion that cooperates with the second detection switch, wherein: The first detection switch is located below the latch of the equipment slot. When the latch is open, the first detection switch is off, and when the latch is closed, the first detection switch is closed. The second detection switch is disposed in the equipment slot along the equipment installation direction. When the target pluggable device is installed in the equipment slot, the second detection switch is closed; when the placeholder device is installed in the equipment slot, the second detection switch is open.

4. The equipment installation detection system according to claim 1, characterized in that, The control circuit includes: Multiple first shift registers are provided, the serial output pin of the (i+1)th first shift register is connected to the serial input pin of the ith first shift register, and the multiple parallel input pins of the first shift registers are connected to the outputs of multiple detection circuits, where i is a positive integer. A controller, connected to the serial output pin of a first shift register, is configured to determine the actual installation state sequence of the plurality of device slots in the initial configuration based on the signal output by the serial output pin of the first shift register.

5. The equipment installation detection system according to claim 4, characterized in that, The controller is also configured to generate a machine-readable identifier based on the actual installation state sequence; The display is configured to show the machine-readable identifier; The scanning device is configured to scan the machine-readable identifier and decode it to obtain a decoded sequence; The processor is specifically configured to compare the expected installation state sequence with the decoded sequence bit by bit. If the decoded sequence and the expected installation state sequence are different, an alarm message is generated. The alarm message includes the identifier of the device slot with the installation error.

6. The equipment installation testing system according to any one of claims 2-5, characterized in that, The control circuit is further configured to store a limiting condition table and an interpolation mapping table, receive a target configuration after adjusting the initial configuration, determine the device interpolation characteristic value corresponding to the processor in the target configuration according to the limiting condition table and the interpolation mapping table, determine a target installation state sequence of multiple device slots based on the device interpolation characteristic value, compare the target installation state sequence and the actual installation state sequence bit by bit to obtain the difference results of multiple device slots, and generate a prompt signal based on the difference results; the difference results include one of the pluggable devices to be installed, pluggable devices to be removed, and pluggable devices to be maintained.

7. The equipment installation detection system according to claim 6, characterized in that, Also includes: Indicator lights are provided corresponding to the slots in the equipment. The control circuit is specifically configured such that when the difference result of the device slot is a pluggable device to be installed, the indicator light corresponding to the device slot is controlled to light up in a first mode; when the difference result of the device slot is a pluggable device to be removed, the indicator light corresponding to the device slot is controlled to light up in a second mode; and when the difference result of the device slot is a pluggable device to be maintained, the indicator light corresponding to the device slot is controlled to turn off.

8. The equipment installation detection system according to claim 7, characterized in that, The control circuit includes: The memory is configured to store the actual installation state sequence, the configuration condition table, and the interpolation mapping table. The controller is configured to receive a target configuration after adjusting the initial configuration, determine the device interpolation characteristic value corresponding to the processor in the target configuration according to the limiting condition table and the interpolation mapping table, determine a target installation state sequence of multiple device slots based on the device interpolation characteristic value, compare the target installation state sequence and the actual installation state sequence bit by bit to obtain the difference result of multiple device slots, and generate and output a serial color control signal based on the difference result; Multiple second shift registers are provided. The serial input pin of the first second shift register receives the serial color control signal output by the controller. The serial output pin of the j-th second shift register is connected to the serial input pin of the (j+1)-th second shift register. The parallel output pins of the second shift registers are respectively connected to the indicator lights of the corresponding device slots, which are used to drive the indicator lights to light up the specified color according to the difference result. j is a positive integer.

9. The equipment installation testing system according to claim 8, characterized in that, The indicator light includes at least a first color pin, a second color pin, and a third color pin; The plurality of second shift registers includes three sets of cascaded second shift registers, wherein: The parallel output pins of the first group of second shift registers are respectively connected to the first color pins of the indicator lights of the multiple device slots; The parallel output pins of the second group of second shift registers are respectively connected to the second color pins of the indicator lights of the multiple device slots; The parallel output pins of the third group of second shift registers are respectively connected to the third color pins of the indicator lights of multiple device slots; The serial color control signal output by the controller includes a first color signal, a second color signal, and a third color signal. The first color signal is input to the serial input pin of the first group of second shift registers, the second color signal is input to the serial input pin of the second group of second shift registers, and the third color signal is input to the serial input pin of the third group of second shift registers.

10. A method for testing equipment installation, characterized in that, include: Obtain a modular bill of materials for the initial configuration, the modular bill of materials including device interpolation characteristic values ​​corresponding to the processor, the device interpolation characteristic values ​​being used to indicate the expected installation state sequence of multiple device slots under the initial configuration; The actual installation status sequence of multiple equipment slots under the initial configuration is determined by the installation status signal output by the detection circuit located on the equipment slot; the installation status signal is used to indicate whether the equipment installed in the equipment slot is a target pluggable device or a placeholder device. The expected installation state sequence is compared with the actual installation state sequence bit by bit, and the detection result information is generated and output based on the comparison results.

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