I2c bus capacitive load testing method and system
The I2C bus capacitive load testing system, which utilizes the binary search method and formula fine-tuning algorithm, solves the problem of low efficiency in I2C bus capacitive load testing, achieving fast and accurate capacitive load testing and improving testing efficiency and result reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HONGJUN RUITONG MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2026-06-17
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the testing efficiency of capacitive loads on the I2C bus is low, making it difficult to accurately test whether the capacitive load capacity of a chip meets the specification requirements.
An I2C bus capacitive load testing system was built using a binary search coarse search and formula fine-tuning algorithm. The system includes a control device, master device, slave device, load capacitance measurement module, electrical characteristic parameter testing module, capacitive load adjustment module, and pull-up resistor. The target range of the capacitive load was locked by binary search, and fine-tuning was performed according to the set rise time and pull-up resistor value until the capacitive load value converged.
It enables fast and accurate testing of capacitive loads on the I2C bus, reduces the number of trial and error attempts, improves testing efficiency, and ensures the reproducibility and accuracy of test results.
Smart Images
Figure CN122431968A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of I2C bus technology, and more specifically, to an I2C bus capacitive load testing method and system. Background Technology
[0002] I2C (Inter-Integrated Circuit, two-wire serial bus) is a commonly used bus for communication between the CPU and peripheral devices in a chip. Its design must strictly adhere to the electrical specifications of the standard protocol to ensure compatibility with any I2C device. Otherwise, communication anomalies may occur in practical applications.
[0003] I2C bus capacitive load is a key parameter limiting the number of devices that can be connected. Due to differences in pin capacitance among different devices, it is difficult to accurately test whether the chip's I2C capacitive load capacity meets the specification requirements during the post-silicon verification stage.
[0004] Alternatively, even if a test system is built specifically for testing the capacitive load of the I2C bus, its testing efficiency is still low. Summary of the Invention
[0005] The purpose of this application is to provide an I2C bus capacitive load testing method and system to solve the problem of low testing efficiency of I2C bus capacitive load in the prior art.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: On one hand, this application provides an I2C bus capacitive load testing method. The method is applied to the control device of an I2C bus capacitive load testing system. The I2C bus capacitive load testing system further includes a master device, a slave device, a load capacitance measurement module, an electrical characteristic parameter testing module, a capacitive load adjustment module, and pull-up resistors. The master device and the slave device communicate via an I2C bus, which is connected to a power supply via the pull-up resistors. The control device is connected to the load capacitance measurement module, the electrical characteristic parameter testing module, and the capacitive load adjustment module, respectively, and all three modules are connected to the I2C bus. The method includes: Upon receiving the test command, a coarse search is performed using the binary search method to pinpoint the target range where the capacitive load of the I2C bus is located. Within the target range, the capacitive load adjustment module is finely adjusted based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor until the capacitive load value of the I2C bus converges, and the finally converged capacitive load value is taken as the maximum capacitive load value of the I2C bus; wherein, the measured rise time is obtained based on the electrical characteristic parameter testing module.
[0007] Optionally, the step of using a binary search method to perform a coarse search and pinpoint the target range where the capacitive load of the I2C bus is located includes: Set the initial search interval [Cmin, Cmax]; Set Cset to Cmax and drive the slave device to perform read and write operations. If the read and write operations fail, set Cset to the midpoint value of the initial search interval and drive the slave device to perform read and write operations. Cset represents the capacitive load setting value. Repeat the steps of updating the search interval based on the results of the read and write operations and setting Cset as the midpoint value of the current search interval until the width of the search interval reaches the set value or the number of read and write operations reaches the threshold, and use the finally determined search interval as the target interval; wherein, the width of the search interval is Cmax-Cmin, and the width of the current search interval is half of the width of the previous search interval.
[0008] Optionally, the step of updating the capacitive load search range based on the result of the read / write operation includes: If the read / write operation is successful, the capacitive load search range is updated to [Cset, Cmax]. If the read / write operation fails, the capacitive load search range is updated to [Cmin, Cset].
[0009] Optionally, when the initial search interval is set to [0, 1000], the width of the target interval is 125pF.
[0010] Optionally, the step of fine-tuning the capacitive load adjustment module based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor includes: When the last read / write test passed, the capacitive load value was set to: Cset=Cset1+(Trspec–Tr) / ln(0.9 / 0.1)*Rset; Where Cset represents the setting value during the current test, Cset1 represents the setting value during the previous test, Trspec represents the set rise time, Tr represents the measured rise time, and Rset represents the resistance value of the pull-up resistor.
[0011] Optionally, the step of fine-tuning the capacitive load adjustment module based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor includes: If the previous read / write test failed, set the capacitive load value to: Cset=Cset1+(Tr-Trspec) / ln(0.9 / 0.1)*Rset; Where Cset represents the setting value during the current test, Cset1 represents the setting value during the previous test, Trspec represents the set rise time, Tr represents the measured rise time, and Rset represents the resistance value of the pull-up resistor.
[0012] Optionally, within the target range, the capacitive load adjustment module is fine-tuned based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor until the capacitive load value of the I2C bus converges. This step includes: When the previous read / write test fails and the current read / write test succeeds, the capacitive load value of the I2C bus is determined to have converged.
[0013] Optionally, the resistance value of the pull-up resistor satisfies the formula: Rset=(VCC – VOLmax) / 3; Where Rset represents the value of the pull-up resistor, VCC represents the power supply voltage, and VOLmax represents the maximum value of the output low level.
[0014] Optionally, the load capacitance measurement module includes an LCR bridge, the electrical characteristic parameter testing module includes an oscilloscope, and the capacitive load adjustment module includes a programmable capacitive load.
[0015] On the other hand, this application embodiment also provides an I2C bus capacitive load testing system. The I2C bus capacitive load testing system includes a control device, a master device, a slave device, a load capacitance measurement module, an electrical characteristic parameter testing module, a capacitive load adjustment module, and pull-up resistors. The master device and the slave device communicate via an I2C bus, which is connected to a power supply through the pull-up resistors. The control device is connected to the load capacitance measurement module, the electrical characteristic parameter testing module, and the capacitive load adjustment module, respectively, and all three modules are connected to the I2C bus. The control device is used to execute the above-described method.
[0016] Compared with the prior art, this application has the following advantages: This application provides an I2C bus capacitive load testing method. This method is applied to the control device of an I2C bus capacitive load testing system. The I2C bus capacitive load testing system also includes a master device, a slave device, a load capacitance measurement module, an electrical characteristic parameter testing module, a capacitive load adjustment module, and pull-up resistors. The master device and slave device communicate via an I2C bus, which is connected to a power supply via pull-up resistors. The control device is connected to the load capacitance measurement module, the electrical characteristic parameter testing module, and the capacitive load adjustment module, all of which are connected to the I2C bus. Upon receiving a test command, a binary search is used for coarse searching to pinpoint the target range where the capacitive load of the I2C bus is located. Within the target range, the capacitive load adjustment module is fine-tuned based on the set rise time, the measured rise time, and the pull-up resistor value until the capacitive load value of the I2C bus converges. The finally converged capacitive load value is taken as the maximum capacitive load value of the I2C bus. The measured rise time is obtained from the electrical characteristic parameter testing module.
[0017] On the one hand, the solution provided in this application establishes a dedicated I2C bus capacitive load testing system, which can accurately test the I2C capacitive load capacity. On the other hand, in actual testing, the approximate range of the maximum capacitive load of the I2C bus is quickly determined using a binary search method. Then, within this range, closed-loop fine-tuning is performed based on the set rise time, the measured rise time, and the pull-up resistor value, thereby significantly reducing the number of trial and error attempts and improving testing efficiency. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A schematic diagram of the I2C bus capacitive load testing system provided in the embodiments of this application.
[0020] Figure 2 An exemplary flowchart of the I2C bus capacitive load testing method provided in the embodiments of this application.
[0021] Figure 3 Provided for the embodiments of this application Figure 2 An exemplary flowchart of the sub-step S102.
[0022] Figure 4Another exemplary flowchart of the I2C bus capacitive load testing method provided in the embodiments of this application.
[0023] In the picture: 110 - Control device; 120 - Master device; 130 - Slave device; 140 - Load capacitance measurement module; 150 - Electrical characteristic parameter testing module; 160 - Capacitive load adjustment module; R1 - First pull-up resistor; R2 - Second pull-up resistor. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0025] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0027] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Some embodiments of this application are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0028] As described in the background section, the capacitive load of the I2C bus must meet certain specifications. For example, for the I2C bus of a certain chip, the capacitive load is required to be 1000pF. In actual testing, the maximum capacitive load value of the I2C bus should be 1000pF or above; otherwise, it is a product that does not meet the specification requirements.
[0029] However, it is currently difficult to accurately test whether a chip's I2C capacitive load capacity meets the specification requirements during the post-silicon verification stage. Alternatively, even if a dedicated test system for testing I2C bus capacitive load is built, its testing efficiency is low.
[0030] In view of this, in order to solve the above problems, this application provides an I2C bus capacitive load testing method, which quickly achieves the testing of the maximum capacitive load value of the I2C bus by using a binary search coarse search plus formula fine-tuning algorithm.
[0031] It should be noted that the I2C bus capacitive load testing method provided in this application can be applied to the control device of an I2C bus capacitive load testing system. Please refer to [link / reference]. Figure 1 The I2C bus capacitive load testing system also includes a master device 120, a slave device 130, a load capacitance measurement module 140, an electrical characteristic parameter testing module 150, a capacitive load adjustment module 160, and pull-up resistors. The master device 120 and the slave device 130 communicate via an I2C bus, which is connected to the power supply via pull-up resistors. The control device 110 is connected to the load capacitance measurement module 140, the electrical characteristic parameter testing module 150, and the capacitive load adjustment module 160, and all three modules are connected to the I2C bus.
[0032] In existing technologies, testing the maximum capacitance that an I2C bus can withstand often requires engineers to manually replace capacitors of different values, capture waveforms repeatedly with an oscilloscope, and rely on experience to determine if communication is abnormal. This is not only time-consuming and labor-intensive but also prone to inconsistent results due to differences in operation. This application, however, constructs a closed-loop testing system that is uniformly scheduled by a control device 110 and involves multiple dedicated hardware modules working collaboratively. This transforms the verification of I2C bus capacitive loads from manual, repetitive wiring measurements into a standardized process that can be automatically executed, remotely controlled, and yields reproducible results.
[0033] For example, the control device 110 can be an MCU, CPLD, FPGA, or other similar device, serving as the core controller of the entire test system. It coordinates the actions of each module to execute the entire automated test process. The master device 120 can be a CPU, i.e., the chip to be verified. The slave device 130 can be an EEPROM, used to communicate with the CPU so that electrical characteristic waveforms can be captured by the electrical characteristic parameter testing module 150 during communication. The load capacitance measurement module 140 can be an LCR bridge, used to measure the load capacitance value of the CPU's I2C pins. The electrical characteristic parameter testing module 150 can be an oscilloscope, used to test the electrical characteristic parameters of the I2C bus, including voltage and timing, meeting relevant specifications and supporting automated testing. The start, termination, and result reading of the test can be remotely controlled via a network. The capacitive load adjustment module 160 can be a programmable capacitive load, used to adjust the capacitive load of the I2C bus. The MCU can set its capacitance value via GPIO. The pull-up resistors include a first pull-up resistor R1 and a second pull-up resistor R2. The resistance values of the first pull-up resistor R1 and the second pull-up resistor R2 are equal. Since the electrical parameters of the I / O pins with VCC differ between different chips, the resistance value must be selected according to the formula to ensure that the pull-up strength matches the chip's driving capability. The resistance value of the pull-up resistor satisfies the formula: Rset = (VCC – VOLmax) / 3; where Rset represents the resistance value of the pull-up resistor, VCC represents the power supply voltage, and VOLmax represents the maximum value of the output low level.
[0034] As can be seen, the MCU establishes connections with the load capacitance measurement module 140 (i.e., LCR digital bridge), the electrical characteristic parameter test module 150 (i.e., oscilloscope), and the capacitive load adjustment module 160 (i.e., programmable capacitive load), and all three are directly connected to the I2C bus under test. One end of the I2C bus is connected to the CPU (the chip to be verified, as the master device 120), and the other end is connected to the EEPROM (as the slave device 130). The bus is connected to the power supply (i.e., VCC) through pull-up resistors (i.e., R1 / R2). This forms a test loop that truly reflects the chip's application environment.
[0035] In practical applications, the MCU can remotely start an oscilloscope via a network to automatically capture voltage and timing waveforms on the I2C bus, including key electrical characteristics such as rise time, fall time, and high / low level width. Simultaneously, the MCU can control a programmable capacitive load to output specific capacitance values according to instructions, simulating different levels of external parasitic capacitance. When it is necessary to confirm the total amount of distributed capacitance actually present on the current I2C bus, the MCU will trigger an LCR digital bridge to directly measure the CPU's I2C pins. All these hardware modules are deployed around the same I2C bus, ensuring realistic signal paths and clear interface relationships, allowing the test results to accurately reflect the CPU's I2C drive boundaries in the actual circuit.
[0036] Based on this, please refer to Figure 2 The I2C bus capacitive load test method provided in this application includes: S102, upon receiving the test command, uses a binary search method to perform a coarse search and locks the target range where the capacitive load of the I2C bus is located.
[0037] S104, within the target range, fine-tunes the capacitive load adjustment module based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor until the capacitive load value of the I2C bus converges, and takes the finally converged capacitive load value as the maximum capacitive load value of the I2C bus; wherein, the measured rise time is obtained based on the electrical characteristic parameter test module.
[0038] Understandably, compared to the existing technology of randomly selecting different capacitance values, this application uses a binary search coarse search plus formula fine-tuning algorithm to quickly test the maximum capacitive load value of the I2C bus, thereby significantly improving testing efficiency.
[0039] Please refer to Figure 3 Step S102 includes: S1021, Set the initial search interval [Cmin, Cmax].
[0040] S1022, set Cset to Cmax and drive the slave device to perform read and write operations. If the read and write operations fail, set Cset to the midpoint value of the initial search interval and drive the slave device to perform read and write operations. Cset represents the capacitive load setting value.
[0041] S1023, Repeat the steps of updating the search interval based on the results of the read and write operations and setting Cset as the midpoint value of the current search interval until the width of the search interval reaches the set value or the number of read and write operations reaches the threshold, and use the finally determined search interval as the target interval; wherein, the width of the search interval is Cmax-Cmin, and the width of the current search interval is half of the width of the previous search interval.
[0042] Once the user issues a test command on the computer client, the system will begin automatic testing. It should be noted that the target maximum capacitive load value of the I2C bus differs for different chips. For example, for chip A, the target maximum capacitive load value of its I2C bus is 1000pF; for chip B, the target maximum capacitive load value of its I2C bus is 1200pF. Therefore, for different chips, it is necessary to confirm their target maximum capacitive load value according to their datasheets, and then set the initial search interval [Cmin, Cmax].
[0043] Generally, Cmin is set to 0pF and Cmax is set to the target maximum capacitive load value. For example, if the target maximum capacitive load value of chip A is 1000pF, then Cmax is set to 1000pF. Therefore, for chip A, its initial search region is [0, 1000].
[0044] Next, Cset is set to Cmax, and the slave device 130 is driven to perform read and write operations. Then, it is determined whether the read and write operations pass. Cset represents the capacitive load setting value. The determination of whether the read and write operations pass is based on the test results of the electrical characteristic parameter test module 150. For example, when the test results of the electrical characteristic parameter test module 150 exceed the set threshold, it means that the test has passed; when the test results of the electrical characteristic parameter test module 150 are lower than the set threshold, it means that the test has failed.
[0045] Specifically, if the maximum capacitive load value corresponding to a certain chip is 900pF, then when the capacitive load of the I2C bus is set to 900pF using a programmable capacitive load, the test result of the electrical characteristic parameter test module 150 will be considered as passing. Of course, if the capacitive load of the I2C bus is set to a value less than 900pF using a programmable capacitive load, such as setting the capacitive load of the I2C bus to 800pF, the test result of the electrical characteristic parameter test module 150 will also be considered as passing. However, if the capacitive load of the I2C bus is set to a value greater than 900pF using a programmable capacitive load, such as setting the capacitive load of the I2C bus to 1000pF, the test result of the electrical characteristic parameter test module 150 will be considered as failing, specifically, the test result of the electrical characteristic parameter test module 150 will be below the threshold.
[0046] Furthermore, by setting up an LCR bridge, the load capacitance value of the CPU's I2C pins can be measured in real time, thereby determining whether the capacitive load value set by the programmable capacitive load is accurate. If it is inaccurate, it can be adjusted accordingly.
[0047] Based on this, if Cset is set to Cmax and read / write operations pass, it indicates that the chip's maximum capacitive load value meets the specification; that is, the chip's maximum capacitive load value is necessarily greater than or equal to the target capacitive load value in its technical datasheet. If read / write operations fail, it indicates that the chip's maximum capacitive load value does not meet the specification, and its actual value will be less than the target capacitive load value in its technical datasheet. Furthermore, when the maximum capacitive load value does not meet the specification, it is necessary to determine the chip's maximum capacitive load value to adjust subsequent processes.
[0048] It should be noted that when the maximum capacitive load value does not meet the specification, it means that the maximum capacitive load value of the I2C bus corresponding to the chip may be located at any value between Cmin and Cmax. In the existing technology, it is necessary to gradually change and adjust its capacitive load and then determine it, which will lead to slow testing efficiency.
[0049] In this application, a binary search method is used to first determine the range. When Cset is set to Cmax and the read / write operation fails, Cset is set to the midpoint of the initial search interval, that is, the value of Cset is set to (Cmin+Cmax) / 2, and the slave device 130 is driven to perform read / write operations.
[0050] Then, the steps of updating the search interval based on the results of the read and write operations and setting Cset to the midpoint value of the current search interval are repeated until the width of the search interval reaches the set value or the number of read and write operations reaches the threshold. For example, until the width of the search interval reaches 125pF or the number of read and write operations reaches 4, the finally determined search interval is taken as the target interval. The width of the search interval is the difference between Cmax and Cmin, and the width of the current search interval is half the width of the previous search interval.
[0051] If the read / write operation succeeds, the capacitive load search range is updated to [Cset, Cmax]; if the read / write operation fails, the capacitive load search range is updated to [Cmin, Cset].
[0052] The following example, using an initial search interval of [0, 1000] and a target interval width of 125pF, provides a detailed explanation of the binary search method for coarse search: First, set Cset to 1000pF, perform read and write operations, and determine whether the read and write operations pass. If they pass, the test ends, indicating that the maximum capacitive load of the CPU's I2C bus is greater than or equal to 1000pF, exceeding the target value. If they fail, it means that the maximum capacitive load of the I2C bus is less than 1000pF, and further testing is needed to determine its actual maximum capacitive load.
[0053] At this point, Cset is set to half of the initial search range, i.e., Cset=500pF, and the read and write operations are performed again. The read and write operations are checked to see if they pass. If they pass, the capacitive load search range is updated to [500, 1000]. If they fail, the capacitive load search range is updated to [0, 500].
[0054] At the same time, the value of Cset is updated according to the current capacitive load search range. For the search range of [500, 1000], Cset is updated to (500+1000) / 2=750pF; for the search range of [0, 500], Cset is updated to (0+500) / 2=250pF, and the read and write operations are checked again.
[0055] For Cset=750pF, if the read / write operation succeeds, the current capacitive load search range is updated to [750, 1000] again. If the read / write operation fails, the current capacitive load search range is updated to [500, 750] again, and the value of Cset is updated again. For a search range of [750, 1000], Cset is updated to 875pF; for a search range of [500, 750], Cset is updated to 625pF, and so on.
[0056] Again, based on Cset=875pF, determine whether the read / write operation is successful. If successful, update the search range to [875, 1000]; if unsuccessful, update the search range to [750, 875].
[0057] Based on this, since the width of the search interval is already locked at 125pF, or the number of times the read / write operation has been checked has reached 4 (e.g., 4 checks were performed based on Cset=1000pF, 500pF, 750pF, and 875pF respectively), the locked search interval can be used as the target interval for the binary search. For example, the target interval could be [875, 1000], [750, 875], [625, 750], [500, 625], etc.
[0058] After determining the target range of the capacitive load, the capacitive load adjustment module 160 can be fine-tuned based on a formula constructed from the set rise time, the measured rise time, and the pull-up resistor value. Specifically, when the previous read / write test passed, the capacitive load value is set as follows: Cset=Cset1+(Trspec–Tr) / ln(0.9 / 0.1)*Rset; Where Cset represents the setting value during the current test, Cset1 represents the setting value during the previous test, Trspec represents the set rise time, Tr represents the measured rise time, and Rset represents the resistance value of the pull-up resistor.
[0059] If the previous read / write test failed, set the capacitive load value to: Cset=Cset1+(Tr-Trspec) / ln(0.9 / 0.1)*Rset; Where Cset represents the setting value during the current test, Cset1 represents the setting value during the previous test, Trspec represents the set rise time, Tr represents the measured rise time, and Rset represents the resistance value of the pull-up resistor.
[0060] And, please see Figure 4 The steps for fine-tuning the capacitive load adjustment module based on the set rise time, the measured rise time, and the pull-up resistor value until the capacitive load value of the I2C bus converges include: When the previous read / write test fails and the current read / write test succeeds, the capacitive load value of the I2C bus is considered to have converged.
[0061] In this application, to determine whether the capacitive load value of the I2C bus has converged, it is necessary to satisfy the following conditions during the fine-tuning stage: first, the test read / write operation fails, and then the current test result passes. This process can determine that the capacitive load value of the I2C bus has converged, and the finally converged capacitive load value is taken as the maximum capacitive load value of the I2C bus.
[0062] In practical applications, after coarsely determining the target interval using the binary search method, the maximum or minimum value of the target interval is directly used to finely adjust the capacitive load adjustment module 160 based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor. For example, if the target interval is determined to be [750, 875], then the measured rise time corresponding to Cset=875pF is determined. This measured rise time is a parameter read from the test results obtained by the MCU after acquiring the test results from the oscilloscope.
[0063] Then, the value of Cset for the next iteration is determined according to the formula Cset = Cset1 + (Tr - Trspec) / ln(0.9 / 0.1) * Rset. This formula can be derived from the following derivation: Trspec = C (time constant) * Rset * Cspec; Tr = C (time constant) * Rset * Cset; Therefore, Cspec - Cset = (Trspec - Tr) / C (time constant) * Rset; That is, Cspec = Cset + (Trspec - Tr) / C (time constant) * Rset; C (time constant) = ln(0.9 / 0.1) = 2.2.
[0064] Where Cspec represents the set capacitor corresponding to the set rise time. It can be seen that by determining the value of Cset for the next time through Cset=Cset1+(Tr-Trspec) / ln(0.9 / 0.1)*Rset, the value of Cset for the next time is actually adjusted to be equal to Cspec, that is, a value that is more closely matched with the set rise time. This value is theoretically closer to the actual maximum capacitive load value of the I2C bus.
[0065] As can be seen, by fine-tuning the formula, this application actually adjusts Cset to be closer to the theoretical maximum capacitive load value of the I2C bus. In other words, although there is an error between the theoretical value and the actual value, each fine-tuning process is a process of getting closer to the actual maximum capacitive load value. This avoids testing one by one in equal steps during the fine-tuning stage, and confirms the actual maximum capacitive load value of the I2C bus in a more efficient way.
[0066] Furthermore, it should be noted that when adjusting using the formulas, Cset=Cset1+(Trspec–Tr) / ln(0.9 / 0.1)*Rset is used as the upward adjustment formula, and Cset=Cset1+(Tr-Trspec) / ln(0.9 / 0.1)*Rset is used as the downward adjustment formula. That is, when the previous read / write operation test failed, it means that the previously set Cset value was too high, and the downward adjustment formula needs to be used to lower the Cset value; when the previous read / write operation test passed, it means that the previously set Cset value was too low, and the upward adjustment formula needs to be used to increase the Cset value in order to determine a more accurate actual maximum capacitive load value of the I2C bus.
[0067] It should also be noted that, to obtain a more accurate maximum capacitive load value for the I2C bus, the previous read / write operation test must have failed, and the current read / write operation must have passed. The Cset value set in this test is the maximum capacitive load value for the I2C bus. Furthermore, during fine-tuning, the minimum value of the target range is used as the initial value. In this way, the system will first go through a process of passing the test, then failing the test, and finally passing the test again, resulting in higher accuracy.
[0068] For example, if the target range is [625, 750] and the maximum capacitive load of the I2C bus is 700pF, then during fine-tuning, Cset is first set to 625pF. At this point, read and write operations pass. Therefore, the value of Cset is increased using an upward adjustment formula. If the value of Cset is updated to 695pF using the formula, the read and write operation test will still show as passed. Then, a second upward adjustment is performed using the formula. For example, if the second upward adjustment updates the value of Cset to 705pF, when a read and write operation test is performed again, since 705pF is greater than 700pF, the capacitive load setting has exceeded the limit that the I2C bus can withstand, and the read and write operation test will show as failed. Based on this, the system will further decrease the value of Cset according to a downward adjustment formula. For example, decreasing the value of Cset to 702pF will still result in a failed read and write operation test; however, if the value of Cset is decreased to 698pF, the read and write operation test will pass.
[0069] Since the 705pF test failed and the 698pF read / write operation test passed, the convergence condition of the I2C bus capacitive load value was triggered. Therefore, the system determined that the I2C bus capacitive load value had converged and set the final converged capacitive load value as the maximum capacitive load value of the I2C bus, that is, the maximum capacitive load value of the I2C bus was set to 698pF.
[0070] Understandably, by determining this convergence condition, the maximum capacitive load value of the I2C bus can be quickly determined, improving testing efficiency. For example, actual testing shows that for a chip with a labeled maximum capacitive load value of 1000pF, determining its actual maximum capacitive load value only requires four coarse binary search tests and three to six fine-tuning tests, greatly improving efficiency. On the other hand, although there may be a certain deviation between the tested maximum capacitive load value and the actual maximum capacitive load value of the I2C bus—for example, the actual maximum capacitive load value might be 700pF, but the tested value might be 698pF, a difference of 2pF—after fine-tuning the formula in this application, the difference is substantially small and within an acceptable error range. Furthermore, by using the failure of the previous read / write test and the success of the current read / write test as the convergence condition, it can be ensured that the maximum capacitive load test value will be slightly less than the actual maximum capacitive load value. This leaves a certain amount of redundancy in subsequent use, effectively avoiding overload during actual use and improving the performance.
[0071] In summary, this application provides an I2C bus capacitive load testing method. This method is applied to the control device of an I2C bus capacitive load testing system. The I2C bus capacitive load testing system also includes a master device, a slave device, a load capacitance measurement module, an electrical characteristic parameter testing module, a capacitive load adjustment module, and pull-up resistors. The master device and slave device communicate via an I2C bus, which is connected to the power supply via pull-up resistors. The control device is connected to the load capacitance measurement module, the electrical characteristic parameter testing module, and the capacitive load adjustment module, respectively. The value measurement module, electrical characteristic parameter testing module, and capacitive load adjustment module are all connected to the I2C bus. Upon receiving a test command, a binary search is used for coarse searching to pinpoint the target range of the capacitive load on the I2C bus. Within the target range, the capacitive load adjustment module is fine-tuned based on the set rise time, the measured rise time, and the pull-up resistor value until the capacitive load value of the I2C bus converges. The final converged capacitive load value is taken as the maximum capacitive load value of the I2C bus. The measured rise time is obtained from the electrical characteristic parameter testing module. On one hand, the solution provided in this application establishes a dedicated I2C bus capacitive load testing system, thus accurately testing the I2C capacitive load capacity. On the other hand, in actual testing, the approximate range of the maximum capacitive load on the I2C bus is quickly determined using a binary search method. Then, within this range, a closed-loop fine-tuning is performed based on the set rise time, the measured rise time, and the pull-up resistor value, significantly reducing the number of trial and error attempts and improving testing efficiency.
[0072] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can also be implemented in other ways. The system embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function.
[0073] It should also be noted that in some alternative implementations, the functions marked in the boxes may occur in a different order than those shown in the accompanying drawings. For example, two consecutive boxes may actually be executed in essentially parallel order, or they may sometimes be executed in reverse order, depending on the functions involved.
[0074] It should also be noted that each box in a block diagram and / or flowchart, as well as combinations of boxes in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0075] In addition, the functional modules in the embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0076] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
[0077] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for testing capacitive load on an I2C bus, characterized in that, The method is applied to the control device of an I2C bus capacitive load testing system. The I2C bus capacitive load testing system further includes a master device, a slave device, a load capacitance measurement module, an electrical characteristic parameter testing module, a capacitive load adjustment module, and pull-up resistors. The master device and the slave device communicate via an I2C bus, which is connected to a power supply through the pull-up resistors. The control device is connected to the load capacitance measurement module, the electrical characteristic parameter testing module, and the capacitive load adjustment module, respectively, and all three modules are connected to the I2C bus. The method includes: Upon receiving the test command, a coarse search is performed using the binary search method to pinpoint the target range where the capacitive load of the I2C bus is located. Within the target range, the capacitive load adjustment module is finely adjusted based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor until the capacitive load value of the I2C bus converges, and the finally converged capacitive load value is taken as the maximum capacitive load value of the I2C bus; wherein, the measured rise time is obtained based on the electrical characteristic parameter testing module.
2. The I2C bus capacitive load testing method according to claim 1, characterized in that, The steps for performing a coarse search using a binary search method and identifying the target range where the capacitive load of the I2C bus is located include: Set the initial search interval [Cmin, Cmax]; Set Cset to Cmax and drive the slave device to perform read and write operations. If the read and write operations fail, set Cset to the midpoint value of the initial search interval and drive the slave device to perform read and write operations. Cset represents the capacitive load setting value. Repeat the steps of updating the search interval based on the results of the read and write operations and setting Cset as the midpoint value of the current search interval until the width of the search interval reaches the set value or the number of read and write operations reaches the threshold, and use the finally determined search interval as the target interval; wherein, the width of the search interval is Cmax-Cmin, and the width of the current search interval is half of the width of the previous search interval.
3. The I2C bus capacitive load testing method according to claim 2, characterized in that, The steps for updating the capacitive load search range based on the results of the read and write operations include: If the read / write operation is successful, the capacitive load search range is updated to [Cset, Cmax]. If the read / write operation fails, the capacitive load search range is updated to [Cmin, Cset].
4. The I2C bus capacitive load testing method according to claim 1, characterized in that, When the initial search interval is set to [0, 1000], the width of the target interval is 125pF.
5. The I2C bus capacitive load testing method according to claim 1, characterized in that, The steps for fine-tuning the capacitive load adjustment module based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor include: When the last read / write test passed, the capacitive load value was set to: Cset=Cset1+(Trspec–Tr) / ln(0.9 / 0.1)*Rset; Where Cset represents the setting value during the current test, Cset1 represents the setting value during the previous test, Trspec represents the set rise time, Tr represents the measured rise time, and Rset represents the resistance value of the pull-up resistor.
6. The I2C bus capacitive load testing method according to claim 1, characterized in that, The steps for fine-tuning the capacitive load adjustment module based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor include: If the previous read / write test failed, set the capacitive load value to: Cset=Cset1+(Tr-Trspec) / ln(0.9 / 0.1)*Rset; Where Cset represents the setting value during the current test, Cset1 represents the setting value during the previous test, Trspec represents the set rise time, Tr represents the measured rise time, and Rset represents the resistance value of the pull-up resistor.
7. The I2C bus capacitive load testing method according to claim 1, characterized in that, Within the target range, the capacitive load adjustment module is fine-tuned based on the set rise time, the measured rise time, and the resistance value of the pull-up resistor until the capacitive load value of the I2C bus converges. This process includes: When the previous read / write test fails and the current read / write test succeeds, the capacitive load value of the I2C bus is determined to have converged.
8. The I2C bus capacitive load testing method according to claim 1, characterized in that, The resistance value of the pull-up resistor satisfies the formula: Rset=(VCC – VOLmax) / 3; Where Rset represents the value of the pull-up resistor, VCC represents the power supply voltage, and VOLmax represents the maximum value of the output low level.
9. The I2C bus capacitive load testing method according to claim 1, characterized in that, The load capacitance measurement module includes an LCR bridge, the electrical characteristic parameter testing module includes an oscilloscope, and the capacitive load adjustment module includes a programmable capacitive load.
10. An I2C bus capacitive load testing system, characterized in that, The I2C bus capacitive load testing system includes a control device, a master device, a slave device, a load capacitance measurement module, an electrical characteristic parameter testing module, a capacitive load adjustment module, and pull-up resistors. The master device and the slave device communicate via an I2C bus, which is connected to a power supply via the pull-up resistors. The control device is connected to the load capacitance measurement module, the electrical characteristic parameter testing module, and the capacitive load adjustment module, respectively, and all three modules are connected to the I2C bus. The control device is used to execute the method described in any one of claims 1 to 9.