Ufs excitation generator, excitation verification method, electronic device, and storage medium
By designing a UFS stimulus generator compatible with different hosts, and utilizing a sequence generator and data format conversion component, the problem of UFS stimulus generators being incompatible with different hosts was solved, improving verification efficiency and coverage, and achieving rapid adaptation and efficient verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MAXIO TECHNOLOGY (HANGZHOU) CO LTD
- Filing Date
- 2025-01-20
- Publication Date
- 2026-07-21
Smart Images
Figure CN122431972A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of data storage technology, and in particular relates to a UFS stimulus generator, stimulus verification method, electronic device and storage medium. Background Technology
[0002] With the rapid development of flash memory technology in mobile devices such as smartphones, mobile phone memory cards are shifting from Security Digital (SD) cards and embedded Multi Media Cards (eMMC) to Universal Flash Storage (UFS). Research on host control chips in UFS is of great significance. As the frequency of mobile phone upgrades increases, chip development cycles are also shortening, placing higher demands on chip design and verification technologies. Verification objectives are evolving from functional correctness and performance compliance to meeting the needs of rapid adaptation to business applications. Therefore, it is necessary to complete module function verification in a short period of time to ensure functional correctness and complete verification.
[0003] Since UFS devices need to be compatible with different hosts, and host excitation generators in related technologies are usually only applicable to specific host scenarios, it is of great significance to study excitation generators that can be compatible with different hosts. Summary of the Invention
[0004] The purpose of this application is to provide a UFS stimulus generator, stimulus verification method, electronic device, and storage medium to solve the problem that UFS stimulus generators are incompatible with different hosts in related technologies.
[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a UFS stimulus generator, comprising: a sequence generator, configured to randomly generate stimulus sequence data packets of a first data format based on the Universal Flash Storage (UFS) version information of the current verification environment, wherein the stimulus sequence data packets include data packets specified by the UFS protocol and / or data packets that violate the UFS protocol; a stimulus sending component, configured to integrate and process the stimulus sequence data packets to obtain expected verification data; a stimulus transmission component, configured to convert the expected verification data into stimulus data of a second data format, and to receive stimulus feedback data generated by a verification object based on the stimulus data and convert it into actual verification data of the first data format, wherein the second data format is a data format matching the interface of the verification object; and a stimulus receiving component, configured to send the received actual verification data to a comparator; wherein the comparator is configured to compare the expected verification data and the actual verification data to obtain a verification result.
[0006] Secondly, embodiments of this application provide an incentive verification method, comprising: controlling a sequence generator to randomly generate incentive sequence data packets in a first data format based on the UFS version information of the current verification environment, wherein the incentive sequence data packets include data packets specified by the UFS protocol and / or data packets that violate the UFS protocol; controlling an incentive sending component to integrate the incentive sequence data packets to obtain expected verification data; controlling an incentive transmission component to convert the expected verification data into incentive data in a second data format, and receiving incentive feedback data generated by a verification object based on the incentive data and converting it into actual verification data in the first data format, wherein the second data format is a data format that matches the interface of the verification object; controlling an incentive receiving component to send the received actual verification data to a comparator; and controlling the comparator to compare the expected verification data and the actual verification data to obtain a verification result.
[0007] Thirdly, embodiments of this application provide an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.
[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method as described in the first aspect.
[0009] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: In this embodiment, when verifying a verification object, a sequence generator randomly generates a first data format stimulus sequence data packet based on the UFS version information of the current verification environment. The stimulus sequence data packet includes data packets specified by the UFS protocol and / or data packets that violate the UFS protocol. A stimulus sending component integrates the stimulus sequence data packets to obtain expected verification data. A stimulus transmission component converts the expected verification data into stimulus data in a second data format, and receives stimulus feedback data generated by the verification object based on the stimulus data and converts it into actual verification data in the first data format. The second data format is a data format that matches the interface of the verification object. A stimulus receiving component sends the received actual verification data to a comparator. The comparator compares the expected verification data and the actual verification data to obtain a verification result. In this embodiment, a first data format stimulus sequence data packet is randomly generated based on the UFS version information of the current verification environment, thereby generating stimulus data. Different hosts have different UFS version information for their verification environments; therefore, this embodiment is compatible with different hosts. Attached Figure Description
[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A schematic diagram of a UFS excitation generator is provided for one embodiment of this application; Figure 2 A schematic diagram of the excitation transmission process of a UFS excitation generator provided for one embodiment of this application; Figure 3 A schematic diagram of the excitation receiving process of a UFS excitation generator provided for one embodiment of this application; Figure 4 A flowchart illustrating an incentive verification method provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation
[0011] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0012] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, "and / or" in this application indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. It should be noted that all data involved in this application was obtained with the user's authorization.
[0013] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.
[0014] Figure 1 This is a schematic diagram of a UFS excitation generator provided as an embodiment of this application. Figure 1 As shown, the UFS stimulus generator 100 of this application embodiment may specifically include: a sequence generator 101, a stimulus transmission component 102, a stimulus transmission component 103, a stimulus receiving component 104, and a comparator 105, wherein: Sequence generator 101 is used to randomly generate stimulus sequence data packets in a first data format based on the Universal Flash Storage (UFS) version information of the current verification environment.
[0015] Specifically, there can be various types of sequence generators; that is, this application embodiment can employ multiple sequence generators. The UFS version information of the current verification environment refers to the version information of the UFS protocol in the currently configured verification environment. Sequence generator 101 randomly generates stimulus sequence data packets based on the version information of the current verification environment. The data format of this stimulus data packet is a data format matching the current verification environment, denoted as the first data format. The stimulus sequence data packet in the first data format is then sent to the stimulus sending component 102.
[0016] The stimulus sequence data packet may specifically include: various UFS Protocol Information Unit (UPIU) data packets specified by the UFS protocol (such as UFS2.2, UFS3.1, and UFS4.0), and / or UPIU data packets that violate the UFS protocol, such as UPIU data packets with modified reserved field values or parameter setting ranges. A UPIU data packet is a data packet in units of UPIU.
[0017] The UFS version information is a macro definition in the verification environment configuration file regarding the UFS protocol version. During compilation, the verification environment distinguishes different UFS versions based on this configured version information and generates stimuli according to different versions. For example, only when configured with UFS 4.0 will the Total EHSL length field in the UPIU packet be randomly selected and compared during transmission. The UFS stimulus generator in this embodiment can achieve verification environments with different UFS versions by changing the macro definition regarding the UFS protocol version information in the verification environment configuration file. This allows for rapid switching of simulation environments under multi-project parallel conditions, enabling verification for different projects.
[0018] In some embodiments, the verification environment selects the interface width based on the configured macros. If the macro configuration for the UFS protocol version information is UFS 4.0, the data width at the interface connecting to the verification object 200 will be extended to 128 bits. Simultaneously, when packaging the stimulus data, it will also be packaged into several 128-bit data packets according to the data width information. Therefore, different version information will convert the stimulus data into data packets of different data formats, and different parsing methods will be used during unpacking and comparison, but the final obtained UPIU data format will be consistent.
[0019] The stimulus sending component 102 is used to integrate and process the stimulus sequence data packets to obtain the desired verification data.
[0020] Specifically, the stimulus sending component 102 receives stimulus sequence data packets generated by various sequence generators, integrates and processes the received stimulus sequence data packets to obtain expected verification data, and sends the expected verification data to the stimulus transmission component 103 and the comparator 105 respectively. The stimulus sending component 102 can send the expected verification data to a queue for use by the comparator 105. There can be multiple comparators 105, in which case each expected verification data can be distributed to each comparator 105.
[0021] The integrated processing of received stimulus sequence data packets may specifically include performing at least one of the following processing: sorting (i.e., sorting the stimulus sequence data packets according to the pre-built expected verification data acquisition order), error annotation, and parameter modification (modifying a part of the content in the stimulus sequence data packets), etc. For example, for the "continue write" function in Device Management, a sequence of data packets needs to be sent in which the function of multiple query request UPIUs is a Standard write request, the opcode is a write descriptor, and the descriptor IDN is a configuration descriptor. The UFS stimulus generator constructs an stimulus sequence that satisfies the condition that during the time period when the first query request has not returned a query response, the bConfDescContinue field of the first and subsequent query requests needs to be set to 1, while the bConfDescContinue field of the last query request needs to be set to 0.
[0022] It should be noted that the UFS stimulus generator in this embodiment can completely randomize the stimulus to any domain and can autonomously control the stimulus sequence. For example, in the query request example above, a normal stimulus generator might need to spend a lot of effort to cover the scenario of continuing to write requests, while the stimulus generator in this embodiment can cover both the query request with randomized functionality and the scenario of continuing to write requests, thus accelerating the collection of verification coverage.
[0023] If verification of the error-injection scenario is required, error-injection processing can be performed on the sequence and / or fields in the stimulus sequence data packet.
[0024] Error annotation in a sequence refers to modifying the parameters in any sequence of the stimulus sequence data packet. For example, in the scenario described above, the function parameter in the query request of any sequence (e.g., the last one) in the query request sequence data packet can be changed from a standard write request to a non-standard write request. A specific example is as follows: the last query request in the query request sequence data packet is annotated with a non-standard write request function parameter, and the bConfDescContinue field is still 0. In this case, the verification environment needs to check that the query response should not be "Success," and this sequence cannot be considered a successful configuration. The UFS stimulus generator configures the expected information about the query response, i.e., the expected verification data, during the integration and construction of the current sequence.
[0025] In addition to injecting errors into the sequence, the UFS stimulus generator also allows injecting errors into fields within the transmitted stimulus. For example, to address a size error, the data size of the stimulus sequence data packet can be increased or decreased to correct the length error. For instance, in the scenario described above, after obtaining the UPIU data packet, the data size is increased or decreased based on the data segment length. The amount of data added or decreased can be modified according to the design file for different UFS versions, but this is not based on the UFS version itself, but rather on the specific UFS version of the Device Under Test (DUT).
[0026] The stimulus transmission component 103 is used to convert the expected verification data into stimulus data in a second data format, and to convert the stimulus feedback data generated by the verification object 200 based on the stimulus data into actual verification data in a first data format. The second data format is a data format that matches the interface of the verification object 200.
[0027] Specifically, the stimulus transmission component 103 receives expected verification data in a first data format sent by the stimulus transmission component 102, and performs data format conversion on the expected verification data in the first data format, converting it into stimulus data in a second data format. The second data format is a data format that matches the interface of the verification object 200.
[0028] The excitation transmission component 103 sends excitation data in a second data format to the verification object 200. The verification object 200 receives the excitation data in a second data format through an interface, generates excitation feedback data in a second data format based on the excitation data in the second data format, and sends the excitation feedback data in the second data format to the excitation transmission component 103.
[0029] The excitation transmission component 103 receives the excitation feedback data in the second data format sent by the verification object 200, performs data format conversion on the excitation feedback data in the second data format, converts the excitation feedback data in the second data format into actual verification data in the first data format, and sends the actual verification data in the first data format to the excitation receiving component 104.
[0030] The stimulus receiving component 104 is used to send the received actual verification data to the comparator 105.
[0031] Specifically, the stimulus receiving component 104 receives the actual verification data in the first data format sent by the stimulus transmitting component 103, and sends the actual verification data in the first data format to the comparator 105 where the corresponding expected verification data is located.
[0032] Comparator 105 is used to compare the expected verification data with the actual verification data to obtain the verification result.
[0033] Specifically, comparator 105 compares the expected verification data in the first data format sent by stimulus sending component 102 with the actual verification data in the corresponding first data format sent by stimulus receiving component 104. If the expected verification data and the actual verification data are consistent, a verification result of successful verification is generated; if the expected verification data and the actual verification data are inconsistent, a verification result of failed verification is generated.
[0034] It should be noted here that the UFS excitation generator 100 in this embodiment may also include a reference model ( Figure 1 (Not shown in the image) The stimulus sending component 102 can send expected verification data to the reference model, which implements the same function as the verification object 200, and pass the output reference verification data to the comparator 105 for comparison with the actual verification data sent to the comparator 105 by the stimulus receiving component 104 or the actual verification data sent to the comparator 105 by the verification object 200. The verification object 200 can also send expected verification data related to firmware (FW) behavior to the reference model for comparison.
[0035] Furthermore, the excitation transmission component 103 can be specifically used to: determine whether a reset instruction exists. If no reset instruction exists, the expected verification data is converted into excitation data in a second data format. If a reset instruction exists, the conversion of the expected verification data into excitation data in the second data format is stopped.
[0036] Specifically, because the timing of the reset command is highly random, a reset can easily occur halfway through the distribution of stimulus data. In this case, the verification object 200 will stop receiving stimulus data, even though the stimulus data has already been sent from the stimulus transmission component 103 of the UFS stimulus generator. Therefore, to avoid a mismatch between the actual number of verification data and the expected number of verification data due to a reset, the UFS stimulus generator has a reset control function that stops the distribution of new stimulus data before the reset operation is triggered. If there is stimulus data being distributed, the stimulus transmission component 103 will determine whether to discard the distributed stimulus data based on the behavior of the verification object 200, thereby achieving a more accurate comparison.
[0037] As one feasible implementation, after receiving expected verification data in a first data format sent by the incentive sending component 102, the incentive transmission component 103 determines whether a reset command exists. If no reset command exists, the incentive transmission component 103 proceeds normally with the subsequent process, that is, converting the expected verification data in the first data format into incentive data in a second data format and sending the incentive data in the second data format to the verification object 200. If a reset command exists, the incentive transmission component 103 stops converting the expected verification data in the first data format into incentive data in the second data format, and if there is incentive data being sent, the incentive transmission component 103 discards or retains the incentive data being sent based on the behavior of the verification object 200.
[0038] As one feasible implementation, after receiving expected verification data in a first data format sent by the incentive sending component 102 and determining that no reset instruction is currently present, the incentive transmission component 103 converts the expected verification data into incentive data in a second data format, and determines whether it has received incentive data requiring flow control sent by the incentive receiving component 104 calling the sequence generator 101 and the incentive sending component 102 (the transmission process for incentive data requiring flow control is the same as that for normal incentive data). If the incentive transmission component 103 currently receives incentive data requiring flow control sent by the incentive receiving component 104 calling the sequence generator 101 and the incentive sending component 102, it inserts or modifies (i.e., retains or discards) the incentive data based on the incentive data requiring flow control, and sends the final incentive data to the verification object 200. If the incentive transmission component 103 currently does not receive incentive data requiring flow control sent by the incentive receiving component 104 calling the sequence generator 101 and the incentive sending component 102, it does not process the incentive data and sends it directly to the verification object 200.
[0039] Furthermore, the stimulus receiving component 104 can also be used to: after sending the received actual verification data to the comparator 105, parse the flow control-related data sent by the stimulus transmission component 103, and determine whether flow control measures need to be implemented based on the parsing result. If it is determined that flow control measures need to be implemented, the sequence generator 101 and the stimulus sending component 102 are invoked to send the stimulus data requiring flow control. If it is determined that flow control measures do not need to be implemented, the sequence generator 101 and the stimulus sending component 102 are not invoked to send the stimulus data requiring flow control.
[0040] Specifically, after sending the received actual verification data to the comparator 105, the stimulus receiving component 104 can also perform certain flow control measures, such as constructing a correspondence between the data output (DATA OUT) signal and the ready to transfer (RTT) signal under different scenarios, to assist the stimulus sending component 102 in sending DATA OUT. RTT indicates that the verification object informs the host that it is ready to receive the data output signal sent by the host.
[0041] Flow control refers to the process control of subsequent data transmission based on the data fed back by the verification object 200 after the excitation generator sends data to the verification object 200. This includes the control of data transmission speed, data transmission content, and the control of inserting or changing data (i.e., retaining or discarding).
[0042] When the stimulus receiving component 104 sends the received actual verification data to the comparator 105 and there is a current need to perform flow control measures, it calls the sequence generator 101 and the stimulus sending component 102 to send the stimulus data that needs flow control to the stimulus transmission component 103, so as to indicate that the stimulus data should be inserted or modified at time node A of the stimulus sending process.
[0043] Here, time node A refers to the time node when the UFS excitation generator 100 needs to perform process control, that is, to obtain the RTT information to be transmitted from the device to the host, and to parse and convert the RTT information into a data output (DATA OUT) packet and send it to the device.
[0044] To clearly illustrate the workflow of the UFS excitation generator in this application embodiment, the following is combined with... Figure 2 The stimulus transmission process of the UFS stimulus generator is described in detail. For example... Figure 2 As shown, the stimulus transmission process of the UFS stimulus generator in this embodiment includes: S201, the sequence generator randomly generates an excitation sequence data packet in the first data format based on the version information of the current verification environment.
[0045] S202, the stimulus sending component integrates and processes the stimulus sequence data packets to obtain the expected verification data.
[0046] S203, the excitation transmission component determines whether a reset command exists. If yes, it returns to step S201. If no, it proceeds to step S204.
[0047] S204, the stimulus transmission component converts the expected verification data into stimulus data in a second data format.
[0048] S205, the excitation transmission component determines whether it has received the excitation data requiring flow control sent by the excitation receiving component at time node A, which calls the sequence generator and the excitation sending component. If yes, proceed to step S206. If no, proceed to step S207.
[0049] S206, the excitation transmission component inserts or modifies the excitation data. Proceed to step S207.
[0050] S207, send the stimulus data to the verification object. Return to step S201.
[0051] To clearly illustrate the workflow of the UFS excitation generator in this application embodiment, the following is combined with... Figure 3 The excitation receiving process of the UFS excitation generator is described in detail. For example... Figure 3 As shown, the stimulus receiving process of the UFS stimulus generator in this embodiment includes: S301, the excitation transmission component receives excitation feedback data generated by the verification object based on the excitation data.
[0052] S302, the excitation transmission component converts the excitation feedback data into actual verification data in a first data format.
[0053] S303, the stimulus receiving component sends the received actual verification data to the comparator.
[0054] S304, the stimulus receiving component determines whether flow control measures need to be implemented. If yes, proceed to step S305. If no, proceed to step S306.
[0055] S305, at time node A, the sequence generator and the stimulus sending component are invoked to send the stimulus data requiring flow control to the stimulus transmission component. Execute step S306.
[0056] S306, the comparator compares the expected verification data with the actual verification data to obtain the verification result. Return to step S301.
[0057] In summary, the UFS stimulus generator of this application randomly generates stimulus sequence data packets in a first data format based on the UFS version information of the current verification environment, thereby generating stimulus data. Since the UFS version information of the verification environment differs for different hosts, this application embodiment is compatible with different hosts. Reset control prevents mismatches between the number of actual and expected verification data due to reset. Flow control measures allow for the insertion or modification of stimulus data when flow control is required. Based on a general verification methodology, a fully functional UFS stimulus generator is constructed, capable of sending stimulus data in both IT-level and UT-level verification environments, exhibiting a degree of reusability. It can completely randomize any domain of the stimulus and autonomously control the generation of the stimulus sequence, improving test coverage and verification efficiency, thus demonstrating practicality.
[0058] It should be noted that in general verification scenarios, the verification strategies for IT and UT have different focuses, and the data comparisons are performed in different forms. The UFS stimulus generator in this embodiment can be reused for both IT and UT because not only the stimulus transmission part can be reused, but also the generation of expectations and the final data comparison are performed in the same format, greatly shortening the time required to build the verification environment.
[0059] This application also provides an incentive verification method. For example... Figure 4 As shown, the stimulus verification method of this application embodiment, applied in a UFS stimulus generator, may specifically include the following steps: S401, the control sequence generator randomly generates a first data format stimulus sequence data packet based on the UFS version information of the current verification environment. The stimulus sequence data packet includes data packets specified by the UFS protocol and / or data packets that violate the UFS protocol.
[0060] S402, control the excitation sending component to integrate and process the excitation sequence data packets to obtain the desired verification data.
[0061] S403, the control stimulus transmission component converts the expected verification data into stimulus data in a second data format, and receives the stimulus feedback data generated by the verification object based on the stimulus data and converts it into actual verification data in a first data format, wherein the second data format is a data format that matches the interface of the verification object.
[0062] S404, the control stimulus receiving component sends the received actual verification data to the comparator.
[0063] S405, the comparator controls the comparison between the expected verification data and the actual verification data to obtain the verification result.
[0064] In this embodiment of the application, the specific process of the incentive verification method can be found in the relevant description in the above UFS incentive generator embodiment, and will not be repeated here.
[0065] In summary, the stimulus verification method of this application randomly generates stimulus sequence data packets in a first data format based on the UFS version information of the current verification environment, thereby generating stimulus data. Since the UFS version information of the verification environment differs for different hosts, this application embodiment is compatible with different hosts. Reset control avoids mismatches between the number of actual and expected verification data due to reset. Flow control measures allow for the insertion or modification of stimulus data when flow control is required. Based on a general verification methodology, a fully functional UFS stimulus generator is constructed, capable of sending stimulus data in both IT-level and UT-level verification environments, exhibiting a degree of reusability. It can completely randomize any stimulus domain and autonomously control the generation of the stimulus sequence, improving test coverage and verification efficiency, thus demonstrating practicality.
[0066] This application also provides an electronic device. For example... Figure 5 As shown, the electronic device 500 can vary considerably depending on its configuration or performance. It may include one or more processors 501 and memory 502, with memory 502 storing one or more application programs or data. Memory 502 can be temporary or persistent storage. The application programs stored in memory 502 may include one or more modules (not shown), each module including a series of computer-executable instructions for the electronic device 500. Furthermore, processor 501 may be configured to communicate with memory 502 and execute the series of computer-executable instructions in memory 502 on the electronic device 500. The electronic device 500 may also include one or more power supplies 503, one or more wired or wireless network interfaces 504, one or more input / output interfaces 505, and one or more keyboards 506.
[0067] Specifically, in this embodiment, the electronic device includes a memory and one or more programs, wherein one or more programs are stored in the memory, and one or more programs may include one or more modules, and each module may include a series of computer-executable instructions for use in the electronic device, and is configured to be executed by one or more processors. The one or more programs include computer-executable instructions for performing the following: The control sequence generator randomly generates a first data format of stimulus sequence data packets based on the UFS version information of the current verification environment. The stimulus sequence data packets include data packets specified by the UFS protocol and / or data packets that violate the UFS protocol. The control stimulus transmission component integrates and processes the stimulus sequence data packets to obtain the desired verification data; The control stimulus transmission component converts the expected verification data into stimulus data in a second data format, and receives the stimulus feedback data generated by the verification object based on the stimulus data and converts it into actual verification data in a first data format. The second data format is a data format that matches the interface of the verification object. The control stimulus receiving component sends the received actual verification data to the comparator; The control comparator compares the expected verification data with the actual verification data to obtain the verification result.
[0068] The electronic device in this application embodiment randomly generates stimulus sequence data packets in a first data format based on the UFS version information of the current verification environment, thereby generating stimulus data. Since the UFS version information of the verification environment differs for different hosts, this application embodiment is compatible with different hosts. Reset control avoids mismatches between the actual and expected number of verification data due to reset. Flow control measures allow for the insertion or modification of stimulus data when flow control is required. Based on a general verification methodology, a fully functional UFS stimulus generator is constructed, capable of transmitting stimulus data in both IT-level and UT-level verification environments, exhibiting a degree of reusability. It can completely randomize any stimulus domain and autonomously control the generation of the stimulus sequence, improving test coverage and verification efficiency, thus demonstrating practicality.
[0069] This application also proposes a readable storage medium storing one or more computer programs, each including instructions. When executed by a processor in an electronic device comprising multiple applications, the program or instructions enable the processor to perform the various processes of the above-described method for accessing vehicle-mounted millimeter-wave radar data, specifically for executing: The control sequence generator randomly generates a first data format of stimulus sequence data packets based on the UFS version information of the current verification environment. The stimulus sequence data packets include data packets specified by the UFS protocol and / or data packets that violate the UFS protocol. The control stimulus transmission component integrates and processes the stimulus sequence data packets to obtain the desired verification data; The control stimulus transmission component converts the expected verification data into stimulus data in a second data format, and receives the stimulus feedback data generated by the verification object based on the stimulus data and converts it into actual verification data in a first data format. The second data format is a data format that matches the interface of the verification object. The control stimulus receiving component sends the received actual verification data to the comparator; The control comparator compares the expected verification data with the actual verification data to obtain the verification result.
[0070] The readable storage medium of this application embodiment randomly generates stimulus sequence data packets in a first data format based on the UFS version information of the current verification environment, thereby generating stimulus data. Since the UFS version information of the verification environment differs for different hosts, this application embodiment is compatible with different hosts. Reset control avoids mismatches between the actual and expected number of verification data due to reset. Flow control measures allow for the insertion or modification of stimulus data when flow control is required. Based on a general verification methodology, a fully functional UFS stimulus generator is constructed, capable of sending stimulus data in both IT-level and UT-level verification environments, exhibiting a degree of reusability. It can completely randomize any stimulus domain and autonomously control the generation of the stimulus sequence, improving test coverage and verification efficiency, thus demonstrating practicality.
[0071] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.
[0072] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.
[0073] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0074] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0075] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0076] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0077] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0078] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0079] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.
[0080] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0081] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.
[0082] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0083] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A UFS excitation generator, characterized in that, include: A sequence generator is used to randomly generate a first data format of stimulus sequence data packets based on the Universal Flash Storage (UFS) version information of the current verification environment. The stimulus sequence data packets include data packets specified by the UFS protocol and / or data packets that violate the UFS protocol. An incentive transmission component is used to integrate and process the incentive sequence data packets to obtain the desired verification data; An incentive transmission component is used to convert the expected verification data into incentive data in a second data format, and to receive incentive feedback data generated by the verification object based on the incentive data and convert it into actual verification data in the first data format, wherein the second data format is a data format that matches the interface of the verification object; An incentive receiving component is used to send the received actual verification data to the comparator; The comparator is used to compare the expected verification data and the actual verification data to obtain the verification result.
2. The UFS excitation generator according to claim 1, characterized in that, The stimulus sending component integrates the stimulus sequence data packets, including at least one of the following processes: sorting, error correction, and parameter modification.
3. The UFS excitation generator according to claim 2, characterized in that, The incentive transmission component performs sorting processing on the incentive sequence data packets, including: The incentive sending component sorts the incentive sequence data packets according to the pre-built order of acquisition of the expected verification data.
4. The UFS excitation generator according to claim 2, characterized in that, The incentive sending component performs error annotation processing on the incentive sequence data packets, including: The incentive sending component performs error annotation processing on the sequences and / or fields in the incentive sequence data packet. The error handling for sequences includes: When the stimulus sequence data packet is a query request sequence data packet, the functional parameters in the query request of any sequence in the query request sequence data packet are changed from standard write request to non-standard write request; Error handling for fields includes: Increase or decrease the amount of data in the stimulus sequence data packet to change the length of the stimulus sequence data packet.
5. The UFS excitation generator according to claim 1, characterized in that, The UFS version information is a macro definition in the verification environment configuration file regarding the UFS protocol version information.
6. The UFS excitation generator according to any one of claims 1 to 5, characterized in that, The excitation transmission component is specifically used for: Determine if a reset command is currently in effect; If it does not exist, the expected verification data is converted into the stimulus data in the second data format; If it exists, then stop converting the expected verification data into the incentive data in the second data format, and if there is incentive data being issued, then discard or retain the incentive data being issued according to the behavior of the verification object.
7. The UFS excitation generator according to claim 6, characterized in that, The excitation transmission component is specifically used for: After converting the expected verification data into the stimulus data in the second data format, if the stimulus receiving component calls the sequence generator and the stimulus sending component to send stimulus data requiring flow control, then the stimulus data is inserted or modified based on the stimulus data requiring flow control.
8. The UFS excitation generator according to claim 7, characterized in that, The excitation receiving component is also used for: The flow control-related data sent by the incentive transmission component is parsed, and the flow control measures are determined based on the parsing results. If necessary, the sequence generator and the stimulus sending component are invoked to send the stimulus data requiring flow control; If not required, the sequence generator and the stimulus sending component will not be invoked to send the stimulus data requiring flow control.
9. An incentive verification method, characterized in that, include: The control sequence generator randomly generates a first data format of stimulus sequence data packets based on the UFS version information of the current verification environment. The stimulus sequence data packets include data packets specified by the UFS protocol and / or data packets that violate the UFS protocol. The control stimulus transmission component integrates and processes the stimulus sequence data packets to obtain the desired verification data; The control stimulus transmission component converts the expected verification data into stimulus data in a second data format, and receives stimulus feedback data generated by the verification object based on the stimulus data and converts it into actual verification data in the first data format, wherein the second data format is a data format that matches the interface of the verification object; The control stimulus receiving component sends the received actual verification data to the comparator; The comparator is controlled to compare the expected verification data and the actual verification data to obtain the verification result.
10. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method as claimed in claim 9.
11. A readable storage medium, characterized in that, A program or instructions are stored on the readable storage medium, which, when executed by a processor, implement the steps of the method as described in claim 9.