A fault injection method and system for key resources of an SRAM type FPGA

Abstract

The application discloses a fault injection method and system for key resources of SRAM type FPGA, and relates to the technical field of integrated circuit reliability testing. The logical coordinates of a target configurable logic block and a lookup table of a to-be-tested circuit in the SRAM type FPGA are extracted, and a fault address list is generated according to the logical coordinates; according to the sequence of the fault address list, internal configuration ports in the FPGA are driven to read configuration frame data including target resource configuration information from a configuration memory and temporarily store the configuration frame data in a data cache area; in the data cache area, each target bit is sequentially subjected to single-frame logical inversion according to the sequence of the fault address list, and after single-target-bit inversion, the to-be-tested circuit is activated to run a preset test vector; the test result of the to-be-tested circuit is compared with a pre-stored correct result; when the number of fault injection cycles reaches a preset threshold, the physical address of the injection point and the corresponding comparison result are uploaded to an upper computer. The method improves the reliability of SEU evaluation of the DUT.

Description

Technical Field

[0001] This application relates to the field of integrated circuit reliability testing technology, and in particular to a fault injection method and system for critical resources of SRAM-type FPGAs. Background Technology

[0002] Static Random-Access Memory (SRAM) type Field Programmable Gate Arrays (FPGAs) are widely used in aerospace, industrial control, and other fields due to their reconfigurability, high performance, and low cost. However, SRAM-based FPGAs contain a large number of memory cells that are sensitive to Single Event Upsets (SEUs) in the space radiation environment. SEUs can cause logic levels in the memory to flip, thereby changing the logic function of the circuit and even causing system failures. This severely limits their application in aerospace and other fields with high reliability requirements.

[0003] The Serving Usage Detection Unit (SEU) in the internal configuration memory of an SRAM-based FPGA has a significant impact on system reliability. Therefore, fault injection testing of the designed circuit to assess its reliability is crucial. Fault injection, as an effective method for evaluating FPGA sensitivity to SEUs, has been researched both domestically and internationally. Existing fault injection methods employ hardware injection. Hardware injection can be further divided into external and internal fault injection depending on the configuration port: external injection reconfigures the FPGA through external configuration ports (selectMAP, JTAG), while internal injection reconfigures through the Internal Configuration Access Port (ICAP). Internal injection has the advantage of being faster than external injection, allowing faults to be injected into the configuration memory without interrupting the operation of the Design Under Test (DUT). However, internal injection still faces the following problems: the FPGA's configuration bitstream contains a large number of routing resources, unused logic resources, and control bits. Random injection often flips to invalid regions, resulting in a large amount of invalid data during testing. Especially during fault injection testing, faults may be injected into system components other than the DUT, causing system failure and making it impossible to complete the SEU reliability assessment of the DUT. Summary of the Invention

[0004] Therefore, it is necessary to provide a fault injection method and system for critical resources of SRAM-type FPGAs to address the above-mentioned technical problems.

[0005] The following technical solution is adopted in this specification: This specification provides a fault injection method for critical resources of SRAM-type FPGAs, including: Extract the logical coordinates of the target configurable logic block and lookup table of the circuit under test in the Static Random Access Memory (SRAM) type Field Programmable Gate Array (FPGA), and generate a fault address list based on the logical coordinates; the fault address list includes the configuration frame address, word offset, and bit offset; According to the order of the fault address list, the internal configuration port in the SRAM-type FPGA reads the configuration frame data, which includes the target resource configuration information, from the configuration memory and temporarily stores it in the data buffer. In the data buffer, each target bit is sequentially flipped using single-frame logic according to the order of the fault address list. After flipping a single target bit, the circuit under test is activated to run a preset test vector, and the test result of the circuit under test is compared with the pre-stored correct result. Single-frame logic flipping includes flipping the previous fault point again to achieve fault repair when injecting the next fault point in the same configuration frame, and flipping the current fault point to achieve fault injection. When the number of fault injection cycles reaches a preset threshold, the physical address of the injection point and the corresponding comparison results are uploaded to the host computer.

[0006] Optionally, the method further includes: After completing the logical flip of all target bits in the current frame and recording the test results, the original configuration data before the flip is written back to the configuration memory through the internal configuration port, so that the FPGA can be restored to a fault-free state to prepare for fault injection in the next frame.

[0007] Optionally, the method further includes: Generate a full address list of target configurable logic blocks and lookup tables for each submodule of the circuit under test; Perform full-coverage fault injection based on the full address list; Based on the fault injection results, the sensitive bit rate and sensitive resource rate of each submodule are calculated. For any given sensitivity rate, targeted reinforcement is implemented for submodules with sensitivity rates exceeding a preset sensitivity threshold, while the remaining modules retain their original design.

[0008] Optionally, a list of fault addresses is generated based on logical coordinates, including: For any target configurable logic block and lookup table, the logical coordinates are mapped to the address according to the configuration architecture parameters of the SRAM-type FPGA to obtain the configuration frame address, word offset and bit offset. The configuration frame address, word offset, and bit offset of all logical coordinates are integrated to obtain the fault address list.

[0009] Optionally, the logical coordinates include the vertical and horizontal physical coordinates of the target configurable logic block, the horizontal coordinates of the slice resource where the lookup table is located, and the sequence index of the lookup table within the slice; based on the configuration architecture parameters of the SRAM-type FPGA, the logical coordinates are address-mapped to obtain the configuration frame address, word offset, and bit offset, including: Based on the relationship between the vertical physical coordinates of the target configurable logic block and the row number of the SRAM-type FPGA clock region, determine whether the target resource belongs to the top or bottom half of the region, and calculate the row address of the configuration frame. The horizontal physical coordinates of the target configurable logical block are directly mapped to the column address of the configuration frame; The secondary frame address of the configuration frame is determined based on the parity of the horizontal coordinate of the slice resource where the lookup table is located. The base word offset is calculated based on the relative position of the vertical physical coordinates of the target configurable logic block within the clock region. Based on the sequence index of the lookup table within the slice, the basic word offset and intra-frame bit offset are fine-tuned to obtain the word offset and bit offset, and the row address, column address, and secondary frame address of the configuration frame are determined as the configuration frame address.

[0010] This specification provides a fault injection system for critical resources of SRAM-type FPGAs. The system is used to implement the above-mentioned fault injection method for critical resources of SRAM-type FPGAs. The system includes a host computer and an SRAM-type FPGA. The SRAM-type FPGA is connected to the host computer through a communication port. The SRAM-type FPGA includes a fault injection controller, an address list memory, an ICAP controller, a frame data buffer module, a design under test module, and a comparison module. The host computer is used to extract the logical coordinates of the target configurable logic block and lookup table of the circuit under test in the SRAM-type FPGA, and generate a fault address list based on the logical coordinates; the fault address list includes the configuration frame address, word offset, and bit offset. The address list memory is connected to the fault injection controller and is used to cache the list of fault addresses to be injected from the host computer. The ICAP controller, connected to the fault injection controller, is used to sequentially drive the ICAP ports inside the SRAM-type FPGA to read configuration frame data, including target resource configuration information, from the configuration memory according to the order of the fault address list. The frame data caching module is used to temporarily store the configuration frame data read from the internal configuration port into the data buffer area, and in the data buffer area, each target bit is sequentially flipped in a single frame according to the order of the fault address list. The design under test module is used to activate the circuit under test to run a preset test vector after a single target bit flips. The comparison module is used to compare the test results of the circuit under test with the pre-stored correct results; The fault injection controller is connected to the communication interface to parse the host computer's instructions and coordinate the entire fault injection process. When the number of fault injection cycles reaches a preset threshold, it uploads the physical address of the injection point and the corresponding comparison results to the host computer.

[0011] Optionally, the ICAP controller, after completing the logic flip of all target bits in the current frame and recording the test results, writes back the original configuration data before the flip to the configuration memory through the internal configuration port, so that the FPGA is restored to a fault-free state in preparation for continuing the fault injection of the next frame.

[0012] Optionally, the fault injection controller has a built-in closed-loop control state machine for executing a five-stage process of readback, injection, testing, repair, and uploading. In the readback phase, the ICAP controller is driven to read the target configuration frame into the frame data buffer module. During the injection phase, based on the word offset and bit offset in the physical address list, a logical flip is performed on the specified bit in the cached data; During the testing phase, the circuit under test is activated to run preset test vectors, and the comparison module records whether the output is abnormal. During the repair phase, after injecting all target bits of the current frame, the original unflipped data is written back to the configuration memory. During the upload phase, after reaching the preset number of injection cycles, the data packet containing the physical address and comparison results is sent to the host computer via the communication interface.

[0013] Optionally, the ICAP controller has a built-in finite state machine. The state transitions of the finite state machine include: idle state, synchronization state, read configuration state, write configuration state, and desynchronization state. The idle state indicates waiting for a start signal; the synchronization state indicates sending a synchronization word to activate the ICAP interface; the read configuration state indicates sequentially executing the send read command, write frame address, and data read; the write configuration state indicates sequentially executing the send write command, write frame address, and data write; and the desynchronization state indicates sending a desynchronization command to release control of the ICAP interface.

[0014] Optionally, the host computer extracts the logical physical coordinates through a script running in the host computer's EDA tool. The script extracts location parameters, including lookup table sequence numbers, slice coordinates, and configurable logic block coordinates, from the design database after placement and routing.

[0015] This specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described fault injection method for critical resources of an SRAM-type FPGA.

[0016] This specification provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-described fault injection method for critical resources of an SRAM-type FPGA.

[0017] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects: In the fault injection method for critical resources of SRAM-type FPGAs provided in this specification, existing technologies often involve random injection that flips to a large number of non-DUT regions, causing the evaluation results to become invalid or abnormal. However, this invention extracts the logical coordinates of the target configurable logic block and lookup table to generate a fault address list containing only critical resources. This ensures that each fault injection falls on the configuration bit that truly affects the DUT's function, allowing the test results to accurately reflect the sensitivity of the DUT's critical resources to SEU, avoiding misjudgments caused by invalid injection, and thus improving the internal validity of the evaluation results. Furthermore, the internal configuration port is used to read the configuration frame data into the buffer, and a single-frame logic flip is performed in the buffer. That is, the previous fault point is repaired before injecting the current fault point, thus ensuring that there is always only one active fault in the circuit. At the same time, since the entire process does not interrupt the operation of the circuit under test, the DUT is always in a real working environment and will not produce ambiguity or non-repeatability due to the coupling of multiple faults, thereby improving the reliability of the DUT's SEU evaluation. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 This document provides a flowchart illustrating a fault injection method for critical resources of an SRAM-type FPGA. Figure 2 This document provides a flowchart for the automated generation of a configuration frame fault address list. Figure 3 This specification provides a hierarchical mapping relationship between the logic resources and physical configuration frame addresses of an SRAM-type FPGA. Figure 4 This document provides a schematic diagram of a fault injection system for critical resources of an SRAM-type FPGA. Figure 5 This specification provides a finite state machine state transition diagram for an ICAP read / write control interface. Figure 6 This specification provides a closed-loop control flowchart that integrates fault injection, testing, and in-situ repair. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without creative effort are within the scope of protection of this application.

[0021] SRAM-based FPGAs have two main types of internal memory: user memory and configuration memory. User memory includes BRAM, DRAM, and flip-flops. The values ​​in user memory constantly change as the circuit operates; therefore, single-event faults (SEUs) occurring in user memory are temporary and are usually corrected by reassignment during circuit operation. However, they may transmit erroneous data to subsequent circuits before reassignment, leading to system data errors. Configuration memory stores all routing information, look-up table (LUT) contents, and input / output (I / O) configurations. SEUs occurring in this type of memory are permanent and directly affect the circuit structure. For example, changes to the truth table of the look-up table used to form combinational logic, or short circuits and open circuits in routing, will persist unless reconfigured and cannot be eliminated by reset logic. Furthermore, configuration memory typically accounts for over 90% of the total storage resources of an FPGA; therefore, permanent SEU failures occurring in configuration memory have the greatest impact on FPGA reliability.

[0022] Existing fault injection methods are mainly divided into two categories: software simulation and hardware simulation. The main limitation of software simulation is that as the circuit size continues to increase, the time required for gate-level simulation using tools such as ModelSim increases exponentially. Furthermore, the software environment cannot realistically reproduce the transient pulses, current changes, and propagation delays caused by the SEU in the actual hardware circuit, resulting in deviations between the evaluation results and the actual aerospace or industrial environment.

[0023] Hardware injection is fast and most closely approximates real-world scenarios. Depending on the configuration port, it can be divided into external and internal fault injection: external injection reconfigures the FPGA through an external configuration port, while internal injection reconfigures through an internal configuration port. Its advantage is its speed; it can inject faults into the configuration memory without interrupting the operation of the DUT (Device Under Test). However, besides the aforementioned inability to perform SEU (Search Engine Utility) reliability assessment of the DUT, internal injection faces the following problems: Traditional ICAP-based injection controllers often have simple state machines, typically supporting only single injections or simple loops. Each fault injection requires a "readback-modification-writeback-test-restore" process, resulting in low efficiency and inflexibility. There is a lack of efficient hardware state machines that can integrate a complete closed loop of "readback-injection-test-record-repair," making automated, continuous, large-scale fault injection testing difficult. Furthermore, it cannot achieve precise resource-specific fault injection control, and vendor configuration frame formats are usually confidential or extremely complex. Existing solutions typically rely on cumbersome reverse engineering or use vendor-provided, large, and closed toolchains (such as Xilinx SEM IP). These tools often only provide error detection and correction functions and do not support flexible, user-defined fault injection for specific resources, making fault injection testing unable to provide effective guidance for the selective hardening of the DUT.

[0024] Based on this, the present invention aims to solve the problems of large injection blindness, inability to accurately control specific logic resources, and low test efficiency caused by the lack of closed-loop repair mechanism in traditional hardware state machines in existing SRAM-type FPGA fault injection technology.

[0025] This invention proposes a fault injection method and system for critical resources of SRAM-based FPGAs. The system includes a host computer and an FPGA terminal. The host computer uses a preset algorithm to precisely map the logical coordinates of CLBs and LUTs extracted from the netlist to physical configuration frame addresses. The FPGA terminal has a built-in fault injection controller that drives the ICAP interface to read and write back configuration frames. This invention employs a closed-loop hardware process of "read-injection-testing-repair," and in particular, introduces a continuous flip-over mechanism within a single frame and an in-situ repair mechanism, achieving bit-level precise traversal injection without interrupting circuit operation. Experimental results show that this system can significantly improve the effectiveness of fault injection and accurately assess the sensitivity of different logic submodules to single-event flips, providing effective guidance for selective hardening of FPGA designs. Compared with existing technologies, this invention has the following significant advantages:

[0026] (1) Resource-level precise injection is achieved: Unlike traditional random injection, this invention can accurately locate specific Configurable Logic Block (CLB) or LUT unit, avoiding invalid tests or system crashes caused by injecting faults into invalid areas or non-test areas (such as I / O control blocks, clock management units), and significantly improving the proportion of valid faults.

[0027] (2) An efficient closed-loop testing process was constructed: A hardware state machine integrating "readback-injection-testing-recording-repair" was designed, especially the "continuous flipping within a single frame" mechanism. First, a frame of data is read and temporarily stored. By flipping the original data bit by bit, the data injected for each fault is only 1 bit different from the original data. This allows the flipping introduced by the previous fault to be repaired at the same time as the next fault injection, instead of having to read, write, and repair a configuration frame for each fault injection, further improving the fault injection speed. After completing all the bits related to a specific resource in a frame, the fault is cleared by writing back the original configuration frame data. At this time, the fault injection experiment for the next configuration frame can continue, which greatly improves the speed and automation of continuous fault injection.

[0028] (3) High flexibility and strong versatility: The hardware and software co-engineering architecture is adopted. The address calculation is completed on the host computer and the injection execution is completed in the hardware. This ensures that the complex mapping algorithm is easy to update (to adapt to different FPGA models) and the execution efficiency of fault injection is guaranteed.

[0029] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart illustrating a fault injection method for critical resources of an SRAM-type FPGA as described in this specification, specifically including the following steps: S101 extracts the logical coordinates of the target configurable logic block and lookup table of the circuit under test in the Static Random Access Memory (SRAM) type Field Programmable Gate Array (FPGA), and generates a fault address list based on the logical coordinates; the fault address list includes the configuration frame address, word offset, and bit offset.

[0031] Specifically, script tools can be used to extract the logical coordinates, i.e. physical coordinates, of the target configurable logic block and lookup table on the SRAM-type FPGA chip. These coordinates include the vertical and horizontal physical coordinates of the target configurable logic block, the horizontal coordinates of the slice resource where the lookup table is located, and the sequence index of the lookup table within the slice.

[0032] In one embodiment, generating a fault address list based on logical coordinates includes: for any target configurable logic block and lookup table, mapping the logical coordinates to addresses according to the configuration architecture parameters of the SRAM-type FPGA to obtain the configuration frame address, word offset, and bit offset; and integrating the configuration frame address, word offset, and bit offset of all logical coordinates to obtain the fault address list.

[0033] In one embodiment, based on the configuration architecture parameters of the SRAM-type FPGA, address mapping of logical coordinates is performed to obtain the configuration frame address, word offset, and bit offset. This includes: determining the top or bottom half of the target resource based on the relationship between the vertical physical coordinates of the target configurable logic block and the row number of the SRAM-type FPGA clock region, and calculating the row address of the configuration frame; directly mapping the horizontal physical coordinates of the target configurable logic block to the column address of the configuration frame; determining the secondary frame address of the configuration frame based on the parity of the horizontal coordinates of the slice resource where the lookup table is located; calculating the basic word offset based on the relative position of the vertical physical coordinates of the target configurable logic block within the clock region; fine-tuning the basic word offset and the intra-frame bit offset based on the sequence index of the lookup table within the slice to obtain the word offset and bit offset; and determining the row address, column address, and secondary frame address of the configuration frame as the configuration frame address.

[0034] To achieve precise injection of specific CLB or LUT resources, this embodiment employs a strategy of "logical coordinate extraction + physical address mapping." For example... Figure 2 As shown, Figure 2 Here is a flowchart for the automated generation of a configuration frame fault address list. The automated generation process specifically includes the following steps:

[0035] Compilation and synthesis: Compiling and synthesizing the design under test (DUT).

[0036] Create Pblocks: Create physical constraint blocks (Pblocks) for the DUT or its submodules to limit the layout and routing range.

[0037] Implementation: After creating Pblocks for the DUT, ensure that the DUT is implemented in the Pblock region.

[0038] Locking: After the design implementation is completed, the logic resources (fixed cells) after layout are locked. This process ensures that the resource arrangement of the DUT remains fixed during the bit stream generation process, thereby ensuring that the generated fault injection address and the hardware logic finally downloaded into the FPGA are strictly consistent.

[0039] Information extraction: Using TCL script commands, extract the logical coordinate information of each resource from the implemented design, including SLICE_X, CLB_X, CLB_Y and the LUT sequence number LUT_sequence (A / B / C / D).

[0040] Address calculation: The extracted coordinate information is read using a Python script (Address Generate.py), and a mapping algorithm specific to a particular FPGA model is used to generate the corresponding physical configuration frame address list.

[0041] Mapping algorithm parameter definition: This embodiment takes the Xilinx XC7K325T chip as an example. The key architecture parameters required for its mapping algorithm are shown in Table 1. The architecture parameters are adjusted to adapt to different models of SRAM-type FPGA chips.

[0042] Table 1. Parameter definitions required for configuring the frame address mapping algorithm. To more intuitively illustrate the derivation basis of the configuration frame address mapping algorithm of this invention, Figure 3 This example illustrates the hierarchical mapping between the logic resources and physical configuration frame addresses of the SRAM-based FPGA (using the Xilinx 7 series as an example) selected in this embodiment. The FPGA chip is physically divided into two halves: Top and Bottom. Each half contains several horizontal clock rows. Each row further contains several columns of resources horizontally. For example... Figure 3 As shown in the middle section, a zoom-in view of a specific column reveals that different word addresses in the configuration frame data corresponding to that column represent different CLB resources at different vertical coordinates (CLB_Y). For example, CLB_Y174 corresponds to Word48 and Word49. Further, as... Figure 3 As shown on the right, for a specific SLICE resource, the bit distribution of its internal lookup table (LUT A / B / C / D) in the configuration frame has a fixed mapping relationship with the SLICE's parity position (Odd X / Even X) in the CLB. For example, for a SLICE located at Even X, the configuration information of its LUT D is stored in the high 16 bits of Word 49.

[0043] based on Figure 3 Based on the physical structural laws shown, this invention proposes a mapping algorithm, the specific process of which is as follows: By extracting the logical coordinates (X, Y, Odd / Even), the corresponding WordOffset and BitOffset can be accurately calculated using mathematical formulas. Here, " / " represents rounding, and "%" represents modulo operation. The algorithm calculates the physical address based on the input logical coordinates: The CLB address first determines whether the resource is located in the top or bottom half (tb) based on the relationship between CLB_Y and clb_num * b_rows, and calculates the row address; the column address is directly determined by CLB_X; the word offset (word_offset_CLB) is calculated based on the modulo operation result of CLB_Y within the clock region combined with CLB_length. The LUT address is based on the CLB address, determining the minor frame address (minor_LUT) according to the parity of SLICE_X; the word offset is fine-tuned according to the LUT_sequence (A / B / C / D) (e.g., incrementing by 1 for sequence C or D), and the bit offset within the frame (bit_offset_LUT, e.g., offsetting by 16 bits for sequence B or D) is determined.

[0044] This embodiment determines the half-zone location of the target resource based on the extracted CLB ordinate (CLB_Y) and the clock region distribution parameters of the FPGA chip, thereby determining the configuration frame type and row address. It directly maps the column address based on the CLB x-ordinate (CLB_X). Combining the LUT's sequence number (A / B / C / D) and the parity of its SLICE column, it uses offset calculation logic to derive the specific minor address range (minor_LUT), word offset, and intra-frame bit offset. This algorithm also introduces device architecture parameters as configuration variables, enabling adaptation to different FPGA chip models by adjusting key parameters, thus improving the method's versatility and flexibility.

[0045] S102, according to the order of the fault address list, the internal configuration port in the SRAM-type FPGA reads the configuration frame data, which includes the target resource configuration information, from the configuration memory and temporarily stores it in the data buffer.

[0046] S103, in the data buffer, according to the order of the fault address list, each target bit is sequentially flipped using single-frame logic. After flipping a single target bit, the circuit under test is activated to run a preset test vector, and the test result of the circuit under test is compared with the pre-stored correct result. Single-frame logic flipping includes flipping the previous fault point again to achieve fault repair when injecting the next fault point in the same configuration frame, and flipping the current fault point to achieve fault injection.

[0047] Specifically, based on the calculated word offset and bit offset, specific bits of the frame configuration data are logically flipped (0 becomes 1 or 1 becomes 0).

[0048] The pre-stored correct result is obtained by running the gold model with preset test vectors.

[0049] In this embodiment, a continuous flipping mechanism within a single frame is adopted, where the data written to ICAP each time differs from the original frame data by only 1 bit. When injecting the next fault point within the same configuration frame, the previous fault point is flipped again to achieve repair, and the current fault point is flipped to achieve injection, thereby merging the repair and injection operations. After completing the injection of all bits related to the target resource within the current configuration frame, the original configuration frame data is written back to the configuration memory to clear the last fault within the frame.

[0050] S104. When the number of fault injection cycles reaches the preset threshold, the physical address of the injection point and the corresponding comparison result are uploaded to the host computer.

[0051] In one embodiment, after completing the logical flip of all target bits in the current frame and recording the test results, the original configuration data before the flip is written back to the configuration memory through the internal configuration port, so that the FPGA is restored to a fault-free state in preparation for continuing the fault injection of the next frame.

[0052] Specifically, after all bits related to a specific resource in a frame are fault-injected and the test results are recorded, the original configuration data before the flip is written back to the configuration memory using the ICAP interface to eliminate the impact of the current fault and restore the FPGA to a fault-free state so as to perform fault injection for the next frame of data, thereby realizing continuous and independent fault traversal testing.

[0053] In one embodiment, a full address list of target configurable logic blocks and lookup tables is generated for each submodule of the circuit under test; full-coverage fault injection is performed based on the full address list; based on the fault injection results, the sensitive bit rate and sensitive resource rate of each submodule are calculated; for any sensitive rate, targeted hardening is implemented for submodules with a sensitive rate higher than a preset sensitive threshold, while the remaining modules retain their original design.

[0054] Among them, (1) Sensitive bit rate: the proportion of bits that cause system output errors after a flip to the total number of injected bits. (2) Sensitive CLB / LUT rate: if all relevant configuration bits in a CLB or LUT are injected and at least once cause an output error, then the CLB / LUT is marked as a sensitive resource. The sensitive resource rate represents the proportion of sensitive resources to the total resources.

[0055] When applying the fault injection method for critical resources of SRAM-type FPGAs provided in this manual, it is not necessary to follow the instructions. Figure 1 The steps shown are executed in sequence. The specific execution order of each step can be determined as needed, and this manual does not impose any restrictions on it.

[0056] The above describes one or more embodiments of a fault injection method for critical resources of SRAM-type FPGAs. Based on the same approach, this specification also provides a corresponding fault injection system for critical resources of SRAM-type FPGAs. This system can achieve bit-level precise location of CLB and LUT resources and realize automated and continuous fault injection and repair through an efficient hardware state machine. The CLB, as the core logic resource in the FPGA architecture, carries the vast majority of user circuits, while the LUT located inside the CLB is the basic physical unit for implementing FPGA combinational logic functions. Both are key factors affecting system reliability.

[0057] The system includes a host computer and an SRAM-type FPGA; the SRAM-type FPGA is connected to the host computer through a communication port; the SRAM-type FPGA includes a fault injection controller, an address list memory, an ICAP controller, a frame data buffer module, a design under test module, and a comparison module.

[0058] The host computer is used to parse the design netlist, extract the logical coordinates of the target configurable logic block and lookup table of the circuit under test in the SRAM-type FPGA, and generate a fault address list based on the logical coordinates; the fault address list includes the configuration frame address, word offset, and bit offset.

[0059] The address list memory is connected to the fault injection controller and is used to cache the list of fault addresses of the fault points to be injected issued by the host computer, providing data support for the injection operation.

[0060] The ICAP controller, connected to the fault injection controller, is used to directly drive the ICAP ports inside the FPGA via the CAP control interface to perform low-level readback and writeback operations of the configuration frame. Specifically, according to the order of the fault address list, it sequentially drives the ICAP ports inside the SRAM-type FPGA to read the configuration frame data, including the target resource configuration information, from the configuration memory. After completing the logical flip of all target bits in the current frame and recording the test results, it writes back the original configuration data before the flip to the configuration memory through the internal configuration port, so that the FPGA is restored to a fault-free state and ready to continue the fault injection of the next frame.

[0061] The frame data buffer module is used to temporarily store the configuration frame data read from the internal configuration port into the data buffer area, and in the data buffer area, each target bit is sequentially flipped in a single frame according to the order of the fault address list.

[0062] The design-under-test (DUT) module is used to activate the circuit under test to run a preset test vector after a single target bit flips, and send the test results to the comparison module.

[0063] The comparison module compares the test results of the circuit under test with pre-stored correct results to detect whether a single-event upset has caused a logic error. The pre-stored correct results are generated using the Golden Model.

[0064] The fault injection controller is connected to the communication interface. As the core scheduling unit, the fault injection controller is used to parse the host computer's instructions and coordinate the entire fault injection process. When the number of fault injection cycles reaches a preset threshold, the physical address of the injection point and the corresponding comparison results are uploaded to the host computer.

[0065] In one embodiment, such as Figure 4 As shown, Figure 4 This document provides a schematic diagram of a fault injection system for critical resources of an SRAM-type FPGA. The system physically consists mainly of a computer (PC) and an FPGA, which communicate with each other via an RS232 serial port.

[0066] The host computer is responsible for running EDA tools (such as Vivado) and address generation scripts to generate a list of fault addresses containing configuration frame addresses and bit offsets, and for sending control commands and receiving the final test data.

[0067] FPGA side: Internally integrates the core logic for fault injection, specifically including: (1) Fault Injector: As the core scheduling unit, it is responsible for parsing the host computer instructions, coordinating the work of each sub-module to carry out fault injection experiments and uploading experimental data.

[0068] (2) Address List: used to cache the physical address sequence of the fault points to be injected, which is sent by the host computer.

[0069] (3) ICAP controller (ICAP Ctrl): Directly drives the ICAP primitives of the FPGA to read and write back the configuration frame.

[0070] (4) Frame Data Buffer Module: Used to temporarily store configuration frame data read from ICAP for bit flipping operations.

[0071] (5) Design under test (DUT) module: The target logic circuit implemented by the user (in the subsequent verification of this embodiment, it is the PIC16F54 microprocessor).

[0072] (6) Comparator module: Used to monitor the output of DUT in real time and determine whether the fault has caused the error by comparing it with the pre-stored correct output (Golden Output).

[0073] In one embodiment, the fault injection controller has a built-in closed-loop control state machine for executing a five-stage process of readback, injection, testing, repair, and upload.

[0074] In the readback phase, the ICAP controller is driven to read the target configuration frame into the frame data buffer module.

[0075] During the injection phase, based on the word offset and bit offset in the physical address list, a logical flip is performed on the specified bit in the cached data.

[0076] During the testing phase, the circuit under test is activated to run the preset test vectors, and the comparison module records whether the output is abnormal.

[0077] During the repair phase, after injecting all target bits of the current frame, the original unflipped data is written back to the configuration memory.

[0078] During the upload phase, after reaching the preset number of injection cycles, the data packet containing the physical address and comparison results is sent to the host computer via the communication interface.

[0079] In one embodiment, the ICAP controller has a built-in finite state machine. The state transitions of the finite state machine include: idle state (IDLE), synchronization state (SYNC), read configuration state, write configuration state, and desynchronization state (DESYNC). The idle state indicates waiting for a start signal; the synchronization state indicates sending a synchronization word to activate the ICAP interface; the read configuration state indicates sequentially executing the send read command (RCFG), write frame address (FAR_R), and data read (FDRO); the write configuration state indicates sequentially executing the send write command (WCFG), write frame address (FAR_W), and data write (FDRI); and the desynchronization state indicates sending a desynchronization command to release control of the ICAP interface.

[0080] To ensure the security of configuration operations, the ICAP controller employs the following... Figure 5The system is managed using a finite state machine. After power-on, the system is in the IDLE state. Upon receiving a start signal, it enters the SYNC state, sends a synchronization word, and then resets the CRC register. Read operations sequentially go through RCFG (read command), FAR_R (write frame address), and FDRO (read data) to read the configuration frame into the buffer. Write operations sequentially go through verifying the development board ID, FAR_W (write frame address), WCFG (write command), and FDRI (write data) to write the modified data back to the configuration memory. After the operations are completed, the system enters the DESYNC state to release control.

[0081] In one embodiment, the host computer extracts the logical physical coordinates through a script running in the host computer's EDA tool. The script extracts location parameters, including lookup table sequence numbers, slice coordinates, and configurable logic block coordinates, from the design database after placement and routing.

[0082] In one embodiment, the closed-loop injection and repair process is as follows: Figure 6 As shown, the fault injection controller executes the following loop: Readback: Read back the target frame data.

[0083] Fault injection: Each write of configuration frame data differs from the original frame data by only 1 bit, thus enabling the repair of the flip caused by the previous fault during the next fault injection, further improving the fault injection speed.

[0084] DUT testing: Run the test vectors and record the comparison results (RECORD).

[0085] Repair: After all bits related to CLB or LUT in a frame have been injected, the original data in the buffer is written back to the FPGA. The fault can be cleared without global reset or reloading of the bit stream. At this time, the fault injection experiment for the next frame can continue, which greatly improves the speed and automation of continuous fault injection.

[0086] UPLOAD: Upload the test results after reaching the predetermined maximum number of injections (INJECT_MAX). Figure 3 The configuration frame data shown corresponds to CLB and LUT, indicating that the maximum number of injections is 64 for CLB and 16 for LUT.

[0087] In one embodiment, to verify the accuracy and practicality of the system of the present invention, a classic microprocessor—PIC16F54 and its internal sub-modules—was selected as the test object. Fault injection experiments were conducted on the Xilinx XC7K325T FPGA platform. The various sub-modules of PIC16F54 (such as instruction fetch module, decoder, ALU, etc.) were laid out in different areas of the FPGA and the area was constrained by Pblock.

[0088] Table 2 lists the actual resource consumption of each test circuit (submodule), covering resources such as CLB, LUT, MUX, and flip-flops (FF).

[0089] Table 2 Resource Consumption List of PIC16F54 Using the aforementioned address generation tool, the precise physical addresses of the CLB and LUT resources occupied by each module in Table 2 were extracted, and a corresponding fault address list was generated. Subsequently, the fault injection system of this invention was used to perform traversal bit-flipping injection on each address in these lists, that is, to perform traversal fault injection tests on the configuration bits related to each CLB and LUT used (64 bits * 36 frames for each CLB-related bit, and 16 bits * 4 frames for each LUT-related bit).

[0090] Tables 3 and 4 show the fault injection results for CLB and LUT resources. The data shows that the overall CLB sensitivity bit rate of the PIC16F54 is 6%, while the sub-modules "Instruction fetch module" and "ALU8" are as high as 12.4% and 8.8% respectively, and are identified as high-sensitivity modules. Further testing of these two sub-modules and their TMR-hardened versions revealed an interesting phenomenon: the LUT sensitivity rate of the "Instruction fetch module" (18.6%) is higher than its CLB sensitivity rate, indicating that its faults are mostly caused by LUT logic flipping; conversely, the LUT sensitivity rate of "ALU8" (5.3%) is lower than its CLB sensitivity rate, suggesting that its faults mainly originate from misconfiguration of routing resources. This means that differentiated hardening strategies need to be adopted for different modules. At the same time, the experimental data also confirms that although TMR technology is effective, it has a huge overhead, and therefore is more suitable for targeted selective hardening. In addition, all sensitivity indicators for the sub-module "Non-addressable register" are 0. Analysis confirmed that this was caused by the load program not actually using the module. A control experiment in which the program could still run normally after the module was removed further verified the correctness of the fault injection platform and the experimental results.

[0091] Table 3. CLB Fault Injection Results for PIC16F54 Table 4. LUT Fault Injection Results for PIC16F54 To quantitatively evaluate the speed improvement brought by the "continuous flipping within a single frame" mechanism, this paper analyzes the configuration overhead of a single-bit fault injection cycle and defines... The time required to read one frame of configuration data via ICAP. The time required to write one frame of data, This represents the total number of bits to be injected with faults. Traditional fault injection typically employs a "read-modify-write-test-restore" process. For each bit flip test, a complete read is required to obtain the current state, the injected fault is written, and after testing, a write (or reconfiguration) is performed to restore the original state. Therefore, to complete... Total configuration time for injecting bits The time consumption is shown in formula (1). The fault injection process proposed in this paper, targeting N target bits within the same frame, only requires the system to perform a read operation at the beginning to cache the frame data in the Frame Data module. Subsequently, during the traversal test, the cached data is used to perform a combined operation of "injecting the current bit + repairing the previous bit," eliminating the need for repeated readings and independent restoration write steps. Therefore, the total configuration time is reduced. As shown in formula (2). Read and write operations take similar amounts of time, let... The theoretical speedup ratio for fault injection is shown in formula (3). When the fault injection target is a CLB, The speedup ratio is approximately 2.9, while when the fault injection object is a LUT... The acceleration ratio is approximately 2.6.

[0092] The experimental data comprehensively demonstrates that the system proposed in this invention can not only stably perform large-scale fault injection (such as full-coverage testing of PIC16F54) and accurately locate faults to specific logic sub-modules (such as ALU, Decoder, etc.) and their corresponding physical resources (CLB / LUT), but more importantly, in terms of testing efficiency, thanks to the significant reduction in configuration port access overhead caused by the 'continuous flipping within a single frame' mechanism, the experimentally measured fault injection speed for CLB and LUT is approximately 2.9 times and 2.6 times faster than traditional methods, respectively. This evaluation capability, which combines fine-grained accuracy with high throughput, helps designers quickly identify weaknesses in their designs, thereby enabling targeted radiation hardening and avoiding blind redundant backups of the entire design. This fully verifies the efficiency and practicality of the system proposed in this invention.

[0093] Specific limitations regarding the fault injection system for critical resources of SRAM-type FPGAs can be found in the limitations on fault injection methods for critical resources of SRAM-type FPGAs mentioned above, and will not be repeated here. Each module in the aforementioned fault injection system for critical resources of SRAM-type FPGAs can be implemented entirely or partially through software, hardware, or a combination thereof.

[0094] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 1 A fault injection method is provided for critical resources of SRAM-type FPGAs.

[0095] This specification also provides a schematic diagram of a computer device. At the hardware level, this computer device includes a processor, an internal bus, a network interface, memory, and non-volatile memory, and may also include other hardware required for various operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then executes it to achieve the above-mentioned functions. Figure 1 A fault injection method is provided for critical resources of SRAM-type FPGAs.

[0096] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A fault injection method for critical resources of SRAM-type FPGAs, characterized in that, The method includes: Extract the logical coordinates of the target configurable logic block and lookup table of the circuit under test in the Static Random Access Memory (SRAM) type Field Programmable Gate Array (FPGA), and generate a fault address list based on the logical coordinates; the fault address list includes the configuration frame address, word offset, and bit offset; According to the order of the fault address list, the internal configuration port in the SRAM-type FPGA reads the configuration frame data, which includes the target resource configuration information, from the configuration memory and temporarily stores it in the data buffer. In the data buffer, each target bit is sequentially flipped using single-frame logic according to the order of the fault address list. After flipping a single target bit, the circuit under test is activated to run a preset test vector, and the test result of the circuit under test is compared with the pre-stored correct result. Single-frame logic flipping includes flipping the previous fault point again to achieve fault repair when injecting the next fault point in the same configuration frame, and flipping the current fault point to achieve fault injection. When the number of fault injection cycles reaches a preset threshold, the physical address of the injection point and the corresponding comparison results are uploaded to the host computer.

2. The method according to claim 1, characterized in that, The method further includes: After completing the logical flip of all target bits in the current frame and recording the test results, the original configuration data before the flip is written back to the configuration memory through the internal configuration port, so that the FPGA can be restored to a fault-free state to prepare for fault injection in the next frame.

3. The method according to claim 1, characterized in that, The method further includes: Generate a full address list of target configurable logic blocks and lookup tables for each submodule of the circuit under test; Perform full-coverage fault injection based on the full address list; Based on the fault injection results, the sensitive bit rate and sensitive resource rate of each submodule are calculated. For any given sensitivity rate, targeted reinforcement is implemented for submodules with sensitivity rates exceeding a preset sensitivity threshold, while the remaining modules retain their original design.

4. The method according to claim 1, characterized in that, A list of fault addresses is generated based on logical coordinates, including: For any target configurable logic block and lookup table, the logical coordinates are mapped to the address according to the configuration architecture parameters of the SRAM-type FPGA to obtain the configuration frame address, word offset and bit offset. The configuration frame address, word offset, and bit offset of all logical coordinates are integrated to obtain the fault address list.

5. The method according to claim 4, characterized in that, Logical coordinates include the vertical and horizontal physical coordinates of the target configurable logical block, as well as the horizontal coordinates of the slice resource where the lookup table is located and the sequence index of the lookup table within the slice. Based on the configuration architecture parameters of the SRAM-type FPGA, the logic coordinates are address-mapped to obtain the configuration frame address, word offset, and bit offset, including: Based on the relationship between the vertical physical coordinates of the target configurable logic block and the row number of the SRAM-type FPGA clock region, determine whether the target resource belongs to the top or bottom half of the region, and calculate the row address of the configuration frame. The horizontal physical coordinates of the target configurable logical block are directly mapped to the column address of the configuration frame; The secondary frame address of the configuration frame is determined based on the parity of the horizontal coordinate of the slice resource where the lookup table is located. The base word offset is calculated based on the relative position of the vertical physical coordinates of the target configurable logic block within the clock region. Based on the sequence index of the lookup table within the slice, the basic word offset and intra-frame bit offset are fine-tuned to obtain the word offset and bit offset, and the row address, column address, and secondary frame address of the configuration frame are determined as the configuration frame address.

6. A fault injection system for critical resources of SRAM-type FPGAs, characterized in that, The system is used to implement the method described in any one of claims 1-5. The system includes a host computer and an SRAM-type FPGA. The SRAM-type FPGA is connected to the host computer through a communication port. The SRAM-type FPGA includes a fault injection controller, an address list memory, an ICAP controller, a frame data buffer module, a design under test module, and a comparison module. The host computer is used to extract the logical coordinates of the target configurable logic block and lookup table of the circuit under test in the SRAM-type FPGA, and generate a fault address list based on the logical coordinates. The fault address list includes the configuration frame address, word offset, and bit offset; The address list storage is connected to the fault injection controller and is used to cache the list of fault addresses to be injected from the host computer. The ICAP controller, connected to the fault injection controller, is used to sequentially drive the ICAP ports inside the SRAM-type FPGA to read configuration frame data, including target resource configuration information, from the configuration memory according to the order of the fault address list. The frame data caching module is used to temporarily store the configuration frame data read from the internal configuration port into the data buffer area, and in the data buffer area, each target bit is sequentially flipped in a single frame according to the order of the fault address list. The design under test module is used to activate the circuit under test to run a preset test vector after a single target bit flips. The comparison module is used to compare the test results of the circuit under test with the pre-stored correct results; The fault injection controller is connected to the communication interface and is used to parse the host computer instructions and coordinate and control the entire fault injection process. When the number of fault injection cycles reaches a preset threshold, the physical address of the injection point and the corresponding comparison result are uploaded to the host computer.

7. The system according to claim 6, characterized in that, The ICAP controller is used to write back the original configuration data before the flip to the configuration memory through the internal configuration port after completing the logic flip of all target bits in the current frame and recording the test results, so that the FPGA can be restored to a fault-free state and ready to continue the fault injection of the next frame.

8. The system according to claim 6, characterized in that, The fault injection controller has a built-in closed-loop control state machine, which is used to execute a five-stage process of readback, injection, testing, repair, and upload. In the readback phase, the ICAP controller is driven to read the target configuration frame into the frame data buffer module. During the injection phase, based on the word offset and bit offset in the physical address list, a logical flip is performed on the specified bit in the cached data; During the testing phase, the circuit under test is activated to run preset test vectors, and the comparison module records whether the output is abnormal. During the repair phase, after injecting all target bits of the current frame, the original unflipped data is written back to the configuration memory. During the upload phase, after reaching the preset number of injection cycles, the data packet containing the physical address and comparison results is sent to the host computer via the communication interface.

9. The system according to claim 6, characterized in that, The ICAP controller has a built-in finite state machine. The state transitions of the finite state machine include: idle state, synchronization state, read configuration state, write configuration state, and desynchronization state. The idle state indicates waiting for a start signal; the synchronization state indicates sending a synchronization word to activate the ICAP interface; the read configuration state indicates sequentially executing the send read command, write frame address, and data readout; the write configuration state indicates sequentially executing the send write command, write frame address, and data write; and the desynchronization state indicates sending a desynchronization command to release control of the ICAP interface.

10. The system according to claim 6, characterized in that, The host computer extracts the logical physical coordinates through a script running in the host computer's EDA tool. The script extracts location parameters, including lookup table sequence numbers, slice coordinates, and configurable logic block coordinates, from the design database after placement and routing.

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